A43L3616AG-6F [AMICC]
DRAM;
| 型号： | A43L3616AG-6F |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | DRAM 动态存储器 内存集成电路 |
| 文件： | 总41页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A43L3616A Series
2M x 16 Bit x 4 Banks Synchronous DRAM
Preliminary
Document Title
2M x 16 Bit x 4 Banks Synchronous DRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
Initial issue
August 7, 2007
November 14, 2007
Preliminary
Change clock frequency from 133MHz to 143MHz at 7ns cycle
time
0.2
0.3
February 20, 2008
May 5, 2008
Add part numbering scheme
Add A43L4608A part number
Modify DC spec.
0.4
0.5
0.6
Add Test Mode description
August 13, 2008
November 11, 2008
January 7, 2009
Add automotive temperature grade
Remove A43L4608A part number
Modify DC current spec.
0.7
0.8
Add 54 balls CSP (8mm x 8mm) package
August 28, 2009
November 8, 2011
Modify tRAS(max.) from 100ns to 100μs
PRELIMINARY (November, 2011, Version 0.8)
AMIC Technology, Corp.
A43L3616A Series
2M x 16 Bit x 4 Banks Synchronous DRAM
Preliminary
Features
JEDEC standard 3.3V ± 0.3V power supply
LVTTL compatible with multiplexed address
Industrial operating range: -40°C to +85°C for –U
Automotive temperature operation:-40°C to +85°C for -A
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Available in 54 Balls CSP (8mm X 8mm) and 54-pin
TSOP(II) packages
Package is available to lead free (-F series)
All Pb-free (Lead-free) products are RoHS compliant
Four banks / Pulse RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
General Description
The A43L3616A is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 X 2,097,152 words by 16
bits, abricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock. I/O transactions are possible on
every clock cycle. Range of operating frequencies,
programmable latencies allow the same device to be useful
for a variety of high bandwidth, high performance memory
system applications.
Pin Configuration
54 Balls CSP (8 mm x 8 mm)
Top View
54 Ball (6X9) CSP
1
2
3
7
8
9
A
B
C
D
E
F
VSS
DQ15
DQ13
DQ11
DQ9
NC
VSSQ
VDDQ
VSSQ
VDDQ
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VDD
DQ0
DQ2
DQ4
DQ6
LDQM
VDD
DQ1
DQ3
DQ5
DQ7
DQ14
DQ12
DQ10
DQ8
UDQM
CLK
CKE
CAS
BA0
RAS
BA1
WE
G
NC
A11
A9
CS
A10
VDD
H
J
A8
A7
A5
A6
A4
A0
A3
A1
A2
VSS
PRELIMINARY (November, 2011, Version 0.8)
1
AMIC Technology, Corp.
A43L3616A Series
Pin Configuration (continued)
TSOP (II)
VDD
1
2
3
54
53
52
VSS
DQ0
VDDQ
DQ1
DQ15
VSSQ
4
5
51
50
DQ14
DQ13
DQ2
VSSQ
DQ3
6
7
8
49
48
47
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC/RFU
UDQM
CLK
CKE
NC
DQ4
VDDQ
DQ5
9
46
45
44
10
11
DQ6
VSSQ
DQ7
12
13
14
15
43
42
41
40
VDD
LDQM
WE
16
17
39
38
CAS
18
19
20
21
22
23
24
25
26
27
37
36
35
34
33
32
31
30
29
28
RAS
CS
BA0
BA1
A11
A9
A8
A10/AP
A0
A7
A6
A1
A2
A5
A3
A4
VDD
VSS
PRELIMINARY (November, 2011, Version 0.8)
2
AMIC Technology, Corp.
A43L3616A Series
Block Diagram
LWE
DQM
Data Input Register
Bank Select
2M X 16
2M X 16
2M X 16
2M X 16
CLK
DQi
Column Decoder
ADD
Latency & Burst Length
LRAS
Programming Register
LWCBR
LCAS
DQM
LRAS
LCBR LWE
Timing Register
DQM
CLK
CKE
CS
RAS
CAS
WE
Notes: This figure shows the A43L3616A.
PRELIMINARY (November, 2011, Version 0.8)
3
AMIC Technology, Corp.
A43L3616A Series
Pin Descriptions
Symbol
Name
Description
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except CLK,
CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA11, Column address: CA0~CA8 (x16).
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
A0~A11
Address
BA0, BA1
Bank Select Address
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
RAS
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Column Address
Strobe
CAS
WE
Write Enable
Enables write operation and Row precharge.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQM,
Data Input/Output
Mask
L(U)DQM
LDQM corresponds to DQ0 ~ DQ7, UDQM corresponds to DQ8 ~ DQ15 .
Data inputs/outputs are multiplexed on the same pins.
DQ0-15
Data Input/Output
Power
Supply/Ground
VDD/VSS
Power Supply: +3.3V±0.3V/Ground.
Data Output
Power/Ground
VDDQ/VSSQ
NC/RFU
Provide isolated Power/Ground to DQs for improved noise immunity.
No Connection
PRELIMINARY (November, 2011, Version 0.8)
4
AMIC Technology, Corp.
A43L3616A Series
Absolute Maximum Ratings*
*Comments
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to +4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to +4.6V
Storage Temperature (TSTG) . . . . . . . . . . -55°C to +125°C
Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . .1W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
Permanent device damage may occur if “Absolute Maximum
Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.
Capacitance (TA=25°C, f=1MHz)
Parameter
Input Capacitance
Symbol
CI1
Condition
A0 to A11, BA0, BA1
Min
2.5
2.5
Typ
Max
3.5
Unit
pF
CI2
3.5
pF
CLK, CKE,
DQM
,
,
,
,
WE
CS RAS CAS
Data Input/Output Capacitance
CI/O
DQ0 to DQ15
4
6.5
pF
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V, TA = 0ºC to +70ºC, -40°C to +85°C for industrial
temperature range or -40°C to +85°C for automotive temperature range)
Parameter
Supply Voltage
Symbol
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
VDD,VDDQ
3.3
3.6
Input High Voltage
VIH
VIL
VOH
VOL
IIL
3.0
VDD+0.3
V
Note 1
Note 2
Input Low Voltage
0
-
0.8
-
V
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Output Loading Condition
V
IOH = -2mA
IOL = 2mA
Note 3
-
0.4
5
V
-5
-
μA
μA
IOL
-5
-
5
Note 4
See Figure 1
Note:
1. VIH (max) = 4.6V AC (pulse width ≤ 10ns).
2. VIL (min) = -1.5V AC (pulse width ≤ 10ns).
3. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V
4. Dout is disabled, 0V ≤ Vout ≤ VDD
PRELIMINARY (November, 2011, Version 0.8)
5
AMIC Technology, Corp.
A43L3616A Series
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
CDC1
CDC2
0.1 + 0.01
0.1 + 0.01
μF
μF
Note: 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C, -40°C to +85°C for industrial temperature range or
-40°C to +85°C for automotive temperature range)
Speed
Symbol
Parameter
Test Conditions
Unit Notes
-6
-7
-75
Operating Current
(One Bank Active)
Burst Length = 1
tRC = tRC(min), tCC = tCC(min), IOL = 0mA
95
85
80
Icc1
mA
mA
1
Precharge Standby
Current in power-down
mode
Icc2 P
CKE = VIL(max), tCC = 10ns
CLK = VIL(max), tCC = ∞
2
Icc2 PS
1.5
CKE = VIH(min), CS = VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2N
15
Precharge Standby
Current in non power-
down mode
mA
CKE = VIH(min), CLK = VIL(max), tCC = ∞
ICC2NS
ICC3N
10
25
20
Input signals are stable.
CKE = VIH(min), CS = VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
mA
mA
Active Standby current
in non power-down
mode (One Bank Active)
CKE = VIH(min), CLK = VIL(max), tCC = ∞
Input signals are stable
ICC3NS
ICC3P
CKE = VIL(max), tcc=10ns
4
2
mA
mA
Active Standby current
in power-down mode
(One Bank Active)
ICC3PS
CKE & CLK = VIL(max), tcc= ∞
Operating Current
(Burst Mode)
IOL = 0mA, Page Bust
All bank Activated, tCCD = tCCD (min)
120
100
90
ICC4
mA
1
2
120
2
110
2
ICC5
ICC6
Refresh Current
tRC = tRC (min)
140
2
mA
mA
Self Refresh Current
CKE = 0.2V
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).
2. Refresh period is 64ms. Addresses are changed only one time during tCC(min).
3. Unless otherwise noted, input swing IeveI is CMOS (VIH /VIL=VDDQ/VSSQ).
PRELIMINARY (November, 2011, Version 0.8)
6
AMIC Technology, Corp.
A43L3616A Series
AC Operating Test Conditions
(VDD = 3.3V ±0.3V, TA = 0°C to +70°C, -40°C to +85°C for industrial temperature range or -40°C to +85°C for automotive
temperature range)
Parameter
Value
AC input levels
VIH/VIL = 2.4V/0.4V
1.4V
Input timing measurement reference level
Input rise and all time (See note3)
Output timing measurement reference level
Output load condition
tr/tf = 1ns/1ns
1.4V
See Fig.2
3.3V
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
VTT =1.4V
1200Ω
50Ω
Output
ZO=50Ω
OUTPUT
50pF
870Ω
50pF
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
AC Characteristics
(AC operating conditions unless otherwise noted)
-6
-7
-75
CAS
Latency
Symbol
tCC
Parameter
Unit
ns
Note
1
Min
6
Max
Min
7
Max
Min
7.5
10
Max
3
2
3
2
3
2
CLK cycle time
1000
1000
1000
10
10
5.4
5.4
5.4
5.4
5.4
6
CLK to valid
Output delay
tSAC
-
-
-
ns
1,2
2
2.5
3
3
3
3
3
tOH
Output data hold time
-
-
-
ns
tCH
tCL
CLK high pulse width
CLK low pulse width
Input setup time
2.5
2.5
1.5
1
-
2.5
2.5
1.5
1
-
2.5
2.5
1.5
1
-
-
ns
ns
ns
ns
ns
3
3
3
3
2
-
-
-
-
2, 3
tSS
-
tSH
tSLZ
Input hold time
-
-
-
CLK to output in Low-Z
1
-
1
-
1
-
3
2
5.4
5.4
5.4
5.4
5.4
6
tSHZ
CLK to output In Hi-Z
-
-
-
ns
-
*All AC parameters are measured from half to half.
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
PRELIMINARY (November, 2011, Version 0.8)
7
AMIC Technology, Corp.
A43L3616A Series
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Symbol
Parameter
Version
Unit
Note
CAS
Latency
-6
-7
-75
tRRD(min)
tRCD(min)
Row active to row active delay
12
14
15
ns
ns
1
1
1
18
20
20
RAS to
delay
CAS
tRP(min)
Row precharge time
18
42
20
45
20
45
ns
ns
tRAS(min)
Row active time
1
1
2,3
tRAS(max)
tRC(min)
100
60
100
63
100
65
μs
Row cycle time
ns
tCDL(min)
tRDL(min)
Last data in new col. Address delay
Last data in row precharge
1
2
1
2
1
2
CLK
CLK
2
2
tCCD(min)
Col. Address to col. Address delay
1
1
1
CLK
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
PRELIMINARY (November, 2011, Version 0.8)
8
AMIC Technology, Corp.
A43L3616A Series
Simplified Truth Table
Command
CKEn-1 CKEn CS RAS
DQM BA0 A10 A9~A0,
BA1 /AP A11
Notes
CAS
L
WE
L
Register
Mode Register Set
Auto Refresh
1,2
H
H
X
L
L
X
X
OP CODE
3
3
3
Refresh
H
L
L
L
L
L
H
H
X
Entry
Self
H
H
Refresh
Exit
L
H
X
X
X
X
H
L
X
L
X
H
X
H
3
4
Bank Active & Row Addr.
H
V
V
Row Addr.
Read &
Column Addr.
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
Column
Addr.
4
H
X
L
H
L
H
X
H
L
4,5
4
Write &
Column
Addr.
H
H
X
X
L
L
H
H
L
L
L
X
X
V
Column Addr.
H
4,5
Reserved
Precharge
H
X
Bank Selection
Both Banks
V
X
L
H
X
L
L
H
L
X
X
H
L
H
X
L
H
X
X
H
X
V
X
X
H
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
Entry
H
L
L
H
L
X
X
X
Clock Suspend or
Active Power Down
X
X
Exit
Entry
H
H
L
Precharge Power Down Mode
Exit
L
H
H
H
X
X
V
X
H
DQM
X
X
6
L
H
X
H
X
No Operation Command
H
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note : 1. OP Code: Operand Code
A0~A11, BA0, BA1: Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.
4. BA0, BA1 : Bank select address.
If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.
If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read write command cannot be issued.
Another bank read write command can be issued at every burst length.
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
PRELIMINARY (November, 2011, Version 0.8)
9
AMIC Technology, Corp.
A43L3616A Series
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address
BA0
BA1
A11
A10/AP
RFU
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
RFU
W.B.L
TM
CAS Latency
BT
Burst Length
(Note 1)
(Note 2)
Test Mode
Type
CAS Latency
A6 A5 A4 Latency
Burst Type
Burst Length
A8 A7
A3
Type
A2 A1 A0
BT=0
BT=1
0
0
1
1
0
1
0
1
Mode Register Set
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
0
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
Vendor
Use
1
2
4
4
Only
3
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Write Burst Length
Length
A9
0
Burst
1
Single Bit
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200μs.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
PRELIMINARY (November, 2011, Version 0.8)
10
AMIC Technology, Corp.
A43L3616A Series
Burst Sequence (Burst Length = 4)
Initial address
Sequential
Interleave
A1
0
A0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
Burst Sequence (Burst Length = 8)
Initial address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
7
1
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
6
7
0
1
2
3
4
0
1
2
3
4
5
6
0
3
2
5
4
7
6
PRELIMINARY (November, 2011, Version 0.8)
11
AMIC Technology, Corp.
A43L3616A Series
Device Operations
Clock (CLK)
command decoder so that
address inputs are ignored.
,
and
, and all the
WE
RAS CAS
Power-Up
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of set up and hold time around positive edge
of the clock for proper functionality and ICC specifications.
The following sequence is recommended for POWER UP
1. Power must be applied to either CKE and DQM inputs to
pull them high and other pins are NOP condition at the
inputs before or along with VDD (and VDDQ) supply.
The clock signal must also be asserted at the same time.
2. After VDD reaches the desired voltage, a minimum pause
of 200 microseconds is required with inputs in NOP
condition.
Clock Enable (CLK)
The clock enable (CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time
same as other inputs), the internal clock is suspended form
the next clock cycle and the state of output and burst address
is frozen as long as the CKE remains low. All other inputs are
ignored from the next clock cycle after CKE goes low. When
both banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power down
mode form the next clock cycle. The SDRAM remains in the
power down mode ignoring the other inputs as long as CKE
remains low. The power down exit is synchronous as the
internal clock is suspended. When CKE goes high at least
“tSS + 1 CLOCK” before the high going edge of the clock, then
the SDRAM becomes active from the same clock edge
accepting all the input commands.
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize the
internal circuitry.
5. Perform a MODE REGISTER SET cycle to program the
CAS latency, burst length and burst type as the default
value of mode register is undefined.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
power-up sequence.
cf.) Sequence of 4 & 5 may be changed.
Mode Register Set (MRS)
The mode register stores the data for controlling the various
operation modes of SDRAM. It programs the CAS latency,
addressing mode, burst length, test mode and various vendor
specific options to make SDRAM useful for variety of different
applications. The default value of the mode register is not
defined, therefore the mode register must be written after
power up to operate the SDRAM. The mode register is
Bank Select (BA0, BA1)
This SDRAM is organized as two independent banks of
4,194,304 words X 8 bits memory arrays. The BA0, BA1
inputs is latched at the time of assertion of
and
CAS
RAS
to select the bank to be used for the operation. The bank
select BA0, BA1 is latched at bank activate, read, write mode
register set and precharge operations.
written by asserting low on
,
,
,
(The
WE
CS RAS CAS
SDRAM should be in active mode with CKE already high
prior to writing the mode register). The state of address pins
A0~A11, BA0 and BA1 in the same cycle as
Address Input (A0 ~ A11)
The 22 address bits required to decode the 4,194,304 word
locations are multiplexed into 12 address input pins
,
,
,
going low is the data written in the
WE
CAS
CS RAS
mode register. One clock cycle is required to complete the
write in the mode register. The mode register contents can
be changed using the same command and clock cycle
requirements during operation as long as both banks are in
the idle state. The mode register is divided into various fields
depending on functionality. The burst length field uses
A0~A2, burst type uses A3, addressing mode uses A4~A6,
A7~A8, A11, BA0 and BA1 are used for vendor specific
options or test mode. And the write burst length is
programmed using A9. A7~A8, A11, BA0 and BA1 must be
set to low for normal SDRAM operation.
(A0~A11). The 12 bit row address is latched along with
,
RAS
BA0 and BA1 during bank activate command. The 9 bit
column address is latched along with
BA1during read or write command.
,
, BA0 and
WE
CAS
NOP and Device Deselect
When
,
and
are high, the SDRAM performs
WE
RAS CAS
no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock like bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is
Refer to table for specific codes for various burst length,
addressing modes and CAS latencies.
entered by asserting
high.
high disables the
CS
CS
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Device Operations (continued)
Bank Activate
Burst Write
The burst write command is similar to burst read command,
and is used to write data into the SDRAM consecutive clock
cycles in adjacent addresses depending on burst length and
The bank activate command is used to select a random row
in an idle bank. By asserting low on
and
with
CS
RAS
desired row and bank addresses, a row access is initiated.
The read or write operation can occur after a time delay of
tRCD(min) from the time of bank activation. tRCD(min) is an
internal timing parameter of SDRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate and
read or write command should be calculated by dividing
tRCD(min) with cycle time of the clock and then rounding off
the result to the next higher integer. The SDRAM has two
internal banks on the same chip and shares part of the
internal circuitry to reduce chip area, therefore it restricts the
activation of both banks immediately. Also the noise
generated during sensing of each bank of SDRAM is high
requiring some time for power supplies recover before the
other bank can be sensed reliably. tRRD(min) specifies the
minimum time required between activating different banks.
The number of clock cycles required between different bank
activation must be calculated similar to tRCD specification. The
minimum time required for the bank to be active to initiate
sensing and restoring the complete row of dynamic cells is
determined by tRAS(min) specification before a precharge
command to that active bank can be asserted. The maximum
time any bank can be in the active state is determined by
tRAS(max). The number of cycles for both tRAS(min) and
tRAS(max) can be calculated similar to tRCD specification.
burst sequence. By asserting low on
,
and
with
WE
CS CAS
valid column address, a write burst is initiated. The data
inputs are provided for the initial address in the same clock
cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though the
internal writing may not have been completed yet. The writing
can not complete to burst length. The burst write can be
terminated by issuing a burst read and DQM for blocking
data inputs or burst write in the same or the other active
bank. The burst stop command is valid only at full page burst
length where the writing continues at the end of burst and the
burst is wrap around. The write burst can also be terminated
by using DQM for blocking data and precharging the bank
“tRDL” after the last data input to be written into the active row.
See DQM OPERATION also.
DQM Operation
The DQM is used to mask input and output operation. It
works similar to
during read operation and inhibits writing
OE
during write operation. The read latency is two cycles from
DQM and zero cycle for write, which means DQM masking
occurs two cycles later in the read cycle and occurs in the
same cycle during write cycle. DQM operation is
synchronous with the clock, therefore the masking occurs for
a complete cycle. The DQM signal is important during burst
interrupts of write with read or precharge in the SDRAM. Due
to asynchronous nature of the internal write, the DQM
operation is critical to avoid unwanted or incomplete writes
when the complete burst write is not required.
Burst Read
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low on
and
with
being high on the positive edge of
WE
CS
CAS
Precharge
the clock. The bank must be active for at least tRCD(min)
before the burst read command is issued. The first output
appears CAS latency number of clock cycles after the issue
of burst read command. The burst length, burst sequence
and latency from the burst read command is determined by
the mode register which is already programmed. The burst
read can be initiated on any column address of the active
row. The address wraps around if the initial address does not
start from a boundary such that number of outputs from each
I/O are equal to the burst length programmed in the mode
register. The output goes into high-impedance at the end of
the burst, unless a new burst read was initiated to keep the
data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or
the other active bank or a precharge command to the same
bank. The burst stop command is valid at every page burst
length.
The precharge operation is performed on an active bank by
asserting low on
,
,
and A10/AP with valid BA
WE
CS RAS
of the bank to be precharged. The precharge command can
be asserted anytime after tRAS(min) is satisfied from the bank
activate command in the desired bank. “tRP” is defined as the
minimum time required to precharge a bank.
The minimum number of clock cycles required to complete
row precharge is calculated by dividing “tRP” with clock cycle
time and rounding up to the next higher integer. Care should
be taken to make sure that burst write is completed or DQM
is used to inhibit writing before precharge command is
asserted. The maximum time any bank can be active is
specified by tRAS(max). Therefore, each bank has to be
precharged within tRAS(max) from the bank activate
command. At the end of precharge, the bank enters the idle
state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when both banks are in idle
state.
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required to complete the auto refresh operation is specified
by “tRC(min)”. The minimum number of clock cycles required
can be calculated by driving “tRC” with clock cycle time and
then rounding up to the next higher integer. The auto refresh
command must be followed by NOP’s until the auto refresh
operation is completed. Both banks will be in the idle state at
the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us or a burst of 4096 auto refresh
cycles once in 64ms.
Device Operations (continued)
Auto Precharge
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy tRAS(min) and “tRP” for the programmed burst length
and CAS latency. The auto precharge command is issued at
the same time as burst read or burst write by asserting high
on A10/AP. If burst read or burst write command is issued
with low on A10/AP, the bank is left active until a new
command is asserted. Once auto precharge command is
given, no new commands are possible to that particular bank
until the bank achieves idle state.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
Four Banks Precharge
Both banks can be precharged at the same time by using
Precharge all command. Asserting low on
,
and
CS RAS
with high on A10/AP after both banks have satisfied
WE
tRAS(min) requirement, performs precharge on both banks. At
the end of tRP after performing precharge all, both banks are
in idle state.
asserting low on
,
,
and CKE with high on
CS RAS CAS
. Once the self refresh mode is entered, only CKE state
WE
being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
Auto Refresh
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP’s
for a minimum time of “tRC” before the SDRAM reaches idle
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to used
burst 4096 auto refresh cycles immediately after exiting self
refresh.
asserting low on
,
and
with high on CKE and
CAS
CS RAS
. The auto refresh command can only be asserted with
both banks being in idle state and the device is not in power
down mode (CKE is high in the previous cycle). The time
WE
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Basic feature And Function Descriptions
1. CLOCK Suspend
1 ) C lic k S u s p e n d e d D u rin g W rite (B L = 4 )
2 ) C lo c k S u s p e n d e d D u rin g R e a d (B L = 4 )
C L K
C M
D
W
R
R D
C K E
M
a s k e d b y C K E
M
a s k e d b y C K E
In te rn a l
C L K
D Q (C L 2 )
D Q (C L 3 )
D 0
D 0
D 1
D 1
D 2
D 2
D 3
D 3
Q 0
Q 1
Q 0
Q 2
Q 1
Q 3
Q 2
Q 3
N o t
W
ritte n
S u s p e n d e d D o u t
N o te : C L K to C L K d is a b le /e n a b le = 1 c lo c k
2. DQM Operation
2) Read Mask (BL=4)
1) Write Mask (BL=4)
CLK
CMD
WR
RD
DQM
Masked by CKE
D3
Masked by CKE
Q1
Hi-Z
Hi-Z
DQ(CL2)
DQ(CL3)
D0
D0
D1
D1
Q0
Q3
Q2
D3
Q1
Q3
DQM to Data-in Mask = 0CLK
DQM to Data-out Mask = 2
2) Read Mask (BL=4)
CLK
CMD
CKE
RD
DQM
Hi-Z
Hi-Z
Hi-Z
Q4
Hi-Z
Hi-Z
Q0
Q2
Q1
Q6
Q5
Q7
Q6
Q8
Q7
DQ(CL2)
DQ(CL3)
Hi-Z
Q3
* Note : 1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.
2. DQM masks both data-in and data-out.
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3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4)Note 1
CLK
CMD
RD
A
RD
B
ADD
DQ(CL2)
DQ(CL3)
QA0 QB0 QB1 QB2 QB3
QA0 QB0 QB1 QB2 QB3
t
CCD
Note2
2) Write interrupted by Write (BL =2)
3) Write interrupted by Read (BL =2)
CLK
WR WR
WR
RD
CMD
t
CCD
tCCD
Note2
Note2
ADD
DQ
A
B
A
B
DA0 DB0 DB1
DQ(CL2)
DQ(CL3)
DA0
QB0 QB1
QB0 QB1
t
CDL
Note3
DA0
t
CDL
Note3
Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.
By “ Interrupt”, to stop burst read/write by access; read, write and block write.
CAS
2. tCCD :
CAS
to
delay. (=1CLK)
CAS
CAS
3. tCDL : Last data in to new column address delay. (= 1CLK).
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4. CAS Interrupt (II) : Read Interrupted Write & DQM
(1) CL=2, BL=4
CLK
i) CMD
RD
RD
WR
D0
DQM
DQ
ii) CMD
D1
D2
D3
D2
WR
DQM
DQ
Hi-Z
D0
D1
D3
D2
D1
RD
RD
WR
iii) CMD
DQM
DQ
Hi-Z
D0
D1
D3
D2
iv) CMD
WR
DQM
DQ
Hi-Z
Note 1
Q0
D0
D3
(2) CL=3, BL=4
CLK
i) CMD
DQM
RD
RD
RD
RD
WR
D0
DQ
D1
D2
D3
D2
ii) CMD
WR
DQM
DQ
D0
D1
D3
D2
iii) CMD
WR
DQM
DQ
D0
D1
D3
D2
D1
iv) CMD
WR
DQM
DQ
Hi-Z
D0
D1
D3
D2
v) CMD
RD
WR
DQM
DQ
Hi-Z
Q0
D0
D3
Note 2
* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.
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5. Write Interrupted by Precharge & DQM
CLK
Note 2
Note 1
CMD
WR
D0
PRE
D3
DQM
DQ
D1
D2
Masked by DQM
Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual banks operation.
6. Precharge
1 ) N o rm a l W rite (B L = 4 )
C L K
C M D
D Q
W R
D 0
P R E
D 1
D 2
D 3
tR D L
2 ) R e a d (B L = 4 )
C L K
C M D
R D
P R E
Q 2
D Q (C L 2 )
Q 0
Q 1
Q 0
Q 3
Q 2
D Q (C L 3 )
Q 1
Q 3
7. Auto Precharge
1) Norm al W rite (BL=4)
CLK
CM D
DQ
W R
D0
D1
D2
D3
Note 1
Auto Precharge Starts
2) Read (BL=4)
CLK
CM D
RD
DQ(CL2)
DQ(CL3)
Q0
Q1
Q0
Q2
Q1
Q3
Q2
Q3
Note 1
Auto Precharge Starts
* Note : 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other active bank can be issued from this point.
At burst read/write with auto precharge,
interrupt of the same/another bank is illegal.
CAS
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8. MRS
Mode Register Set
CLK
Note 1
PRE
MRS
ACT
CMD
t
RP
2CLK
Note : 1. PRE : Both banks precharge if necessary.
MRS can be issued only at all bank precharge state.
9. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
CLK
2) Power Down (=Precharge Power Down) Exit
CLK
CKE
CKE
t
SS
t
SS
Note 2
Note 1
Internal
CLK
Internal
CLK
NOP
ACT
RD
CMD
CMD
10. Auto Refresh & Self Refresh
Note 3
1) Auto Refresh
CLK
Note 4
Note 5
CKE
PRE
Internal
CLK
AR
CMD
CMD
t
RP
tRC
Note 6
2) Self Refresh
CLK
Note 4
CMD
CKE
PRE
SR
CMD
t
RP
tRC
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* Note : 1. Active power down : one or more bank active state.
2. Precharge power down : both bank precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended.
11. About Burst Type Control
At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
Sequential counting
Interleave counting
Basic
MODE
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
Random
MODE
Random column Access
tCCD = 1 CLK
That is similar to Extended Data Out (EDO) Operation of convention DRAM.
12. About Burst Length Control
At MRS A2,1,0 = “000”.
1
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “001”.
Basic
MODE
2
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “010”
4
8
At MRS A2,1,0 = “011”.
At MRS A9=”1”.
Special
MODE
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
tRDL=1 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively
BRSW
Interrupt
RAS
(Interrupted by Precharge)
During read/write burst with auto precharge,
interrupt cannot be issued.
RAS
Interrupt
MODE
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
Interrupt
CAS
During read/write burst with auto precharge,
interrupt can not be issued.
CAS
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Power On Sequence & Auto Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
High level is necessary
tRP
tRC
RAS
CAS
ADDR
KEY
Ra
BA0, BA1
A10/AP
KEY
KEY
BA
Ra
WE
DQM
DQ
High level is necessary
High-Z
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Mode Regiser Set
Row Active
(A-Bank)
: Don't care
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Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
tCL
tCC
High
tRAS
tRC
tSH
*Note 1
CS
tSS
tRCD
tRP
tSH
RAS
tSS
tCCD
tSH
CAS
ADDR
tSS
tSH
tSS
Ra
Ca
Cb
Cc
Rb
tSS
tSH
*Note 2,3
*Note 2,3
*Note 2,3 *Note 4
*Note 2
*Note 2
BA0, BA1
A10/AP
BA
BA
BA
BA
BA
BA
*Note 3
*Note 3
*Note 3 *Note 4
Ra
Rb
tSH
WE
tSS
tSS
tSH
tSH
DQM
DQ
tRAC
tSAC
tSLZ
Qa
Db
Qc
tSS
tOH
tSHZ
Read
Write
Row Active
Read
Row Active
Precharge
: Don't care
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* Note : 1. All inputs can be don’t care when
is high at the CLK high going edge.
CS
2. Bank active & read/write are controlled by BA0, BA1.
BA1
BA0
Active & Read/Write
Bank A
0
0
1
1
0
1
0
1
Bank B
Bank C
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP BA1
BA0
0
Operation
0
0
Disable auto precharge, leave bank A active at end of burst.
Disable auto precharge, leave bank B active at end of burst.
Disable auto precharge, leave bank C active at end of burst.
Disable auto precharge, leave bank D active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
Enable auto precharge, precharge bank C at end of burst.
Enable auto precharge, precharge bank D at end of burst.
1
0
1
0
1
0
0
1
0
1
1
1
0
1
1
4. A10/AP and BA0, BA1 control bank precharge when precharge command is asserted.
A10/AP
BA1
0
BA0
0
Precharge
Bank A
0
0
0
0
1
0
1
Bank B
1
0
Bank C
1
1
Bank D
X
X
All Banks
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Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
*Note 1
tRC
CS
tRCD
RAS
CAS
*Note 2
ADDR
Ra
Ca0
Rb
Cb0
BA0
BA1
A10/AP
WE
Ra
Rb
DQM
tOH
Qa0
DQ
(CL = 2)
Qa1
Qa2
Qa3
Db0
Db0
Db1
Db2
Db3
tRAC
*Note 4
tRDL
tSAC
tSHZ
*Note 3
tOH
DQ
(CL = 3)
Qa0
Qa1
Qa2
Qa3
Db1
Db2
Db3
tRAC
*Note 4
tRDL
tSHZ
tSAC
*Note 3
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after tSHZ from the clock.
3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
PRELIMINARY (November, 2011, Version 0.8)
24
AMIC Technology, Corp.
A43L3616A Series
Page Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
tRCD
RAS
CAS
*Note 2
ADDR
BA0
Ra
Ca0
Cb0
Cc0
Cd0
BA1
A10/AP
WE
Ra
tRDL
tCDL
*Note 2
*Note1
*Note3
DQM
DQ
(CL=2)
Qa0
Qa1
Qb0
Qa1
Qb1
Qb0
Dc0
Dc1
Dd0
Dd0
Dd1
DQ
(CL=3)
Qa0
Dc0
Dc1
Dd1
Row Active
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
PRELIMINARY (November, 2011, Version 0.8)
25
AMIC Technology, Corp.
A43L3616A Series
Page Read Cycle at Different Bank @Burst Length = 4
* Note : 1.
can be don’t care when
, and
RAS CAS
are high at the clock high going edge.
WE
CS
2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.
PRELIMINARY (November, 2011, Version 0.8)
26
AMIC Technology, Corp.
A43L3616A Series
Page Write Cycle at Different Bank @Burst Length=4
* Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.
PRELIMINARY (November, 2011, Version 0.8)
27
AMIC Technology, Corp.
A43L3616A Series
Read & Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
RAa
CAa
RBb
CBb
RAc
CAc
ADDR
BA0
BA1
A10/AP
RAa
RBb
RAc
tCDL
*Note 1
WE
DQM
DQ
(CL=2)
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
QAc0 QAc1
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(D-Bank)
Read
(B-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: Don't care
* Note : tCDL should be met to complete write.
PRELIMINARY (November, 2011, Version 0.8)
28
AMIC Technology, Corp.
A43L3616A Series
Read & Write Cycle with Auto Precharge @Burst Length=4
*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode)
PRELIMINARY (November, 2011, Version 0.8)
29
AMIC Technology, Corp.
A43L3616A Series
Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4
* Note : DQM needed to prevent bus contention.
PRELIMINARY (November, 2011, Version 0.8)
30
AMIC Technology, Corp.
A43L3616A Series
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
* Note 2
tSS
tSS
tSS
tSS
* Note 1
*Note 3
CS
RAS
CAS
Ra
Ca
ADDR
BA0
BA1
A10/AP
WE
Ra
DQM
DQ
Qa0
Qa1
Qa2
Precharge
Power-down
Exit
Precharge
Power-
down
Read
Precharge
Row Active
Entry
Active
Power-
down
Exit
Active
Power-down
Entry
: Don't care
* Note : 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least “1CLK + tSS” prior to Row active command.
3. Cannot violate minimum refresh specification. (64ms)
PRELIMINARY (November, 2011, Version 0.8)
31
AMIC Technology, Corp.
A43L3616A Series
Self Refresh Entry & Exit Cycle
* Note : TO ENTER SELF REFRESH MODE
1. with CKE should be low at the same clock cycle.
CS RAS CAS
,
&
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5.
starts from high.
CS
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.
If the system uses burst refresh.
PRELIMINARY (November, 2011, Version 0.8)
32
AMIC Technology, Corp.
A43L3616A Series
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
CLOCK
CKE
High
High
*Note 2
CS
tRC
RAS
CAS
* Note 1
* Note 3
Key
Ra
ADDR
WE
DQM
DQ
Hi-Z
Hi-Z
MRS
Auto Refresh
New Command
: Don't care
New
Command
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
* Note : 1.
,
,
&
activation at the same clock cycle with address key will set internal
WE
CS RAS CAS
mode register.
2. Minimum 2 clock cycles should be met before new
3. Please refer to Mode Register Set table.
activation.
RAS
PRELIMINARY (November, 2011, Version 0.8)
33
AMIC Technology, Corp.
A43L3616A Series
Function Truth Table (Table 1)
Current
CS RAS
BA
Address
Action
Note
CAS
WE
State
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
NOP
NOP
X
ILLEGAL
2
2
X
H
L
BA
BA
BA
X
CA, A10/AP ILLEGAL
IDLE
H
H
L
RA
Row Active; Latch Row Address
L
PA
NOP
4
5
5
L
H
L
X
Auto Refresh or Self Refresh
L
L
OP Code
Mode Register Access
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
NOP
NOP
Row
X
ILLEGAL
2
Active
H
L
BA
BA
BA
BA
X
CA,A10/AP Begin Read; Latch CA; Determine AP
CA,A10/AP Begin Write; Latch CA; Determine AP
L
H
H
L
H
L
RA
PA
X
ILLEGAL
2
L
Precharge
L
X
X
H
L
ILLEGAL
X
H
H
H
H
L
X
H
H
L
X
X
NOP(Continue Burst to End →Row Active)
NOP(Continue Burst to End →Row Active)
Term burst →Row Active
X
X
X
X
H
L
BA
BA
BA
BA
X
CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
3
3
2
3
Read
L
CA,AP
Term burst; Begin Write; Latch CA; Determine AP
ILLEGAL
H
H
L
H
L
RA
PA
X
L
Term Burst; Precharge timing for Reads
ILLEGAL
L
X
X
H
L
X
H
H
H
H
L
X
H
H
L
X
X
NOP(Continue Burst to End→Row Active)
NOP(Continue Burst to End→Row Active)
ILLEGAL
X
X
X
X
H
L
BA
BA
BA
BA
X
CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
3
3
2
3
Write
L
H
H
L
H
L
RA
ILLEGAL
L
A10/AP
Term Burst; Precharge timing for Writes
ILLEGAL
L
X
X
H
L
X
X
X
X
X
H
H
H
H
L
X
H
H
L
X
NOP(Continue Burst to End→Precharge)
NOP(Continue Burst to End→Precharge)
ILLEGAL
X
Read with
Auto
Precharge
X
H
L
BA
BA
BA
X
CA,A10/AP ILLEGAL
CA,A10/AP ILLEGAL
2
2
L
H
L
X
X
RA, PA
X
ILLEGAL
ILLEGAL
L
2
PRELIMINARY (November, 2011, Version 0.8)
34
AMIC Technology, Corp.
A43L3616A Series
Function Truth Table (Table 1, Continued)
Current
CS RAS
BA
Address
Action
Note
CAS
WE
State
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
NOP(Continue Burst to End→Precharge)
NOP(Continue Burst to End→Precharge)
ILLEGAL
Write with
Auto
X
H
L
BA
BA
BA
X
CA,A10/AP ILLEGAL
CA,A10/AP ILLEGAL
2
2
Precharge
L
H
L
X
X
X
H
L
RA, PA
ILLEGAL
L
X
X
X
X
ILLEGAL
2
X
H
H
H
L
X
H
H
L
X
NOP→Idle after tRP
NOP→Idle after tRP
ILLEGAL
X
X
Precharge
X
H
L
BA
BA
BA
X
CA,A10/AP ILLEGAL
2
2
2
4
H
H
L
RA
PA
X
ILLEGAL
L
NOP→Idle after tRP
ILLEGAL
L
X
X
H
L
X
H
H
H
L
X
H
H
L
X
X
NOP→Row Active after tRCD
NOP→Row Active after tRCD
ILLEGAL
X
X
X
X
Row
Activating
X
H
L
BA
BA
BA
X
CA,A10/AP ILLEGAL
2
2
2
2
H
H
L
RA
PA
X
ILLEGAL
L
ILLEGAL
L
X
X
X
X
X
X
ILLEGAL
X
H
H
L
X
H
L
X
X
NOP→Idle after tRC
NOP→Idle after tRC
ILLEGAL
X
X
Refreshing
X
X
H
L
X
X
ILLEGAL
L
X
X
ILLEGAL
Abbreviations
RA = Row Address
NOP = No Operation Command
BA = Bank Address
AP = Auto Precharge
PA = Precharge All
CA = Column Address
Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle.
2. Illegal to bank in specified state: Function may be legal in the bank indicated by BA, depending on the state of that
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).
5. Illegal if any banks is not idle.
PRELIMINARY (November, 2011, Version 0.8)
35
AMIC Technology, Corp.
A43L3616A Series
Function Truth Table for CKE (Table 2)
Current
State
CKE CKE
CS
RAS
Address
Action
Note
CAS
WE
n-1
n
H
X
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
L
L
H
H
H
H
H
L
6
6
Exit Self Refresh→ABI after tRC
Exit Self Refresh→ABI after tRC
ILLEGAL
Self
L
L
Refresh
L
L
X
X
X
X
X
H
L
ILLEGAL
L
L
X
X
X
X
H
H
L
ILLEGAL
L
X
X
H
L
X
X
X
H
H
H
L
NOP(Maintain Self Refresh)
INVALID
H
L
X
H
H
H
H
H
L
7
7
Exit Power Down→ABI
Exit Power Down→ABI
ILLEGAL
Both
Bank
Precharge
Power
L
L
L
L
L
X
X
X
X
X
H
L
ILLEGAL
Down
L
L
X
X
X
X
H
H
L
ILLEGAL
L
X
X
H
L
X
X
X
H
H
H
L
NOP(Maintain Power Down Mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
H
H
H
H
H
H
H
H
L
H
L
8
8
L
All
Banks
Idle
L
L
L
L
X
X
H
L
ILLEGAL
L
L
H
L
ILLEGAL
L
L
L
Enter Self Refresh
ILLEGAL
8
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP
H
H
L
H
L
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain clock Suspend
Any State
Other than
Listed
9
9
H
L
Above
L
Abbreviations : ABI = All Banks Idle
Note: 6. After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low to
high transition to issue a new command.
7. CKE low to high transition is asynchronous as if restarts internal clock.
A minimum setup time “tSS + one clock” must be satisfied before any command other than exit.
8. Power-down and self refresh can be entered only from the all banks idle state.
9. Must be a legal command.
PRELIMINARY (November, 2011, Version 0.8)
36
AMIC Technology, Corp.
A43L3616A Series
Part Numbering Scheme
X XX
A43
X X X X X X
XX
Package Material
Blank: normal
F: PB free
Temperature
Blank : 0°C ~ 70°C
U:-40°C ~ 85°C Industrial grade
Automative grade
A:-40°C ~ 85°C
Speed
95: 105 MHz
75: 133 MHz
7: 143 MHz
6: 166 MHz
55: 183 MHz
5: 200 MHz
Package Type
V: TSOP
G: CSP
Device Version*
Mobile Function*
I/O Width
08: 8 I/O
16: 16 I/O
32: 32 I/O
Device Density
06: 1M
16: 2M
26: 4M
36: 8M
46: 16M
56: 32M
83: 256K
Operating Vcc
L: 3V~3.6V
P: 2.3V~2.7V
E: 1.7V~2.0V
Device Type
A43: AMIC SDRAM
* Optional
PRELIMINARY (November, 2011, Version 0.8)
37
AMIC Technology, Corp.
A43L3616A Series
Ordering Information
Part No.
Cycle Time (ns)
Clock Frequency (MHz)
166 @ CL = 3
100 @ CL = 2
166 @ CL = 3
100 @ CL = 2
166 @ CL = 3
100 @ CL = 2
166 @ CL = 3
100 @ CL = 2
143 @ CL = 3
100 @ CL = 2
143 @ CL = 3
100 @ CL = 2
143 @ CL = 3
100 @ CL = 2
143 @ CL = 3
100 @ CL = 2
143 @ CL = 3
100 @ CL = 2
143 @ CL = 3
100 @ CL = 2
133 @ CL = 3
100 @ CL = 2
133 @ CL = 3
100 @ CL = 2
133 @ CL = 3
100 @ CL = 2
133 @ CL = 3
100 @ CL = 2
Access Time
5.4 ns @ CL = 3
5.4 ns @ CL = 2
5.4 ns @ CL = 3
5.4 ns @ CL = 2
5.4 ns @ CL = 3
5.4 ns @ CL = 2
5.4 ns @ CL = 3
5.4 ns @ CL = 2
5.4 ns @ CL = 3
5.4 ns @ CL = 2
5.4 ns @ CL = 3
5.4 ns @ CL = 2
5.4 ns @ CL = 3
5.4 ns @ CL = 2
5.4 ns @ CL = 3
5.4 ns @ CL = 2
5.4 ns @ CL = 3
5.4 ns @ CL = 2
5.4 ns @ CL = 3
5.4 ns @ CL = 2
5.4 ns @ CL = 3
6 ns @ CL = 2
Package
54 TSOP (II)
(Pb-Free)
A43L3616AV -6F
A43L3616AV -6UF
A43L3616AG -6F
A43L3616AG -6UF
A43L3616AV -7F
A43L3616AV -7UF
A43L3616AV -7AF
A43L3616AG -7F
A43L3616AG -7UF
A43L3616AG -7AF
A43L3616AV -75F
A43L3616AV -75UF
A43L3616AG -75F
A43L3616AG -75UF
54 TSOP (II)
(Pb-Free)
6
54B Pb-Free CSP
54B Pb-Free CSP
54 TSOP (II)
(Pb-Free)
54 TSOP (II)
(Pb-Free)
54 TSOP (II)
(Pb-Free)
7
54B Pb-Free CSP
54B Pb-Free CSP
54B Pb-Free CSP
54 TSOP (II)
(Pb-Free)
5.4 ns @ CL = 3
6 ns @ CL = 2
54 TSOP (II)
(Pb-Free)
7.5
5.4 ns @ CL = 3
6 ns @ CL = 2
54B Pb-Free CSP
54B Pb-Free CSP
5.4 ns @ CL = 3
6 ns @ CL = 2
Note: -U is for industrial operating temperature range -40ºC to +85ºC.
-A is for automotive operating temperature range -40ºC to +85ºC.
PRELIMINARY (November, 2011, Version 0.8)
38
AMIC Technology, Corp.
A43L3616A Series
Package Information
54 Balls CSP (8 x 8 mm) Outline Dimensions
unit: mm
8.00 ± 0.10
0.40 ± 0.05
PRELIMINARY (November, 2011, Version 0.8)
39
AMIC Technology, Corp.
A43L3616A Series
Package Information
TSOP 54 (Type II) Outline Dimensions
unit: inches/mm
Detail "A"
R1
54
28
0.21 REF
R2
0.665 REF
θ
L
L
1
1
27
D
Detail "A"
S
-C-
e
b
0.1
Seating Plane
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
Min
-
Nom
Max
1.20
0.15
1.05
0.45
0.21
A
A1
A2
b
-
0.047
0.006
0.041
0.018
0.008
-
0.002
0.037
0.012
0.005
0.004
0.05
0.95
0.30
0.12
-
0.039
1.00
-
-
c
-
-
D
0.875 BSC
0.028 REF
0.463 BSC
0.400 BSC
0.031 BSC
0.020
22.22 BSC
0.71 REF
11.76 BSC
10.16 BSC
0.80 BSC
0.50
S
E
E1
e
L
0.016
0.024
0.40
0.60
L1
R1
R2
θ
0.031 REF
-
0.80 REF
-
0.005
0.005
0°
-
0.12
0.12
0°
-
-
0.010
8°
-
0.25
8°
-
-
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY (November, 2011, Version 0.8)
40
AMIC Technology, Corp.
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