A29L320UV-70U [AMICC]
4M X 8 Bit / 2M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory; 4M ×8位/ 2M x 16位的CMOS 3.3伏只,引导扇区闪存型号: | A29L320UV-70U |
厂家: | AMIC TECHNOLOGY |
描述: | 4M X 8 Bit / 2M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory |
文件: | 总44页 (文件大小:589K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
A29L320 Series
4M X 8 Bit / 2M X 16 Bit CMOS 3.3 Volt-only,
Boot Sector Flash Memory
Preliminary
Document Title
4M X 8 Bit / 2M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
September 21, 2005
Preliminary
PRELIMINARY (September, 2005, Version 0.0)
AMIC Technology, Corp.
A29L320 Series
4M X 8 Bit / 2M X 16 Bit CMOS 3.3 Volt-only,
Boot Sector Flash Memory
Preliminary
Features
ꢀSingle power supply operation
ꢀCFI (Common Flash Interface) compliant
- Regulated voltage range: 3.0 to 3.6 volt read and write
operations for compatibility with high performance 3.3
volt microprocessors
- Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices
ꢀAccess times:
ꢀCompatible with JEDEC-standards
- 70/90 (max.)
ꢀCurrent:
- Pinout and software compatible with single-power-supply
Flash memory standard
- 9 mA typical active read current
- Superior inadvertent write protection
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
ꢀFlexible sector architecture
ꢀ
Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
Data
ꢀReady /
pin (RY /
)
BY
BUSY
- Eight 8 Kbyte sectors
- Sixty-three 64 kbyte sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
- Provides a hardware method of detecting completion of
program or erase operations (not available on 44-pin
SOP)
ꢀErase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that
sector. Temporary Sector Unprotect feature allows code
changes in previously locked sectors
ꢀUnlock Bypass Program Command
- Reduces overall programming time when issuing
multiple program command sequence
ꢀTop or bottom boot block configurations available
ꢀEmbedded Algorithms
ꢀHardware reset pin (
)
RESET
- Hardware method to reset the device to reading array
data
ꢀ
/ACC input pin
WP
- Write protect (
protect status
) function allows protection of sector
WP
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
Embedded Program algorithm automatically writes and
verifies data at specified addresses
- Acceleration (ACC) function provides accelerated
program times
ꢀPackage options
-
- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
ꢀTypical 10,000 program/erase cycles per sector
ꢀ20-year data retention at 125°C
- Reliable operation for the life of the system
General Description
of 70 and 90ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
The A29L320 is a 32Mbit, 3.3 volt-only Flash memory
organized as 2,097,152 words of 16 bits or 4,194,304 bytes
of 8 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16
bits of data appear on I/O0~I/O15. The A29L320 is offered in
48-ball FBGA, 44-pin SOP and 48-Pin TSOP packages. This
device is designed to be programmed in-system with the
standard system 3.3 volt VCC supply. Additional 12.0 volt
VPP is not required for in-system write or erase operations.
However, the A29L320 can also be programmed in standard
EPROM programmers.
The A29L320 has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29L320 has a second toggle bit, I/O2, to indicate whether
the addressed sector is being selected for erase. The
A29L320 also offers the ability to program in the Erase
Suspend mode. The standard A29L320 offers access times
device has separate chip enable (
), write enable (
)
WE
CE
and output enable (
) controls.
OE
The device requires only a single 3.3 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29L320 is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
PRELIMINARY
(September, 2005, Version 0.0)
1
AMIC Technology, Corp.
A29L320 Series
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
contents of other sectors. The A29L320 is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
algorithm
-
an internal algorithm that automatically
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.
The hardware
pin terminates any operation in
RESET
progress and resets the internal state machine to reading
array data. The pin may be tied to the system reset
RESET
The host system can detect whether a program or erase
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
operation is complete by observing the RY /
pin, or by
BY
reading the I/O7 (
Polling) and I/O6 (toggle) status bits.
Data
After a program or erase cycle has been completed, the
device is ready to read array data or accept another
command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
Pin Configurations
ꢀTSOP (I)
A15
A14
A13
A12
A11
A10
A9
A8
A20
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
A16
BYTE
VSS
I/O15(A-1)
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
9
10
11
12
13
14
15
16
17
18
19
WE
RESET
NC
WP/ACC
RY/BY
A18
A29L320V
A17
A7
A6
A5
A4
A3
A2
A1
20
21
22
23
24
29
28
27
26
25
I/O0
OE
VSS
CE
A0
PRELIMINARY
(September, 2005, Version 0.0)
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AMIC Technology, Corp.
A29L320 Series
Pin Configurations (continued)
ꢀTFBGA
TFBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
BYTE
I/O15(A-1) VSS
G5
A5
B5
C5
D5
E5
F5
H5
A9
A8
A10
A11
I/O7
I/O14
I/O13
I/O6
A4
B4
C4
D4
E4
F4
G4
H4
WE
RESET
B3
NC
A19
I/O5
I/O12
VCC
I/O4
A3
C3
D3
E3
F3
G3
H3
RY/BY
WP/ACC A18
A20
I/O2
I/O10
I/O11
I/O3
A2
B2
C2
A6
D2
A5
E2
F2
G2
H2
A7
A17
I/O0
I/O8
I/O9
I/O1
A1
B1
C1
A2
D1
A1
E1
F1
G1
H1
A3
A4
A0
CE
OE
VSS
PRELIMINARY
(September, 2005, Version 0.0)
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AMIC Technology, Corp.
A29L320 Series
Block Diagram
RY/BY
I/O0 - I/O15 (A-1)
VCC
VSS
Sector Switches
Input/Output
Buffers
Erase Voltage
Generator
RESET
State
Control
WE
BYTE
PGM Voltage
Generator
Command
Register
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
A0-A20
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
A0 – A20
I/O0 - I/O14
Description
Address Inputs
Data Inputs/Outputs
Data Input/Output, Word Mode
I/O15
I/O15 (A-1)
A-1
LSB Address Input, Byte Mode
Chip Enable
CE
WE
Write Enable
Output Enable
OE
Hardware Reset
RESET
BYTE
Selects Byte Mode or Word Mode
Ready/
- Output
BUSY
RY/
BY
VSS
Ground
VCC
NC
Power Supply
Pin not connected internally
PRELIMINARY
(September, 2005, Version 0.0)
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AMIC Technology, Corp.
A29L320 Series
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended periods
may affect device reliability.
Storage Temperature Plastic Packages. . . -65°C to + 150°C
Ambient Temperature with Power Applied. -55°C to + 125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . ……. . -0.5V to +4.0V
A9,
&
(Note 2) . . . . . . . . . . . …. -0.5 to +12.5V
RESET
OE
All other pins (Note 1) . . . . . . . . . . …. . -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . …. . 200mA
Notes:
Operating Ranges
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC +0.5V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0V
for periods up to 20ns.
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . ….. . . 0°C to +70°C
Extended Range Devices
Ambient Temperature (TA)
For –I series. . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
For –U series . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
2. Minimum DC input voltage on A9,
and
is
-
OE
RESET
and
0.5V. During voltage transitions, A9,
OE
RESET
may overshoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may
overshoot to 14.0V for periods up to 20ns.
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . . …...+3.0V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
Table 1. A29L320 Device Bus Operations
Operation
A0 - A20
(Note 1)
I/O0 - I/O7
I/O8 - I/O15
=VIH
/
WE
WP
ACC
CE
OE
RESET
=VIL
BYTE
BYTE
I/O8~I/O14=High-Z
Read
Write
Accelerated
Program
Standby
L
L
L
L
H
H
H
L
L
H
H
H
L/H
(Note 3)
VHH
AIN
AIN
AIN
DOUT
DOUT
I/O15=A-1
(Note 4)
(Note 4)
(Note 4)
(Note 4)
High-Z
High-Z
X
X
H
X
High-Z
High-Z
VCC ±
0.3 V
VCC ±
0.3 V
Output Disable
Reset
L
X
L
H
X
H
H
X
L
H
X
L
L/H
L/H
X
X
High-Z
High-Z
High-Z
High-Z
X
High-Z
High-Z
Sector Protect
(Note 2)
Sector Unprotect
(Note 2)
Temporary Sector
Unprotect
L/H
Sector Address,
A6=L, A1=H, A0=L
(Note 4)
X
X
Sector Address,
A6=H, A1=H, A0=L
L
H
X
L
L
(Note 3)
(Note 3)
(Note 4)
(Note 4)
X
X
X
X
AIN
(Note 4)
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Notes:
1. Addresses are A20:A0 in word mode (
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector
Block Protection and Unprotection”.
=VIH), A20: A in byte mode (
=VIL).
BYTE
BYTE
-1
3. If
/ACC=VIL, the two outermost boot sectors remain protected. If
/ACC=VIH, the two outermost boot
WP
WP
sector protection depends on whether they were last protected or unprotected using the method described in
“Sector/Sector Block Protection and Unprotection. If /ACC = VHH, all sectors are unprotected.
WP
4. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
PRELIMINARY
(September, 2005, Version 0.0)
5
AMIC Technology, Corp.
A29L320 Series
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Word/Byte Configuration
The
pin determines whether the I/O pins I/O15-I/O0
BYTE
Program and Erase Operation Status
operate in the byte or word configuration. If the
pin is
BYTE
set at logic ”1”, the device is in word configuration, I/O15-I/O0
are active and controlled by and
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section for
timing diagrams.
.
OE
CE
If the
pin is set at logic “0”, the device is in byte
BYTE
configuration, and only I/O0-I/O7 are active and controlled by
and . I/O8-I/O14 are tri-stated, and I/O15 pin is used
CE
OE
as an input for the LSB(A-1) address function.
Standby Mode
Requirements for Reading Array Data
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
To read array data from the outputs, the system must drive
the
and
pins to VIL.
is the power control and
CE
OE
CE
placed in the high impedance state, independent of the
input.
OE
selects the device.
is the output control and gates array
OE
data to the output pins.
should remain at VIH all the time
WE
during read operation. The
The device enters the CMOS standby mode when the
&
CE
pin determines whether
BYTE
pins are both held at VCC ± 0.3V. (Note that this is a
RESET
more restricted voltage range than VIH.) If
the device outputs array data in words and bytes. The
internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device
remains enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
and
CE
RESET
are held at VIH, but not within VCC ± 0.3V, the device will be
in the standby mode, but the standby current will be greater.
The device requires the standard access time (tCE) before it
is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 and ICC4 in the DC Characteristics tables represent the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
Writing Commands/Command Sequences
sleep mode is independent of the
,
and
control
OE
WE
CE
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC4 in the
DC Characteristics table represents the automatic sleep
mode current specification.
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive
and
to VIL, and
CE
WE
to VIH. For program operations, the
pin
BYTE
OE
determines whether the device accepts program data in
bytes or words, Refer to “Word/Byte Configuration” for more
information. The device features an Unlock Bypass mode to
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “
Output Disable Mode
When the
input is at VIH, output from the device is
OE
disabled. The output pins are placed in the high impedance
state.
Word / Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequence. An erase
operation can erase one sector, multiple sectors, or the
entire device. The Sector Address Tables indicate the
address range that each sector occupies. A "sector address"
consists of the address inputs required to uniquely select a
sector. See the "Command Definitions" section for details on
erasing a sector or the entire chip, or suspending/resuming
the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
: Hardware Reset Pin
RESET
The
pin provides a hardware method of resetting
RESET
the device to reading array data. When the system drives the
pin low for at least a period of tRP, the device
RESET
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the
pulse. The device also resets the
RESET
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the
pulse.
RESET
When
is held at VSS ± 0.3V, the device draws
RESET
CMOS standby current (ICC4 ). If
within VSS ± 0.3V, the standby current will be greater.
is held at VIL but not
RESET
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
PRELIMINARY
(September, 2005, Version 0.0)
6
AMIC Technology, Corp.
A29L320 Series
The
pin may be tied to the system reset circuitry. A
RY/
to determine whether the reset operation is
BY
complete. If
RESET
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
is asserted when a program or erase
RESET
operation is not executing (RY/
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after
pin is “1”), the reset
BY
If
is asserted during a program or erase operation,
pin remains a “0” (busy) until the internal reset
RESET
the RY/
the
pin return to VIH.
RESET
BY
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor
Refer to the AC Characteristics tables for
parameters and diagram.
RESET
Table 2. A29L320 Top Boot Block Sector Address Table
Sector Size
Address Range (in hexadecimal)
Sector
A20-A12
Byte Mode (x8)
000000 - 00FFFF
010000 - 01FFFF
020000 - 02FFFF
030000 - 03FFFF
040000 - 04FFFF
050000 - 05FFFF
060000 - 06FFFF
070000 - 07FFFF
080000 - 08FFFF
090000 - 09FFFF
0A0000 - 0AFFFF
0B0000 - 0BFFFF
0C0000 - 0CFFFF
0D0000 - 0DFFFF
0E0000 - 0EFFFF
0F0000 - 0FFFFF
100000 - 10FFFF
110000 - 11FFFF
120000 - 12FFFF
130000 - 13FFFF
140000 - 14FFFF
150000 - 15FFFF
160000 - 16FFFF
170000 - 17FFFF
180000 - 18FFFF
190000 - 19FFFF
1A0000 - 1AFFFF
1B0000 - 1BFFFF
1C0000 - 1CFFFF
1D0000 - 1DFFFF
1E0000 - 1EFFFF
1F0000 - 1FFFFF
200000 – 20FFFF
210000 – 21FFFF
220000 – 22FFFF
(Kbytes/ Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Word Mode (x16)
SA0
SA1
000000XXX
000001XXX
000010XXX
000011XXX
000100XXX
000101XXX
000110XXX
000111XXX
001000XXX
001001XXX
001010XXX
001011XXX
001100XXX
001101XXX
001110XXX
001111XXX
010000XXX
010001XXX
010010XXX
010011XXX
010100XXX
010 101XXX
010110XXX
010111XXX
011000XXX
011001XXX
011010XXX
011011XXX
011100XXX
011101XXX
011110XXX
011111XXX
100000XXX
100001XXX
100010XXX
000000 - 007FFF
008000 - 00FFFF
010000 - 017FFF
018000 - 01FFFF
020000 - 027FFF
028000 - 02FFFF
030000 - 037FFF
038000 - 03FFFF
040000 - 047FFF
048000 - 04FFFF
050000 - 057FFF
058000 - 05FFFF
060000 - 067FFF
068000 - 06FFFF
070000 - 077FFF
078000 - 07FFFF
080000 - 087FFF
088000 - 08FFFF
090000 - 097FFF
098000 - 09FFFF
0A0000 - 0A7FFF
0A8000 - 0AFFFF
0B0000 - 0B7FFF
0B8000 - 0BFFFF
0C0000 - 0C7FFF
0C8000 - 0CFFFF
0D0000 - 0D7FFF
0D8000 - 0DFFFF
0E0000 - 0E7FFF
0E8000 - 0EFFFF
0F0000 - 0F7FFF
0F8000 - 0FBFFF
100000 - 107FFF
108000 – 10FFFF
110000 - 17FFFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
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(September, 2005, Version 0.0)
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AMIC Technology, Corp.
A29L320 Series
Sector Size
Address Range (in hexadecimal)
Sector
A20-A12
Byte Mode (x8)
230000 - 23FFFF
240000 - 24FFFF
250000 - 25FFFF
260000 - 26FFFF
270000 - 27FFFF
280000 - 28FFFF
290000 - 29FFFF
2A0000 – 2AFFFF
2B0000 – 2BFFFF
2C0000 – 2CFFFF
2D0000 – 2DFFFF
2E0000 – 2EFFFF
2F0000 – 2FFFFF
300000 – 30FFFF
310000 – 31FFFF
320000 – 32FFFF
330000 – 33FFFF
340000 – 34FFFF
350000 – 35FFFF
360000 – 36FFFF
370000 – 37FFFF
380000 – 38FFFF
390000 – 39FFFF
3A0000 – 3AFFFF
3B0000 – 3BFFFF
3C0000 – 3CFFFF
3D0000 – 3DFFFF
3E0000 – 3EFFFF
3F0000 – 3FFFFF
3F2000 – 3F3FFF
3F4000 – 3F5FFF
3F6000 – 3F7FFF
3F8000 – 3F9FFF
3FA000 – 3FBFFF
3FC000 – 3FDFFF
3FE000 – 3FFFFF
(Kbytes/ Kwords)
Word Mode (x16)
118000 - 11FFFF
120000 - 127FFF
128000 – 12FFFF
130000 – 137FFF
138000 – 13FFFF
140000 – 147FFF
148000 – 14FFFF
150000 – 157FFF
158000 – 15FFFF
160000 – 167FFF
168000 – 16FFFF
170000 – 177FFF
178000 – 17FFFF
180000 – 187FFF
188000 – 18FFFF
190000 – 197FFF
198000 – 19FFFF
1A0000 – 1A7FFF
1A8000 – 1AFFFF
1B0000 – 1B7FFF
1B8000 – 1BFFFF
1C0000 – 1C7FFF
1C8000 – 1CFFFF
1D0000 – 1D7FFF
1D8000 – 1DFFFF
1E0000 – 1E7FFF
1E8000 – 1EFFFF
1F0000 – 1F7FFF
1F8000 – 1F8FFF
1F9000 – 1F9FFF
1FA000 – 1FAFFF
1FB000 – 1FBFFF
1FC000 – 1FCFFF
1FD000 – 1FDFFF
1FE000 – 1FEFFF
1FF000 – 1FFFFF
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
100011XXX
100100XXX
100101XXX
100110XXX
100111XXX
101000XXX
101001XXX
101010XXX
101011XXX
101100XXX
101101XXX
101110XXX
101111XXX
110000XXX
110001XXX
110010XXX
110011XXX
110100XXX
110101XXX
110110XXX
110111XXX
111000XXX
111001XXX
111010XXX
111011XXX
111100XXX
111101XXX
111110XXX
111111000
111110001
111111010
111110011
111111100
111110101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Note:
Address range is A20 : A-1 in byte mode and A20 : A0 in word mode. See “Word/Byte Configuration” section.
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AMIC Technology, Corp.
A29L320 Series
Table 3. A29L320 Bottom Boot Block Sector Address Table
Sector
A20 -A12
Sector Size
Address Range (in hexadecimal)
(Kbytes/ Kwords)
Byte Mode (x8)
000000 - 001FFF
002000 - 003FFF
004000 - 005FFF
006000 - 007FFF
008000 - 009FFF
00A000 – 00BFFF
00C000 – 00DFFF
00E000 - 00FFFF
010000 - 01FFFF
020000 - 02FFFF
030000 - 03FFFF
040000 - 04FFFF
050000 - 05FFFF
060000 - 06FFFF
070000 - 07FFFF
080000 - 08FFFF
090000 - 09FFFF
0A0000 – 0AFFFF
0B0000 – 0BFFFF
0C0000 – 0CFFFF
0D0000 – 0DFFFF
0E0000 – 0EFFFF
0F0000 – 0FFFFF
100000 - 10FFFF
110000 - 11FFFF
120000 - 12FFFF
130000 - 13FFFF
140000 - 14FFFF
140000 - 14FFFF
160000 - 16FFFF
170000 - 17FFFF
180000 - 18FFFF
190000 - 19FFFF
1A0000 – 1AFFFF
1B0000 – 1BFFFF
Word Mode (x16)
000000 - 000FFF
001000 - 001FFF
002000 - 002FFF
003000 - 003FFF
004000 - 004FFF
005000 - 005FFF
006000 - 006FFF
007000 - 007FFF
008000 - 00FFFF
010000 - 017FFF
018000 – 01FFFF
020000 - 027FFF
028000 – 02FFFF
030000 - 037FFF
038000 – 03FFFF
040000 – 047FFF
048000 – 04FFFF
050000 – 057FFF
058000 – 05FFFF
060000 – 067FFF
068000 – 06FFFF
070000 – 077FFF
078000 – 07FFFF
080000 – 087FFF
088000 – 07FFFF
090000 – 097FFF
098000 – 09FFFF
0A0000 – 0A7FFF
0A8000 – 0AFFFF
0B0000 – 0B7FFF
0B8000 – 0BFFFF
0C0000 – 0C7FFF
0C8000 – 0CFFFF
0D0000 – 0D7FFF
0D8000 – 0DFFFF
SA0
SA1
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
1010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
8/4
8/4
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
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(September, 2005, Version 0.0)
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AMIC Technology, Corp.
A29L320 Series
Sector
A20 -A12
Sector Size
Address Range (in hexadecimal)
(Kbytes/ Kwords)
Byte Mode (x8)
1C0000 – 1CFFFF
1D0000 – 1DFFFF
1E0000 – 1EFFFF
1F0000 – 1FFFFF
200000 – 20FFFF
210000 – 21FFFF
220000 – 22FFFF
230000 – 23FFFF
240000 – 24FFFF
250000 – 25FFFF
260000 – 26FFFF
270000 – 27FFFF
280000 – 28FFFF
290000 – 29FFFF
2A0000 – 2AFFFF
2B0000 – 2BFFFF
2C0000 – 2CFFFF
2D0000 – 2DFFFF
2E0000 – 2EFFFF
2F0000 – 2FFFFF
300000 – 30FFFF
310000 – 31FFFF
320000 – 32FFFF
330000 – 33FFFF
340000 – 34FFFF
350000 – 35FFFF
360000 – 36FFFF
370000 – 37FFFF
380000 – 38FFFF
390000 – 39FFFF
3A0000 – 3AFFFF
3B0000 – 3BFFFF
3C0000 – 3CFFFF
3D0000 – 3DFFFF
3E0000 – 3EFFFF
3F0000 – 3FFFFF
Word Mode (x16)
0E0000 – 0E7FFF
0E8000 – 0EFFFF
0F0000 – 0F7FFF
0F8000 – 0FFFFF
100000 – 107FFF
108000 – 10FFFF
110000 – 117FFF
118000 – 11FFFF
120000 – 127FFF
128000 – 12FFFF
130000 – 137FFF
138000 – 13FFFF
140000 – 147FFF
148000 – 14FFFF
150000 – 157FFF
158000 – 15FFFF
160000 – 167FFF
168000 – 16FFFF
170000 – 177FFF
178000 – 17FFFF
180000 – 187FFF
188000 – 18FFFF
190000 – 197FFF
198000 – 19FFFF
1A0000 – 1A7FFF
1A8000 – 1AFFFF
1B0000 – 1B7FFF
1B8000 – 1BFFFF
1C0000 – 1C7FFF
1C8000 – 1CFFFF
1D0000 – 1D7FFF
1D8000 – 1DFFFF
1E0000 – 1E7FFF
1E8000 – 1EFFFF
1F0000 – 1F7FFF
1F8000 – 1FFFFF
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Note:
Address range is A20 : A-1 in byte mode and A20 : A0 in word mode. See “Word/Byte Configuration” section.
PRELIMINARY
(September, 2005, Version 0.0)
10
AMIC Technology, Corp.
A29L320 Series
sector protection, the sector address must appear on the
appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.To access the
autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown in
the Command Definitions table. This method does not
require VID. See "Command Definitions" for details on using
the autoselect mode.
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
a
device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pin A9. Address
pins A6, A1, and A0 must be as shown in Autoselect Codes
(High Voltage Method) table. In addition, when verifying
Table 4. A29L320 Autoselect Codes (High Voltage Method)
Mode
Description
A20 A11 A9 A8 A6 A5 A1 A0
I/O8
to
I/O7
to
WE
CE
OE
to
to
to
to
A12 A10
A7
A2
I/O15
I/O0
Manufacturer ID: AMIC
L
L
L
L
H
H
X
X
X
X
VID
X
X
L
L
X
X
L
L
L
X
37h
F6h
Device ID:
22h
Word
VID
H
A29L320
Byte
X
F6h
F9h
(Top Boot Block)
Device ID:
Word
22h
A29L320
L
L
L
L
L
L
H
H
H
X
X
X
X
X
VID
VID
VID
X
X
X
L
L
L
X
X
X
L
H
H
H
H
L
Byte
X
X
F9h
7Fh
(Bottom Boot Block)
Continuation ID
01h
(protected)
X
X
Sector Protection Verification
SA
00h
(unprotected)
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.
Note: The autoselect codes may also be accessed in-system via command sequences.
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AMIC Technology, Corp.
A29L320 Series
Sector Protection/Unprotection
Temporary Sector Unprotect
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the
pin to VID.
RESET
During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the
pin, all the previously
RESET
Sector protection / unprotection can be implemented via two
methods. The primary method requires VID on the
protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
pin only, and can be implemented either in-system or
RESET
via programming equipment. Figure 2 shows the algorithm
and the Sector Protect / Unprotect Timing Diagram illustrates
the timing waveforms for this feature. This method uses
standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle. The alternate
method must be implemented using programming
equipment. The procedure requires a high voltage (VID) on
address pin A9 and the control pins.
START
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
RESET = VID
(Note 1)
Hardware Data Protection
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device
is powered up to read array data to avoid accidentally writing
data to the array.
Perform Erase or
Program Operations
RESET = VIH
Write Pulse "Glitch" Protection
Temporary Sector
Unprotect
Completed (Note 2)
Noise pulses of less than 5ns (typical) on
do not initiate a write cycle.
,
or
WE
OE CE
Logical Inhibit
Write cycles are inhibited by holding any one of
=VIL,
OE
CE
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
= VIH or
= VIH. To initiate a write cycle,
and
WE
CE
must be a logical zero while
is a logical one.
WE
OE
Power-Up Write Inhibit
Figure 1. Temporary Sector Unprotect Operation
If
=
= VIL and
= VIH during power up, the
OE
WE
device does not accept commands on the rising edge of
. The internal state machine is automatically reset to
CE
WE
reading array data on the initial power-up.
PRELIMINARY
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12
AMIC Technology, Corp.
A29L320 Series
START
START
Protect all sectors:
The indicated portion of
the sector protect
PLSCNT=1
PLSCNT=1
algorithm must be
performed for all
RESET=VID
RESET=VID
unprotected sectors prior
to issuing the first sector
unprotect address
Wait 1 us
Wait 1 us
No
No
No
Temporary Sector
Unprotect Mode
First Write
Cycle=60h?
First Write
Cycle=60h?
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
All sectors
protected?
Sector Protec:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
Reset
PLSCNT=1
Increment
PLSCNT
Wait 500 ms
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Read from
sector address
with A6=0,
Increment
PLSCNT
A1=1, A0=0
No
Read from sector
address with A6=1,
A1=1, A0=0
No
PLSCNT
=25?
Data=01h?
Yes
No
Set up
next sector
address
Yes
No
PLSCNT=
1000?
Yes
Data=00h?
Yes
Protect another
sector?
Device failed
Yes
No
Remove VID
from RESET
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
from RESET
Sector Protect
complete
Sector Protect
Algorithm
Sector Unprotect
Algorithm
Write reset
Command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/Unprotect Algorithms
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(September, 2005, Version 0.0)
13
AMIC Technology, Corp.
A29L320 Series
Common Flash Memory Interface (CFI)
device is ready to read array data. The system can read CFI
information at the addresses given in Table 5-8. In word
mode, the upper address bits (A7-MSB) must be all zeros.
To terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command when the
device is in the autoselect mode. The device enters the CFI
query mode, and the system can read CFI data at the
addresses given in Table 5-8. The system must write the
reset command to return the device to the autoselect mode.
The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms to
be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and
forward- and backward-compatible for the specified flash
device families. Flash vendors can standardize their existing
interface for long-term compatibility.
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h in word
mode (or address AAh in byte mode), any time the
Table 5. CFI Query Identification String
Addresses
Addresses
Data
Description
(Word Mode)
(Byte Mode)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
Table 6 System Interface String
Addresses
(Word Mode)
1Bh
Addresses
(Byte Mode)
36h
Data
Description
0027h
0036h
VCC Min. (write/erase)
I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt
1Ch
38h
VCC Max. (write/erase)
I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
Vpp Min. voltage (00h = no Vpp pin present)
Vpp Max. voltage (00h = no Vpp pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
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(September, 2005, Version 0.0)
14
AMIC Technology, Corp.
A29L320 Series
Table 7 Device Geometry Definition
Addresses
(Word Mode)
27h
Addresses
(Byte Mode)
4Eh
Data
Description
0016h
0002h
0000h
0000h
0000h
0002h
0007h
0000h
0020h
0000h
003Eh
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Device Size = 2N byte
28h
50h
Flash Device Interface description
29h
52h
2Ah
54h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Bh
56h
2Ch
58h
Number of Erase Block Regions within device
2Dh
5Ah
2Eh
5Ch
Erase Block Region 1 Information
(refer to the CFI specification)
2Fh
5Eh
30h
60h
31h
62h
32h
64h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
33h
66h
34h
68h
35h
6Ah
36h
6Ch
37h
6Eh
38h
40h
39h
72h
3Ah
74h
3BH
3Ch
76h
78h
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15
AMIC Technology, Corp.
A29L320 Series
Table 8 Primary Vendor-Specific Extended Query
Addresses
Addresses
(Byte Mode)
80h
Data
Description
(Word Mode)
40h
41h
42h
43h
44h
45h
0050h
0052h
0049h
0031h
0030h
0000h
82h
Query-unique ASCII string “PRI”
84h
86h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
Erase Suspend
88h
8Ah
46h
47h
48h
49h
8Ch
8Eh
90h
92h
0002h
0004h
0001h
0004h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29L160 mode
Simultaneous Operation
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
94h
96h
98h
9Ah
9Ch
9Eh
0000h
0000h
0000h
00B5h
00C5h
000Xh
00 = Not Supported, 01 = Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
00 = Not Supported, D7-D4: Volt, D3-D0: 100mV
ACC (Acceleration) Supply Maximum
00 = Not Supported, D7-D4: Volt, D3-D0: 100mV
Top/Bottom Boot Sector Flag
02 = Bottom Boot Device, 03h = Top Boot Device
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(September, 2005, Version 0.0)
16
AMIC Technology, Corp.
A29L320 Series
Command Definitions
Autoselect Command Sequence
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
All addresses are latched on the falling edge of
or
,
CE
WE
whichever happens later. All data is latched on the rising
edge of or , whichever happens first. Refer to the
WE
CE
appropriate timing diagrams in the "AC Characteristics"
section.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX11h retrieves the
continuation code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address (SA)
and the address 02h in returns 01h if that sector is protected,
or 00h if it is unprotected. Refer to the Sector Address tables
for valid sector addresses.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended
sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See "Erase Suspend/Erase Resume Commands"
for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the
pin. Programming is a
BYTE
four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data are
written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the
programmed cell margin. Table 9 shows the address and data
requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
longer latched. The system can determine the status of the
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
program operation by using I/O7, I/O6, or RY/
. See “White
BY
Operation Status” for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the programming operation. The Byte
Program command sequence should be reinitiated once the
device has reset to reading array data, to ensure data
integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to a
“1”. Attempting to do so may halt the operation and set I/O5 to
The reset command may be written between the sequence
cycles in
a
program command sequence before
programming begins. This resets the device to reading array
data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
“1”, or cause the
Polling algorithm to indicate the
Data
operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
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AMIC Technology, Corp.
A29L320 Series
00h. Addresses are don’t care for both cycle. The device
returns to reading array data.
Figure 3 illustrates the algorithm for the program operation.
See the Erase/Program Operations in “AC Characteristics” for
parameters, and to Program Operation Timings for timing
diagrams.
START
Write Program
Command
Chip Erase Command Sequence
Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements
for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Data Poll
from System
Embedded
Program
algorithm in
progress
Verify Data ?
Yes
No
No
Increment Address
Last Address ?
Yes
Figure 4 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
Programming
Completed
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
out of 50µs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50µs, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sector
erase commands can be assumed to be less than 50µs, the
system need not monitor I/O3. Any command other than
Sector Erase or Erase Suspend during the time-out period
resets the device to reading array data. The system must
rewrite the command sequence and any additional sector
addresses and commands.
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 3. Program Operation
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
bytes or words to the device faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode.
A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 9
shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The first
cycle must contain the data 90h; the second cycle the data
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AMIC Technology, Corp.
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The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further writes
of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
pulse in the command sequence.
WE
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, or I/O2. Refer to "Write
Operation Status" for information on these status bits.
START
4 illustrates the algorithm for the erase operation. Refer to
the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
Write Erase
Command
Sequence
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50µs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
operation. Addresses are "don't cares" when writing the
Erase Suspend command.
Data Poll
from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20µs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
Yes
Erasure Completed
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on I/O7
- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to
determine if a sector is actively erasing or is erase-
suspended. See "Write Operation Status" for information on
these status bits.
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O
3
: Sector Erase Timer" for more information.
Figure 4. Erase Operation
After an erase-suspended program operation is complete,
the system can once again read array data within non-
suspended sectors. The system can determine the status of
the program operation using the I/O7 or I/O6 status bits, just
as in the standard program operation. See "Write Operation
Status" for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
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Table 9. A29L320 Command Definitions
Bus Cycles (Notes 2 - 5)
Third Fourth
Command
Sequence
(Note 1)
First
Addr Data Addr Data
RA RD
Second
Fifth
Sixth
Addr Data Addr Data Addr Data
Addr Data
Read (Note 6)
Reset (Note 7)
1
1
XXX F0
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555
AAA
555
AAA
555
AAA
555
AAA
2AA
555
2AA
555
2AA
555
2AA
555
555
AAA
555
AAA
555
AAA
555
Manufacturer ID
4
4
4
4
AA
55
55
55
55
90
90
90
90
X00
37
Device ID,
Top Boot Block
Device ID,
Bottom Boot Block
X01 22F4
X02 F4
X01 22F9
X02 F9
X03
X06
AA
AA
Continuation ID
AA
7F
AAA
(SA) XX00
Word
555
AA
2AA
555
555
AAA
Sector Protect Verify
(Note 9)
X02
XX01
4
55
90
00
01
(SA)
X04
Byte
AAA
Word
Byte
Byte
Byte
Word
Byte
55
98
AA
CFI Query (Note 10)
Program
1
4
3
555
AAA
2AA 55
555
2AA 55
555
555 A0
AAA
555 20
AAA
PA
PD
AA
555
AAA
Unlock Bypass
AA
Unlock Bypass Program (Note 2
11)
XXX A0
PA
PD
Unlock Bypass Reset (Note 12)
2
XXX 90
XXX
00
Word
555
AA
2AA 55
555
555 80
AAA
555
AAA
555 AA
AAA
AA
2AA 55
555
2AA 55
555
555
AAA
SA
10
30
Chip Erase
6
Byte
Word
Byte
AAA
555
2AA
555
55
555
80
Sector Erase
6
AA
AAA
AAA
Erase Suspend (Note 13)
Erase Resume (Note 14)
1
1
XXX B0
XXX 30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the
whichever happens later.
or
pulse,
CE
WE
PD = Data to be programmed at location PA. Data latches on the rising edge of
or
pulse, whichever happens first.
CE
WE
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20- A12 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A20 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information.
10. Command is valid when device is ready to read array data or when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass
mode.
13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
14. The Erase Resume command is valid only during the Erase Suspend mode.
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A29L320 Series
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/
the A29L320 to determine the status of a write operation.
Table 10 and the following subsections describe the
are provided in
BY
START
functions of these status bits. I/O7, I/O6 and RY/
each
BY
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
Read I/O
Address = VA
7
-I/O
0
I/O7:
Polling
Data
The
Polling bit, I/O7, indicates to the host system
Data
whether an Embedded Algorithm is in progress or completed,
Yes
I/O
7
= Data ?
No
or whether the device is in Erase Suspend. Polling is
Data
pulse in the
valid after the rising edge of the final
program or erase command sequence.
WE
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
No
I/O5 = 1?
Yes
protected sector,
Polling on I/O7 is active for
Data
approximately 2µs, then the device returns to reading array
data.
Read I/O7 - I/O0
During the Embedded Erase algorithm,
Polling
Data
Address = VA
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Polling produces a "1" on I/O7.This is analogous to the
Data
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O7.
Yes
I/O7
= Data ?
No
After an erase command sequence is written, if all sectors
selected for erasing are protected,
Polling on I/O7 is
Data
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0
on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output Enable
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
(
) is asserted low. The
Polling Timings (During
Data
OE
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 10 shows the outputs for
2. I/O
7
should be rechecked even if I/O
may change simultaneously with I/O
5 = "1" because
I/O7
5
.
Data
Polling algorithm.
Polling on I/O7. Figure 5 shows the
Data
Figure 5. Data Polling Algorithm
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AMIC Technology, Corp.
A29L320 Series
RY/
: Read/
Busy
BY
I/O2: Toggle Bit II
The RY/
is a dedicated, open-drain output pin that
BY
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
indicates whether an Embedded algorithm is in progress or
complete. The RY/ status is valid after the rising edge of
BY
pulse in the command sequence. Since RY/
the final
WE
BY
pins can be tied
rising edge of the final
pulse in the command sequence.
is an open-drain output, several RY/
WE
BY
together in parallel with a pull-up resistor to VCC. (The
RY/ pin is not available on the 44-pin SOP package)
I/O2 toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may
BY
use either
or
to control the read cycles.) But I/O2
CE
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
OE
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information.
Refer to Table 10 to compare outputs for I/O2 and I/O6.
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle
Bit Timings figure for the toggle bit timing diagram. The I/O2
vs. I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form.
Table 10 shows the outputs for RY/
. Refer to “
RESET
BY
Timings”, “Timing Waveforms for Program Operation” and
“Timing Waveforms for Chip/Sector Erase Operation” for
more information.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
Reading Toggle Bits I/O6, I/O2
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7 - I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and store
the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7 - I/O0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).
of the final
pulse in the command sequence (prior to the
WE
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
(The system may use either
or
to control the read
CE
OE
cycles.) When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the device
enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O7 (see the subsection on " I/O7 :
Polling").
Data
If a program address falls within a protected sector, I/O6
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 6 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O2 vs.
I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on " I/O2: Toggle Bit
II".
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
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The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O5
produces a "1."
START
Read I/O7-I/O0
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50µs. See also the "Sector Erase Command
Sequence" section.
Read I/O7-I/O0
(Note 1)
No
Toggle Bit
= Toggle ?
Yes
After the sector erase command sequence is written, the
No
I/O5 = 1?
system should read the status on I/O7 (
Polling) or I/O6
Data
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted. Table 10 shows the outputs for I/O3.
Yes
- I/O
Read I/O
7
0
(Notes 1,2)
Twice
No
Toggle Bit
= Toggle ?
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O
5
changes to "1". See text.
Figure 6. Toggle Bit Algorithm
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Table 10. Write Operation Status
I/O7
I/O6
I/O5
(Note 2)
0
I/O3
I/O2
RY/
BY
Operation
(Note 1)
(Note 1)
Standard
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
N/A
1
No toggle
0
I/O7
0
0
0
Toggle
Toggle
0
1
Erase
Reading within Erase
Suspended Sector
1
No toggle
N/A
Suspend
Mode
Reading within Non-Erase
Suspend Sector
Data
I/O7
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
Toggle
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
20ns
PRELIMINARY
(September, 2005, Version 0.0)
24
AMIC Technology, Corp.
A29L320 Series
DC Characteristics
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
Min.
Typ.
Max.
Unit
ILI
Input Load Current
VIN = VSS to VCC. VCC = VCC Max
VCC = VCC Max, A9 =12.5V
±1.0
35
µA
µA
µA
ILIT
ILO
A9 Input Load Current
Output Leakage Current
VOUT = VSS to VCC. VCC = VCC Max
±1.0
5 MHz
9
2
16
= VIL,
= VIH
CE
Byte Mode
OE
OE
1 MHz
5 MHz
1 MHz
4
VCC Active Read Current
(Notes 1, 2)
ICC1
ICC2
mA
mA
9
2
16
4
= VIL,
CE
Word Mode
= VIH
=VIH
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)
20
0.2
0.2
30
5
= VIL,
= VIH,
CE
OE
ICC3
ICC4
VCC Standby Current (Note 2)
µA
µA
= VCC ± 0.3V
RESET
CE
VCC Standby Current During Reset
(Note 2)
= VSS ± 0.3V
RESET
5
ICC5
Automatic Sleep Mode
(Note 2, 4, 5)
0.2
5
VIH = VCC ± 0.3V; VIL = VSS ± 0.3V
µA
VIL
VIH
Input Low Level
Input High Level
-0.5
0.8
V
V
0.7 x VCC
VCC + 0.3
Voltage for Autoselect and
Temporary Unprotect Sector
Output Low Voltage
VID
VCC = 3.3 V
11.5
V
12.5
0.45
VOL
VOH1
VOH2
IOL = 4.0mA, VCC = VCC Min
IOH = -2.0 mA, VCC = VCC Min
IOH = -100 µA, VCC = VCC Min
V
V
V
0.85 x VCC
VCC - 0.4
Output High Voltage
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with
at VIH. Typical VCC is 3.3V.
OE
2. Maximum ICC specifications are tested with VCC = VCC max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current
is 200nA.
5. Not 100% tested.
PRELIMINARY
(September, 2005, Version 0.0)
25
AMIC Technology, Corp.
A29L320 Series
DC Characteristics (continued)
Zero Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1MHz
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
8
3.6V
3.0V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note : T = 25°C
Typical ICC1 vs. Frequency
PRELIMINARY
(September, 2005, Version 0.0)
26
AMIC Technology, Corp.
A29L320 Series
AC Characteristics
Read Only Operations
Parameter Symbols
Description
Test Setup
Speed
Unit
JEDEC
Std
-70
-90
Read Cycle Time (Note 1)
Address to Output Delay
tAVAV
tRC
Min.
70
90
ns
ns
= VIL
tAVQV
tACC
CE
Max.
70
90
= VIL
OE
Chip Enable to Output Delay
Output Enable to Output Delay
tELQV
tGLQV
tCE
Max.
Max.
Min.
70
30
0
90
35
0
ns
ns
ns
= VIL
OE
tOE
Read
Output Enable Hold
Time (Note 1)
tOEH
Toggle and
ns
Min.
10
25
10
30
Polling
Data
Chip Enable to Output High Z
(Notes 1)
tEHQZ
tGHQZ
tHZ
tDF
Max.
ns
ns
Output Enable to Output High Z
(Notes 1)
25
0
30
0
Output Hold Time from Addresses,
tAXQX
tOH
Min.
ns
or
, Whichever Occurs First
CE OE
(Note 1)
Notes:
1. Not 100% tested.
2. See Test Conditions and Test Setup for test specifications.
Timing Waveforms for Read Only Operation
tRC
Addresses
Addresses Stable
t
ACC
CE
OE
t
DF
t
OE
t
OEH
WE
t
CE
t
OH
High-Z
High-Z
Output
Output Valid
RESET
RY/BY
0V
PRELIMINARY
(September, 2005, Version 0.0)
27
AMIC Technology, Corp.
A29L320 Series
AC Characteristics
Hardware Reset (
Parameter
)
RESET
Description
Test Setup
All Speed Options
Unit
JEDEC
Std
Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
RESET
tREADY
Max
20
µs
Pin Low (Not During Embedded
RESET
Algorithms) to Read or Write (See Note)
tREADY
Max
500
ns
tRP
tRH
Min
Min
Min
Min
500
50
0
ns
ns
ns
µs
Pulse Width
RESET
RESET
High Time Before Read (See Note)
Recovery Time
tRB
RY/
BY
tRPD
20
Low to Standby Mode
RESET
Note: Not 100% tested.
Timings
RESET
RY/BY
CE, OE
RESET
t
RH
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
RY/BY
t
RB
CE, OE
RESET
t
RP
PRELIMINARY
(September, 2005, Version 0.0)
28
AMIC Technology, Corp.
A29L320 Series
Temporary Sector Unprotect
Parameter
Description
All Speed Options
Unit
ns
JEDEC
Std
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
4
Setup Time for Temporary Sector
Unprotect
RESET
tRSP
µs
Note: Not 100% tested.
Temporary Sector Unprotect Timing Diagram
12V
0 or 3V
RESET
0 or 3V
tVIDR
tVIDR
Program or Erase Command Sequence
CE
WE
t
RSP
RY/BY
AC Characteristics
Word/Byte Configuration (
Parameter
)
BYTE
Description
All Speed Options
Unit
JEDEC
Std
-70
-90
tELFL/tELFH
Max
5
ns
to
Switching Low or High
BYTE
CE
Switching Low to Output High-Z
Switching High to Output Active
BYTE
BYTE
tFLQZ
tHQV
Max
Min
25
70
30
90
ns
ns
PRELIMINARY
(September, 2005, Version 0.0)
29
AMIC Technology, Corp.
A29L320 Series
Timings for Read Operations
BYTE
CE
OE
BYTE
t
ELFL
Data Output
(I/O -I/O14
Data Output
(I/O -I/O
BYTE
I/O -I/O14
0
0
)
0
7)
Switching
from word to
byte mode
I/O15
Output
Address Input
I/O15 (A-1)
t
FLQZ
t
ELFH
BYTE
Data Output
(I/O -I/O
Data Output
(I/O0-I/O14)
I/O -I/O14
0
0
7
)
BYTE
Switching
from byte to
word mode
I/O15
Output
Address Input
I/O15 (A-1)
t
FHQV
Timings for Write Operations
BYTE
CE
The falling edge of the last WE signal
WE
BYTE
t
SET
(tAS
)
t
HOLD(tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
PRELIMINARY
(September, 2005, Version 0.0)
30
AMIC Technology, Corp.
A29L320 Series
AC Characteristics
Erase and Program Operations
Parameter
Description
Speed
Unit
JEDEC
tAVAV
Std
tWC
tAS
-70
-90
Write Cycle Time (Note 1)
Min.
Min.
Min.
Min.
Min.
Min.
70
90
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
tAVWL
tWLAX
tDVWH
tWHDX
0
tAH
45
35
45
45
Data Setup Time
tDS
Data Hold Time
tDH
0
0
Output Enable Setup Time
Read Recover Time Before Write
tOES
tGHWL
tGHWL
Min.
0
ns
(
high to
low)
WE
OE
tELWL
tWHEH
tWLWH
tWHWL
tCS
tCH
Min.
Min.
Min.
0
0
ns
ns
ns
ns
Setup Time
Hold Time
CE
CE
tWP
tWPH
35
35
Write Pulse Width
Write Pulse Width High
Min.
Typ.
30
20
Byte
Byte Programming Operation
(Note 2)
tWHWH1
tWHWH2
tWHWH1
µs
Word
Typ.
40
tWHWH2
tvcs
Sector Erase Operation (Note 2)
VCC Set Up Time (Note 1)
Typ.
Min.
Min
Min
1.0
50
0
sec
µs
ns
ns
tRB
Recovery Time from RY/
(Note 1)
BY
tBUSY
90
Program/Erase Valid to RY/
Delay (Note 1)
BY
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
PRELIMINARY
(September, 2005, Version 0.0)
31
AMIC Technology, Corp.
A29L320 Series
Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tWC
tAS
Addresses
CE
PA
PA
555h
PA
t
AH
tCH
OE
t
WP
t
WHWH1
WE
t
CS
t
WPH
t
DS
t
DH
Data
A0h
PD
DOUT
Status
t
RB
t
BUSY
RY/BY
VCC
t
VCS
Note :
1. PA = program addrss, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
PRELIMINARY
(September, 2005, Version 0.0)
32
AMIC Technology, Corp.
A29L320 Series
Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
Read Status Data
tAS
tWC
SA
555h for chip erase
VA
Addresses
CE
2AAh
VA
tAH
OE
tCH
t
WP
WE
t
WPH
tWHWH2
tCS
tDS
tDH
In
Progress
Data
55h
30h
10h for chip erase
Complete
tRB
tBUSY
RY/BY
tVCS
VCC
Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustratin shows device in word mode.
PRELIMINARY
(September, 2005, Version 0.0)
33
AMIC Technology, Corp.
A29L320 Series
Timing Waveforms for
Polling (During Embedded Algorithms)
Data
t
RC
Addresses
CE
VA
VA
VA
t
ACC
CE
t
t
CH
t
OE
OE
t
DF
t
OEH
WE
t
OH
High-Z
Valid Data
I/O
7
Complement
Complement
Status Data
True
True
High-Z
I/O0
- I/O
6
Valid Data
High-Z
Status Data
t
BUSY
RY/BY
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
PRELIMINARY
(September, 2005, Version 0.0)
34
AMIC Technology, Corp.
A29L320 Series
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
t
RC
Addresses
CE
VA
VA
VA
VA
t
ACC
t
CE
tCH
t
OE
OE
tDF
t
OEH
WE
tOH
I/O6
,
I/O2
High-Z
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
t
BUSY
(second read)
(stop togging)
RY/BY
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
PRELIMINARY
(September, 2005, Version 0.0)
35
AMIC Technology, Corp.
A29L320 Series
Timing Waveforms for Sector Protect/Unprotect
V
ID
IH
V
RESET
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
40h
60h
60h
Data
CE
Sector Protect:150us
Sector Unprotect:15ms
1us
WE
OE
Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0
Timing Waveforms for I/O2 vs. I/O6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE
I/O
Erase
Suspend
Program
Erase
Erase
Erase Suspend
Erase Suspend
Read
Erase
Complete
Read
6
I/O2
I/O2
and I/O
6
toggle with OE and CE
Note : Both I/O
6
and I/O
2
toggle with OE or CE. See the text on I/O
6
and I/O
2
in the section "Write Operation Status" for
more information.
PRELIMINARY
(September, 2005, Version 0.0)
36
AMIC Technology, Corp.
A29L320 Series
Timing Waveforms for Alternate
Controlled Write Operation
CE
PA for program
SA for sector erase
555 for chip erase
555 for program
2AA for erase
Data Polling
PA
Addresses
t
WC
tAS
tAH
tWH
WE
OE
t
WHWH1 or 2
t
CP
t
BUSY
t
CPH
CE
t
WS
tDS
t
DH
Data
I/O7
DOUT
t
RH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET
RY/BY
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O
7
= Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Sector Erase Time
Typ. (Note 1)
Max. (Note 2)
Unit
sec
sec
µs
Comments
1.0
35
20
40
22
15
8
Excludes 00h programming
prior to erasure
Chip Erase Time
Byte Programming Time
Word Programming Time
300
500
33
Excludes system-level
overhead (Note 5)
µs
Chip Programming Time
(Note 3)
Byte Mode
Word Mode
sec
sec
22
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 9
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.
PRELIMINARY
(September, 2005, Version 0.0)
37
AMIC Technology, Corp.
A29L320 Series
Latch-up Characteristics
Description
Min.
-1.0V
Max.
VCC+1.0V
+100 mA
12.5V
Input Voltage with respect to VSS on all I/O pins
VCC Current
-100 mA
-1.0V
Input voltage with respect to VSS on all pins except I/O pins
(including A9,
and
)
RESET
OE
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.
TSOP and SOP Pin Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
VIN=0
Typ.
Max.
7.5
12
Unit
pF
CIN
COUT
CIN2
6
Output Capacitance
VOUT=0
VIN=0
8.5
7.5
pF
Control Pin Capacitance
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
Data Retention
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
20
125°C
PRELIMINARY
(September, 2005, Version 0.0)
38
AMIC Technology, Corp.
A29L320 Series
Test Conditions
Test Specifications
Test Condition
-70
-90
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL(including jig capacitance)
Input Rise and Fall Times
30
5
100
5
pF
ns
V
Input Pulse Levels
0.0 - 3.0
1.5
0.0 - 3.0
1.5
Input timing measurement reference levels
Output timing measurement reference levels
V
1.5
1.5
V
Test Setup
3.3 V
2.7 KΩ
Device
Under
Test
Diodes = IN3064 or Equivalent
CL
6.2 KΩ
PRELIMINARY
(September, 2005, Version 0.0)
39
AMIC Technology, Corp.
A29L320 Series
Ordering Information
Top Boot Sector Flash
Active Read
Current
Typ. (mA)
Program/Erase
Current
Standby Current
Access Time
(ns)
Part No.
Package
Typ. (µA)
Typ. (mA)
A29L320TV-70
48Pin TSOP
48Pin TSOP
A29L320TV-70U
A29L320TV-70I
A29L320TV-70F
A29L320TV-70UF
A29L320TV-70IF
A29L320TG-70
A29L320TG-70U
A29L320TG-70I
A29L320TG-70F
A29L320TG-70UF
A29L320TG-70IF
A29L320TV-90
48Pin TSOP
48 Pin Pb-Free TSOP
48 Pin Pb-Free TSOP
48 Pin Pb-Free TSOP
48-ball TFBGA
48-ball TFBGA
48-ball TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48Pin TSOP
A29L320TV-90U
A29L320TV-90I
A29L320TV-90F
A29L320TV-90UF
A29L320TV-90IF
A29L320TG-90
A29L320TG-90U
A29L320TG-90I
A29L320TG-90F
A29L320TG-90UF
A29L320TG-90IF
48Pin TSOP
48Pin TSOP
48Pin Pb-Free TSOP
48Pin Pb-Free TSOP
48Pin Pb-Free TSOP
48-ball TFBGA
48-ball TFBGA
48-ball TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
Note: -U is for industrial operating temperature range: -40°C to +85°C
-I is for industrial operating temperature range: -25°C to +85°C
PRELIMINARY
(September, 2005, Version 0.0)
40
AMIC Technology, Corp.
A29L320 Series
Ordering Information (continued)
Bottom Boot Sector Flash
Active Read
Current
Typ. (mA)
Program/Erase
Current
Standby Current
Access Time
Part No.
(ns)
Package
Typ. (µA)
Typ. (mA)
A29L320UV-70
48Pin TSOP
48Pin TSOP
A29L320UV-70U
A29L320UV-70I
A29L320UV-70F
A29L320UV-70UF
A29L320UV-70IF
A29L320UG-70
A29L320UG-70U
A29L320UG-70I
A29L320UG-70F
A29L320UG-70UF
A29L320UG-70IF
A29L320UV-90
48Pin TSOP
48 Pin Pb-Free TSOP
48 Pin Pb-Free TSOP
48 Pin Pb-Free TSOP
48-ball TFBGA
48-ball TFBGA
48-ball TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48Pin TSOP
A29L320UV-90U
A29L320UV-90I
A29L320UV-90F
A29L320UV-90UF
A29L320UV-90IF
A29L320UG-90
A29L320UG-90U
A29L320UG-90I
A29L320UG-90F
A29L320UG-90UF
A29L320UG-90IF
48Pin TSOP
48Pin TSOP
48Pin Pb-Free TSOP
48Pin Pb-Free TSOP
48Pin Pb-Free TSOP
48-ball TFBGA
48-ball TFBGA
48-ball TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
48-ball Pb-Free TFBGA
Note: -U is for industrial operating temperature range: -40°C to +85°C
-I is for industrial operating temperature range: -25°C to +85°C
PRELIMINARY
(September, 2005, Version 0.0)
41
AMIC Technology, Corp.
A29L320 Series
Package Information
TSOP 48L (Type I) Outline Dimensions
unit: inches/mm
D
D1
1
48
D
24
25
θ
L
Detail "A"
Detail "A"
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
Min
Nom
Max
A
A1
A2
b
-
0.047
0.006
0.042
0.011
0.008
0.795
0.728
0.476
-
-
1.20
0.15
0.002
0.037
0.007
0.004
0.779
0.720
-
-
0.039
0.009
-
0.05
0.94
0.18
0.12
19.80
18.30
-
-
1.00
1.06
0.22
0.27
c
-
0.20
D
D1
E
e
0.787
0.724
0.472
0.020 BASIC
0.020
0.011 Typ.
-
20.00
18.40
12.00
0.50 BASIC
0.50
20.20
18.50
12.10
L
0.016
0.024
0.40
0.60
S
y
0.28 Typ.
-
-
0.004
8°
-
0.10
8°
0°
-
0°
-
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(September, 2005, Version 0.0)
42
AMIC Technology, Corp.
A29L320 Series
Package Information
48 Balls CSP (6 x 8 mm) Outline Dimensions
(48TFBGA)
unit: mm
TOP VIEW
BOTTOM VIEW
b
1
2 3 4 5 6
6
5 4 3 2 1
H
G
F
H
G
F
E
D
C
B
A
E
D
C
B
A
e
D1
Ball*A1 CORNER
SIDE VIEW
D
C
SEATING PLANE
0.10 C
Dimensions in mm
Symbol
Min.
Nom.
Max.
A
A1
b
-
-
0.25
1.20
0.30
0.40
6.10
0.20
0.30
5.90
-
D
6.00
D1
e
4.00 BSC
0.80
-
-
E
7.90
8.00
8.10
E1
5.60 BSC
PRELIMINARY
(September, 2005, Version 0.0)
43
AMIC Technology, Corp.
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