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A29L004TY-90F [AMICC]

Flash, 512KX8, 90ns, PDSO32, 8 X 14 MM, ROHS COMPLIANT, STSOP1-32;
A29L004TY-90F
型号： A29L004TY-90F
厂家： AMIC TECHNOLOGY    AMIC TECHNOLOGY
描述：

Flash, 512KX8, 90ns, PDSO32, 8 X 14 MM, ROHS COMPLIANT, STSOP1-32

光电二极管 内存集成电路
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A29L004 Series  
512K X 8 Bit CMOS 3.0 Volt-only,  
Boot Sector Flash Memory  
Document Title  
512K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory  
Revision History  
Rev. History  
Issue Date  
Remark  
Preliminary  
Final  
0.0  
1.0  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
1.7  
Initial issue  
October 30, 2002  
October 7, 2003  
February 23, 2004  
June 8, 2004  
Final version release  
Modify typical sector erase time from 0.7sec. to 1sec.  
Change 32L sTSOP body size from 8x14mm to 8x13.4mm  
Add Pb-Free package type  
July 28, 2004  
Add 32L sTSOP 8x14mm package type & erase/program time modification  
Add IR Reflow Condition of Pb Free Type  
Add DIP 32 package type  
March 16, 2005  
June 17, 2005  
February 6, 2007  
November 24, 2010  
Page 1: Change from typical 100,000 cycles to minimum 100,000 cycles  
(November, 2010, Version 1.7)  
AMIC Technology, Corp.  
A29L004 Series  
512K X 8 Bit CMOS 3.0 Volt-only,  
Boot Sector Flash Memory  
Features  
„ Single power supply operation  
- Embedded Program algorithm automatically writes and  
verifies data at specified addresses  
„ Minimum 100,000 program/erase cycles per sector  
„ 20-year data retention at 125°C  
- Reliable operation for the life of the system  
„ Compatible with JEDEC-standards  
- Full voltage range: 2.7 to 3.6 volt read and write  
operations for battery-powered applications  
- Regulated voltage range: 3.0 to 3.6 volt read and write  
operations for compatibility with high performance 3.3  
volt microprocessors  
„ Access times:  
- Pinout and software compatible with single-power-supply  
Flash memory standard  
- 70/90 (max.)  
„ Current:  
- Superior inadvertent write protection  
- 4 mA typical active read current  
- 20 mA typical program/erase current  
- 200 nA typical CMOS standby  
„
Polling and toggle bits  
- Provides a software method of detecting completion of  
program or erase operations  
Data  
- 200 nA Automatic Sleep Mode current  
„ Flexible sector architecture  
„ Ready /  
pin (RY /  
)
BY  
BUSY  
- Provides a hardware method of detecting completion of  
program or erase operations (not available on 32-pin  
DIP, PLCC & (s)TSOP packages)  
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors  
- Any combination of sectors can be erased  
- Supports full chip erase  
„ Erase Suspend/Erase Resume  
- Sector protection:  
- Suspends a sector erase operation to read data from, or  
program data to, a non-erasing sector, then resumes the  
erase operation  
A hardware method of protecting sectors to prevent any  
inadvertent program or erase operations within that  
sector. Temporary Sector Unprotect feature allows code  
changes in previously locked sectors  
„ Unlock Bypass Program Command  
- Reduces overall programming time when issuing  
multiple program command sequence  
„ Top or bottom boot block configurations available  
„ Embedded Algorithms  
„ Hardware reset pin (  
)
RESET  
- Hardware method to reset the device to reading array  
data (not available on 32 pin DIP, PLCC & (s)TSOP  
packages)  
„ Package options  
- 40-pin TSOP (forward type), 32-pin DIP, PLCC or  
(s)TSOP (forward type)  
- All Pb-free (Lead-free) products are RoHS compliant  
- Embedded Erase algorithm will automatically erase the  
entire chip or any combination of designated sectors and  
verify the erased sectors  
General Description  
The A29L004 is a 4Mbit, 3.0 volt-only Flash memory  
organized as 524,288 bytes of 8 bits. The 8 bits of data  
appear on I/O0 - I/O7. The A29L004 is offered in 40-pin  
TSOP, 32-pin DIP, PLCC or (s)TSOP packages. This device  
is designed to be programmed in-system with the standard  
system 3.0 volt VCC supply. Additional 12.0 volt VPP is not  
required for in-system write or erase operations. However,  
the A29L004 can also be programmed in standard EPROM  
programmers.  
The A29L004 is entirely software command set compatible  
with the JEDEC single-power-supply Flash standard.  
Commands are written to the command register using  
standard microprocessor write timings. Register contents  
serve as input to an internal state-machine that controls the  
erase and programming circuitry. Write cycles also internally  
latch addresses and data needed for the programming and  
erase operations. Reading data out of the device is similar to  
reading from other Flash or EPROM devices.  
The A29L004 has the first toggle bit, I/O6, which indicates  
whether an Embedded Program or Erase is in progress, or it  
is in the Erase Suspend. Besides the I/O6 toggle bit, the  
A29L004 has a second toggle bit, I/O2, to indicate whether  
the addressed sector is being selected for erase. The  
A29L004 also offers the ability to program in the Erase  
Suspend mode. The standard A29L004 offers access times  
of 70 and 90ns, allowing high-speed microprocessors to  
operate without wait states. To eliminate bus contention the  
Device programming occurs by writing the proper program  
command sequence. This initiates the Embedded Program  
algorithm - an internal algorithm that automatically times the  
program pulse widths and verifies proper program margin.  
Device erasure occurs by executing the proper erase  
command sequence. This initiates the Embedded Erase  
algorithm  
-
an internal algorithm that automatically  
preprograms the array (if it is not already programmed)  
before executing the erase operation. During erase, the  
device automatically times the erase pulse widths and  
verifies proper erase margin. The Unlock Bypass mode  
facilitates faster programming times by requiring only two  
write cycles to program data instead of four.  
device has separate chip enable (  
), write enable (  
)
WE  
CE  
and output enable (  
) controls.  
OE  
The device requires only a single 3.0 volt power supply for  
both read and write functions. Internally generated and  
regulated voltages are provided for the program and erase  
operations.  
The host system can detect whether a program or erase  
operation is complete by observing the RY /  
pin (not  
BY  
(November, 2010, Version 1.7)  
1
AMIC Technology, Corp.  
A29L004 Series  
available on 32-pin DIP, PLCC & (s)TSOP), or by reading the  
I/O7 ( Polling) and I/O6 (toggle) status bits. After a  
or program data to, any other sector that is not selected for  
erasure. True background erase can thus be achieved.  
Data  
The hardware  
pin terminates any operation in  
RESET  
program or erase cycle has been completed, the device is  
ready to read array data or accept another command.  
The sector erase architecture allows memory sectors to be  
erased and reprogrammed without affecting the data  
contents of other sectors. The A29L004 is fully erased when  
shipped from the factory.  
The hardware sector protection feature disables operations  
for both program and erase in any combination of the  
sectors of memory. This can be achieved via programming  
equipment.  
progress and resets the internal state machine to reading  
array data (not available on 32-pin DIP, PLCC & (s)TSOP).  
The  
pin may be tied to the system reset circuitry. A  
RESET  
system reset would thus also reset the device, enabling the  
system microprocessor to read the boot-up firmware from the  
Flash memory.  
The device offers two power-saving features. When  
addresses have been stable for a specified amount of time,  
the device enters the automatic sleep mode. The system can  
also place the device into the standby mode. Power  
consumption is greatly reduced in both these modes.  
The Erase Suspend/Erase Resume feature enables the user  
to put erase on hold for any period of time to read data from,  
Pin Configurations  
„ 32-pin DIP  
„ 40-pin TSOP  
„ PLCC  
„ 32-pin TSOP (8mm X 20mm)  
„ 32-pin sTSOP (8mm X 13.4mm)  
„ 32-pin sTSOP (8mm X 14mm)  
A11  
A9  
A8  
A13  
A14  
A17  
WE  
VCC  
A18  
A16  
1
2
3
4
5
6
7
8
9
10  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
OE  
A10  
CE  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
A7  
5
29  
28  
27  
26  
A14  
A13  
A8  
A6  
A5  
6
7
A29L004V (8mm X 20mm)  
A29L004X (8mm X 13.4mm)  
A29L004Y (8mm X 14mm)  
GND  
I/O2  
A9  
A4  
A3  
A2  
A1  
8
A29L004L  
A15  
A12  
A7  
11  
12  
13  
22  
21  
20  
I/O1  
I/O0  
A0  
25  
24  
A11  
9
10  
11  
OE  
A6  
A5  
A4  
14  
15  
16  
19  
18  
17  
A1  
A2  
A3  
23  
22  
21  
A10  
A0  
12  
13  
CE  
I/O7  
I/O0  
(November, 2010, Version 1.7)  
2
AMIC Technology, Corp.  
A29L004 Series  
Block Diagram  
RY/BY (N/A 32-pin PLCC, (s)TSOP)  
I/O0 - I/O7  
VCC  
VSS  
Sector Switches  
Input/Output  
Buffers  
Erase Voltage  
Generator  
RESET  
(N/A 32-pin PLCC,  
(s)TSOP)  
State  
Control  
WE  
PGM Voltage  
Generator  
Command  
Register  
Chip Enable  
Output Enable  
Logic  
STB  
Data Latch  
CE  
OE  
Y-Decoder  
Y-Gating  
STB  
VCC Detector  
Timer  
A0-A18  
X-decoder  
Cell Matrix  
Pin Descriptions  
Pin No.  
A0 - A18  
I/O0 - I/O7  
Description  
Address Inputs  
Data Inputs/Outputs  
Chip Enable  
CE  
WE  
Write Enable  
Output Enable  
OE  
Hardware Reset (N/A 32-pin DIP, PLCC, (s)TSOP)  
RESET  
Ready/  
- Output (N/A 32-pin DIP, PLCC, (s)TSOP)  
BUSY  
RY/  
BY  
VSS  
Ground  
VCC  
NC  
Power Supply  
Pin not connected internally  
(November, 2010, Version 1.7)  
3
AMIC Technology, Corp.  
A29L004 Series  
Absolute Maximum Ratings*  
Notes:  
1. Minimum DC voltage on input or I/O pins is -0.5V. During  
voltage transitions, input or I/O pins may undershoot VSS  
to -2.0V for periods of up to 20ns. Maximum DC voltage  
on input and I/O pins is VCC +0.5V. During voltage  
transitions, input or I/O pins may overshoot to VCC +2.0V  
for periods up to 20ns.  
Storage Temperature Plastic Packages . …… .0°C to + 70°C  
Ambient Temperature with Power Applied…… 0°C to + 70°C  
Voltage with Respect to Ground  
VCC (Note 1) . . . . . . . . . . . . . . . . . . . …... . . . -0.5V to +4.0V  
A9,  
&
(Note 2) . . . . . . . . . . ….. . -0.5 to +12.5V  
RESET  
OE  
All other pins (Note 1) . . . . . . . . . . . ….. -0.5V to VCC + 0.5V  
Output Short Circuit Current (Note 3) . . . . . . . ….. … 200mA  
Moisture Sensitivity Level (MSL) ….IPC/JEDEC J-STD-020C  
2. Minimum DC input voltage on A9,  
and  
is  
-
OE  
RESET  
and  
0.5V. During voltage transitions, A9,  
OE  
RESET  
-
-
-
-
IR Reflow Cycle : 3 Cycles  
Peak 260°C , 10 seconds  
255°C, 20-40 seconds  
may overshoot VSS to -2.0V for periods of up to 20ns.  
Maximum DC input voltage on A9 is +12.5V which may  
overshoot to 14.0V for periods up to 20ns. (  
N/A on 32-pin DIP, PLCC & (s)TSOP)  
is  
RESET  
220°C, 70 seconds upward  
3. No more than one output is shorted at a time. Duration of  
the short circuit should not be greater than one second.  
Operating Ranges  
*Comments  
Commercial (C) Devices  
Stresses above those listed under "Absolute Maximum  
Ratings" may cause permanent damage to this device.  
These are stress ratings only. Functional operation of  
this device at these or any other conditions above  
those indicated in the operational sections of these  
specification is not implied or intended. Exposure to  
the absolute maximum rating conditions for extended periods  
may affect device reliability.  
Ambient Temperature (TA) . . . . . . . ….. . . . . . . 0°C to +70°C  
VCC Supply Voltages  
VCC for all devices . . . . . . . . . . . . . . . ….. . . +2.7V to +3.6V  
Operating ranges define those limits between which the  
functionally of the device is guaranteed.  
Device Bus Operations  
This section describes the requirements and use of the  
device bus operations, which are initiated through the  
internal command register. The command register itself does  
not occupy any addressable memory location. The register is  
composed of latches that store the commands, along with  
the address and data information needed to execute the  
command. The contents of the register serve as inputs to the  
internal state machine. The state machine outputs dictate the  
function of the device. The appropriate device bus operations  
table lists the inputs and control levels required, and the  
resulting output. The following subsections describe each of  
these operations in further detail.  
Table 1. A29L004 Device Bus Operations  
Operation  
A0 – A18  
I/O0 - I/O7  
WE  
CE  
OE  
RESET  
(N/A 32-pin DIP, PLCC, (s)TSOP)  
Read  
L
L
H
X
H
X
H
H
L
H
AIN  
AIN  
X
DOUT  
DIN  
Write  
L
H
CMOS Standby  
Output Disable  
Hardware Reset  
X
H
X
L
High-Z  
High-Z  
High-Z  
DIN  
VCC ± 0.3 V  
VCC ± 0.3 V  
L
X
L
H
L
X
X
Sector Protect  
(See Note 2)  
VID  
Sector Address, A6=L,  
A1=H, A0=L  
Sector Unprotect  
(See Note 2)  
L
H
X
L
VID  
VID  
Sector Address,  
A6=H, A1=H, A0=L  
DIN  
DIN  
Temporary Sector  
Unprotect  
X
X
AIN  
Legend:  
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In  
Notes:  
1. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.  
2. This function is not available on 32-pin DIP, PLCC & (s)TSOP packages.  
(November, 2010, Version 1.7)  
4
AMIC Technology, Corp.  
A29L004 Series  
Requirements for Reading Array Data  
The device enters the CMOS standby mode when the  
&
CE  
pins (  
only on 32-pin DIP, PLCC & (s)TSOP  
CE  
packages) are both held at VCC ± 0.3V. (Note that this is a  
more restricted voltage range than VIH.) If and  
RESET  
To read array data from the outputs, the system must drive the  
and  
pins to VIL.  
is the power control and selects  
CE  
OE  
OE  
the output pins.  
CE  
is the output control and gates array data to  
should remain at VIH all the time during  
CE  
RESET  
the device.  
(N/A on 32-pin DIP, PLCC & (s)TSOP packages) are held at  
VIH, but not within VCC ± 0.3V, the device will be in the  
standby mode, but the standby current will be greater. The  
device requires the standard access time (tCE) before it is  
ready to read data.  
If the device is deselected during erasure or programming, the  
device draws active current until the operation is completed.  
ICC3 and ICC4 in the DC Characteristics tables represent the  
standby current specification.  
WE  
read operation. The internal state machine is set for reading  
array data upon device power-up, or after a hardware reset.  
This ensures that no spurious alteration of the memory content  
occurs during the power transition. No command is necessary  
in this mode to obtain array data. Standard microprocessor  
read cycles that assert valid addresses on the device address  
inputs produce valid data on the device data outputs. The  
device remains enabled for read access until the command  
register contents are altered.  
Automatic Sleep Mode  
See "Reading Array Data" for more information. Refer to the  
AC Read Operations table for timing specifications and to the  
Read Operations Timings diagram for the timing waveforms,  
lCC1 in the DC Characteristics table represents the active  
current specification for reading array data.  
The automatic sleep mode minimizes Flash device energy  
consumption. The device automatically enables this mode  
when addresses remain stable for tACC +30ns. The automatic  
sleep mode is independent of the  
,
and  
control  
OE  
WE  
CE  
signals. Standard address access timings provide new data  
when addresses are changed. While in sleep mode, output  
data is latched and always available to the system. ICC4 in the  
DC Characteristics table represents the automatic sleep mode  
current specification.  
Writing Commands/Command Sequences  
To write a command or command sequence (which includes  
programming data to the device and erasing sectors of  
memory), the system must drive  
and  
to VIL, and  
CE  
WE  
Output Disable Mode  
to VIH. The device features an Unlock Bypass mode to  
OE  
facilitate faster programming. Once the device enters the  
Unlock Bypass mode, only two write cycles are required to  
program a byte, instead of four.  
The “Byte Program Command Sequence” section has details  
on programming data to the device using both standard and  
Unlock Bypass command sequence. An erase operation can  
erase one sector, multiple sectors, or the entire device. The  
Sector Address Tables indicate the address range that each  
sector occupies. A "sector address" consists of the address  
inputs required to uniquely  
When the  
input is at VIH, output from the device is  
OE  
disabled. The output pins are placed in the high impedance  
state.  
: Hardware Reset Pin (N/A on 32-pin DIP, PLCC &  
RESET  
(s)TSOP packages)  
The pin provides a hardware method of resetting the  
RESET  
device to reading array data. When the system drives the  
pin low for at least a period of tRP, the device  
RESET  
select a sector. See the "Command Definitions" section for  
immediately terminates any operation in progress, tristates all  
data output pins, and ignores all read/write attempts for the  
duration of the  
details on erasing  
a
sector or the entire chip, or  
suspending/resuming the erase operation.  
pulse. The device also resets the  
RESET  
After the system writes the autoselect command sequence,  
the device enters the autoselect mode. The system can then  
read autoselect codes from the internal register (which is  
separate from the memory array) on I/O7 - I/O0. Standard read  
cycle timings apply in this mode. Refer to the "Autoselect  
Mode" and "Autoselect Command Sequence" sections for  
more information.  
ICC2 in the DC Characteristics table represents the active  
current specification for the write mode. The "AC  
Characteristics" section contains timing specification tables  
and timing diagrams for write operations.  
internal state machine to reading array data. The operation  
that was interrupted should be reinitiated once the device is  
ready to accept another command sequence, to ensure data  
integrity.  
Current is reduced for the duration of the  
pulse.  
RESET  
When  
is held at VSS ± 0.3V, the device draws CMOS  
RESET  
standby current (ICC4 ). If  
is held at VIL but not within  
RESET  
VSS ± 0.3V, the standby current will be greater.  
The pin may be tied to the system reset circuitry. A  
RESET  
system reset would thus also reset the Flash memory,  
enabling the system to read the boot-up firmware from the  
Flash memory.  
Program and Erase Operation Status  
If  
is asserted during a program or erase operation,  
RESET  
the RY/  
During an erase or program operation, the system may check  
the status of the operation by reading the status bits on I/O7 -  
I/O0. Standard read cycle timings and ICC read specifications  
apply. Refer to "Write Operation Status" for more information,  
and to each AC Characteristics section for timing diagrams.  
pin remains a “0” (busy) until the internal reset  
BY  
operation is complete, which requires a time tREADY (during  
Embedded Algorithms). The system can thus monitor RY/  
BY  
to determine whether the reset operation is complete. If  
is asserted when a program or erase operation is not  
Standby Mode  
RESET  
executing (RY/  
pin is “1”), the reset operation is completed  
BY  
within a time of tREADY (not during Embedded Algorithms). The  
system can read data tRH after the pin return to VIH.  
When the system is not reading or writing to the device, it can  
place the device in the standby mode. In this mode, current  
consumption is greatly reduced, and the outputs are placed in  
RESET  
Refer to the AC Characteristics tables for  
and diagram.  
parameters  
RESET  
the high impedance state, independent of the  
input.  
OE  
(November, 2010, Version 1.7)  
5
AMIC Technology, Corp.  
A29L004 Series  
Table 2. A29L004 Top Boot Block Sector Address Table  
Sector  
A18  
A17  
A16  
A15  
A14  
A13  
Sector Size  
(Kbytes)  
Address Range  
(in hexadecimal)  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
64  
64  
64  
64  
64  
64  
64  
32  
8
00000h - 0FFFFh  
10000h - 1FFFFh  
20000h - 2FFFFh  
30000h - 3FFFFh  
40000h - 4FFFFh  
50000h - 5FFFFh  
60000h - 6FFFFh  
70000h - 77FFFh  
78000h - 79FFFh  
7A000h - 7BFFFh  
7C000h - 7FFFFh  
1
1
0
1
8
1
1
X
16  
Table 3. A29L004 Bottom Boot Block Sector Address Table  
Sector  
A18  
A17  
A16  
A15  
A14  
A13  
Sector Size  
(Kbytes)  
Address Range  
(in hexadecimal)  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
X
0
16  
8
00000h - 03FFFh  
04000h - 05FFFh  
06000h - 07FFFh  
08000h - 0FFFFh  
10000h - 1FFFFh  
20000h - 2FFFFh  
30000h - 3FFFFh  
40000h - 4FFFFh  
50000h - 5FFFFh  
60000h - 6FFFFh  
70000h - 7FFFFh  
0
1
1
8
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32  
64  
64  
64  
64  
64  
64  
64  
X
X
X
X
X
X
X
(November, 2010, Version 1.7)  
6
AMIC Technology, Corp.  
A29L004 Series  
Autoselect Mode  
The autoselect mode provides manufacturer and device  
identification, and sector protection verification, through  
identifier codes output on I/O7 - I/O0. This mode is primarily  
intended for programming equipment to automatically match  
on the appropriate highest order address bits. Refer to the  
corresponding Sector Address Tables. The Command  
Definitions table shows the remaining address bits that are  
don't care. When all necessary bits have been set as  
required, the programming equipment may then read the  
corresponding identifier code on I/O7 - I/O0.To access the  
autoselect codes in-system, the host system can issue the  
autoselect command via the command register, as shown in  
the Command Definitions table. This method does not  
require VID. See "Command Definitions" for details on using  
the autoselect mode.  
a
device to be programmed with its corresponding  
programming algorithm. However, the autoselect codes can  
also be accessed in-system through the command register.  
When using programming equipment, the autoselect mode  
requires VID (11.5V to 12.5 V) on address pin A9. Address  
pins A6, A1, and A0 must be as shown in Autoselect  
Codes (High Voltage Method) table. In addition, when  
verifying sector protection, the sector address must appear  
Table 4. A29L004 Autoselect Codes (High Voltage Method)  
Description  
A18 A12  
to to  
A13 A10  
A9  
A8  
to  
A7  
X
A6  
A5  
to  
A2  
X
A1  
A0  
I/O7  
to  
WE  
CE  
OE  
I/O0  
37h  
Manufacturer ID: AMIC  
Device ID: A29L004  
L
L
L
L
H
H
X
X
X
X
VID  
VID  
L
L
L
L
L
X
X
H
34h  
(Top Boot Block)  
Device ID: A29L004  
(Bottom Boot Block)  
B5h  
7Fh  
L
L
L
L
H
H
X
X
X
X
VID  
X
X
L
L
X
X
L
H
H
Continuation ID  
VID  
H
01h  
(protected)  
Sector Protection Verification  
L
L
H
SA  
X
VID  
X
L
X
H
L
00h  
(unprotected)  
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.  
Note: The autoselect codes may also be accessed in-system via command sequences.  
(November, 2010, Version 1.7)  
7
AMIC Technology, Corp.  
A29L004 Series  
Sector Protection/Unprotection  
Temporary Sector Unprotect (N/A on 32-pin DIP,  
PLCC & (s)TSOP packages)  
The hardware sector protection feature disables both  
program and erase operations in any sector. The hardware  
sector unprotection feature re-enables both program and  
erase operations in previously protected sectors.  
It is possible to determine whether a sector is protected or  
unprotected. See “Autoselect Mode” for details.  
This feature allows temporary unprotection of previous  
protected sectors to change data in-system. The Sector  
Unprotect mode is activated by setting the  
pin to VID.  
RESET  
During this mode, formerly protected sectors can be  
programmed or erased by selecting the sector addresses.  
Sector protection / unprotection can be implemented via two  
methods. The primary method requires VID on the  
Once VID is removed from the  
pin, all the previously  
RESET  
protected sectors are protected again. Figure 1 shows the  
algorithm, and the Temporary Sector Unprotect diagram  
shows the timing waveforms, for this feature.  
pin only (N/A on 32-pin DIP, PLCC & (s)TSOP  
RESET  
packages), and can be implemented either in-system or via  
programming equipment. Figure 2 shows the algorithm and  
the Sector Protect / Unprotect Timing Diagram illustrates the  
timing waveforms for this feature. This method uses standard  
microprocessor bus cycle timing. For sector unprotect, all  
unprotected sectors must first be protected prior to the first  
sector unprotect write cycle. The alternate method must be  
implemented using programming equipment. The procedure  
requires a high voltage (VID) on address pin A9 and the  
control pins.  
START  
RESET = VID  
(Note 1)  
The device is shipped with all sectors unprotected.  
It is possible to determine whether a sector is protected or  
unprotected. See "Autoselect Mode" for details.  
Hardware Data Protection  
Perform Erase or  
Program Operations  
The requirement of command unlocking sequence for  
programming or erasing provides data protection against  
inadvertent writes (refer to the Command Definitions table).  
In addition, the following hardware data protection measures  
prevent accidental erasure or programming, which might  
otherwise be caused by spurious system level signals during  
VCC power-up transitions, or from system noise. The device  
is powered up to read array data to avoid accidentally writing  
data to the array.  
RESET = VIH  
Write Pulse "Glitch" Protection  
Temporary Sector  
Unprotect  
Completed (Note 2)  
Noise pulses of less than 5ns (typical) on  
do not initiate a write cycle.  
,
or  
OE CE  
WE  
Logical Inhibit  
Notes:  
Write cycles are inhibited by holding any one of  
=VIL,  
OE  
CE  
1. All protected sectors unprotected.  
2. All previously protected sectors are protected once again.  
= VIH or  
= VIH. To initiate a write cycle,  
and  
WE  
CE  
must be a logical zero while  
is a logical one.  
WE  
OE  
Figure 1. Temporary Sector Unprotect Operation  
Power-Up Write Inhibit  
If  
=
= VIL and  
= VIH during power up, the  
OE  
WE  
device does not accept commands on the rising edge of  
. The internal state machine is automatically reset to  
CE  
WE  
reading array data on the initial power-up.  
(November, 2010, Version 1.7)  
8
AMIC Technology, Corp.  
A29L004 Series  
START  
START  
Protect all sectors:  
The indicated portion of  
the sector protect  
PLSCNT=1  
PLSCNT=1  
algorithm must be  
performed for all  
RESET=VID  
RESET=VID  
unprotected sectors prior  
to issuing the first sector  
unprotect address  
Wait 1 us  
Wait 1 us  
No  
No  
No  
Temporary Sector  
Unprotect Mode  
First Write  
Cycle=60h?  
First Write  
Cycle=60h?  
Temporary Sector  
Unprotect Mode  
Yes  
Yes  
Set up sector  
address  
All sectors  
protected?  
Sector Protect  
Write 60h to sector  
address with A6=0,  
A1=1, A0=0  
Yes  
Set up first sector  
address  
Sector Unprotect:  
Write 60h to sector  
address with A6=1,  
A1=1, A0=0  
Wait 150 us  
Verify Sector  
Protect: Write 40h  
to sector address  
with A6=0, A1=1,  
A0=0  
Reset  
PLSCNT=1  
Increment  
PLSCNT  
Wait 15 ms  
Verify Sector  
Unprotect : Write  
40h to sector  
address with A6=1,  
A1=1, A0=0  
Read from  
sector address  
with A6=0,  
Increment  
PLSCNT  
A1=1, A0=0  
No  
Read from sector  
address with A6=1,  
A1=1, A0=0  
No  
PLSCNT  
=25?  
Data=01h?  
Yes  
No  
Set up  
next sector  
address  
Yes  
No  
PLSCNT=  
1000?  
Yes  
Data=00h?  
Yes  
Protect another  
sector?  
Device failed  
Yes  
No  
Remove VID  
from RESET  
No  
Last sector  
verified?  
Device failed  
Write reset  
command  
Yes  
Remove VID  
from RESET  
Sector Protect  
complete  
Sector Protect  
Algorithm  
Sector Unprotect  
Algorithm  
Write reset  
Command  
Sector Unprotect  
complete  
Figure 2. In-System Sector Protect/Unprotect Algorithms  
(November, 2010, Version 1.7)  
9
AMIC Technology, Corp.  
A29L004 Series  
Command Definitions  
Autoselect Command Sequence  
Writing specific address and data commands or sequences  
into the command register initiates device operations. The  
Command Definitions table defines the valid register  
command sequences. Writing incorrect address and data  
values or writing them in the improper sequence resets the  
device to reading array data.  
The autoselect command sequence allows the host system to  
access the manufacturer and devices codes, and determine  
whether or not a sector is protected. The Command  
Definitions table shows the address and data requirements.  
This method is an alternative to that shown in the Autoselect  
Codes (High Voltage Method) table, which is intended for  
PROM programmers and requires VID on address bit A9.  
The autoselect command sequence is initiated by writing two  
unlock cycles, followed by the autoselect command. The  
device then enters the autoselect mode, and the system may  
read at any address any number of times, without initiating  
another command sequence.  
All addresses are latched on the falling edge of  
or  
,
CE  
WE  
whichever happens later. All data is latched on the rising  
edge of or , whichever happens first. Refer to the  
WE  
CE  
appropriate timing diagrams in the "AC Characteristics"  
section.  
A read cycle at address XX00h retrieves the manufacturer  
code and another read cycle at XX03h retrieves the  
continuation code. A read cycle at address XX01h returns the  
device code. A read cycle containing a sector address (SA)  
and the address 02h in returns 01h if that sector is protected,  
or 00h if it is unprotected. Refer to the Sector Address tables  
for valid sector addresses.  
Reading Array Data  
The device is automatically set to reading array data after  
device power-up. No commands are required to retrieve  
data. The device is also ready to read array data after  
completing an Embedded Program or Embedded Erase  
algorithm. After the device accepts an Erase Suspend  
command, the device enters the Erase Suspend mode. The  
system can read array data using the standard read timings,  
except that if it reads at an address within erase-suspended  
sectors, the device outputs status data. After completing a  
programming operation in the Erase Suspend mode, the  
system may once again read array data with the same  
exception. See "Erase Suspend/Erase Resume Commands"  
for more information on this mode.  
The system must issue the reset command to re-enable the  
device for reading array data if I/O5 goes high, or while in the  
autoselect mode. See the "Reset Command" section, next.  
See also "Requirements for Reading Array Data" in the  
"Device Bus Operations" section for more information. The  
Read Operations table provides the read parameters, and  
Read Operation Timings diagram shows the timing diagram.  
The system must write the reset command to exit the  
autoselect mode and return to reading array data.  
Byte Program Command Sequence  
Programming is a four-bus-cycle operation. The program  
command sequence is initiated by writing two unlock write  
cycles, followed by the program set-up command. The  
program address and data are written next, which in turn  
initiate the Embedded Program algorithm. The system is not  
required to provide further controls or timings. The device  
automatically provides internally generated program pulses  
and verify the programmed cell margin. Table 5 shows the  
address and data requirements for the byte program  
command sequence.  
When the Embedded Program algorithm is complete, the  
device then returns to reading array data and addresses are  
longer latched. The system can determine the status of the  
Reset Command  
Writing the reset command to the device resets the device to  
reading array data. Address bits are don't care for this  
command. The reset command may be written between the  
sequence cycles in an erase command sequence before  
erasing begins. This resets the device to reading array data.  
Once erasure begins, however, the device ignores reset  
commands until the operation is complete.  
program operation by using I/O7, I/O6, or RY/  
pin DIP, PLCC & (s)TSOP packages). See “Write Operation  
Status” for information on these status bits.  
Any commands written to the device during the Embedded  
Program Algorithm are ignored. Note that a hardware reset  
immediately terminates the programming operation. The Byte  
Program command sequence should be reinitiated once the  
device has reset to reading array data, to ensure data  
integrity.  
(N/A on 32-  
BY  
The reset command may be written between the sequence  
cycles in  
a
program command sequence before  
programming begins. This resets the device to reading array  
data (also applies to programming in Erase Suspend mode).  
Once programming begins, however, the device ignores  
reset commands until the operation is complete.  
The reset command may be written between the sequence  
cycles in an autoselect command sequence. Once in the  
autoselect mode, the reset command must be written to  
return to reading array data (also applies to autoselect during  
Erase Suspend).  
Programming is allowed in any sequence and across sector  
boundaries. A bit cannot be programmed from a “0” back to a  
“1”. Attempting to do so may halt the operation and set I/O5 to  
“1”, or cause the  
Polling algorithm to indicate the  
Data  
operation was successful. However, a succeeding read will  
show that the data is still “0”. Only erase operations can  
convert a “0” to a “1”.  
If I/O5 goes high during a program or erase operation, writing  
the reset command returns the device to reading array data  
(also applies during Erase Suspend).  
(November, 2010, Version 1.7)  
10  
AMIC Technology, Corp.  
A29L004 Series  
00h. Addresses are don’t care for both cycle. The device  
returns to reading array data.  
START  
Figure 3 illustrates the algorithm for the program operation.  
See the Erase/Program Operations in “AC Characteristics” for  
parameters, and to Program Operation Timings for timing  
diagrams.  
Write Program  
Command  
Sequence  
Chip Erase Command Sequence  
Chip erase is a six-bus-cycle operation. The chip erase  
command sequence is initiated by writing two unlock cycles,  
followed by a set-up command. Two additional unlock write  
cycles are then followed by the chip erase command, which  
in turn invokes the Embedded Erase algorithm. The device  
does not require the system to preprogram prior to erase. The  
Embedded Erase algorithm automatically preprograms and  
verifies the entire memory for an all zero data pattern prior to  
electrical erase. The system is not required to provide any  
controls or timings during these operations. The Command  
Definitions table shows the address and data requirements  
for the chip erase command sequence.  
Any commands written to the chip during the Embedded  
Erase algorithm are ignored. The system can determine the  
status of the erase operation by using I/O7, I/O6, or I/O2. See  
"Write Operation Status" for information on these status bits.  
When the Embedded Erase algorithm is complete, the device  
returns to reading array data and addresses are no longer  
latched.  
Data Poll  
from System  
Embedded  
Program  
algorithm in  
progress  
Verify Data ?  
Yes  
No  
Increment Address  
Last Address ?  
Yes  
Figure 4 illustrates the algorithm for the erase operation. See  
the Erase/Program Operations tables in "AC Characteristics"  
for parameters, and to the Chip/Sector Erase Operation  
Timings for timing waveforms.  
Programming  
Completed  
Sector Erase Command Sequence  
Sector erase is a six-bus-cycle operation. The sector erase  
command sequence is initiated by writing two unlock cycles,  
followed by a set-up command. Two additional unlock write  
cycles are then followed by the address of the sector to be  
erased, and the sector erase command. The Command  
Definitions table shows the address and data requirements  
for the sector erase command sequence.  
Note : See the appropriate Command Definitions table for  
program command sequence.  
Figure 3. Program Operation  
The device does not require the system to preprogram the  
memory prior to erase. The Embedded Erase algorithm  
automatically programs and verifies the sector for an all zero  
data pattern prior to electrical erase. The system is not  
required to provide any controls or timings during these  
operations.  
Unlock Bypass Command Sequence  
The unlock bypass feature allows the system to program  
bytes or words to the device faster than using the standard  
program command sequence. The unlock bypass command  
sequence is initiated by first writing two unlock cycles. This is  
followed by a third write cycle containing the unlock bypass  
command, 20h. The device then enters the unlock bypass  
After the command sequence is written, a sector erase time-  
out of 50μs begins. During the time-out period, additional  
sector addresses and sector erase commands may be  
written. Loading the sector erase buffer may be done in any  
sequence, and the number of sectors may be from one sector  
to all sectors. The time between these additional cycles must  
be less than 50μs, otherwise the last address and command  
might not be accepted, and erasure may begin. It is  
recommended that processor interrupts be disabled during  
this time to ensure all commands are accepted. The  
interrupts can be re-enabled after the last Sector Erase  
command is written. If the time between additional sector  
erase commands can be assumed to be less than 50μs, the  
system need not monitor I/O3. Any command other than  
Sector Erase or Erase Suspend during the time-out period  
resets the device to reading array data. The system must  
rewrite the command sequence and any additional sector  
addresses and commands.  
mode.  
A two-cycle unlock bypass program command  
sequence is all that is required to program in this mode. The  
first cycle in this sequence contains the unlock bypass  
program command, A0h; the second cycle contains the  
program address and data. Additional data is programmed in  
the same manner. This mode dispenses with the initial two  
unlock cycles required in the standard program command  
sequence, resulting in faster total programming time. Table 5  
shows the requirements for the command sequence.  
During the unlock bypass mode, only the Unlock Bypass  
Program and Unlock Bypass Reset commands are valid. To  
exit the unlock bypass mode, the system must issue the two-  
cycle unlock bypass reset command sequence. The first  
cycle must contain the data 90h; the second cycle the data  
(November, 2010, Version 1.7)  
11  
AMIC Technology, Corp.  
A29L004 Series  
The system can monitor I/O3 to determine if the sector erase  
timer has timed out. (See the " I/O3: Sector Erase Timer"  
section.) The time-out begins from the rising edge of the final  
The system may also write the autoselect command  
sequence when the device is in the Erase Suspend mode.  
The device allows reading autoselect codes even at  
addresses within erasing sectors, since the codes are not  
stored in the memory array. When the device exits the  
autoselect mode, the device reverts to the Erase Suspend  
mode, and is ready for another valid operation. See  
"Autoselect Command Sequence" for more information.  
The system must write the Erase Resume command  
(address bits are "don't care") to exit the erase suspend  
mode and continue the sector erase operation. Further writes  
of the Resume command are ignored. Another Erase  
Suspend command can be written after the device has  
resumed erasing.  
pulse in the command sequence.  
WE  
Once the sector erase operation has begun, only the Erase  
Suspend command is valid. All other commands are ignored.  
When the Embedded Erase algorithm is complete, the device  
returns to reading array data and addresses are no longer  
latched. The system can determine the status of the erase  
operation by using I/O7, I/O6, or I/O2. Refer to "Write  
Operation Status" for information on these status bits.  
4 illustrates the algorithm for the erase operation. Refer to  
the Erase/Program Operations tables in the "AC  
Characteristics" section for parameters, and to the Sector  
Erase Operations Timing diagram for timing waveforms.  
Erase Suspend/Erase Resume Commands  
START  
The Erase Suspend command allows the system to interrupt  
a sector erase operation and then read data from, or  
program data to, any sector not selected for erasure. This  
command is valid only during the sector erase operation,  
including the 50μs time-out period during the sector erase  
command sequence. The Erase Suspend command is  
ignored if written during the chip erase operation or  
Embedded Program algorithm. Writing the Erase Suspend  
command during the Sector Erase time-out immediately  
terminates the time-out period and suspends the erase  
operation. Addresses are "don't cares" when writing the  
Erase Suspend command.  
Write Erase  
Command  
Sequence  
Data Poll  
from System  
Embedded  
Erase  
When the Erase Suspend command is written during a  
sector erase operation, the device requires a maximum of  
20μs to suspend the erase operation. However, when the  
Erase Suspend command is written during the sector erase  
time-out, the device immediately terminates the time-out  
period and suspends the erase operation.  
algorithm in  
progress  
No  
Data = FFh ?  
After the erase operation has been suspended, the system  
can read array data from or program data to any sector not  
selected for erasure. (The device "erase suspends" all  
sectors selected for erasure.) Normal read and write timings  
and command definitions apply. Reading at any address  
within erase-suspended sectors produces status data on I/O7  
- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to  
determine if a sector is actively erasing or is erase-  
suspended. See "Write Operation Status" for information on  
these status bits.  
Yes  
Erasure Completed  
Note :  
1. See the appropriate Command Definitions table for erase  
command sequences.  
After an erase-suspended program operation is complete,  
the system can once again read array data within non-  
suspended sectors. The system can determine the status of  
the program operation using the I/O7 or I/O6 status bits, just  
as in the standard program operation. See "Write Operation  
Status" for more information.  
2. See "I/O  
3
: Sector Erase Timer" for more information.  
Figure 4. Erase Operation  
(November, 2010, Version 1.7)  
12  
AMIC Technology, Corp.  
A29L004 Series  
Table 5. A29L004 Command Definitions  
Command Sequence  
(Note 1)  
Bus Cycles (Notes 2 - 5)  
Third Fourth  
Addr Data Addr Data Addr Data Addr Data  
First  
Addr Data Addr Data  
RA RD  
Second  
Fifth  
Sixth  
Read (Note 6)  
Reset (Note 7)  
Manufacturer ID  
1
1
4
XXX F0  
555 AA  
2AA 55  
2AA 55  
555  
555  
90 X00  
37  
34  
Device ID,  
4
555 AA  
90  
X01  
Top Boot Block  
Device ID,  
4
4
555 AA  
555 AA  
2AA  
55  
555  
90  
X01  
X03  
B5  
7F  
Bottom Boot Block  
Continuation ID  
2AA 55  
555 90  
555 90  
Sector Protect Verify  
(Note 9)  
(SA) XX00  
4
555 AA  
555 AA  
2AA 55  
X02  
PA  
XX01  
PD  
Program  
4
3
2AA 55  
2AA 55  
555 A0  
555 20  
Unlock Bypass  
555  
AA  
Unlock Bypass Program (Note 10)  
Unlock Bypass Reset (Note 11)  
Chip Erase  
2
2
6
6
XXX A0  
XXX 90  
555 AA  
PA  
PD  
00  
XXX  
2AA 55  
2AA 55  
555 80  
555  
AA  
2AA 55  
2AA 55  
555  
SA  
10  
30  
Sector Erase  
555  
AA  
555  
80  
555 AA  
Erase Suspend (Note 12)  
Erase Resume (Note 13)  
1
1
XXX B0  
XXX 30  
Legend:  
X = Don't care  
RA = Address of the memory location to be read.  
RD = Data read from location RA during read operation.  
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the  
whichever happens later.  
or  
pulse,  
CE  
WE  
PD = Data to be programmed at location PA. Data latches on the rising edge of  
or  
pulse, whichever happens first.  
CE  
WE  
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A13 select a unique sector.  
Note:  
1. See Table 1 for description of bus operations.  
2. All values are in hexadecimal.  
3. Except when reading array or autoselect data, all bus cycles are write operation.  
4. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required.  
5. No unlock or command cycles required when reading array data.  
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high  
(while the device is providing status data).  
7. The fourth cycle of the autoselect command sequence is a read cycle.  
8. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more  
information.  
9. The Unlock Bypass command is required prior to the Unlock Bypass Program command.  
10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass  
mode.  
11. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.  
12. The Erase Resume command is valid only during the Erase Suspend mode.  
(November, 2010, Version 1.7)  
13  
AMIC Technology, Corp.  
A29L004 Series  
Write Operation Status  
START  
Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/  
the A29L004 to determine the status of a write operation  
are provided in  
BY  
(RY/ pin is not available on 32-pin DIP, PLCC & (s)TSOP  
BY  
packages). Table 6 and the following subsections describe  
the functions of these status bits. I/O7, I/O6 and RY/ each  
offer a method for determining whether a program or erase  
operation is complete or in progress. These three bits are  
discussed first.  
Read I/O  
Address = VA  
7
-I/O  
0
BY  
I/O7:  
Polling  
Data  
Yes  
I/O7  
= Data ?  
No  
The  
Polling bit, I/O7, indicates to the host system  
Data  
whether an Embedded Algorithm is in progress or completed,  
or whether the device is in Erase Suspend. Polling is  
Data  
pulse in the  
valid after the rising edge of the final  
program or erase command sequence.  
WE  
During the Embedded Program algorithm, the device outputs  
on I/O7 the complement of the datum programmed to I/O7.  
This I/O7 status also applies to programming during Erase  
Suspend. When the Embedded Program algorithm is  
complete, the device outputs the datum programmed to I/O7.  
The system must provide the program address to read valid  
status information on I/O7. If a program address falls within a  
No  
I/O5 = 1?  
Yes  
protected sector,  
approximately 2μs, then the device returns to reading array  
data.  
Polling on I/O7 is active for  
Data  
Read I/O  
Address = VA  
7 - I/O0  
During the Embedded Erase algorithm,  
Polling  
Data  
produces a "0" on I/O7. When the Embedded Erase algorithm  
is complete, or if the device enters the Erase Suspend mode,  
Yes  
Polling produces a "1" on I/O7.This is analogous to the  
Data  
I/O7  
= Data ?  
complement/true datum output described for the Embedded  
Program algorithm: the erase function changes all the bits in  
a sector to "1"; prior to this, the device outputs the  
"complement," or "0." The system must provide an address  
within any of the sectors selected for erasure to read valid  
status information on I/O7.  
No  
After an erase command sequence is written, if all sectors  
FAIL  
PASS  
selected for erasing are protected,  
Polling on I/O7 is  
Data  
active for approximately 100μs, then the device returns to  
reading array data. If not all selected sectors are protected,  
the Embedded Erase algorithm erases the unprotected  
sectors, and ignores the selected sectors that are protected.  
When the system detects I/O7 has changed from the  
complement to true data, it can read valid data at I/O7 - I/O0  
on the following read cycles. This is because I/O7 may  
change asynchronously with I/O0 - I/O6 while Output Enable  
Note :  
1. VA = Valid address for programming. During a sector  
erase operation, a valid address is an address within any  
sector selected for erasure. During chip erase, a valid  
address is any non-protected sector address.  
2. I/O  
7
should be rechecked even if I/O  
may change simultaneously with I/O  
5 = "1" because  
I/O7  
5
.
(
) is asserted low. The  
Polling Timings (During  
Data  
OE  
Embedded Algorithms) in the "AC Characteristics" section  
illustrates this. Table 6 shows the outputs for Polling  
Figure 5. Data Polling Algorithm  
Data  
Polling algorithm.  
on I/O7. Figure 5 shows the  
Data  
(November, 2010, Version 1.7)  
14  
AMIC Technology, Corp.  
A29L004 Series  
sector is erase-suspended. Toggle Bit II is valid after the  
RY/  
: Read/  
(N/A on 32-pin DIP, PLCC &  
Busy  
BY  
rising edge of the final  
I/O2 toggles when the system reads at addresses within  
those sectors that have been selected for erasure. (The  
pulse in the command sequence.  
WE  
(s)TSOP packages)  
The RY/  
is a dedicated, open-drain output pin that  
BY  
indicates whether an Embedded algorithm is in progress or  
complete. The RY/ status is valid after the rising edge of  
system may use either  
or  
to control the read  
CE  
OE  
cycles.) But I/O2 cannot distinguish whether the sector is  
actively erasing or is erase-suspended. I/O6, by comparison,  
indicates whether the device is actively erasing, or is in Erase  
Suspend, but cannot distinguish which sectors are selected  
for erasure. Thus, both status bits are required for sector and  
mode information. Refer to Table 6 to compare outputs for  
I/O2 and I/O6.  
Figure 6 shows the toggle bit algorithm in flowchart form, and  
the section " I/O2: Toggle Bit II" explains the algorithm. See  
also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle  
Bit Timings figure for the toggle bit timing diagram. The I/O2  
vs. I/O6 figure shows the differences between I/O2 and I/O6 in  
graphical form.  
BY  
pulse in the command sequence. Since  
the final  
WE  
RY/  
is an open-drain output, several RY/  
pins can be  
BY  
BY  
tied together in parallel with a pull-up resistor to VCC.  
If the output is low (Busy), the device is actively erasing or  
programming. (This includes programming in the Erase  
Suspend mode.) If the output is high (Ready), the device is  
ready to read array data (including during the Erase Suspend  
mode), or is in the standby mode.  
Table 6 shows the outputs for RY/  
. Refer to “  
RESET  
BY  
Timings”, “Timing Waveforms for Program Operation” and  
“Timing Waveforms for Chip/Sector Erase Operation” for  
more information.  
Reading Toggle Bits I/O6, I/O2  
I/O6: Toggle Bit I  
Refer to Figure 6 for the following discussion. Whenever the  
system initially begins reading toggle bit status, it must read  
I/O7 - I/O0 at least twice in a row to determine whether a  
toggle bit is toggling. Typically, a system would note and  
store the value of the toggle bit after the first read. After the  
second read, the system would compare the new value of the  
toggle bit with the first. If the toggle bit is not toggling, the  
device has completed the program or erase operation. The  
system can read array data on I/O7 - I/O0 on the following  
read cycle.  
Toggle Bit I on I/O6 indicates whether an Embedded Program  
or Erase algorithm is in progress or complete, or whether the  
device has entered the Erase Suspend mode. Toggle Bit I  
may be read at any address, and is valid after the rising edge  
of the final  
pulse in the command sequence (prior to the  
WE  
program or erase operation), and during the sector erase  
time-out.  
During an Embedded Program or Erase algorithm operation,  
successive read cycles to any address cause I/O6 to toggle.  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the system also  
should note whether the value of I/O5 is high (see the section  
on I/O5). If it is, the system should then determine again  
whether the toggle bit is toggling, since the toggle bit may  
have stopped toggling just as I/O5 went high. If the toggle bit  
is no longer toggling, the device has successfully completed  
the program or erase operation. If it is still toggling, the  
device did not complete the operation successfully, and the  
system must write the reset command to return to reading  
array data.  
The remaining scenario is that the system initially determines  
that the toggle bit is toggling and I/O5 has not gone high. The  
system may continue to monitor the toggle bit and I/O5  
through successive read cycles, determining the status as  
described in the previous paragraph. Alternatively, it may  
choose to perform other system tasks. In this case, the  
system must start at the beginning of the algorithm when it  
returns to determine the status of the operation (top of Figure  
6).  
(The system may use either  
or  
to control the read  
CE  
OE  
cycles.) When the operation is complete, I/O6 stops toggling.  
After an erase command sequence is written, if all sectors  
selected for erasing are protected, I/O6 toggles for  
approximately 100μs, then returns to reading array data. If  
not all selected sectors are protected, the Embedded Erase  
algorithm erases the unprotected sectors, and ignores the  
selected sectors that are protected.  
The system can use I/O6 and I/O2 together to determine  
whether a sector is actively erasing or is erase-suspended.  
When the device is actively erasing (that is, the Embedded  
Erase algorithm is in progress), I/O6 toggles. When the  
device enters the Erase Suspend mode, I/O6 stops toggling.  
However, the system must also use I/O2 to determine which  
sectors are erasing or erase-suspended. Alternatively, the  
system can use I/O7 (see the subsection on " I/O7 :  
Polling").  
Data  
If a program address falls within a protected sector, I/O6  
toggles for approximately 2μs after the program command  
sequence is written, then returns to reading array data.  
I/O6 also toggles during the erase-suspend-program mode,  
and stops toggling once the Embedded Program algorithm is  
complete.  
The Write Operation Status table shows the outputs for  
Toggle Bit I on I/O6. Refer to Figure 6 for the toggle bit  
algorithm, and to the Toggle Bit Timings figure in the "AC  
Characteristics" section for the timing diagram. The I/O2 vs.  
I/O6 figure shows the differences between I/O2 and I/O6 in  
graphical form. See also the subsection on " I/O2: Toggle Bit II".  
I/O5: Exceeded Timing Limits  
I/O5 indicates whether the program or erase time has  
exceeded a specified internal pulse count limit. Under these  
conditions I/O5 produces a "1." This is a failure condition that  
indicates the program or erase cycle was not successfully  
completed.  
The I/O5 failure condition may appear if the system tries to  
program a "1 "to a location that is previously programmed to  
"0." Only an erase operation can change a "0" back to a "1."  
Under this condition, the device halts the operation, and  
when the operation has exceeded the timing limits, I/O5  
produces a "1."  
I/O2: Toggle Bit II  
The "Toggle Bit II" on I/O2, when used with I/O6, indicates  
whether a particular sector is actively erasing (that is, the  
Embedded Erase algorithm is in progress), or whether that  
Under both these conditions, the system must issue the  
reset command to return the device to reading array data.  
(November, 2010, Version 1.7)  
15  
AMIC Technology, Corp.  
A29L004 Series  
I/O3: Sector Erase Timer  
After writing a sector erase command sequence, the system  
may read I/O3 to determine whether or not an erase  
operation has begun. (The sector erase timer does not apply  
to the chip erase command.) If additional sectors are  
selected for erasure, the entire time-out also applies after  
each additional sector erase command. When the time-out  
is complete, I/O3 switches from "0" to "1." The system may  
ignore I/O3 if the system can guarantee that the time  
between additional sector erase commands will always be  
less than 50μs. See also the "Sector Erase Command  
Sequence" section.  
START  
Read I/O  
7
-I/O  
0
Read I/O  
7
-I/O  
0
(Note 1)  
After the sector erase command sequence is written, the  
system should read the status on I/O7 (  
Polling) or I/O6  
Data  
(Toggle Bit I) to ensure the device has accepted the  
command sequence, and then read I/O3. If I/O3 is "1", the  
internally controlled erase cycle has begun; all further  
commands (other than Erase Suspend) are ignored until the  
erase operation is complete. If I/O3 is "0", the device will  
accept additional sector erase commands. To ensure the  
command has been accepted, the system software should  
check the status of I/O3 prior to and following each  
subsequent sector erase command. If I/O3 is high on the  
second status check, the last command might not have been  
accepted. Table 6 shows the outputs for I/O3.  
No  
Toggle Bit  
= Toggle ?  
Yes  
No  
I/O5 = 1?  
Yes  
- I/O  
Read I/O  
7
0
(Notes 1,2)  
Twice  
No  
Toggle Bit  
= Toggle ?  
Yes  
Program/Erase  
Operation Not  
Commplete, Write  
Reset Command  
Program/Erase  
Operation Complete  
Notes :  
1. Read toggle bit twice to determine whether or not it is  
toggling. See text.  
2. Recheck toggle bit because it may stop toggling as I/O  
5
changes to "1". See text.  
Figure 6. Toggle Bit Algorithm  
(November, 2010, Version 1.7)  
16  
AMIC Technology, Corp.  
A29L004 Series  
Table 6. Write Operation Status  
I/O7  
I/O6  
I/O5  
I/O3  
I/O2  
RY/  
BY  
Operation  
(Note 1)  
(Note 2)  
(Note 1) (N/A on 32-pin DIP, PLCC  
& (s)TSOP packages)  
Standard  
Mode  
Embedded Program  
Algorithm  
Toggle  
Toggle  
0
0
N/A  
1
No  
toggle  
0
I/O7  
0
Embedded Erase  
Algorithm  
Toggle  
0
No  
toggle  
Erase  
Suspend  
Mode  
Reading within Erase  
Suspended Sector  
1
0
N/A  
Toggle  
1
Reading within Non-  
Erase Suspended Sector  
Data  
I/O7  
Data  
Data  
0
Data  
N/A  
Data  
N/A  
1
0
Erase-Suspend-Program  
Toggle  
Notes:  
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.  
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.  
See “I/O5: Exceeded Timing Limits” for more information.  
Maximum Negative Input Overshoot  
20ns  
20ns  
+0.8V  
-0.5V  
-2.0V  
20ns  
Maximum Positive Input Overshoot  
20ns  
VCC+2.0V  
VCC+0.5V  
2.0V  
20ns  
20ns  
(November, 2010, Version 1.7)  
17  
AMIC Technology, Corp.  
A29L004 Series  
DC Characteristics  
CMOS Compatible  
Parameter  
Symbol  
Parameter Description  
Test Description  
Min.  
Typ.  
Max.  
Unit  
ILI  
Input Load Current  
VIN = VSS to VCC. VCC = VCC Max  
VCC = VCC Max, A9 =12.5V  
±1.0  
35  
μA  
μA  
μA  
ILIT  
ILO  
A9 Input Load Current  
Output Leakage Current  
VOUT = VSS to VCC. VCC = VCC Max  
±1.0  
5 MHz  
4
2
10  
4
VCC Active Read Current  
(Notes 1, 2)  
ICC1  
= VIL,  
= VIH  
OE  
CE  
mA  
1 MHz  
VCC Active Write (Program/Erase)  
Current (Notes 2, 3, 4)  
ICC2  
20  
30  
mA  
= VIL,  
=VIH  
OE  
CE  
CE  
ICC3  
ICC4  
VCC Standby Current (Note 2)  
1
1
1
5
5
μA  
= VIH,  
= VCC ± 0.3V  
RESET  
VCC Standby Current During Reset  
(Note 2) (N/A on 32-pin DIP, PLCC &  
(s)TSOP packages)  
μA  
= VSS ± 0.3V  
RESET  
ICC5  
Automatic Sleep Mode  
(Note 2, 4, 5)  
5
VIH = VCC ± 0.3V; VIL = VSS ± 0.3V  
μA  
VIL  
VIH  
VID  
Input Low Level  
-0.5  
0.8  
V
V
Input High Level  
0.7 x VCC  
VCC + 0.3  
Voltage for Autoselect and  
Temporary Unprotect Sector  
Output Low Voltage  
VCC = 3.3 V  
11.5  
12.5  
0.45  
V
VOL  
VOH1  
VOH2  
IOL = 4.0mA, VCC = VCC Min  
IOH = -2.0 mA, VCC = VCC Min  
IOH = -100 μA, VCC = VCC Min  
V
V
V
0.85 x VCC  
VCC - 0.4  
Output High Voltage  
Notes:  
1. The ICC current listed is typically less than 2 mA/MHz, with  
at VIH. Typical VCC is 3.0V.  
OE  
2. Maximum ICC specifications are tested with VCC = VCC max.  
3. ICC active while Embedded Algorithm (program or erase) is in progress.  
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current  
is 1μA.  
5. Not 100% tested.  
(November, 2010, Version 1.7)  
18  
AMIC Technology, Corp.  
A29L004 Series  
DC Characteristics (continued)  
Zero Power Flash  
25  
20  
15  
10  
5
0
0
500  
1000  
1500  
2000  
2500  
3000  
3500  
4000  
Time in ns  
Note: Addresses are switching at 1MHz  
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)  
10  
8
3.6V  
2.7V  
6
4
2
0
1
2
3
4
5
Frequency in MHz  
Note : T = 25°C  
Typical ICC1 vs. Frequency  
(November, 2010, Version 1.7)  
19  
AMIC Technology, Corp.  
A29L004 Series  
AC Characteristics  
Read Only Operations  
Parameter Symbols  
Description  
Test Setup  
Speed  
Unit  
JEDEC  
Std  
-70  
-90  
Read Cycle Time (Note 1)  
Address to Output Delay  
tAVAV  
tRC  
Min.  
70  
90  
ns  
= VIL  
tAVQV  
tACC  
CE  
Max.  
70  
90  
ns  
= VIL  
OE  
Chip Enable to Output Delay  
Output Enable to Output Delay  
tELQV  
tGLQV  
tCE  
Max.  
Max.  
Min.  
70  
30  
0
90  
35  
0
ns  
ns  
ns  
= VIL  
OE  
tOE  
Read  
Output Enable Hold  
tOEH  
Toggle and  
Polling  
Time (Note 1)  
ns  
Min.  
10  
25  
10  
30  
Data  
Chip Enable to Output High Z  
(Notes 1)  
tEHQZ  
tGHQZ  
tDF  
tDF  
Max.  
ns  
ns  
Output Enable to Output High Z  
(Notes 1)  
25  
0
30  
0
Output Hold Time from Addresses,  
tAXQX  
tOH  
Min.  
ns  
or  
, Whichever Occurs First  
CE OE  
(Note 1)  
Notes:  
1. Not 100% tested.  
2. See Test Conditions and Test Setup for test specifications.  
Timing Waveforms for Read Only Operation  
t
RC  
Addresses  
Addresses Stable  
t
ACC  
CE  
OE  
t
DF  
t
OE  
t
OEH  
WE  
t
CE  
t
OH  
High-Z  
High-Z  
Output  
Output Valid  
RESET  
RY/BY  
0V  
(November, 2010, Version 1.7)  
20  
AMIC Technology, Corp.  
A29L004 Series  
AC Characteristics  
Hardware Reset (  
Parameter  
, N/A on 32-pin DIP, PLCC & (s)TSOP packages)  
RESET  
Description  
Test Setup  
All Speed Options  
Unit  
JEDEC  
Std  
Pin Low (During Embedded  
Algorithms) to Read or Write (See Note)  
RESET  
tREADY  
Max  
20  
μs  
Pin Low (Not During Embedded  
RESET  
Algorithms) to Read or Write (See Note)  
tREADY  
Max  
500  
ns  
tRP  
tRH  
Min  
Min  
Min  
Min  
500  
50  
0
ns  
ns  
ns  
μs  
Pulse Width  
RESET  
RESET  
High Time Before Read (See Note)  
Recovery Time  
tRB  
RY/  
BY  
tRPD  
20  
Low to Standby Mode  
RESET  
Note: Not 100% tested.  
Timings  
RESET  
RY/BY  
CE, OE  
RESET  
t
RH  
t
RP  
tReady  
Reset Timings NOT during Embedded Algorithms  
Reset Timings during Embedded Algorithms  
tReady  
RY/BY  
t
RB  
CE, OE  
RESET  
t
RP  
(November, 2010, Version 1.7)  
21  
AMIC Technology, Corp.  
A29L004 Series  
Temporary Sector Unprotect (N/A on 32-pin DIP, PLCC & (s)TSOP packages)  
Parameter  
Description  
All Speed Options  
Unit  
ns  
JEDEC  
Std  
tVIDR  
VID Rise and Fall Time (See Note)  
Min  
Min  
500  
4
Setup Time for Temporary Sector  
RESET  
Unprotect  
tRSP  
μs  
Note: Not 100% tested.  
Temporary Sector Unprotect Timing Diagram  
12V  
0 or 3V  
RESET  
0 or 3V  
t
VIDR  
tVIDR  
Program or Erase Command Sequence  
CE  
WE  
t
RSP  
RY/BY  
(November, 2010, Version 1.7)  
22  
AMIC Technology, Corp.  
A29L004 Series  
AC Characteristics  
Erase and Program Operations  
Parameter  
Description  
Speed  
Unit  
JEDEC  
Std  
-70  
-90  
tAVAV  
tAVWL  
tWC  
tAS  
Write Cycle Time (Note 1)  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
70  
90  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
0
tWLAX  
tDVWH  
tWHDX  
tAH  
45  
35  
45  
45  
tDS  
tDH  
Data Hold Time  
0
0
0
tOES  
tGHWL  
Output Enable Setup Time  
tGHWL  
Read Recover Time Before Write  
high to low)  
(
WE  
OE  
tELWL  
tWHEH  
tWLWH  
tWHWL  
tWHWH1  
tCS  
tCH  
Min.  
Min.  
Min.  
Min.  
Typ.  
0
0
ns  
ns  
ns  
ns  
μs  
Setup Time  
Hold Time  
CE  
CE  
tWP  
Write Pulse Width  
35  
35  
tWPH  
tWHWH1  
Write Pulse Width High  
30  
17  
Byte Programming Operation  
(Note 2)  
tWHWH2  
tWHWH2  
Sector Erase Operation (Note 2)  
Typ.  
Min.  
1
sec  
tvcs  
VCC Set Up Time (Note 1)  
50  
μs  
tRB  
Recovery Time from RY/  
BY  
(N/A on 32-pin DIP, PLCC & (s)TSOP packages)  
Program/Erase Valid to RY/ Delay  
Min  
Min  
0
ns  
ns  
tBUSY  
BY  
(N/A on 32-pin DIP, PLCC & (s)TSOP packages)  
90  
Notes:  
1. Not 100% tested.  
2. See the "Erase and Programming Performance" section for more information.  
(November, 2010, Version 1.7)  
23  
AMIC Technology, Corp.  
A29L004 Series  
Timing Waveforms for Program Operation  
Program Command Sequence (last two cycles)  
Read Status Data (last two cycles)  
t
WC  
tAS  
Addresses  
CE  
PA  
PA  
555h  
PA  
t
AH  
t
CH  
OE  
t
WP  
t
WHWH1  
WE  
t
CS  
t
WPH  
t
DS  
t
DH  
Data  
A0h  
PD  
DOUT  
Status  
t
RB  
t
BUSY  
RY/BY  
VCC  
t
VCS  
Note :  
1. PA = program addrss, PD = program data, Dout is the true data at the program address.  
2. Illustration shows device in word mode.  
(November, 2010, Version 1.7)  
24  
AMIC Technology, Corp.  
A29L004 Series  
Timing Waveforms for Chip/Sector Erase Operation  
Erase Command Sequence (last two cycles)  
Read Status Data  
t
AS  
t
WC  
SA  
555h for chip erase  
VA  
Addresses  
CE  
2AAh  
VA  
tAH  
OE  
t
CH  
t
WP  
WE  
t
WPH  
t
WHWH2  
tCS  
t
DS  
tDH  
In  
Progress  
Data  
55h  
30h  
10h for chip erase  
Complete  
tRB  
tBUSY  
RY/BY  
t
VCS  
VCC  
Note :  
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").  
2. Illustratin shows device in word mode.  
(November, 2010, Version 1.7)  
25  
AMIC Technology, Corp.  
A29L004 Series  
Timing Waveforms for  
Polling (During Embedded Algorithms)  
Data  
tRC  
Addresses  
VA  
VA  
VA  
tAC  
C
CE  
tCH  
OE  
tCE  
tOE  
tDF  
tOEH  
WE  
tOH  
High-Z  
Valid Data  
I/O7  
Complement  
Complement  
Status Data  
True  
True  
High-Z  
I/O0 - I/O6  
High-Z  
Status Data  
Valid Data  
tBUSY  
RY/BY  
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data  
read cycle.  
Timing Waveforms for Toggle Bit (During Embedded Algorithms)  
tRC  
Addresses  
CE  
VA  
VA  
VA  
VA  
tAC  
C
tCE  
tCH  
tOE  
OE  
tDF  
tOEH  
WE  
tOH  
I/O6 , I/O2  
High-Z  
Valid Status  
(first read)  
Valid Status  
Valid Status  
Valid Data  
tBUSY  
(second read)  
(stop togging)  
RY/BY  
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status  
read cycle, and array data read cycle.  
(November, 2010, Version 1.7)  
26  
AMIC Technology, Corp.  
A29L004 Series  
Timing Waveforms for Sector Protect/Unprotect  
VID  
VIH  
RESET  
SA, A6,  
A1, A0  
Valid*  
Valid*  
Valid*  
Status  
Sector Protect/Unprotect  
Verify  
40h  
60h  
60h  
Data  
CE  
Sector Protect:150us  
Sector Unprotect:15ms  
1us  
WE  
OE  
Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0  
Timing Waveforms for I/O2 vs. I/O6  
Enter  
Embedded  
Erasing  
Erase  
Suspend  
Enter Erase  
Suspend Program  
Erase  
Resume  
WE  
I/O  
Erase  
Suspend  
Program  
Erase  
Erase  
Erase Suspend  
Erase Suspend  
Read  
Erase  
Complete  
Read  
6
I/O2  
I/O2  
and I/O  
6
toggle with OE and CE  
Note : Both I/O  
6
and I/O  
2
toggle with OE or CE. See the text on I/O  
6
and I/O  
2
in the section "Write Operation Status" for  
more information.  
(November, 2010, Version 1.7)  
27  
AMIC Technology, Corp.  
A29L004 Series  
AC Characteristics  
Erase and Program Operations  
Alternate  
Controlled Writes  
CE  
Parameter  
Description  
Speed  
Unit  
JEDEC  
Std  
tWC  
tAS  
-70  
-90  
tAVAV  
tAVEL  
tELAX  
tDVEH  
tEHDX  
Write Cycle Time (Note 1)  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
70  
90  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
0
tAH  
45  
35  
45  
45  
tDS  
tDH  
Data Hold Time  
0
0
0
tOES  
tGHEL  
Output Enable Setup Time  
tGHEL  
Read Recover Time Before Write  
(
High to  
Low)  
WE  
OE  
tWLEL  
tEHWH  
tELEH  
tEHEL  
tWS  
tWH  
tCP  
Min.  
Min.  
Min.  
Min.  
0
0
ns  
ns  
ns  
ns  
Setup Time  
Hold Time  
WE  
WE  
CE  
CE  
35  
35  
Pulse Width  
tCPH  
30  
Pulse Width High  
tWHWH1  
tWHWH2  
tWHWH1  
tWHWH2  
Byte Programming Operation (Note 2)  
Sector Erase Operation (Note 2)  
Typ.  
Typ.  
17  
1
μs  
sec  
Notes:  
1. Not 100% tested.  
2. See the "Erase and Programming Performance" section for more information.  
(November, 2010, Version 1.7)  
28  
AMIC Technology, Corp.  
A29L004 Series  
Timing Waveforms for Alternate  
Controlled Write Operation  
CE  
PA for program  
SA for sector erase  
555 for chip erase  
555 for program  
2AA for erase  
Data Polling  
PA  
Addresses  
tWC  
tAS  
tAH  
tWH  
WE  
OE  
tWHWH1 or 2  
tCP  
tBUSY  
tCPH  
tDH  
CE  
tWS  
tDS  
Data  
DOUT  
I/O7  
PD for program  
30 for sector erase 10  
for chip erase  
tRH  
A0 for program  
55 for erase  
RESET  
RY/BY  
Note :  
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data.  
2. Figure indicates the last two bus cycles of the command sequence.  
Erase and Programming Performance  
Parameter  
Sector Erase Time  
Typ. (Note 1)  
Max. (Note 2)  
Unit  
sec  
sec  
μs  
Comments  
1
8
Excludes 00h programming  
prior to erasure  
Chip Erase Time  
11  
17  
64  
Byte Programming Time  
200  
Excludes system-level  
overhead (Note 5)  
Chip Programming Time (Note 3)  
6
13.5  
sec  
Notes:  
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally, programming  
typically assumes checkerboard pattern.  
2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles.  
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes  
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then  
does the device set I/O5 = 1. See the section on I/O5 for further information.  
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.  
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 5  
for further information on command definitions.  
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.  
(November, 2010, Version 1.7)  
29  
AMIC Technology, Corp.  
A29L004 Series  
Latch-up Characteristics  
Description  
Min.  
-1.0V  
Max.  
VCC+1.0V  
+100 mA  
12.5V  
Input Voltage with respect to VSS on all I/O pins  
VCC Current  
-100 mA  
-1.0V  
Input voltage with respect to VSS on all pins except I/O pins  
(including A9,  
and  
)
RESET  
OE  
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at time.  
TSOP Pin Capacitance  
Parameter Symbol  
Parameter Description  
Input Capacitance  
Test Setup  
VIN=0  
Typ.  
6
Max.  
7.5  
12  
Unit  
pF  
CIN  
COUT  
CIN2  
Output Capacitance  
VOUT=0  
VIN=0  
8.5  
7.5  
pF  
Control Pin Capacitance  
9
pF  
Notes:  
1. Sampled, not 100% tested.  
2. Test conditions TA = 25°C, f = 1.0MHz  
PLCC Pin Capacitance  
Parameter Symbol  
Parameter Description  
Test Setup  
VIN=0  
Typ.  
Max.  
6
Unit  
pF  
CIN  
COUT  
CIN2  
Input Capacitance  
4
8
8
Output Capacitance  
Control Pin Capacitance  
VOUT=0  
VPP=0  
pF  
12  
pF  
12  
Notes:  
1. Sampled, not 100% tested.  
2. Test conditions TA = 25°C, f = 1.0MHz  
Data Retention  
Parameter  
Test Conditions  
150°C  
Min  
10  
Unit  
Years  
Years  
Minimum Pattern Data Retention Time  
20  
125°C  
(November, 2010, Version 1.7)  
30  
AMIC Technology, Corp.  
A29L004 Series  
Test Conditions  
Test Specifications  
Test Condition  
-70  
-90  
Unit  
Output Load  
1 TTL gate  
Output Load Capacitance, CL(including jig capacitance)  
Input Rise and Fall Times  
30  
5
100  
5
pF  
ns  
V
Input Pulse Levels  
0.0 - 3.0  
1.5  
0.0 - 3.0  
1.5  
Input timing measurement reference levels  
Output timing measurement reference levels  
V
1.5  
1.5  
V
Test Setup  
3.3 V  
2.7 KΩ  
Device  
Under  
Test  
Diodes = IN3064 or Equivalent  
CL  
6.2 KΩ  
(November, 2010, Version 1.7)  
31  
AMIC Technology, Corp.  
A29L004 Series  
Ordering Information  
Top Boot Sector Flash  
Part No.  
Access Time  
(ns)  
Active Read  
Current  
Program/Erase  
Current  
Standby Current  
Package  
Typ. (μA)  
Typ. (mA)  
Typ. (mA)  
A29L004TL-70  
A29L004TL-70F  
A29L004TX-70  
A29L004TX-70F  
A29L004TV-70  
A29L004TV-70F  
A29L004TW-70  
A29L004TW-70F  
A29L004TY-70  
A29L004TY-70F  
A29L004TL-90  
A29L004TL-90F  
A29L004TX-90  
A29L004TX-90F  
A29L004TV-90  
A29L004TV-90F  
A29L004TW-90  
A29L004TW-90F  
A29L004TY-90  
A29L004TY-90F  
32-pin PLCC  
32-Pin Pb-Free PLCC  
32-pin sTSOP  
(8mm X 13.4mm)  
32-Pin Pb-Free sTSOP  
(8mm X 13.4mm)  
32-pin TSOP  
(8mm X 20mm)  
32-pin Pb-Free TSOP  
(8mm X 20mm)  
40-pin TSOP  
40-pin Pb-Free TSOP  
32-pin sTSOP  
(8mm X 14mm)  
32-Pin Pb-Free sTSOP  
(8mm X 14mm)  
32-pin PLCC  
32-pin Pb-Free PLCC  
32-pin sTSOP  
(8mm X 13.4mm)  
32-pin Pb-Free sTSOP  
(8mm X 13.4mm)  
32-pin TSOP  
(8mm X 20mm)  
32-pin Pb-Free TSOP  
(8mm X 20mm)  
40-pin TSOP  
40-pin Pb-Free TSOP  
32-pin sTSOP  
(8mm X 14mm)  
32-Pin Pb-Free sTSOP  
(8mm X 14mm)  
(November, 2010, Version 1.7)  
32  
AMIC Technology, Corp.  
A29L004 Series  
Bottom Boot Sector Flash  
Part No.  
Access Time  
Active Read  
Current  
Program/Erase  
Current  
Standby Current  
Package  
(ns)  
Typ. (μA)  
Typ. (mA)  
Typ. (mA)  
A29L004U-70  
32-pin DIP  
32-pin Pb-Free DIP  
32-pin PLCC  
A29L004U-70F  
A29L004UL-70  
A29L004UL-70F  
A29L004UX-70  
A29L004UX-70F  
A29L004UV-70  
A29L004UV-70F  
A29L004UW-70  
A29L004UW-70F  
A29L004UY-70  
A29L004UY-70F  
A29L004U-90  
32-pin Pb-Free PLCC  
32-pin sTSOP  
(8mm X 13.4mm)  
32-pin Pb-Free sTSOP  
(8mm X 13.4mm)  
32-pin TSOP  
(8mm X 20mm)  
32-pin Pb-Free TSOP  
(8mm X 20mm)  
70  
4
20  
0.2  
40-pin TSOP  
40-pin Pb-Free TSOP  
32-pin sTSOP  
(8mm X 14mm)  
32-Pin Pb-Free sTSOP  
(8mm X 14mm)  
32-pin DIP  
32-pin Pb-Free DIP  
32-pin PLCC  
A29L004U-90F  
A29L004UL-90  
A29L004UL-90F  
A29L004UX-90  
A29L004UX-90F  
A29L004UV-90  
A29L004UV-90F  
A29L004UW-90  
A29L004UW-90F  
A29L004UY-90  
A29L004UY-90F  
32-pin Pb-Free PLCC  
32-pin sTSOP  
(8mm X 13.4mm)  
32-pin Pb-Free sTSOP  
(8mm X 13.4mm)  
32-pin TSOP  
(8mm X 13.4mm)  
32-pin Pb-Free TSOP  
(8mm X 13.4mm)  
90  
4
20  
0.2  
40-pin TSOP  
40-pin Pb-Free TSOP  
32-pin sTSOP  
(8mm X 14mm)  
32-Pin Pb-Free sTSOP  
(8mm X 14mm)  
(November, 2010, Version 1.7)  
33  
AMIC Technology, Corp.  
A29L004 Series  
Package Information  
P-DIP 32L Outline Dimensions  
unit: inches/mm  
D
32  
17  
1
16  
E
1
Base Plane  
Seating Plane  
B
E
A
θ
e
B
1
Dimensions in inches  
Dimensions in mm  
Symbol  
Min  
-
Nom  
Max  
0.210  
-
Min  
Nom  
Max  
A
-
-
-
-
-
5.334  
-
A1  
A2  
0.015  
0.149  
0.381  
3.785  
0.154  
0.159  
3.912  
4.039  
B
-
-
0.018  
0.050  
-
-
-
-
-
-
0.457  
1.270  
0.254  
-
-
-
B1  
C
D
-
0.010  
1.650  
1.645  
1.655 41.783 41.91 42.037  
0.547 13.64 13.767 13.894  
E
E1  
EA  
e
0.537  
0.590  
0.630  
-
0.542  
0.600  
0.650  
0.100  
0.130  
-
0.610 14.986 15.240 15.494  
0.670 16.002 16.510 17.018  
-
-
2.540  
3.302  
-
-
L
0.120  
0°  
0.140  
15°  
3.048  
0°  
3.556  
15°  
θ
Notes:  
1. The maximum value of dimension D includes end flash.  
2. Dimension E does not include resin fins.  
(November, 2010, Version 1.7)  
34  
AMIC Technology, Corp.  
A29L004 Series  
Package Information  
TSOP 40L TYPE I (10 X 20mm) Outline Dimensions  
unit: inches/mm  
A
A2  
A1  
0.076  
C
Pin1  
D
1
D
Detail "A"  
Gage Plane  
θ
Seating Plane  
L
Dimensions in inches  
Dimensions in mm  
Symbol  
Min  
-
Nom  
Max  
Min  
Nom  
Max  
-
-
-
-
A
A1  
A2  
b
0.047  
0.006  
0.041  
1.20  
0.15  
1.05  
0.27  
0.21  
-
1.00  
0.002  
0.037  
0.05  
0.95  
0.17  
0.10  
0.039  
0.0067 0.0087 0.0106  
0.22  
c
0.004  
-
0.0083  
-
E
0.394 BSC  
0.020 BSC  
0.787 BSC  
0.724 BSC  
0.024  
10.00 BSC  
0.50 BSC  
20.00 BSC  
18.40 BSC  
0.60  
e
D
D1  
L
0.020  
0.028  
0.50  
0.70  
θ
0°  
3°  
5°  
0°  
3°  
5°  
Notes:  
1. Dimension D1 and E do not include mold flash.  
2. The lead width dimension does not include dambar protrusion.  
Total in excess of the lead width dimension at maximum material condition.  
Dambar cannot be located on the lower radius of the foot.  
(November, 2010, Version 1.7)  
35  
AMIC Technology, Corp.  
A29L004 Series  
Package Information  
PLCC 32L Outline Dimension  
unit: inches/mm  
H
D
D
13  
5
14  
4
1
32  
20  
30  
29  
21  
b
e
b
1
GE  
y
θ
GD  
Dimensions in inches  
Dimensions in mm  
Symbol  
Min  
-
Nom  
-
Max  
0.134  
-
Min  
Nom  
-
Max  
A
A1  
A2  
b1  
b
-
3.40  
-
0.0185  
0.105  
0.026  
0.016  
0.008  
0.547  
0.447  
0.044  
0.490  
0.390  
0.585  
0.485  
0.075  
-
-
0.47  
2.67  
0.66  
0.41  
0.20  
13.89  
11.35  
1.12  
12.45  
9.91  
14.86  
12.32  
1.91  
-
-
0.110  
0.028  
0.018  
0.010  
0.550  
0.450  
0.050  
0.510  
0.410  
0.590  
0.490  
0.090  
-
0.115  
0.032  
0.021  
0.014  
0.553  
0.453  
0.056  
0.530  
0.430  
0.595  
0.495  
0.095  
0.003  
10°  
2.80  
0.71  
0.46  
0.254  
13.97  
11.43  
1.27  
12.95  
10.41  
14.99  
12.45  
2.29  
-
2.93  
0.81  
0.54  
0.35  
14.05  
11.51  
1.42  
13.46  
10.92  
15.11  
12.57  
2.41  
0.075  
10°  
C
D
E
e
GD  
GE  
HD  
HE  
L
y
θ
0°  
-
0°  
-
Notes:  
1. Dimensions D and E do not include resin fins.  
2. Dimensions GD & GE are for PC Board surface mount pad pitch  
design reference only.  
(November, 2010, Version 1.7)  
36  
AMIC Technology, Corp.  
A29L004 Series  
Package Information  
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions  
unit: inches/mm  
D
θ
L
L
E
H
D
Detail "A"  
Detail "A"  
y
S
b
Dimensions in inches  
Dimensions in mm  
Symbol  
Min  
-
Nom  
Max  
Min  
Nom  
Max  
A
A1  
A2  
b
-
0.047  
0.006  
0.041  
0.011  
0.008  
0.728  
0.319  
-
-
1.20  
0.15  
1.05  
0.27  
0.20  
18.50  
8.10  
0.002  
0.037  
0.007  
0.004  
0.720  
-
-
0.039  
0.009  
-
0.05  
0.95  
0.18  
0.11  
18.30  
-
-
1.00  
0.22  
-
c
D
E
0.724  
0.315  
0.020 BSC  
0.787  
0.020  
0.032  
-
18.40  
8.00  
0.50 BSC  
20.00  
0.50  
0.80  
-
e
HD  
L
0.779  
0.795  
0.024  
-
19.80  
20.20  
0.60  
-
0.016  
0.40  
LE  
S
-
-
-
-
0.020  
0.003  
5°  
0.50  
0.08  
5°  
y
-
-
-
-
-
-
θ
0°  
0°  
Notes:  
1. The maximum value of dimension D includes end flash.  
2. Dimension E does not include resin fins.  
3. Dimension S includes end flash.  
(November, 2010, Version 1.7)  
37  
AMIC Technology, Corp.  
A29L004 Series  
Package Information  
sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions  
unit: inches/mm  
θ
L
L
E
D
1
D
Detail "A"  
Detail "A"  
0.076MM  
S
b
SEATING PLANE  
Dimensions in inches  
Dimensions in mm  
Symbol  
Min  
-
Nom  
-
Max  
Min  
Nom  
-
Max  
-
A
A1  
A2  
b
0.049  
-
1.25  
-
-
-
0.002  
0.037  
0.007  
0.05  
0.95  
0.17  
0.039  
0.008  
0.041  
0.009  
1.00  
1.05  
0.23  
0.158  
8.10  
0.20  
c
0.0056 0.0059 0.0062 0.142  
0.150  
8.00  
E
0.311  
0.315  
0.020 TYP  
0.528  
0.319  
7.90  
e
0.50 TYP  
13.40  
11.80  
0.50  
D
D1  
L
0.520  
0.461  
0.012  
0.535  
0.469  
0.028  
13.20  
11.70  
0.30  
13.60  
11.90  
0.70  
0.465  
0.020  
LE  
S
0.0275 0.0315 0.0355 0.700  
0.0109 TYP  
0.800  
0.278 TYP  
3°  
0.900  
θ
0°  
3°  
5°  
0°  
5°  
Notes:  
1. The maximum value of dimension D1 includes end flash.  
2. Dimension E does not include resin fins.  
3. Dimension S includes end flash.  
(November, 2010, Version 1.7)  
38  
AMIC Technology, Corp.  
A29L004 Series  
Package Information  
sTSOP 32L TYPE I (8 X 14mm) Outline Dimensions  
unit: inches/mm  
Pin1  
Gage Plane  
θ
L
D
1
Detail "A"  
D
Detail "A"  
b
e
y
Dimensions in inches  
Dimensions in mm  
Symbol  
Min  
-
Nom  
Max  
Min  
Nom  
-
Max  
-
-
-
A
A1  
A2  
b
0.047  
0.006  
0.041  
1.20  
0.15  
1.05  
0.27  
0.21  
8.10  
-
-
0.002  
0.037  
0.05  
0.95  
0.17  
0.10  
7.90  
-
0.039  
1.00  
0.22  
-
0.0067 0.0087 0.0106  
c
0.004  
0.311  
-
-
0.0083  
0.319  
-
E
e
0.315  
0.0197  
0.551  
0.488  
0.024  
-
8.00  
0.50  
14.00  
12.40  
0.60  
-
D
D1  
L
0.543  
0.484  
0.020  
0.000  
0°  
0.559  
0.492  
0.028  
0.003  
5°  
13.80  
12.30  
0.50  
0.00  
0°  
14.20  
12.50  
0.70  
0.076  
y
θ
3°  
3°  
5°  
Notes:  
1. Dimension E does not include mold flash.  
3. Dimension D1 does not include interlead flash.  
4. Dimension b does not include dambar protrusion.  
(November, 2010, Version 1.7)  
39  
AMIC Technology, Corp.  

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