A29040B-70UF [AMICC]
512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory; 512K ×8位CMOS 5.0伏只，统一部门快闪记忆体
| 型号： | A29040B-70UF |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| 文件： | 总29页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A29040B Series
512K X 8 Bit CMOS 5.0 Volt-only,
Uniform Sector Flash Memory
Preliminary
Document Title
512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
0.2
Initial issue
January 14, 2004
July 6, 2004
Preliminary
Add Pb-Free package type
December 6, 2004
Add the product spec of -U series (-40°C ~85°C)
PRELIMINARY (December, 2004, Version 0.2)
AMIC Technology, Corp.
A29040B Series
512K X 8 Bit CMOS 5.0 Volt-only,
Uniform Sector Flash Memory
Preliminary
Features
- Embedded Program algorithm automatically writes and
verifies bytes at specified addresses
ꢀ5.0V ± 10% for read and write operations
ꢀAccess times:
ꢀTypical 100,000 program/erase cycles per sector
- 55/70/90 (max.)
ꢀCurrent:
ꢀ20-year data retention at 125°C
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 µA typical CMOS standby
- Reliable operation for the life of the system
ꢀCompatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
ꢀFlexible sector architecture
- Superior inadvertent write protection
- 8 uniform sectors of 64 Kbyte each
- Any combination of sectors can be erased
- Supports full chip erase
ꢀ
Polling and toggle bits
Data
- Provides a software method of detecting completion of
program or erase operations
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within that
sector
ꢀErase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
ꢀExtended operating temperature range: -40°C~+85°C
for –U series
ꢀPackage options
ꢀEmbedded Erase Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors
and verify the erased sectors
- 32-pin P-DIP, PLCC, or TSOP (Forward type)
General Description
Reading data out of the device is similar to reading from
other Flash or EPROM devices.
The A29040B is a 5.0 volt-only Flash memory organized as
524,288 bytes of 8 bits each. The 512 Kbytes of data are
further divided into eight sectors of 64 Kbytes each for flexible
sector erase capability. The 8 bits of data appear on I/O0 -
I/O7 while the addresses are input on A0 to A18. The
A29040B is offered in 32-pin PLCC, TSOP, and PDIP
packages. This device is designed to be programmed in-
system with the standard system 5.0volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write or
erase operations. However, the A29040B can also be
programmed in standard EPROM programmers.
The A29040B has a second toggle bit, I/O2, to indicate
whether the addressed sector is being selected for erase, and
also offers the ability to program in the Erase Suspend mode.
The standard A29040B offers access times of 55, 70 and 90
ns, allowing high-speed microprocessors to operate without
wait states. To eliminate bus contention the device has
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm
-
an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
The host system can detect whether a program or erase
operation is complete by reading the I/O7 (
Polling) and
Data
I/O6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
separate chip enable (
), write enable (
) and output
WE
CE
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29040B is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the sectors
of memory. This can be achieved via programming
equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program
data to, any other sector that is not selected for erasure.
True background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
enable (
) controls.
OE
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29040B is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
PRELIMINARY (December, 2004, Version 0.2)
1
AMIC Technology, Corp.
A29040B Series
Pin Configurations
ꢀDIP
ꢀPLCC
1
VCC
WE
32
31
30
A18
A16
A15
2
3
4
A17
A12
A7
A14
A13
A8
29
28
27
5
A14
29
A7
5
6
6
7
8
A13
A8
A6
A5
A4
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A9
7
26
A9
8
A11
OE
25
24
23
22
A29040BL
A11
OE
A10
CE
9
A3
A2
9
10
A10
10
11
12
13
14
15
16
11
12
13
CE
A1
A0
A1
A0
I/O7
21
20
19
18
17
I/O0
I/O1
I/O2
VSS
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
ꢀTSOP (Forward type)
A11
A9
A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A29040BV
A6
A5
A4
A1
A2
A3
PRELIMINARY
(December, 2004, Version 0.2)
2
AMIC Technology, Corp.
A29040B Series
Block Diagram
I/O0 - I/O7
VCC
VSS
Input/Output
Buffers
Erase Voltage
Generator
State
Control
WE
PGM Voltage
Generator
Command
Register
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
X-decoder
Cell Matrix
A0-A18
Pin Descriptions
Pin No.
Description
Address Inputs
A0 - A18
I/O0 - I/O7
Data Inputs/Outputs
Chip Enable
CE
Write Enable
Output Enable
Ground
WE
OE
VSS
VCC
Power Supply
PRELIMINARY
(December, 2004, Version 0.2)
3
AMIC Technology, Corp.
A29040B Series
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended periods
may affect device reliability.
Ambient Operating Temperature …. . . . . -55°C to + 125°C
Storage Temperature . . . . . . . . . . …. . . . -65°C to + 125°C
VCC to Ground . . . . . . . . . . . . . . . . . …. . . . . -2.0V to 7.0V
Output Voltage (Note 1) . . . . . . . . . . . . ….. . . -2.0V to 7.0V
A9 &
(Note 2) . . . . . . . . . . . . . . . . . . …. -2.0V to 12.5V
OE
All other pins (Note 1) . . . . . . . . . . . . . . . . . …-2.0V to 7.0V
Output Short Circuit Current (Note 3) . . . . . . . …. . . 200mA
Notes:
Operating Ranges
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, inputs may undershoot VSS to -2.0V
for periods of up to 20ns. Maximum DC voltage on output
and I/O pins is VCC +0.5V. During voltage transitions,
outputs may overshoot to VCC +2.0V for periods up to
20ns.
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . ……. . . . 0°C to +70°C
Extended Range Devices
Ambient Temperature (TA) . . . . . . . . . …….. -40°C to +85°C
2. Minimum DC input voltage on A9 pins is -0.5V. During
VCC Supply Voltages
voltage transitions, A9 and
may overshoot VSS to -
OE
2.0V for periods of up to 20ns. Maximum DC input
voltage on A9 and is +12.5V which may overshoot to
VCC for ± 10% devices ….. ….. . . . . . . . . . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
OE
13.5V for periods up to 20ns.
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus
operations table lists the inputs and control levels required,
and the resulting output. The following subsections describe
each of these operations in further detail.
Table 1. A29040B Device Bus Operations
Operation
I/O0 - I/O7
CE
OE
WE
A0 – A18
Read
L
L
H
AIN
DOUT
DIN
Write
L
H
X
X
H
L
X
X
H
AIN
X
CMOS Standby
TTL Standby
Output Disable
VCC ± 0.5 V
High-Z
High-Z
High-Z
H
L
X
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the "Sector Protection/Unprotection" section, for more information.
PRELIMINARY
(December, 2004, Version 0.2)
4
AMIC Technology, Corp.
A29040B Series
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
ICC2 in the Characteristics table represents the active current
specification for the write mode. The "AC Characteristics"
section contains timing specification tables and timing
diagrams for write operations.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
and
pins to VIL.
is the power control and
CE
OE
CE
selects the device.
OE
data to the output pins.
is the output control and gates array
should remain at VIH all the time
WE
during read operation. The internal state machine is set for
reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration of
the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section for
timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the
input.
OE
Writing Commands/Command Sequences
The device enters the CMOS standby mode when the
pin is held at VCC ± 0.5V. (Note that this is a more restricted
voltage range than VIH.) The device enters the TTL standby
CE
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive
and
to VIL, and
CE
WE
mode when
is held at VIH. The device requires the
CE
to VIH. An erase operation can erase one sector,
OE
standard access time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
multiple sectors, or the entire device. The Sector Address
Tables indicate the address range that each sector occupies.
A "sector address" consists of the address inputs required to
uniquely select a sector. See the "Command Definitions"
section for details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard
read cycle timings apply in this mode. Refer to the
Output Disable Mode
When the
input is at VIH, output from the device is
OE
disabled. The output pins are placed in the high impedance
state.
Table 2. Sector Addresses Table
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A18
0
A17
A16
Address Range
00000h - 0FFFFh
10000h - 1FFFFh
20000h - 2FFFFh
30000h - 3FFFFh
40000h - 4FFFFh
50000h - 5FFFFh
60000h - 6FFFFh
70000h - 7FFFFh
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
1
1
1
Note: All sectors are 64 Kbytes in size.
PRELIMINARY
(December, 2004, Version 0.2)
5
AMIC Technology, Corp.
A29040B Series
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.To access the
autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown in
the Command Definitions table. This method does not
require VID. See "Command Definitions" for details on using
the autoselect mode.
a
device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pinA9. Address
pins A6, A1, and AO must be as shown in Autoselect Codes
(High Voltage Method) table. In addition, when verifying
sector protection, the sector address must appear on the
Table 3. A29040B Autoselect Codes (High Voltage Method)
Identifier Code on
I/O7 - I/O0
Description
A18 - A16 A15 - A10
A9 A8 - A7
A5 - A2
A6
A1
AO
Manufacturer ID: AMIC
Device ID: A29040B
X
X
X
X
VID
VID
X
X
VIL
VIL
X
X
VIL
VIL
VIL
VIH
37h
86h
01h (protected)
00h (unprotected)
Sector Protection
Verification
Sector
Address
X
X
VID
X
X
VIL
X
X
VIH
VIH
VIL
VIH
Continuation ID
X
VID
VIL
7Fh
Sector Protection/Unprotection
Power-Up Write Inhibit
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
Sector protection/unprotection must be implemented using
programming equipment. The procedure requires a high
voltage (VID) on address pin A9 and the control pins.
The device is shipped with all sectors unprotected.
If
=
= VIL and
= VIH during power up, the
OE
WE
CE
device does not accept commands on the rising edge of
. The internal state machine is automatically reset to
WE
reading array data on the initial power-up.
Command Definitions
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
Hardware Data Protection
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device
is powered up to read array data to avoid accidentally writing
data to the array.
All addresses are latched on the falling edge of
or
,
CE
WE
whichever happens later. All data is latched on the rising
edge of or , whichever happens first. Refer to the
WE
CE
appropriate timing diagrams in the "AC Characteristics"
section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm. After the device accepts
an Erase Suspend command, the device enters the
Erase Suspend mode. The system can read array
data using the standard read timings, except that if it
reads at an address within erase-suspended sectors,
the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on
do not initiate a write cycle.
,
or
WE
OE CE
Logical Inhibit
Write cycles are inhibited by holding any one of
=VIL,
OE
CE
= VIH or
= VIH. To initiate a write cycle,
and
WE
CE
must be a logical zero while
is a logical one.
WE
OE
PRELIMINARY
(December, 2004, Version 0.2)
6
AMIC Technology, Corp.
A29040B Series
system may once again read array data with the same
exception. See "Erase Suspend/Erase Resume Commands"
for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
required to provide further controls or timings. The device
automatically provides internally generated program pulses
and verify the programmed cell margin. The Command
Definitions table shows the address and data requirements
for the byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using I/O7 or I/O6. See "Write
Operation Status" for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Programming is allowed in
any sequence and across sector boundaries. A bit cannot be
programmed from a "0" back to a "1 ". Attempting to do so
may halt the operation and set I/O5 to "1", or cause the
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
Polling algorithm to indicate the operation was
Data
successful. However, a succeeding read will show that the
data is still "0". Only erase operations can convert a "0" to a
"1".
The reset command may be written between the sequence
cycles in
a
program command sequence before
START
programming begins. This resets the device to reading array
data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect
during Erase Suspend).
Write Program
Command
Sequence
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
Data Poll
from System
Embedded
Program
algorithm in
progress
Autoselect Command Sequence
The autoselect command sequence allows the host system
to access the manufacturer and devices codes, and
determine whether or not a sector is protected. The
Command Definitions table shows the address and data
requirements. This method is an alternative to that shown in
the Autoselect Codes (High Voltage Method) table, which is
intended for PROM programmers and requires VID on
address bit A9.
Verify Data ?
No
Yes
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system
may read at any address any number of times, without
initiating another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to the Sector
Address tables for valid sector addresses.
Increment Address
Last Address ?
Yes
Programming
Completed
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Note : See the appropriate Command Definitions table for
program command sequence.
Byte Program Command Sequence
Figure 1. Program Operation
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not
PRELIMINARY
(December, 2004, Version 0.2)
7
AMIC Technology, Corp.
A29040B Series
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are
ignored.
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to
provide any controls or timings during these operations. The
Command Definitions table shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched. The system can determine the status of the
erase operation by using I/O7, I/O6, or I/O2. Refer to "Write
Operation Status" for information on these status bits.
Figure 2 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50µs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
operation. Addresses are "don't cares" when writing the
Erase Suspend command.
Figure 2 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
Sector Erase Command Sequence
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20µs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on
I/O7 - I/O0. The system can use I/O7, or I/O6 and I/O2
together, to determine if a sector is actively erasing or is
erase-suspended. See "Write Operation Status" for
information on these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non-
suspended sectors. The system can determine the status of
the program operation using the I/O7 or I/O6 status bits, just
as in the standard program operation. See "Write Operation
Status" for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
out of 50µs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional
cycles must be less than 50µs, otherwise the last address
and command might not be accepted, and erasure may
begin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be
less than 50µs, the system need not monitor I/O3. Any
command other than Sector Erase or Erase Suspend during
the time-out period resets the device to reading array data.
The system must rewrite the command sequence and any
additional sector addresses and commands.
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
pulse in the command sequence.
WE
PRELIMINARY
(December, 2004, Version 0.2)
8
AMIC Technology, Corp.
A29040B Series
START
Write Erase
Command
Sequence
Data Poll
from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
Yes
Erasure Completed
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O
3
: Sector Erase Timer" for more information.
Figure 2. Erase Operation
PRELIMINARY
(December, 2004, Version 0.2)
9
AMIC Technology, Corp.
A29040B Series
Table 4. A29040B Command Definitions
Command
Sequence
(Note 1)
Bus Cycles (Notes 2 - 4)
First
Addr Data Addr Data
RA RD
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data
Read (Note 5)
1
1
4
4
4
Reset (Note 6)
XXX F0
555 AA
555 AA
555 AA
555 AA
Autoselect Manufacturer ID
2AA 55
2AA 55
2AA 55
2AA 55
555 90
X00
X01
X03
37
86
7F
00
(Note 7)
Device ID
555
555
555
90
90
90
Continuation ID
Sector Protect Verify 4
(Note 8)
SA
X02
01
Program
4
6
6
555 AA
555 AA
555 AA
XXX B0
XXX 30
2AA 55
2AA 55
2AA 55
555 A0
PA
555
555
PD
AA
AA
Chip Erase
Sector Erase
555
555
80
80
2AA 55
2AA 55
555
SA
10
30
Erase Suspend (Note 9)
Erase Resume (Note 10)
1
1
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the
whichever happens later.
or
pulse,
CE
WE
PD = Data to be programmed at location PA. Data latches on the rising edge of
or
pulse, whichever happens first.
CE
WE
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A16 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
10. The Erase Resume command is valid only during the Erase Suspend mode.
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AMIC Technology, Corp.
A29040B Series
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, and I/O7, are provided in
the A29040B to determine the status of a write operation.
Table 5 and the following subsections describe the functions
of these status bits. I/O7, I/O6 and I/O2 each offer a method
for determining whether a program or erase operation is
complete or in progress. These three bits are discussed first.
START
Read I/O7-I/O0
Address = VA
I/O7:
Polling
Data
The
Polling bit, I/O7, indicates to the host system
Data
whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data
pulse in
Yes
I/O
7
= Data ?
No
Polling is valid after the rising edge of the final
the program or erase command sequence.
WE
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
No
I/O5 = 1?
protected sector,
Polling on I/O7 is active for
Data
approximately 2µs, then the device returns to reading array
data.
Yes
During the Embedded Erase algorithm,
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Polling
Data
Read I/O
Address = VA
7
- I/O0
Polling produces a "1" on I/O7.This is analogous to the
Data
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O7.
Yes
I/O7
= Data ?
After an erase command sequence is written, if all sectors
selected for erasing are protected,
Polling on I/O7 is
No
Data
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0
on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output Enable
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
(
) is asserted low. The
Polling Timings (During
Data
OE
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 5 shows the outputs for
Data
Polling algorithm.
2. I/O
7
should be rechecked even if I/O
may change simultaneously with I/O
5 = "1" because
I/O7
5
.
Polling on I/O7. Figure 3 shows the
Data
Figure 3. Data Polling Algorithm
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(December, 2004, Version 0.2)
11
AMIC Technology, Corp.
A29040B Series
vs. I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
Reading Toggle Bits I/O6, I/O2
Refer to Figure 4 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7 - I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation. The
system can read array data on I/O7 - I/O0 on the following
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the
system must write the reset command to return to reading
array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
4).
of the final
pulse in the command sequence (prior to
WE
the program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
(The system may use either
or
to control the read
CE
OE
cycles.) When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the
device enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O7 (see the subsection on " I/O7 :
Polling").
Data
If a program address falls within a protected sector, I/O6
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 4 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O2 vs.
I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on " I/O2: Toggle Bit
II".
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O5
produces a "1."
I/O2: Toggle Bit II
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
rising edge of the final
sequence.
pulse in the command
WE
I/O3: Sector Erase Timer
I/O2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time between
additional sector erase commands will always be less than
50µs. See also the "Sector Erase Command Sequence"
section.
system may use either
or
to control the read
CE
OE
cycles.) But I/O2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. I/O6, by comparison,
indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors are
selected for erasure. Thus, both status bits are required for
sector and mode information. Refer to Table 5 to compare
outputs for I/O2 and I/O6.
Figure 4 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle
Bit Timings figure for the toggle bit timing diagram. The I/O2
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(December, 2004, Version 0.2)
12
AMIC Technology, Corp.
A29040B Series
After the sector erase command sequence is written, the
system should read the status on I/O7 ( Polling) or I/O6
START
Data
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted. Table 5 shows the outputs for I/O3.
Read I/O
7
-I/O
0
Read I/O7-I/O
0
(Note 1)
No
Toggle Bit
= Toggle ?
Yes
No
I/O5 = 1?
Yes
- I/O
Read I/O
7
0
(Notes 1,2)
Twice
No
Toggle Bit
= Toggle ?
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation
Commplete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O
5
changes to "1". See text.
Figure 4. Toggle Bit Algorithm
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13
AMIC Technology, Corp.
A29040B Series
Table 5. Write Operation Status
I/O7
I/O6
I/O5
I/O3
I/O2
Operation
(Note 1)
(Note 2)
(Note 1)
Standard
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
0
0
N/A
1
No toggle
Toggle
I/O7
0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector
1
No toggle
N/A
Toggle
Reading within Non-Erase
Suspend Sector
Data
I/O7
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
Toggle
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
20ns
PRELIMINARY
(December, 2004, Version 0.2)
14
AMIC Technology, Corp.
A29040B Series
DC Characteristics
TTL/NMOS Compatible
Parameter
Symbol
ILI
Parameter Description
Test Description
Min.
Typ. Max.
Unit
Input Load Current
VIN = VSS to VCC. VCC = VCC Max
VCC = VCC Max, A9 = 12.5V
±1.0
100
µA
µA
µA
mA
ILIT
ILO
A9 Input Load Current
Output Leakage Current
VOUT = VSS to VCC. VCC = VCC Max
±1.0
ICC1
VCC Active Read Current
(Notes 1, 2)
20
30
30
= VIL,
= VIL,
= VIH
= VIH
CE
CE
CE
OE
ICC2
ICC3
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)
40
mA
mA
=VIH
OE
VCC Standby Current (Note 2)
0.4
1.0
VIL
VIH
VID
Input Low Level
-0.5
2.0
0.8
VCC+0.5
12.5
V
V
V
Input High Level
Voltage for Autoselect
and Sector Protect
Output Low Voltage
Output High Voltage
VCC = 5.25 V
10.5
VOL
VOH
IOL = 12mA, VCC = VCC Min
IOH = -2.5 mA, VCC = VCC Min
0.45
V
V
2.4
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
Min.
Typ. Max.
Unit
ILI
ILIT
ILO
Input Load Current
A9 Input Load Current
VIN = VSS to VCC, VCC = VCC Max
VCC = VCC Max, A9 = 12.5V
±1.0
100
µA
µA
µA
mA
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max
±1.0
ICC1
VCC Active Read Current
(Notes 1,2)
20
30
1
30
40
5
= VIL,
= VIH
CE
CE
CE
OE
ICC2
ICC3
VCC Active Program/Erase Current
(Notes 2,3,4)
mA
= VIL,
= VIH
OE
VCC Standby Current (Notes 2, 5)
µA
= VCC ± 0.5 V
VIL
VIH
VID
Input Low Level
-0.5
0.7 x VCC
10.5
0.8
VCC+0.3
12.5
V
V
V
Input High Level
Voltage for Autoselect and Sector
Protect
VCC = 5.25 V
VOL
VOH1
VOH2
Output Low Voltage
Output High Voltage
IOL = 12.0 mA, VCC = VCC Min
IOH = -2.5 mA, VCC = VCC Min
IOH = -100 µA. VCC = VCC Min
0.45
V
V
V
0.85 x VCC
VCC-0.4
Notes for DC characteristics (both tables):
1. The ICC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with
2. Maximum ICC specifications are tested with VCC = VCC max.
at VIH.
OE
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Not 100% tested.
5. For CMOS mode only, ICC3 = 20µA max at extended temperatures (> +85°C)
PRELIMINARY
(December, 2004, Version 0.2)
15
AMIC Technology, Corp.
A29040B Series
AC Characteristics
Read Only Operations
Parameter Symbols
Speed
Description
Test Setup
Unit
JEDEC
Std
-55
-70
-90
Read Cycle Time (Note 2)
Address to Output Delay
tAVAV
tRC
Min.
55
70
90
ns
ns
= VIL
tAVQV
tACC
CE
Max.
55
70
90
= VIL
OE
Chip Enable to Output Delay
Output Enable to Output Delay
tELQV
tGLQV
tCE
Max.
Max.
Min.
55
30
0
70
30
0
90
35
0
ns
ns
ns
= VIL
OE
tOE
Read
Output Enable Hold
tOEH
Toggle and
Polling
Min.
10
10
Time (Note 2)
10
ns
Data
Chip Enable to Output High Z
(Notes 1,2)
tEHQZ
tGHQZ
tAXQX
tDF
tDF
tOH
Max.
Max.
Min.
18
18
0
20
20
0
20
20
0
ns
ns
ns
Output Enable to Output High Z
(Notes 1,2)
Output Hold Time from Addresses,
or
CE OE
, Whichever Occurs First
Notes:
1. Output driver disable time.
2. Not 100% tested.
Timing Waveforms for Read Only Operation
t
RC
Addresses
CE
Addresses Stable
t
ACC
t
DF
t
OE
OE
t
OEH
WE
t
CE
tOH
High-Z
High-Z
Output
Output Valid
0V
PRELIMINARY
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16
AMIC Technology, Corp.
A29040B Series
AC Characteristics
Erase and Program Operations
Parameter Symbols
Description
Speed
Unit
JEDEC
tAVAV
Std
tWC
tAS
-55
55
-70
70
0
-90
Write Cycle Time (Note 1)
Min.
Min.
Min.
Min.
Min.
Min.
90
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
tAVWL
tWLAX
tDVWH
tWHDX
tAH
40
25
45
30
0
45
45
Data Setup Time
tDS
Data Hold Time
tDH
Output Enable Setup Time
Read Recover Time Before Write
tOES
0
tGHWL
tGHWL
Min.
0
ns
(
high to
low)
WE
OE
tELWL
tWHEH
tWLWH
tCS
tCH
tWP
Min.
Min.
Min.
Min.
0
0
ns
ns
ns
ns
Setup Time
Hold Time
CE
CE
Write Pulse Width
30
35
20
45
tWHWL
tWPH
Write Pulse Width High
Max.
Typ.
50
7
µs
µs
Byte Programming Operation
(Note 2)
tWHWH1
tWHWH2
tWHWH1
Sector Erase Operation
(Note 2)
tWHWH2
Typ.
Min.
1
sec
VCC Set Up Time (Note 1)
tVCS
50
µs
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
PRELIMINARY
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AMIC Technology, Corp.
A29040B Series
Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tWC
tAS
Addresses
CE
PA
PA
555h
PA
tAH
tCH
tWP
tGHWL
OE
tWHWH1
WE
tCS
tWPH
tDS
tDH
Data
A0h
PD
DOUT
Status
tVCS
VCC
Note : PA = program addrss, PD = program data, Dout is the true data at the program address.
Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
Read Status Data
VA
VA
tAS
tWC
SA
Addresses
CE
2AAh
555h for chip erase
tAH
tGHWL
tCH
tWP
OE
WE
tWPH
tDH
tWHWH2
tCS
tDS
In
Data
55h
30h
10h for chip erase
Complete
Progress
tVCS
VCC
Note : SA = Sector Address. VA = Valid Address for reading status data.
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AMIC Technology, Corp.
A29040B Series
Timing Waveforms for
Polling (During Embedded Algorithms)
Data
tRC
Addresses
VA
VA
VA
tACC
tCE
CE
tCH
OE
tOE
tDF
tOEH
WE
tOH
High-Z
Valid Data
I/O7
Complement
Complement True
High-Z
I/O0 - I/O6
Valid Data
Status Data
Status Data
True
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
tRC
Addresses
CE
VA
VA
VA
VA
t
ACC
t
CE
tCH
tOE
OE
tDF
tOEH
WE
tOH
I/O6 , I/O2
Valid Status
(first read)
Valid Status
Valid Status
Valid Status
(second read)
(stop togging)
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
PRELIMINARY
(December, 2004, Version 0.2)
19
AMIC Technology, Corp.
A29040B Series
Timing Waveforms for I/O2 vs. I/O6
Enter
Erase
Enter Erase
Suspend Program
Erase
Resume
Embedded
Suspend
Erasing
WE
Erase
Suspend
Program
Erase
Erase
Erase Suspend
Read
Erase Suspend
Read
Erase
Complete
I/O6
I/O2
I/O2
and I/O
6
toggle with OE and CE
Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Statue" for
more information.
AC Characteristics
Erase and Program Operations
Alternate Controlled Writes
CE
Parameter Symbols
Description
Speed
Unit
JEDEC
tAVAV
tAVEL
Std
tWC
tAS
-55
-70
70
0
-90
Write Cycle Time (Note 1)
Min.
Min.
Min.
Min.
Min.
Min.
Min.
55
90
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
tELAX
tAH
40
25
45
30
0
45
45
tDVEH
tEHDX
tGHEL
tWLEL
tDS
tDH
Data Hold Time
tGHEL
tWS
Read Recover Time Before Write
0
0
Setup Time
Hold Time
WE
WE
tEHWH
tWH
Min.
0
ns
tELEH
tEHEL
tCP
Write Pulse Width
Min.
Min.
Typ.
Typ.
30
20
35
20
7
45
20
ns
ns
tCPH
Write Pulse Width High
tWHWH1
tWHWH2
tWHWH1
tWHWH2
Byte Programming Operation (Note 2)
Sector Erase Operation (Note 2)
µs
1
sec
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
PRELIMINARY
(December, 2004, Version 0.2)
20
AMIC Technology, Corp.
A29040B Series
Timing Waveforms for Alternate
Controlled Write Operation
CE
PA for program
SA for sector erase
555 for chip erase
555 for program
2AA for erase
Data Polling
PA
Addresses
t
WC
tAS
t
AH
t
WH
WE
t
GHEL
OE
CE
t
WHWH1 or 2
t
CP
t
BUSY
t
CPH
t
WS
t
DS
t
DH
Data
DOUT
I/O7
t
RH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O
7
= Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Sector Erase Time
Typ. (Note 1)
Max. (Note 2)
Unit
sec
sec
µs
Comments
1
8
8
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
64
Byte Programming Time
35
3.6
300
10.8
Excludes system-level
overhead (Note 5)
Chip Programming Time (Note 3)
Notes:
sec
1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 100,000 cycles. Additionally,
programming typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5V (4.75V for -55), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
PRELIMINARY
(December, 2004, Version 0.2)
21
AMIC Technology, Corp.
A29040B Series
Latch-up Characteristics
Description
Min.
-1.0V
Max.
Input Voltage with respect to VSS on all I/O pins
VCC Current
VCC+1.0V
+100 mA
-100 mA
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.
TSOP Pin Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
VIN=0
Typ.
6
Max.
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
VOUT=0
VIN=0
8.5
7.5
pF
Control Pin Capacitance
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
PLCC and P-DIP Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
VIN=0
Typ.
Max.
6
Unit
pF
CIN
COUT
CIN2
Input Capacitance
4
8
8
Output Capacitance
Control Pin Capacitance
VOUT=0
VPP=0
pF
12
pF
12
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
Data Retention
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
20
125°C
PRELIMINARY
(December, 2004, Version 0.2)
22
AMIC Technology, Corp.
A29040B Series
Test Conditions
Table 6. Test Specifications
Test Condition
-55
All others
Unit
Output Load
1 TTL gate
100
Output Load Capacitance, CL(including jig capacitance)
Input Rise and Fall Times
30
5
pF
ns
V
20
Input Pulse Levels
0.0 - 3.0
1.5
0.45 - 2.4
0.8, 2.0
0.8, 2.0
Input timing measurement reference levels
Output timing measurement reference levels
V
1.5
V
5.0 V
2.7 KΩ
Device
Under
Test
Diodes = IN3064 or Equivalent
CL
6.2 KΩ
Figure 7. Test Setup
PRELIMINARY
(December, 2004, Version 0.2)
23
AMIC Technology, Corp.
A29040B Series
Ordering Information
Active Read
Current
Typ. (mA)
Program/Erase
Current
Access Time
Standby Current
Part No.
Package
(ns)
Typ. (µA)
Typ. (mA)
A29040B-55
32Pin DIP
32Pin Pb-Free DIP
32Pin PLCC
A29040B-55F
A29040BL-55
A29040BL-55F
A29040BV-55
A29040BV-55F
A29040B-55U
A29040B-55UF
A29040BL-55U
A29040BL-55UF
A29040BV-55U
A29040BV-55UF
A29040B-70
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
32Pin DIP
55
20
30
1
32Pin Pb-Free DIP
32Pin PLCC
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
32Pin DIP
A29040B-70F
A29040BL-70
A29040BL-70F
A29040BV-70
A29040BV-70F
A29040B-70U
A29040B-70UF
A29040BL-70U
A29040BL-70UF
A29040BV-70U
A29040BV-70UF
32Pin Pb-Free DIP
32Pin PLCC
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
32Pin DIP
70
20
30
1
32Pin Pb-Free DIP
32Pin PLCC
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
PRELIMINARY
(December, 2004, Version 0.2)
24
AMIC Technology, Corp.
A29040B Series
Ordering Information (continued)
Access Time
Active Read
Current
Typ. (mA)
Program/Erase
Current
Standby Current
Part No.
(ns)
Package
Typ. (µA)
Typ. (mA)
A29040B-90
32Pin DIP
32Pin Pb-Free DIP
32Pin PLCC
A29040B-90F
A29040BL-90
A29040BL-90F
A29040BV-90
32Pin Pb-Free PLCC
32Pin TSOP
A29040BV-90F
90
A29040B-90U
32Pin Pb-Free TSOP
32Pin DIP
20
30
1
A29040B-90UF
A29040BL-90U
A29040BL-90UF
A29040BV-90U
A29040BV-90UF
32Pin Pb-Free DIP
32Pin PLCC
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
PRELIMINARY
(December, 2004, Version 0.2)
25
AMIC Technology, Corp.
A29040B Series
Package Information
P-DIP 32L Outline Dimensions
unit: inches/mm
D
32
17
1
16
E
1
Base Plane
Seating Plane
B
E
A
θ
e
B
1
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
0.210
-
Min
Nom
Max
A
-
-
-
-
-
5.334
-
A1
A2
0.015
0.149
0.381
3.785
0.154
0.159
3.912
4.039
B
-
-
0.018
0.050
-
-
-
-
-
-
0.457
1.270
0.254
-
-
-
B1
C
D
-
0.010
1.650
1.645
1.655 41.783 41.91 42.037
0.547 13.64 13.767 13.894
E
E1
EA
e
0.537
0.590
0.630
-
0.542
0.600
0.650
0.100
0.130
-
0.610 14.986 15.240 15.494
0.670 16.002 16.510 17.018
-
-
2.540
3.302
-
-
L
0.120
0°
0.140
15°
3.048
0°
3.556
15°
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
PRELIMINARY
(December, 2004, Version 0.2)
26
AMIC Technology, Corp.
A29040B Series
Package Information
PLCC 32L Outline Dimension
unit: inches/mm
HD
D
13
5
4
14
1
32
20
30
29
21
b
e
b
1
GE
y
θ
GD
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
0.134
-
Min
-
Nom
-
Max
3.40
-
A
A1
A2
b1
b
0.0185
0.105
0.026
0.016
0.008
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.075
-
-
0.47
2.67
0.66
0.41
0.20
-
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.510
0.410
0.590
0.490
0.090
-
0.115
0.032
0.021
0.014
0.553
0.453
0.056
0.530
0.430
0.595
0.495
0.095
0.003
10°
2.80
0.71
0.46
0.254
13.97
11.43
1.27
12.95
10.41
14.99
12.45
2.29
-
2.93
0.81
0.54
0.35
14.05
11.51
1.42
13.46
10.92
15.11
12.57
2.41
0.075
10°
C
D
13.89
11.35
1.12
12.45
9.91
14.86
12.32
1.91
-
E
e
GD
GE
HD
HE
L
y
θ
0°
-
0°
-
Notes:
1. Dimensions D and E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
PRELIMINARY
(December, 2004, Version 0.2)
27
AMIC Technology, Corp.
A29040B Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
θ
L
L
E
HD
Detail "A"
Detail "A"
y
S
b
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
Min
Nom
Max
A
A1
A2
b
-
0.047
0.006
0.041
0.011
0.008
0.728
0.319
-
-
1.20
0.15
1.05
0.27
0.20
18.50
8.10
0.002
0.037
0.007
0.004
0.720
-
-
0.039
0.009
-
0.05
0.95
0.18
0.11
18.30
-
-
1.00
0.22
-
c
D
E
0.724
0.315
0.020 BSC
0.787
0.020
0.032
-
18.40
8.00
0.50 BSC
20.00
0.50
0.80
-
e
HD
L
0.779
0.795
0.024
-
19.80
20.20
0.60
-
0.016
0.40
LE
S
-
-
-
-
0.020
0.003
5°
0.50
0.08
5°
y
-
-
-
-
-
-
θ
0°
0°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(December, 2004, Version 0.2)
28
AMIC Technology, Corp.
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