A290021_15 [AMICC]
Boot Sector Flash Memory;
| 型号： | A290021_15 |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | Boot Sector Flash Memory |
| 文件： | 总35页 (文件大小：398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A29002/A290021 Series
256K X 8 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Document Title
256K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
0.2
0.3
Initial issue
May 8, 2000
Preliminary
Add A290021 part data
Add Top/Bottom ordering information
May 31, 2000
June 26, 2000
January 3, 2001
Change ILIT from 50μA to 100μA
Change typical byte programming time from 7μs to 35μs
Erase VCC supply voltage for ± 5% devices in Operation Ranges
Add the time limit tWPH max. = 50μs of command cycle sequence
Correct the Continuation ID command to hexadecimal
Final version release
0.4
February 6, 2001
0.5
1.0
1.1
August 21, 2001
February 6, 2002
Final
Error Correction:
December 24, 2002
July 5, 2004
Page 8: Autoselect Command Sequence (line 15), XX11 → XX03h
Add 32L Pb-free PLCC package type
1.2
1.3
1.4
1.5
1.6
Add Pb-Free package type for all parts
Error correction: Modify Figure 3. Erase Operation
Remove -55 grade specification
August 6, 2004
April 28, 2009
May 26, 2009
Page 1: Change from typical 100,000 cycles to minimum 100,000
cycles
December 21, 2010
1.7
November 26, 2014
Page 4: Change Operating Temperature from “-55°C ~ +125°C” to
“0°C ~ +70°C”
(November, 2014 Version 1.7)
AMIC Technology, Corp.
A29002/A290021 Series
256K X 8 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
Minimum 100,000 program/erase cycles per sector
20-year data retention at 125°C
- Reliable operation for the life of the system
Compatible with JEDEC-standards
5.0V ± 10% for read and write operations
Access times:
- 70/90/120/150 (max.)
Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 μA typical CMOS standby
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
Flexible sector architecture
Polling and toggle bits
Data
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX3 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Provides a software method of detecting completion of
program or erase operations
Erase Suspend/Erase Resume
- Sector protection:
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within that
sector
Hardware reset pin (
)
RESET
Top or bottom boot block configurations available
Embedded Erase Algorithms
- Hardware method to reset the device to reading array
data (not available on A290021)
Package options
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors
and verify the erased sectors
- 32-pin P-DIP, PLCC, or TSOP (Forward type)
- Embedded Program algorithm automatically writes and
verifies bytes at specified addresses
General Description
The A29002 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard.
The A29002 is a 5.0 volt-only Flash memory organized as
262,144 bytes of 8 bits each. The A29002 offers the
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
function, but it is not available on A290021. The
RESET
256 Kbytes of data are further divided into seven sectors for
flexible sector erase capability. The 8 bits of data appear on
I/O0 - I/O7 while the addresses are input on A0 to A17. The
A29002 is offered in 32-pin PLCC, TSOP, and PDIP
packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write or
erase operations. However, the A29002 can also be
programmed in standard EPROM programmers.
The A29002 has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29002 has a second toggle bit, I/O2, to indicate whether the
addressed sector is being selected for erase. The A29002
also offers the ability to program in the Erase Suspend
mode. The standard A29002 offers access times of 70, 90,
120, and 150 ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
algorithm
-
an internal algorithm that automatically
preprograms the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies proper
erase margin.
The host system can detect whether a program or erase
operation is complete by reading the I/O7 (
Polling) and
Data
device has separate chip enable (
), write enable (
)
WE
CE
I/O6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The A29002 is fully erased when shipped
from the factory.
and output enable (
) controls.
OE
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
(November, 2014, Version 1.7)
1
AMIC Technology, Corp.
A29002/A290021 Series
data to, any other sector that is not selected for erasure.
True background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program
The hardware
pin terminates any operation in
RESET
progress and resets the internal state machine to reading
array data (This feature is not available on the A290021).
Pin Configurations
DIP
PLCC
NC on A290021
NC on A290021
1
VCC
WE
32
31
30
RESET
A16
2
3
4
A15
A17
A12
A7
A6
A5
A4
A3
A2
A14
A13
A8
29
28
27
26
5
6
7
8
A14
A13
A8
A7
A6
A5
A4
29
28
27
26
25
24
23
22
21
5
6
A9
7
8
A9
A11
25
24
23
22
A29002L/
A290021L
A11
OE
A10
CE
9
A3
A2
OE
9
10
A10
10
11
11
12
13
CE
A1
A0
A1
A0
I/O
7
12
13
14
15
16
21
20
19
18
17
I/O
I/O
I/O
0
1
2
I/O7
I/O
I/O
I/O
I/O
6
I/O0
5
4
VSS
3
TSOP (Forward type)
A11
A9
A8
A13
A14
A17
WE
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
VCC
RESET
A16
A15
A12
A7
A29002V/A290021V
9
VSS
10
11
12
13
14
15
16
I/O
I/O
I/O
A0
A1
A2
A3
2
1
0
NC on A290021
A6
A5
A4
(November, 2014, Version 1.7)
2
AMIC Technology, Corp.
A29002/A290021 Series
Block Diagram
I/O0 - I/O7
VCC
VSS
Input/Output
Buffers
Erase Voltage
Generator
State
Control
WE
RESET
PGM Voltage
Generator
(N/A A290021)
Command
Register
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
X-decoder
Cell Matrix
A0-A17
Pin Descriptions
Pin No.
A0 - A17
I/O0 - I/O7
Description
Address Inputs
Data Inputs/Outputs
Chip Enable
CE
WE
OE
Write Enable
Output Enable
Hardware Reset (N/A A290021)
Ground
RESET
VSS
VCC
Power Supply
(November, 2014, Version 1.7)
3
AMIC Technology, Corp.
A29002/A290021 Series
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended periods
may affect device reliability.
Ambient Operating Temperature …………….... 0°C to +70°C
Storage Temperature ……………………….. -65°C to +125°C
Ground to VCC …………………………………... -2.0V to 7.0V
Output Voltage (Note 1) ………………………… -2.0V to 7.0V
A9,
&
(Note 2) ………………….. -2.0V to 12.5V
RESET
OE
All other pins (Note 1) ………………………….. -2.0V to 7.0V
Output Short Circuit Current (Note 3)…………………. 200mA
Notes:
Operating Ranges
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, inputs may undershoot VSS to -2.0V
for periods of up to 20ns. Maximum DC voltage on output
and I/O pins is VCC +0.5V. During voltage transitions,
outputs may overshoot to VCC +2.0V for periods up to
20ns.
Commercial (C) Devices
Ambient Temperature (TA) . . ….. . . . . . . . . . 0°C to +70°C
VCC Supply Voltages
VCC for ± 10% devices …. . . . . . . . . . . . . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
2. Minimum DC input voltage on A9 pins is -0.5V. During
voltage transitions, A9,
and
may overshoot
RESET
OE
VSS to -2.0V for periods of up to 20ns. Maximum DC
input voltage on A9 and is +12.5V which may
OE
overshoot to 13.5V for periods up to 20ns. (
N/A on A290021)
is
RESET
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. A29002/A290021 Device Bus Operations
Operation
A0 – A17
I/O0 - I/O7
WE
CE
OE
RESET
(N/A A290021)
Read
Write
L
L
H
X
X
H
X
X
H
L
H
AIN
AIN
X
DOUT
DIN
L
H
CMOS Standby
TTL Standby
X
X
H
X
X
High-Z
High-Z
High-Z
High-Z
X
VCC ± 0.5 V
VCC ± 0.5 V
H
L
X
VCC ± 0.5 V
Output Disable
H
L
X
Reset
X
X
X
Temporary Sector Unprotect (Note)
Legend:
VID
X
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: 1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.
2. This function is not available on A290021.
(November, 2014, Version 1.7)
4
AMIC Technology, Corp.
A29002/A290021 Series
Standby Mode
Requirements for Reading Array Data
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
To read array data from the outputs, the system must drive
the
and
pins to VIL.
is the power control and
CE
OE
CE
selects the device.
OE
data to the output pins.
is the output control and gates array
placed in the high impedance state, independent of the
input.
OE
should remain at VIH all the time
WE
during read operation. The internal state machine is set for
reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration of
the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
The device enters the CMOS standby mode when the
&
CE
pins (
only on A290021) are both held at VCC ±
CE
0.5V. (Note that this is a more restricted voltage range than
VIH.) The device enters the TTL standby mode when is
RESET
CE
(Not available on A290021) is held
held at VIH, while
RESET
at VCC±0.5V. The device requires the standard access time
(tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
Output Disable Mode
Writing Commands/Command Sequences
When the
input is at VIH, output from the device is
OE
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
disabled. The output pins are placed in the high impedance
state.
memory), the system must drive
and
to VIL, and
CE
WE
to VIH. An erase operation can erase one sector,
OE
: Hardware Reset Pin (N/A on A290021)
RESET
multiple sectors, or the entire device. The Sector Address
Tables indicate the address range that each sector occupies.
A "sector address" consists of the address inputs required to
uniquely select a sector. See the "Command Definitions"
section for details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
The
pin provides a hardware method of resetting
RESET
the device to reading array data. When the system drives the
pin low for at least a period of tRP, the device
RESET
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
ICC2 in the Characteristics table represents the active current
specification for the write mode. The "AC Characteristics"
section contains timing specification tables and timing
diagrams for write operations.
the duration of the
pulse. The device also resets the
RESET
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
The
pin may be tied to the system reset circuitry. A
RESET
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for
parameters and diagram.
RESET
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section for
timing diagrams.
(November, 2014, Version 1.7)
5
AMIC Technology, Corp.
A29002/A290021 Series
Table 2. A29002/A290021 Top Boot Block Sector Address Table
Sector
A17
A16
A15
A14
A13
Sector Size
(Kbytes)
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
0
1
1
1
X
X
X
X
0
X
X
X
X
0
64
64
64
32
8
00000h - 0FFFFh
10000h - 1FFFFh
20000h - 2FFFFh
30000h - 37FFFh
38000h - 39FFFh
3A000h - 3BFFFh
3C000h - 3FFFFh
0
1
8
1
X
16
Table 3. A29002/A290021 Bottom Boot Block Sector Address Table
Sector
A17
A16
A15
A14
A13
Sector Size
(Kbytes)
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
X
X
X
0
1
X
0
16
8
00000h - 03FFFh
04000h - 05FFFh
06000h - 07FFFh
08000h - 0FFFFh
10000h - 1FFFFh
20000h - 2FFFFh
30000h - 3FFFFh
1
1
8
X
X
X
X
X
X
X
X
32
64
64
64
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.To access the
autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown in
the Command Definitions table. This method does not
require VID. See "Command Definitions" for details on using
the autoselect mode.
a
device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pinA9. Address
pins A6, A1, and AO must be as shown in Autoselect Codes
(High Voltage Method) table. In addition, when verifying
sector protection, the sector address must appear on the
Table 4. A29002/A290021 Autoselect Codes (High Voltage Method)
Description
A17 - A13 A12 - A10 A9 A8 - A7 A6 A5 - A2 A1
AO
Identifier Code on
I/O7 - I/O0
Manufacturer ID: AMIC
X
X
X
X
VID
VID
X
X
VIL
VIL
X
X
VIL
VIL
VIL
VIH
37h
Device ID: A29002/
A290021
Top Boot Block: 8Ch
Bottom Boot Block: 0Dh
01h (protected)
Sector Protection
Verification
Sector
X
VID
X
VIL
VIL
X
X
VIH
VIH
VIL
VIH
Address
00h (unprotected)
7Fh
Continuation ID
X
X
VID
X
Note:
=VIL,
=VIL and
=VIH when Autoselect Mode
WE
CE
OE
(November, 2014, Version 1.7)
6
AMIC Technology, Corp.
A29002/A290021 Series
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
START
Sector protection/unprotection must be implemented using
programming equipment. The procedure requires a high
voltage (VID) on address pin A9 and the control pins.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
RESET = VID
(Note 1)
Hardware Data Protection
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device
is powered up to read array data to avoid accidentally writing
data to the array.
Perform Erase or
Program Operations
RESET = VIH
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on
do not initiate a write cycle.
,
or
OE CE
WE
Logical Inhibit
Write cycles are inhibited by holding any one of
Temporary Sector
Unprotect
Completed (Note 2)
=VIL,
OE
CE
= VIH or
= VIH. To initiate a write cycle,
and
WE
CE
must be a logical zero while
is a logical one.
WE
OE
Notes:
Power-Up Write Inhibit
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
If
=
= VIL and
= VIH during power up, the
OE
WE
device does not accept commands on the rising edge of
. The internal state machine is automatically reset to
CE
WE
Figure 1. Temporary Sector Unprotect Operation
reading array data on the initial power-up.
Temporary Sector Unprotect (N/A on A290021)
This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the
pin to
RESET
VID. During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the
pin, all the previously
RESET
protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
(November, 2014, Version 1.7)
7
AMIC Technology, Corp.
A29002/A290021 Series
Command Definitions
Autoselect Command Sequence
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
The autoselect command sequence allows the host system
to access the manufacturer and devices codes, and
determine whether or not a sector is protected. The
Command Definitions table shows the address and data
requirements. This method is an alternative to that shown in
the Autoselect Codes (High Voltage Method) table, which is
intended for PROM programmers and requires VID on
address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system
may read at any address any number of times, without
initiating another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to the Sector
Address tables for valid sector addresses.
All addresses are latched on the falling edge of
or
,
CE
WE
whichever happens later. All data is latched on the rising
edge of or , whichever happens first. Refer to the
WE
CE
appropriate timing diagrams in the "AC Characteristics"
section.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended
sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See "Erase Suspend/Erase Resume Commands"
for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated program pulses
and verify the programmed cell margin. The Command
Definitions table shows the address and data requirements
for the byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using I/O7 or I/O6. See "Write
Operation Status" for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Programming is allowed in
any sequence and across sector boundaries. A bit cannot be
programmed from a "0" back to a "1 ". Attempting to do so
may halt the operation and set I/O5 to "1", or cause the
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in
a
program command sequence before
Polling algorithm to indicate the operation was
Data
programming begins. This resets the device to reading array
data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
successful. However, a succeeding read will show that the
data is still "0". Only erase operations can convert a "0" to a
"1".
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect
during Erase Suspend).
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
(November, 2014, Version 1.7)
8
AMIC Technology, Corp.
A29002/A290021 Series
Figure 3 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
START
Sector Erase Command Sequence
Write Program
Command
Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
Data Poll
from System
Embedded
Program
algorithm in
progress
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
Verify Data ?
Yes
After the command sequence is written, a sector erase time-
out of 50μs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional
cycles must be less than 50μs, otherwise the last address
and command might not be accepted, and erasure may
begin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be
less than 50μs, the system need not monitor I/O3. Any
command other than Sector Erase or Erase Suspend during
the time-out period resets the device to reading array data.
The system must rewrite the command sequence and any
additional sector addresses and commands.
No
Increment Address
Last Address ?
Yes
Programming
Completed
Note : See the appropriate Command Definitions table for
program command sequence.
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
Figure 2. Program Operation
pulse in the command sequence.
WE
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are
ignored.
Chip Erase Command Sequence
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched. The system can determine the status of the
erase operation by using I/O7, I/O6, or I/O2. Refer to "Write
Operation Status" for information on these status bits.
Figure 3 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to
provide any controls or timings during these operations. The
Command Definitions table shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50μs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
(November, 2014, Version 1.7)
9
AMIC Technology, Corp.
A29002/A290021 Series
operation. Addresses are "don't cares" when writing the
Erase Suspend command.
START
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20μs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
Write Erase
Command
Sequence
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on
I/O7 - I/O0. The system can use I/O7, or I/O6 and I/O2
together, to determine if a sector is actively erasing or is
erase-suspended. See "Write Operation Status" for
information on these status bits.
Data Poll
from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
After an erase-suspended program operation is complete,
the system can once again read array data within non-
suspended sectors. The system can determine the status of
the program operation using the I/O7 or I/O6 status bits, just
as in the standard program operation. See "Write Operation
Status" for more information.
Yes
Erasure Completed
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O3 : Sector Erase Timer" for more information.
Figure 3. Erase Operation
(November, 2014, Version 1.7)
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AMIC Technology, Corp.
A29002/A290021 Series
Table 5. A29002/A290021 Command Definitions
Command
Sequence
(Note 1)
Bus Cycles (Notes 2 - 4)
Third Fourth
Addr Data Addr Data Addr Data Addr Data
First
Addr Data Addr Data
RA RD
Second
Fifth
Sixth
Read (Note 5)
1
1
4
4
Reset (Note 6)
XXX F0
555 AA
555 AA
Autoselect Manufacturer ID
2AA 55
2AA 55
555 90
X00
X01
37
(Note 7)
Device ID Top
555
90
8C
0D
7F
Bottom
Continuation ID
4
555 AA
555 AA
2AA 55
2AA 55
555
555
90
90
X03
Sector Protect Verify 4
(Note 8)
SA
00
X02
01
Program
4
6
6
555 AA
555 AA
555 AA
XXX B0
XXX 30
2AA 55
2AA 55
2AA 55
555 A0
PA
555
555
PD
Chip Erase
Sector Erase
555
555
80
80
AA
AA
2AA
2AA
55
55
555 10
SA 30
Erase Suspend (Note 9)
Erase Resume (Note 10)
1
1
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the
whichever happens later.
or
pulse,
CE
WE
PD = Data to be programmed at location PA. Data latches on the rising edge of
or
pulse, whichever happens first.
CE
WE
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17 - A13 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A17 - A12 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
10. The Erase Resume command is valid only during the Erase Suspend mode.
11. The time between each command cycle has to be less than 50μs.
(November, 2014, Version 1.7)
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AMIC Technology, Corp.
A29002/A290021 Series
Write Operation Status
START
Several bits, I/O2, I/O3, I/O5, I/O6, and I/O7, are provided in
the A29002/A290021 to determine the status of a write
operation. Table 6 and the following subsections describe
the functions of these status bits. I/O7, I/O6 and I/O2 each
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
Read I/O7-I/O0
Address = VA
I/O7:
Polling
Data
Yes
I/O7 = Data ?
The
Polling bit, I/O7, indicates to the host system
Data
whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
No
I/O5 = 1?
Yes
Polling is valid after the rising edge of the final
WE
Data
pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on I/O7 the complement of the datum programmed
to I/O7. This I/O7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm
is complete, the device outputs the datum programmed to
I/O7. The system must provide the program address to
read valid status information on I/O7. If a program address
No
Read I/O7 - I/O0
Address = VA
falls within a protected sector,
Polling on I/O7 is
Data
active for approximately 2μs, then the device returns to
reading array data.
During the Embedded Erase algorithm,
Polling
Data
produces a "0" on I/O7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Yes
I/O7 = Data ?
Suspend mode,
Polling produces a "1" on I/O7.This
Data
is analogous to the complement/true datum output
described for the Embedded Program algorithm: the erase
function changes all the bits in a sector to "1"; prior to this,
the device outputs the "complement," or "0." The system
must provide an address within any of the sectors selected
for erasure to read valid status information on I/O7.
No
FAIL
PASS
After an erase command sequence is written, if all sectors
selected for erasing are protected,
Polling on I/O7 is
Data
active for approximately 100μs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0
on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.
Figure 4. Data Polling Algorithm
Enable (
) is asserted low. The
Polling Timings
Data
OE
(During Embedded Algorithms) figure in the "AC
Characteristics" section illustrates this. Table 6 shows the
outputs for
Data
Polling algorithm.
Polling on I/O7. Figure 4 shows the
Data
(November, 2014, Version 1.7)
12
AMIC Technology, Corp.
A29002/A290021 Series
Toggle Bit Timings figure for the toggle bit timing diagram.
The I/O2 vs. I/O6 figure shows the differences between I/O2
and I/O6 in graphical form.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
Reading Toggle Bits I/O6, I/O2
Refer to Figure 5 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read I/O7 - I/O0 at least twice in a row to determine whether
a toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation.
The system can read array data on I/O7 - I/O0 on the
following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of I/O5 is high (see the
section on I/O5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as I/O5 went high. If the
toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and I/O5 has not
gone high. The system may continue to monitor the toggle
bit and I/O5 through successive read cycles, determining
the status as described in the previous paragraph.
Alternatively, it may choose to perform other system tasks.
In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation (top of Figure 5).
the rising edge of the final
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause
pulse in the command
WE
I/O6 to toggle. (The system may use either
control the read cycles.) When the operation is complete,
I/O6 stops toggling.
or
to
CE
OE
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100μs, then returns to reading array data. If
not all selected sectors are protected, the Embedded
Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the
device enters the Erase Suspend mode, I/O6 stops
toggling. However, the system must also use I/O2 to
determine which sectors are erasing or erase-suspended.
Alternatively, the system can use I/O7 (see the subsection
on " I/O7 :
Polling").
Data
If a program address falls within a protected sector, I/O6
toggles for approximately 2μs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm
is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O2 vs.
I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on " I/O2: Toggle
Bit II".
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions I/O5 produces a "1." This is a failure
condition that indicates the program or erase cycle was not
successfully completed.
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed
to "0." Only an erase operation can change a "0" back to a
"1." Under this condition, the device halts the operation,
and when the operation has exceeded the timing limits,
I/O5 produces a "1."
I/O2: Toggle Bit II
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
rising edge of the final
sequence.
I/O2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
pulse in the command
WE
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out
is complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50μs. See also the "Sector Erase Command
Sequence" section.
system may use either
or
to control the read
CE
OE
cycles.) But I/O2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. I/O6, by
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status
bits are required for sector and mode information. Refer to
Table 6 to compare outputs for I/O2 and I/O6.
Figure 5 shows the toggle bit algorithm in flowchart form,
and the section " I/O2: Toggle Bit II" explains the algorithm.
See also the " I/O6: Toggle Bit I" subsection. Refer to the
(November, 2014, Version 1.7)
13
AMIC Technology, Corp.
A29002/A290021 Series
After the sector erase command sequence is written, the
system should read the status on I/O7 ( Polling) or
Data
START
I/O6 (Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until
the erase operation is complete. If I/O3 is "0", the device
will accept additional sector erase commands. To ensure
the command has been accepted, the system software
should check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have
been accepted. Table 6 shows the outputs for I/O3.
Read I/O7-I/O0
Read I/O7-I/O0
(Note 1)
No
Toggle Bit
= Toggle ?
Yes
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
(Notes 1,2)
Twice
No
Toggle Bit
= Toggle ?
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O5
changes to "1". See text.
Figure 5. Toggle Bit Algorithm
(November, 2014, Version 1.7)
14
AMIC Technology, Corp.
A29002/A290021 Series
Table 6. Write Operation Status
Operation
I/O7
I/O6
I/O5
(Note 2)
0
I/O3
I/O2
(Note 1)
(Note 1)
No toggle
Standard
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
N/A
I/O7
0
Toggle
0
0
1
Toggle
Toggle
Erase
Reading within Erase
Suspended Sector
1
No toggle
N/A
Suspend
Mode
Reading within Non-Erase
Suspend Sector
Data
I/O7
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
Toggle
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
20ns
(November, 2014, Version 1.7)
15
AMIC Technology, Corp.
A29002/A290021 Series
DC Characteristics
TTL/NMOS Compatible
Parameter
Symbol
ILI
Parameter Description
Test Description
Min.
Typ. Max.
Unit
Input Load Current
A9, Input Load Current
VIN = VSS to VCC. VCC = VCC Max
±1.0
100
μA
μA
ILIT
VCC = VCC Max,
&
OE RESET
A9,
&
=12.5V
OE RESET
ILO
Output Leakage Current
VOUT = VSS to VCC. VCC = VCC Max
±1.0
μA
ICC1
VCC Active Read Current
(Notes 1, 2)
20
30
30
mA
= VIL,
= VIL,
= VIH,
= VIH
CE
CE
CE
OE
ICC2
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)
40
mA
=VIH
OE
ICC3
VCC Standby Current (Note 2)
0.4
1.0
mA
= VCC ± 0.5V
RESET
VIL
VIH
VID
Input Low Level
-0.5
2.0
0.8
VCC+0.5
12.5
V
V
V
Input High Level
Voltage for Autoselect and
Temporary Unprotect Sector
Output Low Voltage
Output High Voltage
VCC = 5.25 V
10.5
VOL
VOH
IOL = 12mA, VCC = VCC Min
IOH = -2.5 mA, VCC = VCC Min
0.45
V
V
2.4
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
Min.
Typ. Max.
Unit
ILI
Input Load Current
A9,
VIN = VSS to VCC, VCC = VCC Max
±1.0
100
μA
μA
ILIT
VCC = VCC Max,
Input Load Current
&
OE RESET
A9,
&
= 12.5V
OE RESET
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max
±1.0
μA
ICC1
VCC Active Read Current
(Notes 1,2)
20
30
1
30
40
5
mA
= VIL,
= VIH
CE
OE
ICC2
ICC3
VCC Active Program/Erase Current
(Notes 2,3,4)
mA
= VIL,
= VIH
CE
OE
VCC Standby Current (Notes 2, 5)
μA
=
= VCC ± 0.5 V
CE RESET
VIL
VIH
VID
Input Low Level
-0.5
0.7 x VCC
10.5
0.8
VCC+0.3
12.5
V
V
V
Input High Level
Voltage for Autoselect and
Temporary Sector Unprotect
Output Low Voltage
Output High Voltage
VCC = 5.25 V
VOL
VOH1
VOH2
IOL = 12.0 mA, VCC = VCC Min
IOH = -2.5 mA, VCC = VCC Min
IOH = -100 μA. VCC = VCC Min
0.45
V
V
V
0.85 x VCC
VCC-0.4
Notes for DC characteristics (both tables):
1. The ICC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with
2. Maximum ICC specifications are tested with VCC = VCC max.
at VIH.
OE
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Not 100% tested.
5. For CMOS mode only, ICC3 = 20μA max at extended temperatures (> +85°C).
6.
is not available on A290021.
RESET
(November, 2014, Version 1.7)
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AMIC Technology, Corp.
A29002/A290021 Series
AC Characteristics
Read Only Operations
Parameter Symbols
Description
Test Setup
Speed
-120
Unit
JEDEC
Std
-70
-90
-150
Read Cycle Time (Note 2)
Address to Output Delay
tAVAV
tRC
Min.
70
90
120
120
150
ns
ns
= VIL
tAVQV
tACC
CE
Max.
70
90
150
= VIL
OE
Chip Enable to Output Delay
Output Enable to Output Delay
tELQV
tGLQV
tCE
Max.
Max.
Min.
70
30
0
90
35
0
120
50
0
150
55
0
ns
ns
ns
= VIL
OE
tOE
Read
Output Enable Hold
tOEH
Toggle and
Polling
Min.
10
10
10
10
Time (Note 2)
ns
Data
Chip Enable to Output High Z
(Notes 1,2)
tEHQZ
tGHQZ
tAXQX
tDF
tDF
tOH
Max.
20
20
0
20
20
0
30
30
0
35
35
0
ns
ns
ns
Output Enable to Output High Z
(Notes 1,2)
Output Hold Time from Addresses,
Min.
or
CE OE
, Whichever Occurs First
Notes:
1. Output driver disable time.
2. Not 100% tested.
Timing Waveforms for Read Only Operation (
=VIH on A29002)
RESET
tRC
Addresses
CE
Addresses Stable
t
ACC
t
DF
tOE
OE
tOEH
WE
tCE
tOH
High-Z
High-Z
Output
Output Valid
0V
(November, 2014, Version 1.7)
17
AMIC Technology, Corp.
A29002/A290021 Series
Hardware Reset (
Parameter
) (N/A on A290021)
Description
RESET
Test Setup
Max
All Speed Options
Unit
JEDEC
Std
tREADY
20
μs
Pin Low (During Embedded
RESET
Algorithms) to Read or Write (See Note)
tREADY
Max
500
ns
Pin Low (Not During Embedded
RESET
Algorithms) to Read or Write (See Note)
tRP
tRH
Min
Min
500
50
ns
ns
Pulse Width
RESET
RESET
High Time Before Read (See Note)
Note: Not 100% tested.
Timings
RESET
CE, OE
t
RH
RESET
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
RESET
t
RP
Temporary Sector Unprotect (N/A on A290021)
Parameter
JEDEC
Description
All Speed Options
Unit
Std
tVIDR
tRSP
VID Rise and Fall Time (See Note)
Min
Min
500
4
ns
μs
Setup Time for Temporary Sector
RESET
Unprotect
Note: Not 100% tested.
Temporary Sector Unprotect Timing Diagram
12V
0 or 5V
RESET
0 or 5V
t
VIDR
tVIDR
Program or Erase Command Sequence
CE
WE
t
RSP
(November, 2014, Version 1.7)
18
AMIC Technology, Corp.
A29002/A290021 Series
AC Characteristics
Erase and Program Operations
Parameter Symbols
Description
Speed
-120
Unit
JEDEC
tAVAV
Std
tWC
tAS
-70
-90
-150
Write Cycle Time (Note 1)
Min.
Min.
Min.
Min.
Min.
Min.
70
90
120
150
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
tAVWL
tWLAX
tDVWH
tWHDX
0
tAH
45
30
45
45
50
50
50
50
Data Setup Time
tDS
Data Hold Time
tDH
0
0
Output Enable Setup Time
Read Recover Time Before Write
tOES
tGHWL
tGHWL
Min.
0
ns
(
high to
low)
WE
OE
tELWL
tWHEH
tWLWH
tCS
tCH
tWP
Min.
Min.
Min.
Min.
Max.
0
0
ns
ns
ns
ns
μs
Setup Time
Hold Time
CE
CE
Write Pulse Width
35
45
50
50
20
50
tWHWL
tWHWH1
tWHWH2
tWPH
Write Pulse Width High
Byte Programming Operation
(Note 2)
tWHWH1
Typ.
7
μs
sec
μs
Sector Erase Operation
(Note 2)
tWHWH2
Typ.
Min.
1
VCC Set Up Time (Note 1)
tVCS
50
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
(November, 2014, Version 1.7)
19
AMIC Technology, Corp.
A29002/A290021 Series
Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
t
WC
tAS
Addresses
CE
PA
PA
555h
PA
t
AH
t
CH
t
GHWL
OE
t
WP
t
WHWH1
WE
t
CS
t
WPH
t
DS
t
DH
Data
VCC
A0h
PD
DOUT
Status
t
VCS
Note : PA = program addrss, PD = program data, Dout is the true data at the program address.
(November, 2014, Version 1.7)
20
AMIC Technology, Corp.
A29002/A290021 Series
Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
Read Status Data
tAS
tWC
SA
555h for chip erase
VA
Addresses
CE
2AAh
VA
t
AH
t
GHWL
t
CH
OE
t
WP
WE
t
WPH
tWHWH2
tCS
t
DS
t
DH
In
Progress
Data
VCC
55h
30h
10h for chip erase
Complete
tVCS
Note : SA = Sector Address. VA = Valid Address for reading status data.
(November, 2014, Version 1.7)
21
AMIC Technology, Corp.
A29002/A290021 Series
Timing Waveforms for
Polling (During Embedded Algorithms)
Data
t
RC
Addresses
CE
VA
VA
VA
t
ACC
t
CE
tCH
t
OE
OE
t
DF
tOEH
WE
tOH
High-Z
Valid Data
I/O7
Complement
Complement True
High-Z
I/O0
- I/O
6
Valid Data
Status Data
Status Data
True
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
(November, 2014, Version 1.7)
22
AMIC Technology, Corp.
A29002/A290021 Series
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
t
RC
Addresses
CE
VA
VA
VA
VA
t
ACC
CE
t
t
CH
t
OE
OE
t
DF
t
OEH
WE
t
OH
I/O6 , I/O2
Valid Status
(first read)
Valid Status
Valid Status
Valid Status
(second read)
(stop togging)
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
(November, 2014, Version 1.7)
23
AMIC Technology, Corp.
A29002/A290021 Series
Timing Waveforms for I/O2 vs. I/O6
Enter
Erase
Enter Erase
Suspend Program
Erase
Resume
Embedded
Suspend
Erasing
WE
Erase
Suspend
Program
Erase
Erase
Erase Suspend
Read
Erase Suspend
Read
Erase
Complete
I/O6
I/O2
I/O2 and I/O6 toggle with OE and CE
Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O 6 and I/O2 in the section "Write Operation Statue" for
more information.
AC Characteristics
Erase and Program Operations
Alternate
Controlled Writes
CE
Parameter Symbols
Description
Speed
-120
Unit
JEDEC
tAVAV
tAVEL
Std
tWC
tAS
-70
-90
-150
Write Cycle Time (Note 1)
Min.
Min.
Min.
Min.
Min.
Min.
Min.
70
90
120
150
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
0
tELAX
tAH
45
30
45
45
50
50
50
50
tDVEH
tEHDX
tGHEL
tWLEL
tDS
tDH
Data Hold Time
0
0
0
tGHEL
tWS
Read Recover Time Before Write
Setup Time
Hold Time
WE
WE
tEHWH
tWH
Min.
0
ns
tELEH
tEHEL
tCP
Write Pulse Width
Min.
Min.
35
20
45
20
50
20
50
20
ns
ns
tCPH
Write Pulse Width High
Byte Programming Operation
(Note 2)
tWHWH1
tWHWH2
tWHWH1
tWHWH2
Typ.
Typ.
7
1
μs
Sector Erase Operation
(Note 2)
sec
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
(November, 2014, Version 1.7)
24
AMIC Technology, Corp.
A29002/A290021 Series
Timing Waveforms for Alternate
Controlled Write Operation (
=VIH on A29002)
CE
RESET
PA for program
SA for sector erase
555 for chip erase
555 for program
2AA for erase
Data Polling
PA
Addresses
t
WC
tAS
t
AH
t
WH
WE
t
GHEL
OE
CE
t
WHWH1 or 2
t
CP
t
BUSY
t
CPH
t
WS
t
DS
t
DH
Data
DOUT
I/O7
t
RH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O
7
= Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Comments
Parameter
Sector Erase Time
Typ. (Note 1)
Max. (Note 2)
Unit
sec
sec
μs
1
8
8
Excludes 00h programming prior
to erasure (Note 4)
Chip Erase Time
64
Byte Programming Time
Chip Programming Time (Note 3)
Notes:
35
3.6
300
10.8
Excludes system-level overhead
(Note 5)
sec
1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
(November, 2014, Version 1.7)
25
AMIC Technology, Corp.
A29002/A290021 Series
Latch-up Characteristics
Description
Min.
-1.0V
Max.
VCC+1.0V
+100 mA
12.5V
Input Voltage with respect to VSS on all I/O pins
-100 mA
-1.0V
VCC Current
Input voltage with respect to VSS on all pins except I/O pins
(including A9,
and
)
RESET
OE
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.
N/A on A290021
RESET
TSOP Pin Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
VIN=0
Typ.
6
Max.
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
VOUT=0
VIN=0
8.5
7.5
pF
Control Pin Capacitance
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
PLCC and P-DIP Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
VIN=0
Typ.
Max.
6
Unit
pF
CIN
COUT
CIN2
Input Capacitance
4
8
8
Output Capacitance
Control Pin Capacitance
VOUT=0
VPP=0
pF
12
pF
12
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
Data Retention
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
20
125°C
(November, 2014, Version 1.7)
26
AMIC Technology, Corp.
A29002/A290021 Series
Test Conditions
Test Specifications
Test Condition
All others
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL(including jig capacitance)
Input Rise and Fall Times
100
20
pF
ns
V
Input Pulse Levels
0.45 - 2.4
0.8, 2.0
0.8, 2.0
Input timing measurement reference levels
Output timing measurement reference levels
V
V
Test Setup
5.0 V
2.7 KΩ
Device
Under
Test
Diodes = IN3064 or Equivalent
CL
6.2 KΩ
(November, 2014, Version 1.7)
27
AMIC Technology, Corp.
A29002/A290021 Series
Ordering Information
Top Boot Sector Flash
Part No.
Access Time
Active Read
Current
Program/Erase
Current
Standby Current
Package
(ns)
Typ. (μA)
Typ. (mA)
Typ. (mA)
A29002T-70
32Pin DIP
32Pin Pb-Free DIP
32Pin PLCC
A290021T-70
A29002T-70F
A290021T-70F
A29002TL-70
A290021TL-70
A29002TL-70F
A290021TL-70F
A29002TV-70
A290021TV-70
A29002TV-70F
A290021TV-70F
A29002T-90
70
20
30
1
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
32Pin DIP
A290021T-90
A29002T-90F
A290021T-90F
A29002TL-90
A290021TL-90
A29002TL-90F
A290021TL-90F
A29002TV-90
A290021TV-90
A29002TV-90F
A290021TV-90F
32Pin Pb-Free DIP
32Pin PLCC
90
20
30
1
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
(November, 2014, Version 1.7)
28
AMIC Technology, Corp.
A29002/A290021 Series
Ordering Information (continued)
Top Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Program/Erase
Current
Standby Current
Package
Typ. (μA)
Typ. (mA)
Typ. (mA)
A29002T-120
32Pin DIP
32Pin Pb-Free DIP
32Pin PLCC
A290021T-120
A29002T-120F
A290021T-120F
A29002TL-120
A290021TL-120
A29002TL-120F
A290021TL-120F
A29002TV-120
A290021TV-120
A29002TV-120F
A290021TV-120F
A29002T-150
120
20
30
1
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
32Pin DIP
A290021T-150
A29002T-150F
A290021T-150F
A29002TL-150
A290021TL-150
A29002TL-150F
A290021TL-150F
A29002TV-150
A290021TV-150
A29002TV-150F
A290021TV-150F
32Pin Pb-Free DIP
32Pin PLCC
150
20
30
1
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
(November, 2014, Version 1.7)
29
AMIC Technology, Corp.
A29002/A290021 Series
Ordering Information (continued)
Bottom Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Program/Erase
Current
Standby Current
Package
Typ. (μA)
Typ. (mA)
Typ. (mA)
A29002U-70
32Pin DIP
32Pin Pb-Free DIP
32Pin PLCC
A290021U-70
A29002U-70F
A290021U-70F
A29002UL-70
A290021UL-70
A29002UL-70F
A290021UL-70F
A29002UV-70
A290021UV-70
A29002UV-70F
A290021UV-70F
A29002U-90
70
20
30
1
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
32Pin DIP
A290021U-90
A29002U-90F
A290021U-90F
A29002UL-90
A290021UL-90
A29002UL-90F
A290021UL-90F
A29002UV-90
A290021UV-90
A29002UV-90F
A290021UV-90F
32Pin Pb-Free DIP
32Pin PLCC
90
20
30
1
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
(November, 2014, Version 1.7)
30
AMIC Technology, Corp.
A29002/A290021 Series
Ordering Information (continued)
Bottom Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Program/Erase
Current
Standby Current
Package
Typ. (μA)
Typ. (mA)
Typ. (mA)
A29002U-120
32Pin DIP
32Pin Pb-Free DIP
32Pin PLCC
A290021U-120
A29002U-120F
A290021U-120F
A29002UL-120
A290021UL-120
A29002UL-120F
A290021UL-120F
A29002UV-120
A290021UV-120
A29002UV-120F
A290021UV-120F
A29002U-150
120
20
30
1
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
32Pin DIP
A290021U-150
A29002U-150F
A290021U-150F
A29002UL-150
A290021UL-150
A29002UL-150F
A290021UL-150F
A29002UV-150
A290021UV-150
A29002UV-150F
A290021UV-150F
32Pin Pb-Free DIP
32Pin PLCC
150
20
30
1
32Pin Pb-Free PLCC
32Pin TSOP
32Pin Pb-Free TSOP
(November, 2014, Version 1.7)
31
AMIC Technology, Corp.
A29002/A290021 Series
Package Information
P-DIP 32L Outline Dimensions
unit: inches/mm
D
32
17
1
16
E
1
Base Plane
Seating Plane
B
B
E
A
θ
e
1
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
0.210
-
Min
Nom
Max
A
-
-
-
-
-
5.334
-
A1
A2
0.015
0.149
0.381
3.785
0.154
0.159
3.912
4.039
B
-
-
0.018
0.050
-
-
-
-
-
-
0.457
1.270
0.254
-
-
-
B1
C
D
-
0.010
1.650
1.645
1.655 41.783 41.91 42.037
0.547 13.64 13.767 13.894
E
E1
EA
e
0.537
0.590
0.630
-
0.542
0.600
0.650
0.100
0.130
-
0.610 14.986 15.240 15.494
0.670 16.002 16.510 17.018
-
-
2.540
3.302
-
-
L
0.120
0°
0.140
15°
3.048
0°
3.556
15°
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
(November, 2014, Version 1.7)
32
AMIC Technology, Corp.
A29002/A290021 Series
Package Information
PLCC 32L Outline Dimension
unit: inches/mm
HD
D
13
5
14
4
1
32
20
30
29
21
b
e
b
1
GE
y
θ
GD
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
0.134
-
Min
-
Nom
-
Max
3.40
-
A
A1
A2
b1
b
0.0185
0.105
0.026
0.016
0.008
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.075
-
-
0.47
2.67
0.66
0.41
0.20
-
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.510
0.410
0.590
0.490
0.090
-
0.115
0.032
0.021
0.014
0.553
0.453
0.056
0.530
0.430
0.595
0.495
0.095
0.003
10°
2.80
0.71
0.46
0.254
13.97
11.43
1.27
12.95
10.41
14.99
12.45
2.29
-
2.93
0.81
0.54
0.35
14.05
11.51
1.42
13.46
10.92
15.11
12.57
2.41
0.075
10°
C
D
13.89
11.35
1.12
12.45
9.91
14.86
12.32
1.91
-
E
e
GD
GE
HD
HE
L
y
θ
0°
-
0°
-
Notes:
1. Dimensions D and E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
(November, 2014, Version 1.7)
33
AMIC Technology, Corp.
A29002/A290021 Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
θ
L
L
E
HD
Detail "A"
Detail "A"
y
S
b
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
Min
Nom
Max
A
A1
A2
b
-
0.047
0.006
0.041
0.011
0.008
0.728
0.319
-
-
1.20
0.15
1.05
0.27
0.20
18.50
8.10
0.002
0.037
0.007
0.004
0.720
-
-
0.039
0.009
-
0.05
0.95
0.18
0.11
18.30
-
-
1.00
0.22
-
c
D
E
0.724
0.315
0.020 BSC
0.787
0.020
0.032
-
18.40
8.00
0.50 BSC
20.00
0.50
0.80
-
e
HD
L
0.779
0.795
0.024
-
19.80
20.20
0.60
-
0.016
0.40
LE
S
-
-
-
-
0.020
0.003
5°
0.50
0.08
5°
y
-
-
-
-
-
-
θ
0°
0°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(November, 2014, Version 1.7)
34
AMIC Technology, Corp.
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