A29001UX-55 [AMICC]
128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory; 128K ×8位CMOS 5.0伏只，引导扇区闪存
| 型号： | A29001UX-55 |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| 文件： | 总36页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A29001/290011 Series
128K X 8 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Document Title
128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
Initial issue
October 19, 2000
January 3, 2001
Preliminary
Change ILIT from 50µA to 100µA
Change typical byte programming time from 7µs to 35µs
Erase VCC supply voltage for ± 5% devices in Operation Ranges
Add the time limit tWPH max. = 50µs of command cycle sequence
Correct the Continuation ID command to hexadecimal
Error Correction:
0.2
February 6, 2001
0.3
0.4
August 21, 2001
December 24, 2002
P.8: Autoselect Command Sequence (line 15), XX11h → XX03h
Final version release
1.0
1.1
October 7, 2003
Final
Add 32Pin Pb-Free TSOP package type for A290011UV-70(U)F &
A290011TV-70(U)F
February 16, 2004
1.2
1.3
Add Pb-Free package type for all parts
Add sTSOP package type.
August 5, 2004
December 1, 2004
(December, 2004, Version 1.3)
AMIC Technology, Corp.
A29001/290011 Series
128K X 8 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
ꢀTypical 100,000 program/erase cycles per sector
ꢀ20-year data retention at 125°C
- Reliable operation for the life of the system
ꢀCompatible with JEDEC-standards
ꢀ5.0V ± 10% for read and write operations
ꢀAccess times:
- 55/70/90 (max.)
ꢀCurrent:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 µA typical CMOS standby
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
ꢀFlexible sector architecture
ꢀ
Polling and toggle bits
Data
- 8 Kbyte/ 4 KbyteX2/ 16 Kbyte/ 32 KbyteX3 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Provides a software method of detecting completion
of program or erase operations
ꢀErase Suspend/Erase Resume
- Sector protection:
- Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector, then
resumes the erase operation
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
ꢀHardware reset pin (
)
RESET
ꢀTop or bottom boot block configurations available
ꢀEmbedded Erase Algorithms
- Hardware method to reset the device to reading array
data (not available on A290011)
ꢀIndustrial operating temperature range: -40°C to +85°C
for – U
ꢀPackage options: 32-pin P-DIP, PLCC, TSOP or
sTSOP (Forward type)
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
General Description
The A29001 is a 5.0 volt-only Flash memory organized as
131,072 bytes of 8 bits each. The A29001 offers the
The A29001 is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the
programming and erase operations. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times
the program pulse widths and verifies proper program
margin.
function, but it is not available on A290011. The
RESET
128 Kbytes of data are further divided into seven sectors for
flexible sector erase capability. The 8 bits of data appear on
I/O0 - I/O7 while the addresses are input on A0 to A16. The
A29001 is offered in 32-pin PLCC, TSOP, sTSOP and PDIP
packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write
or erase operations. However, the A29001 can also be
programmed in standard EPROM programmers.
The A29001 has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29001 has a second toggle bit, I/O2, to indicate whether
the addressed sector is being selected for erase. The
A29001 also offers the ability to program in the Erase
Suspend mode. The standard A29001 offers access times
of 55, 70 and 90 ns allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm
- an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
device has separate chip enable (
), write enable (
)
WE
CE
and output enable (
) controls.
OE
The host system can detect whether a program or erase
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
operation is complete by reading the I/O7 (
Polling)
Data
and I/O6 (toggle) status bits. After a program or erase
cycle has been completed, the device is ready to read
array data or accept another command.
(December, 2004, Version 1.3)
1
AMIC Technology, Corp.
A29001/A290011 Series
The Erase Suspend feature enables the user to put erase
on hold for any period of time to read data from, or
program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
The sector erase architecture allows memory sectors to
be erased and reprogrammed without affecting the data
contents of other sectors. The A29001 is fully erased
when shipped from the factory.
The hardware sector protection feature disables
operations for both program and erase in any
combination of the sectors of memory. This can be
achieved via programming equipment.
The hardware
pin terminates any operation in
RESET
progress and resets the internal state machine to reading
array data (This feature is not available on the A290011).
Pin Configurations
ꢀDIP
ꢀPLCC
NC on A290011
NC on A290011
1
VCC
WE
NC
32
31
30
RESET
A16
2
3
4
A15
A12
A7
A6
A5
A4
A3
A14
A13
A8
29
28
27
26
5
6
7
8
A14
A13
A8
A7
A6
A5
A4
29
28
27
26
25
24
23
22
21
5
6
A9
7
A9
8
A11
25
24
23
22
A29001L/
A290011L
A11
OE
A10
CE
9
A3
A2
OE
9
10
A10
10
11
12
13
14
15
16
A2
A1
A0
11
12
13
CE
A1
A0
I/O
7
21
20
19
18
17
I/O
I/O
I/O
0
1
2
I/O7
I/O
I/O
I/O
I/O
6
5
4
3
I/O0
VSS
ꢀTSOP/sTSOP (Forward type)
A11
A9
A8
A13
A14
NC
1
2
3
4
5
6
7
8
32
OE
A10
CE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
WE
A29001V/A290011V
A29001X/A290011X
VCC
RESET
A16
A15
9
10
11
12
13
14
15
16
NC on A290011
A12
A7
A6
A5
A4
A1
A2
A3
(December, 2004, Version 1.3)
2
AMIC Technology, Corp.
A29001/A290011 Series
Block Diagram
I/O0 - I/O7
VCC
VSS
Input/Output
Buffers
Erase Voltage
Generator
State
Control
WE
RESET
PGM Voltage
Generator
(N/A A290011)
Command
Register
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
X-decoder
Cell Matrix
A0-A16
Pin Descriptions
Pin No.
A0 - A16
I/O0 - I/O7
Description
Address Inputs
Data Inputs/Outputs
Chip Enable
CE
WE
OE
Write Enable
Output Enable
Hardware Reset (N/A A290011)
Ground
RESET
VSS
VCC
Power Supply
(December, 2004, Version 1.3)
3
AMIC Technology, Corp.
A29001/A290011 Series
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
Ambient Operating Temperature . . . . .-55°C to + 125°C
Storage Temperature . . . . . . . . . . . . . . .-65°C to + 150°C
Ground to VCC . . . . . . . . . . . . . . . . . . . .. . . -2.0V to 7.0V
Output Voltage (Note 1) . . . . . . . . . . . . ……-2.0V to 7.0V
A9,
&
(Note 2) . . . . . . . . . . . -2.0V to 12.5V
RESET
OE
All other pins (Note 1) . . . . . . . . . . . . . . . . ..-2.0V to 7.0V
Output Short Circuit Current (Note 3) . .. . . . . . . . 200mA
Notes:
Operating Ranges
1. Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot
VSS to -2.0V for periods of up to 20ns. Maximum DC
voltage on output and I/O pins is VCC +0.5V. During
voltage transitions, outputs may overshoot to VCC
+2.0V for periods up to 20ns.
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . .0°C to +70°C
Extended Range Devices
Ambient Temperature (TA) . . . . . . . . . . . . -40°C to +85°C
2. Minimum DC input voltage on A9 pins is -0.5V. During
voltage transitions, A9,
and
may
overshoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 and is +12.5V
VCC Supply Voltages
OE
RESET
VCC for ± 10% devices . . . . . . . . . . . . . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
OE
which may overshoot to 13.5V for periods up to 20ns.
is N/A on A290011)
(
RESET
3. No more than one output is shorted at a time.
Duration of the short circuit should not be greater than
one second.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is composed of latches that store the commands,
along with the address and data information needed to
execute the command. The contents of the register serve
as inputs to the internal state machine. The state
machine outputs dictate the function of the device. The
appropriate device bus operations table lists the inputs
and control levels required, and the resulting output. The
following subsections describe each of these operations
in further detail.
Table 1. A29001/A290011 Device Bus Operations
Operation
A0 – A16
I/O0 - I/O7
WE
CE
OE
RESET
(N/A A290011)
Read
Write
L
L
H
X
X
H
X
X
H
L
H
AIN
AIN
X
DOUT
DIN
L
H
CMOS Standby
TTL Standby
X
X
H
X
X
High-Z
High-Z
High-Z
High-Z
X
VCC ± 0.5 V
VCC ± 0.5 V
H
L
X
VCC ± 0.5 V
Output Disable
H
L
X
Reset
X
X
X
Temporary Sector Unprotect (Note)
VID
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: 1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.
2. This function is not available on A290011.
(December, 2004, Version 1.3)
4
AMIC Technology, Corp.
A29001/A290011 Series
Standby Mode
Requirements for Reading Array Data
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of the
To read array data from the outputs, the system must drive
the
and
pins to VIL.
is the power control and
CE
OE
CE
selects the device.
is the output control and gates
OE
array data to the output pins.
should remain at VIH all
WE
input.
OE
the time during read operation. The internal state machine
is set for reading array data upon device power-up, or after
a hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to
the AC Read Operations table for timing specifications and
to the Read Operations Timings diagram for the timing
waveforms, lCC1 in the DC Characteristics table represents
the active current specification for reading array data.
The device enters the CMOS standby mode when the
CE
only on A290011) are both held at
&
pins (
CE
RESET
VCC ± 0.5V. (Note that this is a more restricted voltage
range than VIH.) The device enters the TTL standby mode
when
is held at VIH, while
(Not available on
RESET
CE
A290011) is held at VCC±0.5V. The device requires the
standard access time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represents the
standby current specification.
Output Disable Mode
Writing Commands/Command Sequences
When the
input is at VIH, output from the device is
OE
disabled. The output pins are placed in the high impedance
state.
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive
and
CE
WE
: Hardware Reset Pin (N/A on A290011)
RESET
to VIL, and
to VIH. An erase operation can erase one
OE
The
pin provides a hardware method of resetting
RESET
the device to reading array data. When the system drives
the pin low for at least a period of tRP, the device
sector, multiple sectors, or the entire device. The Sector
Address Tables indicate the address range that each
sector occupies. A "sector address" consists of the address
inputs required to uniquely select a sector. See the
"Command Definitions" section for details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register
(which is separate from the memory array) on I/O7 - I/O0.
Standard read cycle timings apply in this mode. Refer to
the "Autoselect Mode" and "Autoselect Command
Sequence" sections for more information.
RESET
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
pulse. The device also resets
RESET
The
pin may be tied to the system reset circuitry.
RESET
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for
parameters and diagram.
ICC2 in the Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
RESET
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
(December, 2004, Version 1.3)
5
AMIC Technology, Corp.
A29001/A290011 Series
Table 2. A29001/A290011 Top Boot Block Sector Address Table
Sector
A16
A15
A14
A13
A12
Sector Size
(Kbytes)
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
0
1
1
1
X
X
X
X
0
X
X
X
X
0
32
32
32
16
4
00000h - 07FFFh
08000h - 0FFFFh
10000h - 17FFFh
18000h - 1BFFFh
1C000h - 1CFFFh
1D000h - 1DFFFh
1E000h - 1FFFFh
0
1
4
1
X
8
Table 3. A29001/A290011 Bottom Boot Block Sector Address Table
Sector
A16
A15
A14
A13
A12
Sector Size
(Kbytes)
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
X
X
X
0
1
X
0
8
4
00000h - 01FFFh
02000h - 02FFFh
03000h - 03FFFh
04000h - 07FFFh
08000h - 0FFFFh
10000h - 17FFFh
18000h - 1FFFFh
1
1
4
X
X
X
X
X
X
X
X
16
32
32
32
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is
primarily intended for programming equipment to
automatically match a device to be programmed with its
corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5V to 12.5 V) on address pinA9.
Address pins A6, A1, and AO must be as shown in
Autoselect Codes (High Voltage Method) table. In
addition, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address
Tables. The Command Definitions table shows the
remaining address bits that are don't care. When all
necessary bits have been set as required, the
programming
equipment
may
then
read
the
corresponding identifier code on I/O7 - I/O0.To access the
autoselect codes in-system, the host system can issue
the autoselect command via the command register, as
shown in the Command Definitions table. This method
does not require VID. See "Command Definitions" for
details on using the autoselect mode.
Table 4. A29001/A290011 Autoselect Codes (High Voltage Method)
Description
A16 - A12 A11 - A10 A9 A8 - A7 A6 A5 - A2 A1
A0
Identifier Code on
I/O7 - I/O0
Manufacturer ID: AMIC
X
X
X
X
VID
X
X
VIL
VIL
X
X
VIL
VIL
VIL
VIH
37h
Device ID: A29001/
A290011
VID
Top Boot Block: A1h
Bottom Boot Block: 4Ch
01h (protected)
Sector Protection
Verification
Sector
X
X
VID
VID
X
X
VIL
VIL
X
X
VIH
VIH
VIL
VIH
Address
00h (unprotected)
7Fh
Continuation ID
X
Note:
=VIL,
=VIL and
OE
=VIH when Autoselect Mode
WE
CE
(December, 2004, Version 1.3)
6
AMIC Technology, Corp.
A29001/A290011 Series
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
START
Sector protection/unprotection must be implemented using
programming equipment. The procedure requires a high
voltage (VID) on address pin A9 and the control pins.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
RESET = VID
(Note 1)
Hardware Data Protection
Perform Erase or
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions
table). In addition, the following hardware data protection
measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level
signals during VCC power-up transitions, or from system
noise. The device is powered up to read array data to
avoid accidentally writing data to the array.
Program Operations
RESET = VIH
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on
,
or
OE CE
Temporary Sector
Unprotect
do not initiate a write cycle.
WE
Completed (Note 2)
Logical Inhibit
Write cycles are inhibited by holding any one of
=VIL,
OE
CE
= VIH or
= VIH. To initiate a write cycle,
and
WE
CE
Notes:
must be a logical zero while
is a logical one.
WE
OE
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Power-Up Write Inhibit
If
=
= VIL and
= VIH during power up, the
OE
WE
device does not accept commands on the rising edge of
. The internal state machine is automatically reset to
CE
Figure 1. Temporary Sector Unprotect Operation
WE
reading array data on the initial power-up.
Temporary Sector Unprotect (N/A A290011)
This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the
pin to
RESET
VID. During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the
pin, all the
RESET
previously protected sectors are protected again. Figure 1
shows the algorithm, and the Temporary Sector Unprotect
diagram shows the timing waveforms, for this feature.
(December, 2004, Version 1.3)
7
AMIC Technology, Corp.
A29001/A290011 Series
Command Definitions
Autoselect Command Sequence
Writing specific address and data commands or
sequences into the command register initiates device
operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the improper
sequence resets the device to reading array data.
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected. The
Command Definitions table shows the address and data
requirements. This method is an alternative to that shown
in the Autoselect Codes (High Voltage Method) table,
which is intended for PROM programmers and requires
VID on address bit A9.
The autoselect command sequence is initiated by writing
two unlock cycles, followed by the autoselect command.
The device then enters the autoselect mode, and the
system may read at any address any number of times,
without initiating another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to the Sector
Address tables for valid sector addresses.
All addresses are latched on the falling edge of
or
WE
, whichever happens later. All data is latched on the
CE
rising edge of
or
, whichever happens first. Refer
WE
CE
to the appropriate timing diagrams in the "AC
Characteristics" section.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode.
The system can read array data using the standard read
timings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. After
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
completing
a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See "Erase Suspend/Erase
Resume Commands" for more information on this mode.
The system must issue the reset command to re-enable
the device for reading array data if I/O5 goes high, or while
in the autoselect mode. See the "Reset Command"
section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing
diagram.
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is
not required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verify the programmed cell margin.
The Command Definitions table shows the address and
data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status of the program operation by using I/O7 or I/O6. See
"Write Operation Status" for information on these status
bits.
Reset Command
Writing the reset command to the device resets the device
to reading array data. Address bits are don't care for this
command. The reset command may be written between
the sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence before
programming begins. This resets the device to reading
array data (also applies to programming in Erase Suspend
mode). Once programming begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be
written to return to reading array data (also applies to
autoselect during Erase Suspend).
Any commands written to the device during the Embedded
Program Algorithm are ignored. Programming is allowed in
any sequence and across sector boundaries. A bit cannot
be programmed from a "0" back to a "1 ". Attempting to do
so may halt the operation and set I/O5 to "1", or cause the
Polling algorithm to indicate the operation was
Data
successful. However, a succeeding read will show that the
data is still "0". Only erase operations can convert a "0" to
a "1".
If I/O5 goes high during a program or erase operation,
writing the reset command returns the device to reading
array data (also applies during Erase Suspend).
(December, 2004, Version 1.3)
8
AMIC Technology, Corp.
A29001/A290011 Series
Figure 3 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
START
Sector Erase Command Sequence
Write Program
Command
Sequence
Sector erase is a six-bus-cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector erase
command. The Command Definitions table shows the
address and data requirements for the sector erase
command sequence.
Data Poll
from System
Embedded
Program
algorithm in
progress
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all
zero data pattern prior to electrical erase. The system is
not required to provide any controls or timings during
these operations.
Verify Data ?
Yes
No
After the command sequence is written, a sector erase
time-out of 50µs begins. During the time-out period,
additional sector addresses and sector erase commands
may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these
additional cycles must be less than 50µs, otherwise the
last address and command might not be accepted, and
erasure may begin. It is recommended that processor
interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-
enabled after the last Sector Erase command is written. If
the time between additional sector erase commands can
be assumed to be less than 50µs, the system need not
monitor I/O3. Any command other than Sector Erase or
Erase Suspend during the time-out period resets the
device to reading array data. The system must rewrite the
command sequence and any additional sector addresses
and commands.
Increment Address
Last Address ?
Yes
Programming
Completed
Note : See the appropriate Command Definitions table for
program command sequence.
The system can monitor I/O3 to determine if the sector
erase timer has timed out. (See the " I/O3: Sector Erase
Timer" section.) The time-out begins from the rising edge
Figure 2. Program Operation
of the final
pulse in the command sequence.
WE
Chip Erase Command Sequence
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands are
ignored.
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase
algorithm automatically preprograms and verifies the
entire memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls
or timings during these operations. The Command
Definitions table shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched. The system can determine the status of
the erase operation by using I/O7, I/O6, or I/O2. Refer to
"Write Operation Status" for information on these status
bits. Figure 3 illustrates the algorithm for the erase
operation. Refer to the Erase/Program Operations tables
in the "AC Characteristics" section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data from,
or program data to, any sector not selected for erasure.
This command is valid only during the sector erase
operation, including the 50µs time-out period during the
sector erase command sequence. The Erase Suspend
The system can determine the status of the erase
operation by using I/O7, I/O6, or I/O2. See "Write Operation
Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched.
(December, 2004, Version 1.3)
9
AMIC Technology, Corp.
A29001/A290011 Series
command is ignored if written during the chip erase
operation or Embedded Program algorithm. Writing the
Erase Suspend command during the Sector Erase time-
out immediately terminates the time-out period and
suspends the erase operation. Addresses are "don't
cares" when writing the Erase Suspend command.
START
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20µs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector
erase time-out, the device immediately terminates the
time-out period and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector
not selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write
timings and command definitions apply. Reading at any
address within erase-suspended sectors produces status
data on I/O7 - I/O0. The system can use I/O7, or I/O6 and
I/O2 together, to determine if a sector is actively erasing or
is erase-suspended. See "Write Operation Status" for
information on these status bits.
Write Erase
Command
Sequence
Data Poll
from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
After an erase-suspended program operation is complete,
the system can once again read array data within non-
suspended sectors. The system can determine the status
of the program operation using the I/O7 or I/O6 status bits,
just as in the standard program operation. See "Write
Operation Status" for more information.
Yes
Erasure Completed
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the device
has resumed erasing.
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O
3
: Sector Erase Timer" for more information.
Figure 3. Erase Operation
(December, 2004, Version 1.3)
10
AMIC Technology, Corp.
A29001/A290011 Series
Table 5. A29001/A290011 Command Definitions
Command
Sequence
(Note 1)
Bus Cycles (Notes 2 - 4)
First
Addr Data Addr Data
RA RD
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data
Read (Note 5)
1
1
4
4
Reset (Note 6)
XXX F0
555 AA
555 AA
Autoselect Manufacturer ID
2AA 55
2AA 55
555 90
X00
X01
37
(Note 7)
Device ID Top
555
90
A1
4C
7F
Bottom
Continuation ID
4
555 AA
555 AA
2AA 55
2AA 55
555
555
90
90
X03
Sector Protect Verify 4
(Note 8)
SA
00
X02
01
Program
4
6
6
555 AA
555 AA
555 AA
XXX B0
XXX 30
2AA 55
2AA 55
2AA 55
555 A0
PA
555
555
PD
Chip Erase
Sector Erase
555
555
80
80
AA
AA
2AA 55
2AA 55
555
SA
10
30
Erase Suspend (Note 9)
Erase Resume (Note 10)
1
1
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the
whichever happens later.
or
pulse,
WE
CE
PD = Data to be programmed at location PA. Data latches on the rising edge of
or
pulse, whichever happens first.
CE
WE
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A16 - A12 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A16 - A12 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend
mode.
10. The Erase Resume command is valid only during the Erase Suspend mode.
11. The time between each command cycle has to be less than 50µs.
(December, 2004, Version 1.3)
11
AMIC Technology, Corp.
A29001/A290011 Series
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, and I/O7, are provided in
the A29001/A290011 to determine the status of a write
operation. Table 6 and the following subsections describe
the functions of these status bits. I/O7, I/O6 and I/O2 each
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
START
Read I/O7-I/O0
Address = VA
I/O7:
Polling
Data
The
Polling bit, I/O7, indicates to the host system
Data
Yes
whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
I/O
7
= Data ?
No
Polling is valid after the rising edge of the final
Data
pulse in the program or erase command sequence.
WE
During the Embedded Program algorithm, the device
outputs on I/O7 the complement of the datum programmed
to I/O7. This I/O7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm
is complete, the device outputs the datum programmed to
I/O7. The system must provide the program address to
read valid status information on I/O7. If a program address
No
I/O5 = 1?
falls within a protected sector,
Polling on I/O7 is
Data
Yes
active for approximately 2µs, then the device returns to
reading array data.
Read I/O
Address = VA
7
- I/O0
During the Embedded Erase algorithm,
Polling
Data
produces a "0" on I/O7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode,
Polling produces a "1" on I/O7.This
Data
is analogous to the complement/true datum output
described for the Embedded Program algorithm: the erase
function changes all the bits in a sector to "1"; prior to this,
the device outputs the "complement," or "0." The system
must provide an address within any of the sectors selected
for erasure to read valid status information on I/O7.
Yes
I/O7
= Data ?
No
After an erase command sequence is written, if all sectors
selected for erasing are protected,
Polling on I/O7 is
Data
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sectors that
are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 -
I/O0 on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
Enable (
) is asserted low. The
Polling Timings
Data
OE
2. I/O
7
should be rechecked even if I/O
may change simultaneously with I/O
5 = "1" because
(During Embedded Algorithms) figure in the "AC
I/O7
5
.
Characteristics" section illustrates this. Table 6 shows the
outputs for
Data
Polling algorithm.
Polling on I/O7. Figure 4 shows the
Data
Figure 4. Data Polling Algorithm
(December, 2004, Version 1.3)
12
AMIC Technology, Corp.
A29001/A290011 Series
The I/O2 vs. I/O6 figure shows the differences between I/O2
and I/O6 in graphical form.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
Reading Toggle Bits I/O6, I/O2
Refer to Figure 5 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read I/O7 - I/O0 at least twice in a row to determine whether
a toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After
the second read, the system would compare the new value
of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase
operation. The system can read array data on I/O7 - I/O0
on the following read cycle.
the rising edge of the final
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause
pulse in the command
WE
I/O6 to toggle. (The system may use either
control the read cycles.) When the operation is complete,
I/O6 stops toggling.
or
to
CE
OE
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If
not all selected sectors are protected, the Embedded
Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the
device enters the Erase Suspend mode, I/O6 stops
toggling. However, the system must also use I/O2 to
determine which sectors are erasing or erase-suspended.
Alternatively, the system can use I/O7 (see the subsection
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of I/O5 is high (see the
section on I/O5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as I/O5 went high. If the
toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and I/O5 has not
gone high. The system may continue to monitor the toggle
bit and I/O5 through successive read cycles, determining
the status as described in the previous paragraph.
Alternatively, it may choose to perform other system tasks.
In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation (top of Figure 5).
on " I/O7 :
Polling").
Data
If a program address falls within a protected sector, I/O6
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm
is complete.
I/O5: Exceeded Timing Limits
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O2
vs. I/O6 figure shows the differences between I/O2 and I/O6
in graphical form. See also the subsection on " I/O2:
Toggle Bit II".
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions I/O5 produces a "1." This is a failure
condition that indicates the program or erase cycle was not
successfully completed.
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed
to "0." Only an erase operation can change a "0" back to a
"1." Under this condition, the device halts the operation,
and when the operation has exceeded the timing limits,
I/O5 produces a "1."
I/O2: Toggle Bit II
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
rising edge of the final
sequence.
pulse in the command
WE
I/O3: Sector Erase Timer
I/O2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
After writing a sector erase command sequence, the
system may read I/O3 to determine whether or not an
erase operation has begun. (The sector erase timer does
not apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also applies
after each additional sector erase command. When the
time-out is complete, I/O3 switches from "0" to "1." The
system may ignore I/O3 if the system can guarantee that
the time between additional sector erase commands will
always be less than 50µs. See also the "Sector Erase
Command Sequence" section. After the sector erase
command sequence is written, the system should read the
system may use either
or
to control the read
CE
OE
cycles.) But I/O2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. I/O6, by
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status
bits are required for sector and mode information. Refer to
Table 6 to compare outputs for I/O2 and I/O6.
Figure 5 shows the toggle bit algorithm in flowchart form,
and the section " I/O2: Toggle Bit II" explains the algorithm.
See also the " I/O6: Toggle Bit I" subsection. Refer to the
Toggle Bit Timings figure for the toggle bit timing diagram.
status on I/O7 (
Polling) or I/O6 (Toggle Bit 1) to
Data
ensure the device has accepted the command sequence,
(December, 2004, Version 1.3)
13
AMIC Technology, Corp.
A29001/A290011 Series
and then read I/O3. If I/O3 is "1", the internally controlled
erase cycle has begun; all further commands (other than
Erase Suspend) are ignored until the erase operation is
complete. If I/O3 is "0", the device will accept additional
sector erase commands. To ensure the command has
been accepted, the system software should check the
status of I/O3 prior to and following each subsequent
sector erase command. If I/O3 is high on the second status
check, the last command might not have been accepted.
Table 6 shows the outputs for I/O3.
START
Read I/O
7
-I/O
0
0
Read I/O
7
-I/O
(Note 1)
No
Toggle Bit
= Toggle ?
Yes
No
I/O5 = 1?
Yes
- I/O
Read I/O
7
0
(Notes 1,2)
Twice
No
Toggle Bit
= Toggle ?
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O
5
changes to "1". See text.
Figure 5. Toggle Bit Algorithm
(December, 2004, Version 1.3)
14
AMIC Technology, Corp.
A29001/A290011 Series
Table 6. Write Operation Status
Operation
I/O7
I/O6
I/O5
(Note 2)
0
I/O3
I/O2
(Note 1)
(Note 1)
No toggle
Standard
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
N/A
I/O7
0
Toggle
0
0
1
Toggle
Toggle
Erase
Reading within Erase
Suspended Sector
1
No toggle
N/A
Suspend
Mode
Reading within Non-Erase
Suspend Sector
Data
I/O7
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
Toggle
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
20ns
(December, 2004, Version 1.3)
15
AMIC Technology, Corp.
A29001/A290011 Series
DC Characteristics
TTL/NMOS Compatible
Parameter
Symbol
ILI
Parameter Description
Test Description
Min.
Typ.
Max.
Unit
Input Load Current
A9, Input Load Current
VIN = VSS to VCC. VCC = VCC Max
±1.0
µA
µA
ILIT
VCC = VCC Max,
100
&
OE RESET
A9,
&
=12.5V
OE RESET
ILO
Output Leakage Current
VOUT = VSS to VCC. VCC = VCC Max
±1.0
µA
ICC1
VCC Active Read Current
(Notes 1, 2)
20
30
30
mA
= VIL,
= VIL,
= VIH,
= VIH
CE
CE
CE
OE
ICC2
ICC3
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)
40
mA
mA
=VIH
OE
VCC Standby Current (Note 2)
0.4
1.0
= VCC ± 0.5V
RESET
VIL
VIH
VID
Input Low Level
-0.5
2.0
0.8
VCC+0.5
12.5
V
V
V
Input High Level
Voltage for Autoselect and
Temporary Unprotect Sector
Output Low Voltage
Output High Voltage
VCC = 5.25 V
10.5
VOL
VOH
IOL = 12mA, VCC = VCC Min
IOH = -2.5 mA, VCC = VCC Min
0.45
V
V
2.4
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
Min.
Typ.
Max.
Unit
ILI
Input Load Current
A9,
VIN = VSS to VCC, VCC = VCC Max
±1.0
µA
µA
ILIT
VCC = VCC Max,
Input Load Current
100
&
OE RESET
A9,
&
= 12.5V
OE RESET
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max
±1.0
µA
ICC1
VCC Active Read Current
(Notes 1,2)
20
30
1
30
mA
= VIL,
= VIH
CE
OE
ICC2
VCC Active Program/Erase Current
(Notes 2,3,4)
40
5
mA
= VIL,
= VIH
CE
OE
ICC3
VCC Standby Current (Notes 2, 5)
µA
=
= VCC ± 0.5 V
CE RESET
VIL
VIH
VID
Input Low Level
-0.5
0.7 x VCC
10.5
0.8
VCC+0.3
12.5
V
V
V
Input High Level
Voltage for Autoselect and
Temporary Sector Unprotect
Output Low Voltage
Output High Voltage
VCC = 5.25 V
VOL
VOH1
VOH2
IOL = 12.0 mA, VCC = VCC Min
IOH = -2.5 mA, VCC = VCC Min
IOH = -100 µA. VCC = VCC Min
0.45
V
V
V
0.85 x VCC
VCC-0.4
Notes for DC characteristics (both tables):
1. The ICC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with
2. Maximum ICC specifications are tested with VCC = VCC max.
at VIH.
OE
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Not 100% tested.
5. For CMOS mode only, ICC3 = 20µA max at extended temperatures (> +85°C).
6.
is not available on A290011.
RESET
(December, 2004, Version 1.3)
16
AMIC Technology, Corp.
A29001/A290011 Series
AC Characteristics
Read Only Operations
Parameter Symbols
Description
Test Setup
Speed
Unit
JEDEC
tAVAV
Std
tRC
-55
55
55
-70
70
70
-90
90
90
Read Cycle Time (Note 2)
Address to Output Delay
Min.
ns
ns
tAVQV
tACC
Max.
= VIL
= VIL
= VIL
CE
OE
tELQV
tGLQV
tCE
Chip Enable to Output Delay
Output Enable to Output Delay
Max.
Max.
Min.
Min.
55
30
0
70
30
0
90
35
0
ns
ns
ns
ns
tOE
tOEH
Output Enable Hold
Time (Note 2)
Read
Toggle and
10
10
10
Polling
Data
tEHQZ
tGHQZ
tAXQX
tDF
tDF
tOH
Chip Enable to Output High Z
Max.
Min.
18
18
0
20
20
0
20
20
0
ns
ns
ns
Output Enable to Output High Z
Output Hold Time from Addresses,
or
CE OE
, Whichever Occurs First
Notes:
1. Output driver disable time.
2. Not 100% tested.
Timing Waveforms for Read Only Operation (
=VIH on A29001)
RESET
t
RC
Addresses
Addresses Stable
t
ACC
CE
OE
t
DF
t
OE
t
OEH
WE
t
CE
t
OH
High-Z
High-Z
Output
Output Valid
0V
(December, 2004, Version 1.3)
17
AMIC Technology, Corp.
A29001/A290011 Series
Hardware Reset (
Parameter
)(N/A on A290011)
RESET
Description
Test Setup
Max
All Speed Options
Unit
µs
JEDEC
Std
tREADY
20
Pin Low (During Embedded
RESET
Algorithms) to Read or Write (See Note)
tREADY
Max
500
ns
Pin Low (Not During Embedded
RESET
Algorithms) to Read or Write (See Note)
tRP
tRH
Min
Min
500
50
ns
ns
Pulse Width
RESET
RESET
High Time Before Read (See Note)
Note: Not 100% tested.
Timings
RESET
CE, OE
t
RH
RESET
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
RESET
t
RP
Temporary Sector Unprotect (N/A on A290011)
Parameter
JEDEC Std
Description
All Speed Options
Unit
tVIDR
tRSP
VID Rise and Fall Time (See Note)
Min
Min
500
4
ns
µs
Setup Time for Temporary Sector
RESET
Unprotect
Note: Not 100% tested.
Temporary Sector Unprotect Timing Diagram
12V
0 or 5V
RESET
0 or 5V
t
VIDR
tVIDR
Program or Erase Command Sequence
CE
WE
t
RSP
(December, 2004, Version 1.3)
18
AMIC Technology, Corp.
A29001/A290011 Series
AC Characteristics
Erase and Program Operations
Parameter Symbols
Speed
Unit
Description
-55
-70
JEDEC
tAVAV
Std
tWC
tAS
-90
55
70
Write Cycle Time (Note 1)
Min.
Min.
Min.
Min.
Min.
Min.
90
ns
ns
ns
ns
ns
ns
tAVWL
tWLAX
tDVWH
tWHDX
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
0
40
25
45
tAH
45
45
30
0
tDS
tDH
tOES
Output Enable Setup Time
0
Read Recover Time Before Write
tGHWL
tGHWL
Min.
0
0
ns
(
high to
low)
WE
OE
tELWL
tWHEH
tWLWH
tCS
tCH
tWP
Min.
Min.
Min.
Min.
Max.
Typ.
ns
ns
Setup Time
Hold Time
CE
CE
0
30
35
Write Pulse Width
45
ns
20
50
7
ns
tWHWL
tWPH
Write Pulse Width High
µs
µs
sec
tWHWH1
tWHWH2
tWHWH1
tWHWH2
tVCS
Byte Programming Operation (Note 2)
Sector Erase Operation (Note 2)
VCC Set Up Time (Note 1)
Typ.
Min.
1
50
µs
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
(December, 2004, Version 1.3)
19
AMIC Technology, Corp.
A29001/A290011 Series
Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
t
WC
tAS
Addresses
CE
PA
PA
555h
PA
t
AH
t
CH
tGHWL
OE
t
WP
tWHWH1
WE
t
CS
t
WPH
t
DS
t
DH
Data
VCC
A0h
PD
DOUT
Status
tVCS
Note : PA = program addrss, PD = program data, Dout is the true data at the program address.
(December, 2004, Version 1.3)
20
AMIC Technology, Corp.
A29001/A290011 Series
Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
Read Status Data
t
AS
t
WC
SA
555h for chip erase
VA
Addresses
CE
2AAh
VA
t
AH
t
GHWL
tCH
OE
t
WP
WE
t
WPH
t
WHWH2
t
CS
t
DS
t
DH
In
Progress
Data
VCC
55h
30h
10h for chip erase
Complete
t
VCS
Note : SA = Sector Address. VA = Valid Address for reading status data.
(December, 2004, Version 1.3)
21
AMIC Technology, Corp.
A29001/A290011 Series
Timing Waveforms for
Polling (During Embedded Algorithms)
Data
tRC
Addresses
CE
VA
VA
VA
t
ACC
CE
t
t
CH
tOE
OE
t
DF
tOEH
WE
t
OH
High-Z
Valid Data
I/O7
Complement
Complement True
High-Z
I/O0
- I/O
6
Valid Data
Status Data
Status Data
True
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
(December, 2004, Version 1.3)
22
AMIC Technology, Corp.
A29001/A290011 Series
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
t
RC
Addresses
CE
VA
VA
VA
VA
t
ACC
CE
t
t
CH
tOE
OE
tDF
t
OEH
WE
t
OH
I/O6 , I/O2
Valid Status
(first read)
Valid Status
Valid Status
Valid Status
(second read)
(stop togging)
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
(December, 2004, Version 1.3)
23
AMIC Technology, Corp.
A29001/A290011 Series
Timing Waveforms for I/O2 vs. I/O6
Enter
Erase
Enter Erase
Suspend Program
Erase
Resume
Embedded
Suspend
Erasing
WE
Erase
Suspend
Program
Erase
Erase
Erase Suspend
Read
Erase Suspend
Read
Erase
Complete
I/O6
I/O2
I/O2
and I/O
6
toggle with OE and CE
Note : Both I/O
6
and I/O
2
toggle with OE or CE. See the text on I/O
6
and I/O
2
in the section "Write Operation Statue" for
more information.
AC Characteristics
Erase and Program Operations
Alternate Controlled Writes
CE
Parameter Symbols
JEDEC Std
Description
Speed
Unit
-55
-70
70
0
-90
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min.
Min.
Min.
Min.
Min.
Min.
Min.
55
90
ns
ns
ns
ns
ns
ns
ns
t
t
AVEL
ELAX
t
AS
AH
DS
DH
Address Setup Time
Address Hold Time
t
40
25
45
30
0
45
45
t
t
t
DVEH
EHDX
GHEL
t
t
Data Setup Time
Data Hold Time
t
GHEL
WS
WH
CP
CPH
Read Recover Time Before Write
0
t
WLEL
t
0
Setup Time
Hold Time
WE
WE
t
EHWH
t
Min.
0
ns
t
ELEH
EHEL
t
Write Pulse Width
Min.
Min.
Typ.
Typ.
30
20
35
20
7
45
20
ns
ns
t
t
Write Pulse Width High
t
t
WHWH1
WHWH2
t
t
WHWH1
WHWH2
Byte Programming Operation (Note 2)
Sector Erase Operation (Note 2)
µs
1
sec
Notes:
3. Not 100% tested.
4. See the "Erase and Programming Performance" section for more information.
(December, 2004, Version 1.3)
24
AMIC Technology, Corp.
A29001/A290011 Series
Timing Waveforms for Alternate
Controlled Write Operation
CE
PA for program
SA for sector erase
555 for chip erase
555 for program
2AA for erase
Data Polling
PA
Addresses
t
WC
tAS
t
AH
t
WH
WE
t
GHEL
OE
CE
t
WHWH1 or 2
t
CP
t
BUSY
t
CPH
t
WS
t
DS
t
DH
Data
DOUT
I/O7
t
RH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O
7
= Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Sector Erase Time
Typ. (Note 1)
Max. (Note 2)
Unit
sec
sec
µs
Comments
1
8
8
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
64
Byte Programming Time
Chip Programming Time (Note 3)
35
3.6
300
10.8
Excludes system-level
overhead (Note 5)
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 100,000 cycles. Additionally,
programming typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5V (4.75V for -55), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only
then does the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table
4 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
(December, 2004, Version 1.3)
25
AMIC Technology, Corp.
A29001/A290011 Series
Latch-up Characteristics
Description
Min.
Max.
Input Voltage with respect to VSS on all I/O pins
-1.0V
VCC+1.0V
+100 mA
VCC Current
-100 mA
Input voltage with respect to VSS on all pins except I/O pins
-1.0V
12.5V
(including A9,
and
)
RESET
OE
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.
N/A on A290011.
RESET
TSOP/sTSOP Pin Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
Typ.
Max.
Unit
CIN
COUT
CIN2
6
7.5
12
9
pF
pF
pF
VIN=0
VOUT=0
VIN=0
8.5
7.5
Output Capacitance
Control Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
PLCC and P-DIP Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ.
Max.
6
Unit
pF
CIN
COUT
CIN2
4
8
8
Input Capacitance
VIN=0
VOUT=0
VPP=0
12
pF
Output Capacitance
Control Pin Capacitance
12
pF
Notes:
3. Sampled, not 100% tested.
4. Test conditions TA = 25°C, f = 1.0MHz
Data Retention
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
20
125°C
(December, 2004, Version 1.3)
26
AMIC Technology, Corp.
A29001/A290011 Series
Test Conditions
Test Specifications
Test Condition
-55
All others
1 TTL gate
100
Unit
Output Load
Output Load Capacitance, CL(including jig capacitance)
Input Rise and Fall Times
30
5
pF
ns
V
20
Input Pulse Levels
0.0 - 3.0
1.5
0.45 - 2.4
0.8, 2.0
0.8, 2.0
Input timing measurement reference levels
Output timing measurement reference levels
V
1.5
V
Test Setup
5.0 V
2.7 KΩ
Device
Under
Test
Diodes = IN3064 or Equivalent
CL
6.2 KΩ
(December, 2004, Version 1.3)
27
AMIC Technology, Corp.
A29001/A290011 Series
Ordering Information
Top Boot Sector Flash
Active Read
Current
Typ. (mA)
Program/Erase
Current
Standby
Current
Typ. (µA)
Part No.
Access Time
Package
(ns)
Typ. (mA)
A29001T-55
32Pin DIP
32Pin Pb-Free DIP
32Pin DIP
A29001T-55F
A290011T-55
A290011T-55F
A29001TL-55
A29001TL-55F
A290011TL-55
A290011TL-55F
A29001TV-55
A29001TV-55F
A290011TV-55
A290011TV-55F
A29001TX-55
A29001TX-55F
A290011TX-55
A290011TX-55F
A29001T-70
32Pin Pb-Free DIP
32Pin PLCC
32Pin Pb-Free PLCC
32Pin PLCC
32Pin Pb-Free PLCC
32Pin TSOP
55
20
30
1
32Pin Pb-Free TSOP
32Pin TSOP
32Pin Pb-Free TSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
32Pin DIP
A29001T-70F
A290011T-70
A290011T-70F
A29001TL-70
A29001TL-70F
A290011TL-70
A290011TL-70F
A29001TV-70
A29001TV-70F
A290011TV-70
A290011TV-70F
A290011TV-70UF
A29001TX-70
A29001TX-70F
A290011TX-70
A290011TX-70F
A290011TX-70UF
32Pin Pb-Free DIP
32Pin DIP
32Pin Pb-Free DIP
32Pin PLCC
32Pin Pb-Free PLCC
32Pin PLCC
32Pin Pb-Free PLCC
32Pin TSOP
70
20
30
1
32Pin Pb-Free TSOP
32Pin TSOP
32Pin Pb-Free TSOP
32Pin Pb-Free TSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
32Pin Pb-Free sTSOP
(December, 2004, Version 1.3)
28
AMIC Technology, Corp.
A29001/A290011 Series
Ordering Information (continued)
Top Boot Sector Flash
Active Read
Current
Typ. (mA)
Program/Erase
Current
Standby
Current
Typ. (µA)
Part No.
Access Time
(ns)
Package
Typ. (mA)
A29001T-90
32Pin DIP
32Pin Pb-Free DIP
32Pin DIP
A29001T-90F
A290011T-90
A290011T-90F
A29001TL-90
A29001TL-90F
A290011TL-90
A290011TL-90F
A29001TV-90
A29001TV-90F
A290011TV-90
A290011TV-90F
A29001TX-90
A29001TX-90F
A290011TX-90
A290011TX-90F
32Pin Pb-Free DIP
32Pin PLCC
32Pin Pb-Free PLCC
32Pin PLCC
32Pin Pb-Free PLCC
32Pin TSOP
90
20
30
1
32Pin Pb-Free TSOP
32Pin TSOP
32Pin Pb-Free sSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
Note: -U is for industrial operating temperature range
(December, 2004, Version 1.3)
29
AMIC Technology, Corp.
A29001/A290011 Series
Ordering Information (continued)
Bottom Boot Sector Flash
Standby
Current
Typ. (µA)
Active Read
Current
Typ. (mA)
Program/Erase
Current Typ.
(mA)
Access Time
Part No.
(ns)
Package
A29001U-55
32Pin DIP
32Pin Pb-Free DIP
32Pin DIP
A29001U-55F
A290011U-55
A290011U-55F
A29001UL-55
A29001UL-55F
A290011UL-55
32Pin Pb-Free DIP
32Pin PLCC
32Pin Pb-Free PLCC
32Pin PLCC
A290011UL-55F
55
A29001UV-55
32Pin Pb-Free PLCC
32Pin TSOP
20
30
1
A29001UV-55F
A290011UV-55
A290011UV-55F
A29001UX-55
A29001UX-55F
A290011UX-55
A290011UX-55F
A29001U-70
32Pin Pb-Free TSOP
32Pin TSOP
32Pin Pb-Free TSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
32Pin DIP
A29001U-70F
A290011U-70
A290011U-70F
A29001UL-70
A29001UL-70F
A290011UL-70
A290011UL-70F
32Pin Pb-Free DIP
32Pin DIP
32Pin Pb-Free DIP
32Pin PLCC
32Pin Pb-Free PLCC
32Pin PLCC
32Pin Pb-Free PLCC
32Pin TSOP
A29001UV-70
70
A29001UV-70F
20
30
1
32Pin Pb-Free TSOP
32Pin TSOP
A290011UV-70
A290011UV-70F
A290011UV-70UF
A29001UX-70
32Pin Pb-Free TSOP
32Pin Pb-Free TSOP
32Pin sTSOP
A29001UX-70F
A290011UX-70
A290011UX-70F
A290011UX-70UF
32Pin Pb-Free sTSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
32Pin Pb-Free sTSOP
(December, 2004, Version 1.3)
30
AMIC Technology, Corp.
A29001/A290011 Series
Ordering Information (continued)
Bottom Boot Sector Flash
Active Read
Current
Typ. (mA)
Program/Erase
Current Typ.
(mA)
Part No.
Access Time
(ns)
Standby
Current
Typ. (µA)
Package
A29001U-90
32Pin DIP
32Pin Pb-Free DIP
32Pin DIP
A29001U-90F
A290011U-90
A290011U-90F
A29001UL-90
A29001UL-90F
A290011UL-90
A290011UL-90F
A29001UV-90
A29001UV-90F
A290011UV-90
A290011UV-90F
A29001UX-90
A29001UX-90F
A290011UX-90
A290011UX-90F
32Pin Pb-Free DIP
32Pin PLCC
32Pin Pb-Free PLCC
32Pin PLCC
32Pin Pb-Free PLCC
32Pin TSOP
90
20
30
1
32Pin Pb-Free TSOP
32Pin TSOP
32Pin Pb-Free TSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
32Pin sTSOP
32Pin Pb-Free sTSOP
Note: -U is for industrial operating temperature range
(December, 2004, Version 1.3)
31
AMIC Technology, Corp.
A29001/A290011 Series
Package Information
P-DIP 32L Outline Dimensions
unit: inches/mm
D
32
17
1
16
E
1
Base Plane
Seating Plane
B
E
A
θ
e
B
1
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
0.210
-
Min
Nom
Max
A
-
-
-
-
-
5.334
-
A1
A2
0.015
0.149
0.381
3.785
0.154
0.159
3.912
4.039
B
-
-
0.018
0.050
-
-
-
-
-
-
0.457
1.270
0.254
-
-
-
B1
C
D
-
0.010
1.650
1.645
1.655 41.783 41.91 42.037
0.547 13.64 13.767 13.894
E
E1
EA
e
0.537
0.590
0.630
-
0.542
0.600
0.650
0.100
0.130
-
0.610 14.986 15.240 15.494
0.670 16.002 16.510 17.018
-
-
2.540
3.302
-
-
L
0.120
0°
0.140
15°
3.048
0°
3.556
15°
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
(December, 2004, Version 1.3)
32
AMIC Technology, Corp.
A29001/A290011 Series
Package Information
PLCC 32L Outline Dimension
unit: inches/mm
HD
D
13
5
4
14
1
32
20
30
29
21
b
e
b
1
GE
y
θ
GD
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
0.134
-
Min
Nom
-
Max
A
A1
A2
b1
b
-
3.40
-
0.0185
0.105
0.026
0.016
0.008
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.075
-
-
0.47
2.67
0.66
0.41
0.20
13.89
11.35
1.12
12.45
9.91
14.86
12.32
1.91
-
-
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.510
0.410
0.590
0.490
0.090
-
0.115
0.032
0.021
0.014
0.553
0.453
0.056
0.530
0.430
0.595
0.495
0.095
0.003
10°
2.80
0.71
0.46
0.254
13.97
11.43
1.27
12.95
10.41
14.99
12.45
2.29
-
2.93
0.81
0.54
0.35
14.05
11.51
1.42
13.46
10.92
15.11
12.57
2.41
0.075
10°
C
D
E
e
GD
GE
HD
HE
L
y
θ
0°
-
0°
-
Notes:
1. Dimensions D and E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
(December, 2004, Version 1.3)
33
AMIC Technology, Corp.
A29001/A290011 Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
θ
L
L
E
H
D
Detail "A"
Detail "A"
y
S
b
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
Min
Nom
Max
A
A1
A2
b
-
0.047
0.006
0.041
0.011
0.008
0.728
0.319
-
-
1.20
0.15
1.05
0.27
0.20
18.50
8.10
0.002
0.037
0.007
0.004
0.720
-
-
0.039
0.009
-
0.05
0.95
0.18
0.11
18.30
-
-
1.00
0.22
-
c
D
E
0.724
0.315
0.020 BSC
0.787
0.020
0.032
-
18.40
8.00
0.50 BSC
20.00
0.50
0.80
-
e
HD
L
0.779
0.795
0.024
-
19.80
20.20
0.60
-
0.016
0.40
LE
S
-
-
-
-
0.020
0.003
5°
0.50
0.08
5°
y
-
-
-
-
-
-
θ
0°
0°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(December, 2004, Version 1.3)
34
AMIC Technology, Corp.
A29001/A290011 Series
Package Information
sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
θ
L
L
E
D
1
D
Detail "A"
Detail "A"
0.076MM
S
b
SEATING PLANE
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
Min
Nom
-
Max
-
A
A1
A2
b
0.049
-
1.25
-
-
-
0.002
0.037
0.007
0.05
0.95
0.17
0.039
0.008
0.041
0.009
1.00
1.05
0.23
0.158
8.10
0.20
c
0.0056 0.0059 0.0062 0.142
0.150
8.00
E
0.311
0.315
0.020 TYP
0.528
0.319
7.90
e
0.50 TYP
13.40
11.80
0.50
D
D1
L
0.520
0.461
0.012
0.535
0.469
0.028
13.20
11.70
0.30
13.60
11.90
0.70
0.465
0.020
LE
S
0.0275 0.0315 0.0355 0.700
0.0109 TYP
0.800
0.278 TYP
3°
0.900
θ
0°
3°
5°
0°
5°
Notes:
1. The maximum value of dimension D1 includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(December, 2004, Version 1.3)
35
AMIC Technology, Corp.
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