AM79D2251JC_技术文档

Intelligent Access™ Voice Solutions

Am79D2251

Dual Intelligent Subscriber Line Audio-Processing Circuit (ISLAC )

DISTINCTIVE CHARACTERISTICS

■ High performance digital signal processor

provides programmable control of all major

linecard functions

— Tone generation

— Metering generation at 12 kHz and 16 kHz

— Envelope shaping and level control

■ Selectable PCM/MPI or GCI digital interfaces

— 32 and 24 kb/s ADPCM to G726, as well as

A-law/µ-law and linear codec

— Supports most available master clock

— Transmit and receive gain

— Two-wire AC impedance

— Transhybrid balance

frequencies from 512 kHz to 8.196 MHz

■ 0 to 70°C commercial operation

— –40°C to 85°C extended temperature range

— Equalization

available

— DC loop feeding

■ +3.3 V DC operation

— Smooth or abrupt polarity reversal

— Loop supervision

■ Exceeds LSSGR and ITU requirements

■ Supports external ringing with on-chip ring-trip

— Off-hook debounce circuit

— Ground-key and ring-trip filters

— Ringing generation and control

— Adaptive hybrid balance

— Line and circuit testing

circuit

— Automatic or manual ring-trip modes

■ DTMF detection according to Q.24

■ 2100 Hz modem tone detection according to V.25

BLOCK DIAGRAM

7

A1

4

VCCA

LD1

ISLIC

VCCD

VREF

B1

DGND1

RC

AGND1

Networks

and

Protection

DGND2

AGND2

TSCA/G

A2

3

P1-P3

7

DRA/DD

ISLIC

LD2

DXA/DU

B2

Dual

ISLAC

RREF

DCLK/S0

PCLK/FS

Ring-Trip

Sense

Resistors

5

MCLK

RSHB

FS/DCL

CS/RST

DIO/S1

INT

BATH

RSLB

RSPB

BATL

BATP

Pub. # 22829 Rev: C Amendment: /0

Issue Date: December 1999

TABLE OF CONTENTS

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Distinctive Characteristics of The Intelligent Access™ Voice chipset . . . . . . . . . . . . . . . . . . . . . . 3

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Linecard Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Intelligent Access™ Voice Chipsets Environmental Ranges . . . . . . . . . . . . . . . . . . . . 14

Electrical Maximum Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Intelligent Access™ Voice Chipsets System Target Specifications . . . . . . . . . . . . . . . . . . . 15

DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Transmission and Signaling Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Transmit and Receive Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Gain Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Total Distortion Including Quantizing Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Discrimination against Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Spurious Out-of-Band Signals at the Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PCM Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PCM Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

GCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

GCI Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

44-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Revision A to Revision B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Revision B to Revision C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2

Am79D2251

The dual ISLAC device, in combination with an ISLIC™ device, implements a two channel

universal telephone line interface. This enables the design of a single, low cost, high performance,

fully software programmable line interface for multiple country applications worldwide. All AC, DC,

and signaling parameters are fully programmable via microprocessor or GCI interfaces. Additionally,

the dual ISLAC device has integrated self-test and line-test capabilities to resolve faults to the line

or line circuit. The integrated test capability is crucial for remote applications where dedicated test

hardware is not cost effective.

DISTINCTIVE CHARACTERISTICS OF THE INTELLIGENT ACCESS™ VOICE CHIPSET

■ Performs all battery feed, ringing, signaling,

■ Exceeds LSSGR and CCITT central office

hybrid and test (BORSCHT) functions

requirements

■ Two chip solution supports high density, multi-

■ Selectable PCM or GCI interface

channel architecture

— Supports most available master clock

■ Single hardware design meets multiple country

frequencies from 512 kHz to 8.192 MHz

requirements through software programming

of:

■ On-hook transmission

■ Power/service denial mode

— Ringing waveform and frequency

— DC loop-feed characteristics and current-limit

— Loop-supervision detection thresholds

— Off-hook debounce circuit

— Ground-key and ring-trip filters

— Off-hook detect de-bounce interval

— Two-wire AC impedance

■ Line-feed characteristics independentof battery

voltage

■ Only 5 V, 3.3 V and battery supplies needed

■ Low idle-power per line

■ Linear power-feed with intelligent power-

management feature

■ Compatible with inexpensive protection

networks; Accommodates low-tolerance fuse

resistors while maintaining longitudinal balance

— Transhybrid balance

— Transmit and receive gains

— Equalization

■ Monitors two-wire interface voltages and

currents for subscriber line diagnostics

— Digital I/O pins

■ Built-in voice-path test modes

— A-law/µ-law and linear selection

■ Power-cross, fault, and foreign voltage

■ Supports internal and external battery-backed

detection

ringing

■ Integrated line-test features

— Leakage

— Self-contained ringing generation and control

— Supports external ringing generator and ring

relay

— Line and ringer capacitance

— Loop resistance

— Ring relay operation synchronized to zero

crossings of ringing voltage and current

■ Integrated self-test features

— Echo gain, distortion, and noise

■ 0 to 70°C commercial operation

— Integrated ring-trip filter and software enabled

manual or automatic ring-trip mode

■ Supports metering generation with envelope

— –40°C to 85°C extended temperature range

shaping

available

■ Smooth or abrupt polarity reversal

■ Adaptive transhybrid balance

— Continuous or adapt and freeze

■ Small physical size

■ Up to three relay drivers per ISLIC™ device

— Configurable as test load switches

■ Supports both loop-start and ground-start

signaling

Am79D2251

3

Figure 1. Dual ISLAC Block Diagram

IREF

VREF

MCLK

VHL1

VLB1

Clock and

Reference

Circuits

FS/DCL

VOUT1

PCLK/FS

VINI1

VSAB1

VIMT1

VILG1

XSB1

Ch 1

Converter

Block

PCM

and

GCI

Interface

and

DXA/DU

DRA/DD

TSCA/G

Time Slot

Assigner

VHL2

VLB2

DCLK/S0

DIO/S1

GCI Control

Logic and

Microprocessor

Interface

VOUT2

VINI2

Digital

Signal

Processor

CS/RST

Ch 2

Converter

Block

INT

VSAB2

VIMT2

VILG2

XSB2

LD1

LD2

P1

ISLIC

Control

Logic

P2

P3

XSC

SHB

Common

External

Sense

SLB

SPB

Inputs

4

Am79D2251

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The ordering

number (valid combination) is formed by a combination of the elements below. Two ISLIC devices

need to be used with this part.

Am79D2251

C

J

TEMPERATURE RANGE

C= Commercial (0°C to +70°C)

PACKAGE TYPE

J = 44-pin plastic leaded chip carrier (PL044)

V = 44-pin thin plastic quad flat pack (PQT044)

DEVICE NAME/DESCRIPTION

Am79D2251

Advanced Dual Intelligent Subscriber Line Audio-

Processing Circuit

Valid Combinations

Valid combinations list configurations planned to

be supported in volume for this device. Consult

the local AMD sales office to confirm availability

of specific valid combinations, and to check on

newly released valid combinations.

Valid Combinations

Am79D2251

JC

VC

Am79D2251

5

CONNECTION DIAGRAMS

Figure 2. 44-Pin PLCC Connection Diagram

6

5

4

3

2

1

44 43 42 41 40

39

38

37

36

AGND2

VILG1

VSAB1

VCCA1

VHL1

7

AGND1

VILG2

8

9

VSAB2

10

11

12

VCCA2

VHL2

VIN2

35

Dual ISLAC

44-Pin PLCC

34

33

32

VIN1

13

14

15

16

17

VOUT1

DGND2

VOUT2

SPB

DGND1

LD2

31

30

29

LD1

CS/RST

DCLK/S0

P3

18 19 20 21 22 23 24 25 26 27 28

Figure 3. 44-Pin TQFP Connection Diagram

44

43

42 41 40 39 38 37 36 35 34

33

32

31

1

AGND2

AGND1

2

3

VILG1

VILG2

VSAB1

VSAB2

4

30

VCCA2

VCCA1

5

29

28

27

26

25

VHL2

VIN2

VHL1

VIN1

Dual ISLAC

44-Pin TQFP

6

7

VOUT2

VOUT1

DGND2

LD1

8

SPB

9

DGND1

10

11

LD2

P3

24

23

CS/RST

DCLK/S0

12 13

14

15 16 17 18 19

20

21 22

6

Am79D2251

PIN DESCRIPTIONS

Pin Name

I/O

Description

AGND1,

AGND2

Analog Ground

Analog circuitry ground returns

O

DCLK/S0

Data Clock/GCI

Address Strap 0

Provides data control for MPIinterface control. For GCI operation, this pin is device address

bit 0. 5 V tolerant.

I

DGND1–

Digital Ground

Digital ground returns

DGND2

DIO/S1

Data I/O/GCI Address

Strap 1

For PCM backplane operation, control data is serially written into and read out of the ISLAC

device via the DIO pin with the MSB first. The data clock (DCLK) determines the data rate.

DIO is high impedance except when data is being transmitted from the ISLAC device under

control of CS/RST. For GCI operation, this pin is device address bit 1. 5 V tolerant.

I/O

I

DRA/DD

RX Path A Backplane

Data/ GCI data

Downstream, Receive

Path B backplane data

For the PCM highway, the receive PCM data is input serially through the DRA ports. The

data input is received every 125 µs and is shifted in, MSB first, in 8-bit PCM or 16-bit linear

bursts at the PCLK rate. The receive port can receive information for direct control of the

ISLIC device. This mode is selected in Device Configuration Register 2 (RTSEN = 1,

RTSMD = 1). When selected, this data is received in an independently programmable

timeslot from the PCM data. For the GCI mode, downstream receive and control data is

accepted on this pin. 5 V tolerant.

DXA/DU

FS/DCL

INT/S2

TX Path A Backplane

Data/GCI Data

Upstream, TX Path B

Backplane Data

For the PCM highway, the transmit PCM data is transmitted serially through the DXA port.

The transmission data output is available every 125 µs and is shifted out, MSB first, in 8-bit

PCM or 16-bit linear bursts at the PCLK rate. DXA is high impedance between bursts and

while the device is in the inactive mode. Can also select a mode (RTSEN = 1, RTSMD = 1

or 0 in Device Configuration Register 2) that transmits the Signaling Register MSB contents

first, in an independently programmable timeslotfrom the PCM data. This data is transmitted

in all modes except disconnect. For the GCI mode, upstream transmit and signaling data is

transferred on this pin. 5 V tolerant.

O

Frame sync/GCI

Downstream Clock

For PCM operation, pin is Frame Sync. PCM operation is selected by the presence of an

8 kHz Frame Sync signal on this pin in conjunction with the PCLK on the PCLK/FS pin

(see below). This 8 kHz pulse identifies the beginning of a frame. The ISLAC device

references individual timeslots with respect to this input, which must be synchronized to

PCLK. GCI operation is selected by the presence of the downstream clock DCL, on this

pin in conjunction with the presence of a FS on the PCLK/FS pin. In GCI mode, the rate

at which data is shifted into or out of the PCM ports is a derivative of this DCL clock as

selected in Device Configuration Register 1. 5 V tolerant.

I

Interrupt/GCI Address

Strap 2

For PCM operation, when a subscriber line requires service, this pin goes to a logic 0 to

interrupt a higher level processor. Several registers work together to control operation of

the interrupt: Signaling and Global Interrupt Registers with their associated Mask

Registers, and the Interrupt Register. See the description at configuration register 6 (Mask)

for operation. Logic drive is selectable between open drain and TTL-compatible outputs.

The S2 function is only available on the dual ISLAC device. For GCI operation, it is the

device address bit 2.

O

IREF

Current Reference

Register Load

External resistor (RREF) connected between this pin and analog ground generates an

accurate, on-chip reference current for the A/D's and D/A's on the ISLAC chip.

I

LD1–LD2

The LD pins output 3-level voltages. When LDn is a logic 0, the destination of the code on

P1–P3 is the relay control latches in the ISLIC control register. When LDn is a logic 1, the

destination of P1–P3 is the mode control latches. LDn is driven to VREF when the contents

of the ISLIC control register must not change.

O

MCLK

Master Clock

For PCM backplane operation, a DSP master clock connects here. A signal is required

only for PCM backplane operation when PCLK is not used as the master clock. MCLK can

bea widevarietyoffrequencies. Upon initializationtheMCLK inputisdisabled, andrelevant

circuitry is driven by a connection to PCLK. The MCLK connection may be re-established

under user control. 5 V tolerant.

I

PCLK/FS

PCM Clock/Frame

Sync

For PCM operation, this is PCM Clock. PCM operation is selected by the presence of a

PCLK signal on this pin in conjunction with the FS on the FS/DCL pin (see below). For

PCM backplane operation, connect a data clock, which determines the rate at which PCM

data is serially shifted into or out of the PCM ports. PCLK can be any multiple of the FS

frequency. The minimum clock frequency for linear/ companded data plus signaling data

is 256 kHz. For GCI operation, this pin is Frame Sync. The FS signal is an 8 kHz pulse

that identifies the beginning of a frame. The ISLAC device references individual timeslots

with respect to this input, which must be synchronized to DCL. 5 V tolerant.

P1–P3

ISLIC Control

Control the operating modes of the two ISLIC devices connected to the dual ISLAC device.

O

Am79D2251

7

Pin Name

I/O

Description

CS/RST

Chip Select/Reset

For PCM backplane operation, a logic low on this pin for 15 or more DCLK cycles resets

the sequential logic in the ISLAC device into a known mode. A logic low placed on this pin

for less than 15 DCLK cycles is a chip select and enables serial data transmission into or

out of the DIO port. For GCI operation, a logic low on this pin—for 1 ms or longer—resets

the sequential logic into a known mode. See Table 2-4 in the Technical Reference for

details. 5 V tolerant.

I

SHB, SLB,

SPB

Battery Sense

Resistors that sense the high, low and positive battery voltages connect here. If only one

negative battery is used, connect both resistors at the supply. If the positive battery is not

used, leave the pin unconnected. These pins are current inputs whose voltage is held at

VREF.

I

TimeslotControlA/GCI

Mode, Time Slot

Control B

For PCM backplane operation, TSCA is active low when PCM data is output on the DXA

pin. The outputs are open-drain and are normally inactive (high impedance). Pull-up loads

should be connected to VCCD. When GCI mode is selected, one of two GCI modes may

be selected by connecting TSCA/G to DGND or VCCD.

TSCA/G,

O

(PCM)

I

(GCI)

VSAB1–

VSAB2

Loop voltage sense

Power Supply

Connect to the VSAB pins of two ISLIC devices.

+3.3 VDC supplies to the analog sections in each of the two channels.

+3.3 VDC supply to all digital sections.

I

VCCA1–

VCCA2

VCCD

VREF

Power Supply

Analog Reference

This pin provides a 1.4 V, single-ended reference to the two ISLIC devices to which the

ISLAC device is connected.

O

I

VHL1–

VHL2

High Level D/A

TX Analog

High-level loop control voltages on these pins are used to control DC-feed, internal ringing,

metering and polarity reversal for each ISLIC device.

VIN1–

VIN2

Analog transmit signals (VTX) from each ISLIC device connect to these pins. The ISLAC

device converts these signals to digital words and processes them. After processing, they

are multiplexed into serial time slots and sent out of the DXA/DU pin.

VLB1–

VLB2

Longitudinal

Reference

Normally connected to VCCA internally. They supply longitudinal reference voltages to the

ISLIC devices during certain test procedures. These outputs are connected internally to

VCCA during ISLIC Active, Standby, Ringing, and Disconnect modes. During test modes,

it can be connected to the receive D/A.

O

I

VIMT1–

VIMT2,

VILG1–

VILG2

Sense

The IMT and ILG pins of two ISLIC devices connect to the VIMT1–VIMT4 and VILG1–

VILG4 pins of the ISLAC chip. These pins are voltage inputs referenced to VREF. They

require external resistors connected between each pin and VREF to convert IMTn and

ILGn into voltages.

VOUT1–

VOUT2

RX Analog

The ISLAC device extracts and processes voice data from time slots on DRA/DD serial

data port. After processing, the ISLAC device converts the voice data to analog signals

that are sent out of these pins to each respective ISLIC device.

O

I

XSB1–

XSB2

External Sense

External resistors connect here that sense an external voltage. In a linecard with external

ringing, they are used to sense the voltage at the line side of the ring-feed resistor. These

pins are currentinputs whose voltage is held atVREF. An internal resistor convertscurrents

flowing in these pins into voltages to be sampled by the A/D.

XSC

Common External

Sense

An external resistor connects here that senses a common reference for external voltages

sensed by resistors connected to XSB1–XSB4. This pin is a current input whose voltage

is held at VREF. An internal resistor converts current flowing in this pin into a voltage to

be sampled by the A/D. This pin is intended for sensing external ringer supply voltages.

However, it can also be used to sense other test points when internal ringing is used.

I

8

Am79D2251

GENERAL DESCRIPTION

The Intelligent Access voice chipsets integrate all functions of the subscriber line for two subscriber

lines. One or more of two chip types are used to implement the linecard; an ISLIC device and a dual

ISLAC device. These provide the following basic functions:

1. The ISLIC device: A high voltage, bipolar IC that drives the subscriber line, maintains

longitudinal balance and senses line conditions.

2. The dual ISLAC device: A low voltage CMOS IC that provides conversion and DSP functions

for 2 channels.

Completeschematicsoflinecardsusing theIntelligentAccessvoicechipsetsforinternalandexternal

ringing are shown in Figure 4 and Figure 5.

The ISLIC device uses reliable, bipolar technology to provide the power necessary to drive a wide

variety of subscriber lines. It can be programmed by the ISLAC device to operate in eight different

modes that control power consumption and signaling modes. This enables it to have full control over

the subscriber loop. The ISLIC device is customized to be used exclusively with the ISLAC device

as part of a multiple-line chipset. The ISLIC device requires only +5 V power and the battery supplies

for its operation.

The ISLIC device implements a linear loop-current feeding method with the enhancement of

intelligent thermal management in a controlled manner. This limits the amount of power dissipated

on the ISLIC chip by dissipating excess power in external resistors.

Each ISLAC device contains high-performance codec circuits that provide A/D and D/A conversion

for voice (codec), DC-feed and supervision signals for two subscriber channels. The ISLAC device

contains a DSP core that handles signaling, DC-feed, supervision and line diagnostics for both

channels.

The DSP core selectively interfaces with three types of backplanes:

■ Standard PCM/MPI

■ Standard GCI

■ Modified GCI with a single analog line per GCI channel

The Intelligent Access voice chipset provides a complete software configurable solution to the

BORSCHT functions as well as complete programmable control over subscriber line DC-feed

characteristics, such as current limit and feed resistance. In addition, these chipsets provide system

level solutions for the loop supervisory functions and metering. In total, they provide a programmable

solution that can satisfy worldwide linecard requirements by software configuration.

Software programmed filter coefficients, DC-feed data and supervision data are easily calculated

with the WinSLAC software. This PC software is provided free of charge. It allows the designer to

enter a description of system requirements. WinSLAC then computes the necessary coefficients

and plots the predicted system results.

The ISLIC interface unit inside the ISLAC device processes information regarding the line voltages,

loop currents and battery voltage levels. These inputs allow the ISLAC device to place several key

ISLIC performance parameters under software control.

Am79D2251

9

The main functions that can be observed and/or controlled through the ISLAC backplane interface are:

■ DC-feed characteristics

■ Ground-key detection

■ Off-hook detection

■ DTMF detection

■ Modem tone (2100 Hz) detection

■ Metering signal

■ Longitudinal operating point

■ Subscriber line voltage and currents

■ Ring-trip detection

■ Abrupt and smooth battery reversal

■ Subscriber line matching

■ Ringing generation

■ Sophisticated line and circuit tests

To accomplish these functions, the ISLIC device collects the following information and feeds it, in

analog form, to the ISLAC device:

■ The metallic (IMT) and longitudinal (ILG) loop currents

■ The AC (VTX) and DC (VSAB) loop voltage

The outputs supplied by the ISLAC device to the ISLIC device are then:

■ A voltage (VHLi) that provides control for the following high-level ISLIC device outputs:

—DC loop current

—Internal ringing signal

—12 or 16 kHz metering signal

■ A low-level voltage proportional to the voice signal (VOUTi)

■ A voltage that controls longitudinal offset for test purposes (VLBi)

The ISLAC device performs the codec and filter functions associated with the four-wire section of

the subscriber line circuitry in a digital switch. These functions involve converting an analog voice

signal into digital PCM samples and converting digital PCM samples back into an analog signal.

During conversion, digital filters are used to band-limit the voice signals.

The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing

function, permit adjustment of the two-wire termination impedance and provide frequency

attenuation adjustment (equalization) of the receive and transmit paths. Adaptive transhybrid

balancing is also included. All programmable digital filter coefficients can be calculated using

WinSLAC software. The PCM codes can be either 16-bit linear two’s-complement or 8-bit

companded A-law or µ-law, with the further option of 32 or 24 kb/s ADPCM compression.

Besides the codec functions, the Intelligent Access voice chipset provides all the sensing, feedback,

andclockingnecessarytocompletelycontrolISLICdevicefunctionswithprogrammableparameters.

System-level parameters under programmable control include active loop current limits, feed

resistance, and feed mode voltages.

The ISLAC device supplies complete mode control to the ISLIC device using the control bus (P1-P3)

and tri-level load signal (LDi).

The Intelligent Access voice chipset provides extensive loop supervision capability including off-hook,

DTMF, ring-trip and ground-key detection. Detection thresholds for these functions are programmable.

A programmable debounce timer is available that eliminates false detection due to contact bounce.

For subscriber line diagnostics, AC and DC line conditions can be monitored using built in test tools.

Measured parameters can be compared to programmed threshold levels to set a pass/fail bit. The

user can choose to send the actual PCM measurement data directly to a higher level processor by

way of the voice channel. Both longitudinal and metallic resistance and capacitance can be

measured, which allows leakage resistance, line capacitance, and telephones to be identified.

10

Am79D2251

Figure 4. Internal Ringing Linecard Schematic

+5 V

3.3 V

VCC

CREF

RSAi

RRXi

RHLai

CHLbi

SA

VOUTi

VHLi

RSN

DGND

RFAi

A

RHLbi

AD

RHLci

RTi

RHLdi

CHLdi

AGND

VCCA

U3

RTESTMi

D1

VREF

CADi

CHPi

VCC

+3.3VDC

VSAB

VTX

VSABi VCCD

HPA

HPB

BD

CS

U4

BATH

DT1i

VINi

D2

CSSi

RFBi

B

VLB

IMT

VLBi

RSBi

VIMTi

SB

CBDi

TMS

RMTi

U1

Am79R241

U2

ISLAC

VREF

RMGPi

DT2i^***

VILGi

ILG

BACK

TMP

TMN

PLANE

RLGi

VREF

RMGLi

DHi

DLi

VREF

BATH

BATL

VBH

VBL

LD

LDi

P1

SPB

GND

CBATHi

CBATLi

P1

P2

P3

SLB

SHB

BATL

BATH

RSLB

RSHB

P2

P3

RSVD

RYE

IREF

R2

R3

RREF

RTESTLi

R1

* CSS required for > 2.2 Vrms metering

** Connections shown for one channel

*** DT2i diode is optional - should be

BGND

RSVD

connected if there is a chance that this chip

may be replaced by Am79R251.

Am79D2251

11

Figure 5. External Ringing Linecard Schematic

+5 V

3.3 V

VCC

CREF

RSAi

RFAi

RRXi

SA

RSN

VOUTi

VHLi

DGND

AGND

RHLai

A

1

8

CHLbi

RHLbi

AD

KRi(A)

CADi

RHLci

RHLdi

CHLdi

VREF

RTi

6

7

RTESTMi

U5

VCCA

VCCD

VCC

+3.3 VDC

VSAB

VTX

VSABi

VINi

2

CHPi

HPA

HPB

BD

DT1i

BATH

CS

CSSi

VLB

IMT

VLBi

RFBi

CBDi

B

4

5

VIMTi

RSBi

KRi (B)

RMTi

SB

TMS

U1

Am79231

VREF

VILGi

ILG

U2

ISLAC

RMGPi

DT2i^***

RLGi

BACK

PLANE

TMP

TMN

VREF

RMGLi

DHi

DLi

LD

GND

P1

LDi

P1

BATH

VBH

VBL

BATL

P2

P3

P2

P3

SPB

SLB

CBATHi

CBATLi

BATL

BATH

RSLB

RSHB

RSVD2

RYE

SHB

IREF

R2H

R3H

RREF

RTESTLi

R1

RGFDLi

KRi

+5 V

BGND

RSVD

XSBi

XSC

* CSS required for > 2.2 Vrms metering

** Connections shown for one channel

*** DT2i is optional - Should be put if there is a chance that

this chip may be replaced by Am79R251.

Ring Bus

RSRBi

RSRC

12

Am79D2251

LINECARD PARTS LIST

The following list defines the parts and part values required to meet target specification limits for

channel i of the linecard (i = 1, 2)

Item

Type

Value

Tol.

Rating

Comments

U1

Am79R241

Am79X22xx

P1001SC

ISLIC device

U2

ISLAC device

U3, U4

U5

100 V

80 V

TECCOR Battrax protector

TISP61089

Transient Voltage Suppresser, Power

Innovations

D1, D2

Diode

1 A

100 V

DHi, DLi, DT1i, DT2i⁴

RFAi, RFBi

RSAi, RSBi

RTi

100 mA

50 ns

Resistor

Capacitor

Resistor

Capacitor

50 Ω

200 kΩ

80.6 kΩ

100 kΩ

69.8 kΩ

1 kΩ

2%

2 W

1/4 W

1/8 W

1 W

Fusible PTC protection resistors

Sense resistors

1%

RRXi

1%

RREF

1%

Current reference

RMGLi, RMGPi

RSHB, RSLB

RHLai

5%

Thermal management resistors

750 kΩ

40.2 kΩ

4.32 kΩ

2.87 kΩ

3.3 nF

0.82 µF

3.01 kΩ

6.04 kΩ

2 kΩ

1%

1/8 W

1/10 W

10 V

1%

RHLbi

1%

RHLci

1%

RHLdi

1%

CHLbi

10 %

1%

Not Polarized

Ceramic

CHLdi

10 V

RMTi

1/8 W

1 W

RLGi

1%

RTESTMi

RTESTLi

1%

Metallic test

2 kΩ

1%

1 W

Longitudinal test

CADi, CBDi ¹

CBATHi, CBATLi

CHPi

22 nF

10%

100 V

Ceramic, not voltage sensitive

Capacitor

100 nF

22 nF

20%

100 V

Ceramic

CSi¹

100 nF

Protector speed up capacitor

CSSi³

Capacitor

56 pF

5%

100 V

Ceramic

Components for External Ringing

RGFDi

Resistor

510 Ω

2%

2 W

1.2 W typ

RSRBi, RSRc

750 kΩ

1/4 W

Matched to within 0.2% for initial tolerance

and 0 to 70° C ambient temperature range.²

17 mW typ

KRi

Relay

5 V Coil

DPDT

Notes:

1. Value can be adjusted to suit application.

2. Can be looser for relaxed ring-trip requirements. 1% match (each resistor ±1%) gives 1.275 mA uncertainty in ringing current

sensing.

3. Required for metering > 2.5 Vrms, otherwise may be omitted.

4. DT2i is optional - Should be put if there is a chance that this chip may be replaced by Am79R251.

Am79D2251

13

ELECTRICAL CHARACTERISTICS

Power Dissipation

Description

Test Conditions

One channel activated

All channels active

All channels inactive

Min

Typ

TBD

Max

TBD

Unit

Dual ISLAC Power

Dissipation

mW

Absolute Maximum Ratings

Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device

failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings

for extended periods can affect device reliability.

Storage Temperature

–60°C ≤ T_A≤ +125°C

–40°C ≤ T_A≤ +85°C

Ambient Temperature, under Bias

Ambient relative humidity (non condensing)

5 to 100%

V

_CCAwith respect to DGND

_CCDwith respect to DGND

–0.4 V to + 3.47 V

V

–0.4 V to + 3.47 V

V_INwith respect to DGND

5 V tolerant pins

–0.4 V to VCCA + 0.4 V

–0.4 to Vcc + 2.25 or 5.25 V,

whichever is less

AGND

DGND ±0.4 V

±100 mA

Latch up immunity (any pin)

Any other pin with respect to DGND

–0.4 V to V_CC

Operating Ranges

Operating ranges define those limits over which the functionality of the device is guaranteed by 100

percent production testing. Specifications outside of the 0 to 70°C range (–40 to 85°C) are

guaranteed through characterization and sample-lot testing production devices at the temperature

extremes.

Intelligent Access™ Voice Chipsets Environmental Ranges

Ambient Temperature

Ambient Relative Humidity

Electrical Maximum Ranges

–40 to +85°C Commercial

15 to 85%

Analog Supply V_CCA

Digital Supply V_CCD

+3.3 V ± 5%

DGND

AGND

0 V

DGND ±50 mV

14

Am79D2251

PERFORMANCE SPECIFICATIONS

The performance targets defined in this section are for the entire linecard comprised of both chips

in the Intelligent Access voice chipsets unless otherwise noted. Specifications for the individual chips

in the set will be published separately (see note 1). T_A= 0 to 70°C unless otherwise noted.

Intelligent Access™ Voice Chipsets System Target Specifications

Item

Condition

Min

Typ

Max

Unit

Note

Peak Ringing Voltage

Active Ringing mode,

RLOAD = 1500 Ω,

VBH = 80 V

70

V

Output Impedance during

internal ringing

Active Ringing mode, Dual

ISLAC generating internal

ringing

200

2

Ω

Sinusoidal Ringing THD

Active Ringing mode,

RLOAD = 1500 Ω,

VBH = 80 V, ISLAC

generating internal

sinusoidal ringing

%

PSRR (VBH, VBL)

Loop open, in anti-sat

f = 50 Hz

2

dB

1, 2

f = 200 to 3400 Hz

12

Notes:

1. Not tested or partially-tested in production.

2. These numbers are only valid when an ISLIC device operates with an ISLAC device, because the ISLAC

generates the anti-sat feed characteristic. When the Intelligent Access voice chipsets operate in the normal

feed region, the performance is controlled by the ISLIC device. See appropriate ISLIC data sheet for

specific PSRR.

Am79D2251

15

DC Specifications

No.

Item

Condition

Min

Typ

Max

Unit Note

1

Input Low Voltage,

All other digital inputs

–0.05

–0.50

1.36 V

0.80 V

V

2

4

Input High Voltage,

All other digital inputs

2.36

2.0

Vcc+0.4

5.25

Input Leakage Current

All digital inputs except MCLK

MCLK

–10

+10

µA

–120

+180

0.3

5

6

Input hysteresis (PCLK/FS, FS/DCL,

MCLK, DIO, DRA)

0.15

0.225

V

2

Ternary output voltages, LD1–2

High voltage

Low voltage

Iout = ±200 µA

Iout = 2 mA

Mid level

VCC–0.45

—

0.4

+10

V

µA

Output current

–10

7

8

9

Output Low Voltage (DXA/DU, DIO,

INT, TSCA)

Iol = 2 mA

0.4

Output Low Voltage

(INT, TSCA)

Iol = 10 mA

Ioh = 400 µA

1.0

V

Output High Voltage (All digital

outputs except INT in open drain

mode and TSCA)

VCC–0.4

10

Input Leakage Current (VIN1–2,

VSAB1–2, VILG1–2, VIMT1–2)

TBD

µA

11

12

Input Leakage Current ( VSAB1–2)

Input voltage (VIN1–2)

µ-law

3.205 dBm0

A-law

3.14 dBm0 to insertion

loss in ADC

VREF

–1.02

VREF

+1.02

V

13

Input Voltage (VSAB 1–2 or VIMT1–2

or VILG1–2)

|Vov–VREF| where Vov is

input overload voltage

0.99

1.02

1.05

14

15

16

Offset voltage allowed on VIN1–2

VHL output offset voltage

VOUT1–2 offset Voltage

–50

+50

mV

9

DISN off

DISN on

–40

–80

+40

+80

17

18

19

20

21

22

23

Output voltage, VREF

Load current = 0 to 10 mA

Source or Sink

1.4

V

Capacitance load on VREF or

VOUT1–2

200

+1

pF

2

Output drive current, VOUT1–2 or

VLB1–2

Source or Sink

–1

mA

Output leakage current

VOUT1–2 or VLB1–2

TBD

1.02

Maximum output voltage on VOUT

|VOUT–VREF| with peak

digital input

0.99

1.05

9

V

VLB1–2 operating voltage

Source current < 250 µA

or sink current < 25 µA.

VREF

–1.02

VREF

+1.02

Maximum output voltage on VHL

(KRFB)

|VHL–VREF| with peak

digital input

0.97

1.00

1.03

24

25

26

Gain from VSAB to VHL

VFD = 1

VFD = 0

4.9

–0.0255

–5

5

5.1

–0.0245

+5

V/V

%

–0.025

% error of VLB voltage (For VLB

equation, see Am79R2xx/

Am79D2251 Technical Reference)

27

Capacitance load on VLB1–2

120

pF

5

16

Am79D2251

No.

Item

Condition

Min

Typ

Max

Unit Note

28

Capacitance load on XSB1–2, XSC

400

pF

5

Transmission and Signaling Specifications

Table 1. 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR

Signal at Digital Interface

A-law digital mW or equivalent (0 dBm0)

µ-law digital mW or equivalent (0 dBm0)

±5,800 peak linear coded sine wave

Transmit

0.5026

0.4987

0.5026

Receive

0.5026

0.4987

0.5025

Unit

Vrms

No.

Item

Insertion Loss

Condition

Min

Typ

Max

Unit

Note

1

Input: 1014Hz, –10dBm0

RG = AR = AX = GR = GX = 0 dB,

AISN, R, X, B and Z filters disabled

A-D

D-A

A-D + D-A

–0.25

–0.15

–0.1

0

+0.25

+0.015

+0.1

6

Temperature = 70°C

Variation over temperature

dB

2

3

Level set error (Error between

setting and actual value)

A-D AX + GX

D-A AR + GR

–0.1

0.1

DR to DX gain in full digital

loopback mode

DR Input: 1014 Hz, –10 dBm0

RG=AR=AX=GR=GX=0 dB,

DISN, R, X, BandZ filters disabled

–0.3

+0.3

4

Idle Channel Noise,

Off-hook and On-hook

Psophometric Weighted (A-law) AX = 0dB

AR = 0dB

dBm0p

11

A-D (PCM output)

D-A (V^OUT)

–69

–78

5

Idle Channel Noise,

C Message weighted (µ-law)

Off-hook and On-hook

AX = 0dB

AR = 0dB

A-D (PCM output)

D-A (V^OUT)

dBrnC0

Bits

+19

+12

+7

6

7

8

9

Coder Offset decision value, Xn A-D, Input signal = 0V

–7

5

GX step size

GR step size

0.1

0 ≤ GX < 12 dB

–12 ≤ GR ≤ 0 dB

PSRR (VCC)

Input: 4.8 to 7.8 kHz, 200 mV p-p

dB

Image frequency

Measure 8000 Hz-Input frequency

A-D

D-A

37

10

11

DISN gain accuracy

Gdisn = ±0.9375 Vin = 0 dBm0

Gdisn = –0.9375 to 0.9375

–0.25

+0.25

525

dB

2

End-to-end group delay

1014 Hz; –10 dBmO

B = Z = 0; X = R = 1

µS

13,

12,

5

12

Crosstalk

same channel

TX to RX

RX to TX

0 dBm0

300 Hz to 3400 Hz

–75

dBm0

Am79D2251

17

No.

Item

Condition

Min

Typ

Max

Unit

Note

13

Crosstalk between channels

TX or RX to TX

0 dBm0

1014 Hz

–76

–78

dBm0

TX or RX to RX

Notes:

1.

These tests are performed with the following load impedances:

Frequency < 12 kHz – Longitudinal impedance = 500 Ω; metallic impedance = 300 Ω

Frequency > 12 kHz – Longitudinal impedance = 90 Ω; metallic impedance = 135 Ω

2.

3.

4.

Not tested or partially tested in production. This parameter is guaranteed by characterization or

correlation to other tests.

This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by

characterization.

When the Intelligent Access voice chipset is in the anti-sat operating region, this parameter will be

degraded. The exact degradation will depend on system design.

5.

6.

Guaranteed by design.

Overall 1.014 kHz insertion loss error of the Intelligent Access voice chipset is guaranteed to be ≤

0.34 dB

7.

These SBAT, PSRR specifications are valid only when the ISLIC is used with the ISLAC, which

generatestheanti-satreference.Sincetheanti-satreferencedependsuponthebatteryvoltagesensed

by the VHB, VLB, and VPB pins of the ISLAC, the PSRR of the kit depends upon the amount of battery

filtering provided by CB.

8.

Must meet at least one of these specifications.

9.

These voltages are referred to VREF

10.

11.

These limits refer to the 2-wire output of an ideal ISLIC but reflect only the capabilities the ISLAC.

When relative levels (dBm0) are used, the specification holds for any setting of (AX + GX) gain from

0 to 12 dB or (AR + GR + RG) from 0 to –12 dB.

12.

13.

Group delay spec valid only when Channels 1–2 occupy consecutive slots in the frame. Programming

channels in non-consecutive timeslots adds 1 frame delay in the Group delay measurements.

The Group delay specification is defined as the sum of the minimum values of the group delays for

transmit and the receive paths when the B, X, R, and Z filters are disabled with null coefficients. See

Figure 15-3 for Group Delay Distortion.

14.

These limits reflect only the capabilities of the dual ISLAC device.

18

Am79D2251

Transmit and Receive Paths

In this section, the transmit path is defined as the analog input to the ISLAC device (VINn) to the

PCM voice output of the ISLAC A-law/µ law speech compressor (See Figure 7-1 in the Am79R2xx/

Am79D2251x Technical Reference). The receive path is defined as the PCM voice input to the

ISLAC speech expander to the analog output of the ISLAC device (VOUTn). All limits defined in this

section are tested with B = 0, Z = 0 and X = R = RG = 1.

When RG is enabled, a gain of –6.02 dB is added to the digital section of the receive path.

When AR is enabled, a nominal gain of –6.02 dB is added to the analog section of the receive path.

When AX is enabled, a nominal gain of +6.02 dB is added to the analog section of the transmit path.

When relative levels (dBm0) are used in any of the following transmission characteristics, the

specification holds for any setting of (AX + GX) gain from 0 to 12 dB or (AR + GR) from 0 to –12 dB.

These transmission characteristics are valid for 0 to 70°C.

Am79D2251

19

Attenuation Distortion

The attenuation of the signal in either path is nominally independent of the frequency. The deviations

from nominal attenuation will stay within the limits shown in Figure 6. The reference frequency is

1014 Hz and the signal level is –10 dBm0.

Figure 6. Transmit and Receive Path Attenuation vs. Frequency

2

Dual ISLAC Specification

1

0.80

0.65

0.6

0.2

0.125

0

Receive path

-0.125

0

Frequency (Hz)

Minimum transmit attenuation at 60 Hz is 24 dB

Group Delay Distortion

For either transmission path, the group delay distortion is within the limits shown in

Figure 7. The minimum value of the group delay is taken as the reference. The signal level should

be –10 dBm0.

Figure 7. Group Delay Distortion

420

Dual ISLAC Specification

(Either Path)

Delay (µS)

150

90

0

Frequency (Hz)

20

Am79D2251

Single Frequency Distortion

The output signal level, at any single frequency in the range of 300 to 3400 Hz, other than that due

to an applied 0 dBm0 sine wave signal with frequency f in the same frequency range, is less than

–46 dBm0. With f swept between 0 to 300 Hz and 3.4 to 12 kHz, any generated output signals other

than f are less than –28 dBm0. This specification is valid for either transmission path.

Intermodulation Distortion

Two sine wave signals of different frequencies, f₁and f₂(not harmonically related) in the range 300

to 3400 Hz and of equal levels in the range –4 to –21 dBm0, do not produce 2 • f₁– f₂products

having a level greater than –42 dB, relative to the level of the two input signals.

A sine wave signal in the frequency band 300 to 3400 Hz with input level –9 dBm0 and a 50 Hz

signal with input level –23 dBm0 does not produce intermodulation products exceeding a level of

–56 dBm0. These specifications are valid for either transmission path.

Am79D2251

21

Gain Linearity

The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 8 (A-law) and

Figure 9 (µ-law) for either transmission path when the input is a sine wave signal of 1014 Hz.

Figure 8. A-law Gain Linearity with Tone Input (Both Paths)

Dual ISLAC Specification

1.5

0.55

0.25

Input

Level

(dBm0)

Gain (dB)

-0.25

0

-55 -50

-40

-10

0 +3

-0.55

-1.5

Figure 9. µ-law Gain Linearity with Tone Input (Both Paths)

Dual ISLAC Specification

1.4

0.45

0.25

Input

Level

(dBm0)

Gain (dB)

0

-55 -50

-37

-10

0

+3

-0.25

-0.45

-1.4

22

Am79D2251

Total Distortion Including Quantizing Distortion

The signal to total distortion ratio will exceed the limits shown in Figure 10 for either path when the

input signal is a sine wave signal of frequency 1014 Hz.

Figure 10. Total Distortion with Tone Input, Both Paths

Dual ISLAC Specification

B

A

A-Law

µ-Law

A

B

C

D

35.5dB 35.5dB

C

D

30dB

25dB

31dB

27dB

Signal-to-Total

Distortion (dB)

-45

-40

-30

0

Input Level (dBm0)

Overload Compression

Figure 11 shows the acceptable region of operation for input signal levels above the reference input

power (0 dBm0). The conditions for this figure are:

(1) 1 dB < GX ≤ +12 dB; (2) –12 dB ≤ GR < –1 dB; (3) Digital voice output connected to digital voice

input; and (4) measurement analog to analog.

Figure 11. A/A Overload Compression

9

8

7

6

Fundamental

Output Power

(dBm0)

5

Acceptable

Region

4

3

2.6

2

1

7

8

9

1

2

3

4

5

6

Fundamental Input Power (dBm0)

Am79D2251

23

Discrimination against Out-of-Band Input Signals

When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be

frequency components below 4 kHz at the digital output which are caused by the out-of-band signal. These

components are at least the specified dB level below the level of a signal at the same output originating from a

1014 Hz sine wave signal with a level of A dBm0 also applied to the analog input. The minimum specifications are

shown in the following table.

Frequency of Out-of-Band Signal

16.6 Hz < f < 45 Hz

Amplitude of Out-of-Band Signal

–25 dBm0 < A ≤ 0 dBm0

Level below A

18 dB

45 Hz < f < 65 Hz

25 dB

65 Hz < f < 100 Hz

10 dB

3400 Hz < f < 4600 Hz

4600 Hz < f < 100 kHz

see Figure 12

32 dB

0

ISLAC Device Specification

–10

–20

Level (dB)

–28 dBm

–32 dB, –25 dBm0 < input < 0 dBm0

–30

–40

–50

3.4

4.0

4.6

19256A-012

Frequency (kHz)

Note:

The attenuation of the waveform below amplitude A between

3400 Hz and 4600 Hz is given by the formula:

π(4000 – f)

Attenuation (db) = 14 – 14sin-------------------------

1200

Figure 12. Discrimination Against Out-of-Band Signals

24

Am79D2251

Spurious Out-of-Band Signals at the Analog Output

With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0 applied

to the digital input, the level of the spurious out-of-band signals at the analog output is less than the limits shown below.

Frequency

Level

4.6 kHz to 40 kHz

40 kHz to 240 kHz

240 kHz to 1 MHz

–32 dBm0

–46 dBm0

–36 dBm0

With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to

the digital input, the level of the signals at the analog output are below the limits in Figure 13. The amplitude of the

spurious out-of-band signals between 3400 Hz and 4600 Hz is given by the formula:

π(f – 4000)

---------------------------

1200

A = – 14 – 14sin

dBm0

0

ISLAC Device Specification

–10

–20

–30

–40

–50

Level (dBm0)

–28 dB

–32 dB

3.4

4.0

4.6

Frequency (kHz)

19256A-013

Figure 13. Spurious Out-of-Band Signals

Am79D2251

25

SWITCHING CHARACTERISTICS

PCM Switching Characteristics

Figure 14. PCM Switching Characteristics

VCC = 3.3 V +5%, AGND = DGND = 0 V

TBD

TEST

POINTS

TBD

Microprocessor Interface

Min and max values are valid for all digital outputs with a 100 pF load, except DIO,DXA, INTL, and

TSCA which are valid with 150 pF loads.

No.

Symbol

Parameter

Data clock period

Min

Typ

Max

Unit

Note

1

t_DCY

122

2

3

4

5

6

t_DCH

t_DCL

t_DCR

t_DCF

t_ICSS

Data clock HIGH pulse width

Data clock LOW pulse width

Rise time of clock

48

1

15

Fall time of clock

Chip select setup time, Input

mode

30

0

t

_DCY–10

ns

7

8

t_ICSH

t_ICSL

Chip select hold time, Input mode

t_DCH–20

Chip select pulse width, Input

mode

8t_DCY

9

t_ICSO

t_IDS

Chip select off time, Input mode

Input data setup time

1, 6

5

10

11

25

30

t_IDH

Input data hold time

12

13

t_OCSS

t_OCSH

t_OCSL

Chip select setup time, Output

mode

30

t_DCY–10

14

15

Chip select hold time, Output

mode

t_DCH–20

Chip select pulse width, Output

mode

8t_DCY

ns

µs

16

17

18

19

20

21

t_OCSO

t_ODD

t_ODH

t_ODOF

t_ODC

t_RST

Chip select off time, output Mode

Output data turn on delay

Output data hold time

Output data turn off delay

Output data valid

1, 6

50

3

50

0

Reset pulse width

50

26

Am79D2251

PCM Interface

No.

Symbol

Parameter

PCM clock period

Min.

Typ

Max

Unit

Note

22

t_PCY

0.122

7.8125

µs

2

23

24

25

26

27

28

29

30

31

32

33

34

35

36

t_PCH

t_PCL

t_PCF

t_PCR

t_FSS

t_FSH

t_TSD

t_TSO

t_DXD

t_DXH

t_DXZ

t_DRS

t_DRH

t_FST

PCM clock HIGH pulse width

PCM clock LOW pulse width

Fall time of clock

48

ns

15

Rise time of clock

FS setup time

30

50

5

t_PCY–30

FS hold time

Delay to TSCA valid

80

3

4

Delay to TSCA off

5

PCM data output delay

PCM data output hold time

PCM data output delay to high-Z

PCM data input setup time

PCM data input hold time

PCM or frame sync jitter time

5

70

5

10

25

5

–97

97

Master Clock

For 2.048 MHz ±100 PPM, 4.096 MHz ±100 PPM, or 8.192 MHz ±100 PPM operation:

No.

Symbol

Parameter

Period: 2.048 MHz

Period: 4.096 MHz

Period: 8.192 MHz

Min

Typ

Max

Unit

No

37

t_MCY

488.23

244.11

122.05

488.28

244.14

122.07

488.33

244.17

122.09

2

38

39

40

41

t_MCR

t_MCF

t_MCH

t_MCL

Rise time of clock

15

ns

Fall time of clock

MCLK HIGH pulse width

MCLK LOW pulse width

48

Notes:

1.

DCLK may be stopped in the HIGH or LOW state indefinitely without loss of information. When CS

makes a transition to the High state, the last byte received will be interpreted by the Microprocessor

Interface logic.

2.

The PCM clock (PCLK or MCLK) frequency must be an integer multiple of the frame sync (FS)

frequency with an accuracy of 100 PPM. This allowance includes any jitter that may occur between

thePCMsignals(FS, PCLK)andMCLK. TheactualPCLKrateisdependentonthenumberofchannels

allocated within a frame. The minimum clock frequency is 128 kHz. A PCLK of 1.544 MHz may be

used for standard U.S. transmission systems.

3.

4.

TSCA is delayed from FS by a typical value of N • t_PCY, where N is the value stored in the time/clock

slot register.

t

_TSOis defined as the time at which the output driver turns off. The actual delay time is dependent on

the load circuitry. The maximum load capacitance on TSCA is 150 pF and the minimum pull-up

resistance is 360 Ω.

5.

6.

The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs

last.

The ISLAC device requires 2.0 µs between SIO operations. If the MPI is being accessed while the

MCLK (or PCLK if combined with MCLK) input is not active, a Chip Select Off time of 20 µs is required

when accessing coefficient RAM.

Am79D2251

27

PCM Switching Waveforms

Figure 15. Master Clock Timing

37

41

V

IH

V

IL

40

38

39

Figure 16. Microprocessor Interface (Input Mode)

1

2

5

V_IH

DCLK

V_IL

3

7

9

4

CS

6

8

10

11

Data

Valid

Data

Valid

Data

Valid

DIO

28

Am79D2251

Figure 17. Microprocessor Interface (Output Mode)

V_IH

V_IL

DCLK

13

14

16

15

CS

20

18

17

19

V_OH

Data

Valid

Data

Valid

Data

Valid

Three-State

DIO

V_OL

Figure 18. PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge))

Time Slot Zero, Clock Slot Zero

27

22

25

26

V_IH

V_IL

PCLK

23

24

28

FS

30

29

TSCA

See Note 4

31

32

33

V_OH

First

DXA

DRA

Bit

V_OL

35

34

V_IH

First

Bit

Second

Bit

V_IL

Am79D2251

29

Figure 19. PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)

Time Slot Zero, Clock Slot Zero

27

22

26

25

V_IH

V_IL

PCLK

23

24

FS

28

30

29

TSCA

DXA

See Note 4

31

32

33

V_OH

First

Bit

V_OL

35

34

V_IH

First

Bit

Second

Bit

DRA

V_IL

GCI Timing Specifications

Symbol

Signal

Parameter

Min

Typ

Max

Unit

t_R, t_F

DCL

Rise/fall time

60

t_DCL

DCL

Period, F_DCL= 2048 kHz

F_DCL= 4096 kHz

478

239

498

249

t

_WH, t_WL

t_R, t_F

t_SF

DCL

FS

Pulse width

90

Rise/fall time

Setup time

60

FS

70

50

t_DCL–50

ns

t_HF

FS

Hold time

t_WFH

t_DDC

t_DDF

t_SD

FS

High pulse width

Delay from DCL edge

Delay from FS edge

Data setup

130

DU

DD

100

150

twH+20

50

t_HD

Data hold

Notes:

1. The Data Clock (DCL) can be stopped in the high or low state without loss of information.

2. A temporary stoppage of DCL must not put the ISLAC into a state in which it does not respond to a software

reset command.

3. All frequency-dependent specifications are guaranteed for clock frequencies within ±100 PPM from

nominal.

30

Am79D2251

GCI Waveforms

DCL

FS

BIT

7

BIT

6

DD,

DU

DETAIL A

t_r

t_f

DCL**

t_WH

t_DCL

t_WL

FS

t_SF

t_HF

t_WFH

t_DDF

DU

t_DDC

t_SD

t_HD

DD

** Timing diagram valid for

F_DCL= 2048 or 4096 KHz

Am79D2251

31

PHYSICAL DIMENSIONS

44-Pin PLCC

.062

.083

.685

.695

.042

.056

.650

.656

Pin 1 I.D.

.685

.695

.500 .590

REF .630

.650

.656

.013

.021

.009

.015

.026

.032

.090

.120

.165

.180

.050 REF

SEATING PLANE

16-038-SQ

PL 044

DA78

6-28-94 ae

TOP VIEW

SIDE VIEW

44-Pin TQFP

44

1

11.80

12.20

9.80

10.20

9.80

10.20

11.80

12.20

11° – 13°

0.95

1.05

1.20 MAX

16-038-PQT-2

PQT 44

7-11-95 ae

11° – 13°

0.80 BSC

0.30

0.45

1.00 REF.

32

Am79D2251

REVISION SUMMARY

Revision A to Revision B

•

Revision A was a condensed version of the datasheet while Revision B contains the full version.

Revision B to Revision C

Page 13, Linecard Parts List, Rows CHLbi and CHLdi: switched the numbers in the “Values” column.

•

The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations

or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci-

fications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any in-

tellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no

liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of

merchantability, fitness for a particular purpose, or infringement of any intellectual property right.

AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the

body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a

situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make

changes to its products at any time without notice.

Trademarks

AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Intelligent Access and WinSLAC are trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am79D2251

33

Am79D2251

34


型号：	AM79D2251JC
厂家：	AMD
描述：	Dual Intelligent Subscriber Line Audio-Processing Circuit (ISLAC) 双智能用户线音频处理电路（ ISLAC ）
文件：	总35页 (文件大小：388K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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