AM29LV800DT-90WCI_技术文档

Am29LV800D

Data Sheet

For new designs, S29AL008D supersedes Am29LV800D and is the factory-recommended migration

path. Please refer to the S29AL008D Data Sheet for specifications and ordering information.

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number Am29LV800D_00 Revision A Amendment 4 Issue Date January 21, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

PRELIMINARY

Am29LV800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

For new designs, S29AL008D supersedes Am29LV800D and is the factory-recommended migration

path. Please refer to the S29AL008D Data Sheet for specifications and ordering information.

Distinctive Characteristics

■ Single power supply operation

■ Top or bottom boot block configurations

available

— 2.7 to 3.6 volt read and write operations

for battery-powered applications

■ Embedded Algorithms

■ Manufactured on 0.23 µm process

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

technology

— Compatible with 0.32 µm Am29LV800

device

— Embedded Program algorithm

automatically writes and verifies data at

specified addresses

■ High performance

— Access times as fast as 70 ns

■ Minimum 1 million write cycle guarantee

■ Ultra low power consumption (typical

per sector

values at 5 MHz)

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package option

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 48-ball FBGA

— 15 mA program/erase current

— 48-pin TSOP

■ Flexible sector architecture

— 44-pin SO

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)

— Superior inadvertent write protection

— Supports full chip erase

■ Data# Polling and toggle bits

— Sector Protection features:

— Provides a software method of detecting

program or erase operation completion

A hardware method of locking a sector to prevent

any program or erase operations within that

sector

■ Ready/Busy# pin (RY/BY#)

Sectors can be locked in-system or via

programming equipment

— Provides a hardware method of detecting

program or erase cycle completion

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■ Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command

sequences

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to

reading array data

This document contains information on a product under development at FASL LLC. The information is intended to

help you evaluate this product. FASL LLC reserves the right to change or discontinue work on this proposed product

without notice.

Publication Am29LV800D_00 Rev. A Amend. 4

Issue Date: January 21, 2005

P R E L I M I N A R Y

General Description

The Am29LV800D is an 8 Mbit, 3.0 volt-only

Flash memory organized as 1,048,576 bytes or

524,288 words. The device is offered in 48-ball

FBGA, 44-pin SO, and 48-pin TSOP packages.

For more information, refer to publication

number 21536. The word-wide data (x16)

appears on DQ15–DQ0; the byte-wide (x8) data

appears on DQ7–DQ0. This device requires only

a single, 3.0 volt V_CCsupply to perform read,

program, and erase operations. A standard

EPROM programmer can also be used to program

and erase the device.

cuting the erase operation. During erase, the

device automatically times the erase pulse

widths and verifies proper cell margin.

The host system can detect whether a program

or erase operation is complete by observing the

RY/BY# pin, or by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a

program or erase cycle has been completed, the

device is ready to read array data or accept

another command.

The sector erase architecture allows memory

sectors to be erased and reprogrammed without

affecting the data contents of other sectors. The

device is fully erased when shipped from the

factory.

This device is manufactured using AMD’s 0.23

µm process technology, and offers all the fea-

tures and benefits of the Am29LV800B, which

was manufactured using 0.32 µm process tech-

nology.

Hardware data protection measures include

a low V_CCdetector that automatically inhibits

write operations during power transitions. The

hardware sector protection feature disables

both program and erase operations in any com-

bination of the sectors of memory. This can be

achieved in-system or via programming equip-

ment.

The standard device offers access times of 70,

90, and 120 ns, allowing high speed micropro-

cessors to operate without wait states. To elim-

inate bus contention the device has separate

chip enable (CE#), write enable (WE#) and

output enable (OE#) controls.

The device requires only a single 3.0 volt

power supply for both read and write func-

tions. Internally generated and regulated volt-

ages are provided for the program and erase

operations.

The Erase Suspend feature enables the user to

put erase on hold for any period of time to read

data from, or program data to, any sector that

is not selected for erasure. True background

erase can thus be achieved.

The device is entirely command set compatible

with the JEDEC single-power-supply Flash

standard. Commands are written to the

command register using standard micropro-

cessor write timings. Register contents serve as

input to an internal state-machine that controls

the erase and programming circuitry. Write

cycles also internally latch addresses and data

needed for the programming and erase opera-

tions. Reading data out of the device is similar

to reading from other Flash or EPROM devices.

The hardware RESET# pin terminates any

operation in progress and resets the internal

state machine to reading array data. The

RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the

device, enabling the system microprocessor to

read the boot-up firmware from the Flash

memory.

The device offers two power-saving features.

When addresses have been stable for a specified

amount of time, the device enters the auto-

matic sleep mode. The system can also place

the device into the standby mode. Power con-

sumption is greatly reduced in both these

modes.

Device programming occurs by executing the

program command sequence. This initiates the

Embedded Program algorithm—an internal

algorithm that automatically times the program

pulse widths and verifies proper cell margin. The

Unlock Bypass mode facilitates faster pro-

gramming times by requiring only two write

cycles to program data instead of four.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce

the highest levels of quality, reliability and cost

effectiveness. The device electrically erases

all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is pro-

grammed using hot electron injection.

Device erasure occurs by executing the erase

command sequence. This initiates the

Embedded Erase algorithm—an internal algo-

rithm that automatically preprograms the array

(if it is not already programmed) before exe-

2

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

Table Of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for FBGA Package ..............7

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Standard Products ......................................................................8

Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .10

Table 1. Am29LV800D Device Bus Operations .10

Word/Byte Configuration ...................................................... 10

Requirements for Reading Array Data ............................... 10

Writing Commands/Command Sequences .........................11

Program and Erase Operation Status ...................................11

Standby Mode ..............................................................................11

Automatic Sleep Mode ..............................................................11

RESET#: Hardware Reset Pin .................................................11

Output Disable Mode ...............................................................12

Table 2. Am29LV800DT Top Boot Block

Sector Addresses ........................................12

Table 3. Am29LV800DB Bottom Boot Block

Sector Addresses ........................................13

Autoselect Mode ........................................................................13

Table 4. Am29LV800D Autoselect Codes

(High Voltage Method) ................................14

Sector Protection/Unprotection .......................................... 14

Temporary Sector Unprotect ............................................... 14

Figure 1. Temporary Sector Unprotect

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 27

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 27

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .28

CMOS Compatible .................................................................. 28

Figure 1. I

Current vs. Time (Showing Active

CC1

and Automatic Sleep Currents) .................... 29

Figure 1. Typical I vs. Frequency ............. 29

CC1

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 1. Test Setup................................... 30

Table 7. Test Specifications ........................................30

Key to Switching Waveforms. . . . . . . . . . . . . . . . 30

Figure 1. Input Waveforms and

Measurement Levels................................... 30

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 31

Read Operations ........................................................................31

Figure 1. Read Operations Timings............... 31

Hardware Reset (RESET#) ....................................................32

Figure 1. RESET# Timings........................... 32

Word/Byte Configuration (BYTE#) ..................................33

Figure 1. BYTE# Timings for Read

Operations................................................ 34

Figure 1. BYTE# Timings for Write

Operations................................................ 34

Erase/Program Operations ....................................................35

Figure 1. Program Operation Timings............ 36

Figure 1. Chip/Sector Erase Operation

Timings .................................................... 37

Figure 1. Data# Polling Timings (During

Embedded Algorithms) ............................... 38

Figure 1. Toggle Bit Timings (During

Operation.................................................. 15

Figure 2. In-System Sector Protect/

Embedded Algorithms) ............................... 38

Figure 1. DQ2 vs. DQ6 ............................... 39

Temporary Sector Unprotect ...............................................39

Figure 1. Temporary Sector Unprotect

Timing Diagram......................................... 39

Figure 1. Sector Protect/Unprotect

Timing Diagram......................................... 40

Alternate CE# Controlled

Erase/Program Operations .................................................... 41

Figure 1. Alternate CE# Controlled Write

Operation Timings...................................... 42

Erase and Programming Performance . . . . . . . . .43

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 43

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 43

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . . .44

TS 048—48-Pin Standard TSOP ........................................ 44

TSR048—48-Pin Reverse TSOP .........................................45

FBB 048—48-Ball Fine-Pitch Ball Grid Array

(FBGA) 6 x 9 mm ................................................................... 46

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 47

VBK 048 - 48 Ball Fine-Pitch Ball Grid Array

(FBGA) 6.15 x 8.15 mm .............................................................47

SO 044—44-Pin Small Outline Package ..........................48

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . .49

Sector Unprotect Algorithms ........................ 16

Hardware Data Protection .....................................................17

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 17

Reading Array Data ...................................................................17

Reset Command .........................................................................17

Autoselect Command Sequence .......................................... 18

Word/Byte Program Command Sequence ....................... 18

Figure 1. Program Operation ........................ 19

Chip Erase Command Sequence .......................................... 19

Sector Erase Command Sequence ...................................... 19

Erase Suspend/Erase Resume Commands ....................... 20

Figure 1. Erase Operation ............................ 21

Table 5. Am29LV800D Command Definitions ..21

Write Operation Status . . . . . . . . . . . . . . . . . . . . 22

DQ7: Data# Polling ..................................................................22

Figure 1. Data# Polling Algorithm ................. 23

RY/BY#: Ready/Busy# .............................................................23

DQ6: Toggle Bit I ......................................................................24

DQ2: Toggle Bit II .....................................................................24

Reading Toggle Bits DQ6/DQ2 ............................................24

DQ5: Exceeded Timing Limits ..............................................25

DQ3: Sector Erase Timer .......................................................25

Figure 1. Toggle Bit Algorithm ...................... 25

Table 6. Write Operation Status ....................26

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

3

P R E L I M I N A R Y

Product Selector Guide

Family Part Number

Am29LV800D

Speed Options

Full Voltage Range: V = 2.7–3.6 V

-70

-90

-120

CC

Max access time, ns (t

)

70

90

35

120

50

ACC

Max CE# access time, ns (t )

70

30

CE

Max OE# access time, ns (t

)

OE

Note: See “AC Characteristics” for full specifications.

Block Diagram

DQ0–DQ15 (A-1)

RY/BY#

V

CC

Sector Switches

SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Chip Enable

Output Enable

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V

Detector

Timer

CC

Cell Matrix

X-Decoder

A0–

4

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

Connection Diagrams

A15

A14

A13

A12

A11

A10

A9

A8

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ4

V_CC

WE#

RESET#

NC

Standard TSOP

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

1

2

3

4

5

6

7

8

A15

A14

A13

A12

A11

A10

A9

A8

NC

48

A16

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

Reverse TSOP

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

OE#

V_SS

CE#

A0

Am29LV800D_

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

5

P R E L I M I N A R Y

Connection Diagrams

RY/BY#

A18

A17

A7

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

41 A9

A6

40 A10

A5

39 A11

A4

38 A12

A3

37 A13

SO

A2

36 A14

A1 10

A0 11

35 A15

34 A16

CE# 12

V_SS13

33 BYTE#

32 V_SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

FBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

DQ5

DQ12

V_CC

DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY#

NC

A18

NC

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V_SS

6

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

V_CC

= 3.0 volt-only single power supply

(see Product Selector Guide for

Special Handling Instructions for FBGA

Package

Special handling is required for Flash Memory

products in FBGA packages.

speed

options and voltage supply

tolerances)

V_SS

Flash memory devices in FBGA packages may

be damaged if exposed to ultrasonic cleaning

methods. The package and/or data integrity

may be compromised if the package body is

exposed to temperatures above 150°C for pro-

longed periods of time.

= Device ground

NC

= Pin not connected internally

Logic Symbol

19

A0–A18

16 or 8

Pin Configuration

DQ0–DQ15

(A-1)

A0–A18 = 19 addresses

DQ0–DQ14= 15 data inputs/outputs

DQ15/A-1 = DQ15 (data input/output, word

mode),

CE#

OE#

WE#

A-1 (LSB address input, byte

mode)

RESET

BYTE#

RY/BY#

BYTE#

CE#

= Selects 8-bit or 16-bit mode

= Chip enable

OE#

= Output enable

WE#

= Write enable

RESET# = Hardware reset pin, active low

RY/BY# = Ready/Busy# output

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

7

P R E L I M I N A R Y

Ordering Information

Standard Products

AMD standard products are available in several packages and operating ranges. The order number

(Valid Combination) is formed by a combination of the elements below.

Am29LV800D

T

-70

E

C

TEMPERATURE RANGE

C

D

I

=

Commercial (0°C to +70°C)

Commercial (0°C to +70°C) with Pb-Free Package

Industrial (–40°C to +85°C)

Industrial (–40°C to +85°C) with Pb-Free Package

F

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package (TSOP) Standard Pinout

(TS 048)

F

=

48-Pin Thin Small Outline Package (TSOP) Reverse Pinout

(TSR048)

S

WB

=

44-Pin Small Outline Package (SO 044)

48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 9 mm package (FBB048)

48-Ball Fine Pitch Ball Grid Array (FBGA)

WC

=

0.80 mm pitch, 6.15 x 8.15 mm package (VBK 048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP and SO Packages

AM29LV800DT-70,

AM29LV800DB-70

EC, EI, ED, EF, FC, FD, FF, FI,

SC, SD, SF, SI

AM29LV800DT-90,

AM29LV800DB-90

EC, EI, ED,EF,FD, FF,FC,

FI,SD, SFSC, SI

AM29LV800DT-120,

AM29LV800DB-120

8

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

Valid Combinations for FBGA Packages

Order Number

Package Marking

WBC

WBI

WBD

WBF

WCC

WCI

WCD

WCF

AM29LV800DT-70,

AM29LV800DB-70

L800DT70V,

L800DB70V

WCC

WCI

WCD

WCF

WBC

WBI

WBD

WBF

C, I,

D,F

AM29LV800DT-90,

AM29LV800DB-90

L800DT90V,

L800DB90V

WBC

WBI

WBD

WBF

AM29LV800DT-120,

AM29LV800DB-120

L800DT12V,

L800DB12V

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD

sales office to confirm availability of specific valid combinations and to check on newly released combinations.

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

9

P R E L I M I N A R Y

Device Bus Operations

This section describes the requirements and use

of the device bus operations, which are initiated

through the internal command register. The

command register itself does not occupy any

addressable memory location. The register is

composed of latches that store the commands,

along with the address and data information

needed to execute the command. The contents

of the register serve as inputs to the internal

state machine. The state machine outputs

dictate the function of the device. Table 1 lists

the device bus operations, the inputs and

control levels they require, and the resulting

output. The following subsections describe each

of these operations in further detail.

Table 1. Am29LV800D Device Bus Operations

DQ8–DQ15

BYTE#

BYTE

#

OE WE RESET

Addresses

(Note 1)

DQ0–

Operation

CE#

#

H

L

#

H

DQ7 = V

= V

IH

IL

Read

Write

L

A

D

OUT

DQ8–DQ14 = High-

Z, DQ15 = A-1

IN

OUT

H

A

D

IN

V

0.3 V

V

CC

0.3 V

CC

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect (Note 2)

L

H

L

V

D

X

ID

IN

Sector Address,

A6 = H, A1 = H,

A0 = L

Sector Unprotect (Note 2)

L

H

X

L

V

D

X

ID

IN

Temporary Sector Unprotect

X

A

D

High-Z

IN

Legend:

L = Logic Low = V , H = Logic High = V , V = 12.0 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out

IL

IH

ID

IN

OUT

Notes:

1. Addresses are A18:A0 in word mode (BYTE# = V ), A18:A-1 in byte mode (BYTE# = V ).

IH

IL

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See

the “Sector Protection/Unprotection” section.

BYTE# pin determines whether the device

outputs array data in words or bytes.

Word/Byte Configuration

The BYTE# pin controls whether the device data

I/O pins DQ15–DQ0 operate in the byte or word

configuration. If the BYTE# pin is set at logic ‘1’,

the device is in word configuration, DQ15–DQ0

are active and controlled by CE# and OE#.

The internal state machine is set for reading

array data upon device power-up, or after a

hardware reset. This ensures that no spurious

alteration of the memory content occurs during

the power transition. No command is necessary

in this mode to obtain array data. Standard

microprocessor read cycles that assert valid

addresses on the device address inputs produce

valid data on the device data outputs. The

device remains enabled for read access until the

command register contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is

in byte configuration, and only data I/O pins

DQ0–DQ7 are active and controlled by CE# and

OE#. The data I/O pins DQ8–DQ14 are

tri-stated, and the DQ15 pin is used as an input

for the LSB (A-1) address function.

Requirements for Reading Array Data

See “Reading Array Data” for more information.

Refer to the AC Read Operations table for timing

specifications and to Figure 1 for the timing dia-

gram. I_CC1in the DC Characteristics table repre-

sents the active current specification for reading

array data.

To read array data from the outputs, the system

must drive the CE# and OE# pins to V_IL. CE# is

the power control and selects the device. OE# is

the output control and gates array data to the

output pins. WE# should remain at V_IH. The

10

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

the high impedance state, independent of the

Writing Commands/Command Sequences

OE# input.

To write a command or command sequence

(which includes programming data to the device

and erasing sectors of memory), the system

must drive WE# and CE# to V_IL, and OE# to

V_IH.

The device enters the CMOS standby mode

when the CE# and RESET# pins are both held at

V_CC0.3 V. (Note that this is a more restricted

voltage range than V_IH.) If CE# and RESET# are

held at V_IH, but not within V_CC0.3 V, the device

will be in the standby mode, but the standby

current will be greater. The device requires stan-

dard access time (t_CE) for read access when the

device is in either of these standby modes,

before it is ready to read data.

For program operations, the BYTE# pin deter-

mines whether the device accepts program data

in bytes or words. Refer to “Word/Byte Configu-

ration” for more information.

The device features an Unlock Bypass mode to

facilitate faster programming. Once the device

enters the Unlock Bypass mode, only two write

cycles are required to program a word or byte,

instead of four. The “Word/Byte Program

Command Sequence” section has details on pro-

gramming data to the device using both stan-

dard and Unlock Bypass command sequences.

If the device is deselected during erasure or pro-

gramming, the device draws active current until

the operation is completed.

In the DC Characteristics table, I_CC3and I_CC4

represents the standby current specification.

Automatic Sleep Mode

An erase operation can erase one sector, mul-

tiple sectors, or the entire device. Tables 2 and

3 indicate the address space that each sector

occupies. A “sector address” consists of the

address bits required to uniquely select a sector.

The “Command Definitions” section has details

on erasing a sector or the entire chip, or sus-

pending/resuming the erase operation.

The automatic sleep mode minimizes Flash

device energy consumption. The device auto-

matically enables this mode when addresses

remain stable for t_ACC+ 30 ns. The automatic

sleep mode is independent of the CE#, WE#,

and OE# control signals. Standard address

access timings provide new data when

addresses are changed. While in sleep mode,

output data is latched and always available to

the system. I_CC4in the DC Characteristics table

represents the automatic sleep mode current

specification.

After the system writes the autoselect command

sequence, the device enters the autoselect

mode. The system can then read autoselect

codes from the internal register (which is sepa-

rate from the memory array) on DQ7–DQ0.

Standard read cycle timings apply in this mode.

Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more infor-

mation.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of

resetting the device to reading array data. When

the RESET# pin is driven low for at least a

period of t_RP, the device immediately termi-

nates any operation in progress, tristates all

output pins, and ignores all read/write com-

mands for the duration of the RESET# pulse.

The device also resets the internal state

machine to reading array data. The operation

that was interrupted should be reinitiated once

the device is ready to accept another command

sequence, to ensure data integrity.

I_CC2in the DC Characteristics table represents

the active current specification for the write

mode. The “AC Characteristics” section contains

timing specification tables and timing diagrams

for write operations.

Program and Erase Operation Status

During an erase or program operation, the

system may check the status of the operation by

reading the status bits on DQ7–DQ0. Standard

read cycle timings and I_CCread specifications

apply. Refer to “Write Operation Status” for

more information, and to “AC Characteristics”

for timing diagrams.

Current is reduced for the duration of the

RESET# pulse. When RESET# is held at

V_SS±0.3 V, the device draws CMOS standby

current (I_CC4). If RESET# is held at V_ILbut not

within V_SS±0.3 V, the standby current will be

greater.

Standby Mode

The RESET# pin may be tied to the system reset

circuitry. A system reset would thus also reset

the Flash memory, enabling the system to read

the boot-up firmware from the Flash memory.

When the system is not reading or writing to the

device, it can place the device in the standby

mode. In this mode, current consumption is

greatly reduced, and the outputs are placed in

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

11

P R E L I M I N A R Y

If RESET# is asserted during a program or erase

Embedded Algorithms). The system can read

data t_RHafter the RESET# pin returns to V_IH.

operation, the RY/BY# pin remains a “0” (busy)

until the internal reset operation is complete,

which requires a time of t_READY(during

Embedded Algorithms). The system can thus

monitor RY/BY# to determine whether the reset

operation is complete. If RESET# is asserted

when a program or erase operation is not exe-

cuting (RY/BY# pin is “1”), the reset operation

is completed within a time of t_READY(not during

Refer to the AC Characteristics tables for

RESET# parameters and to Figure 1 for the

timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the

device is disabled. The output pins are placed in

the high impedance state.

Table 2. Am29LV800DT Top Boot Block Sector Addresses

Address Range (in hexadecimal)

Sector Size

(Kbytes/

Kwords)

(x8)

(x16)

Sector A18 A17 A16 A15 A14 A13 A12

Address Range Address Range

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

X

0

1

X

0

1

X

64/32

32/16

8/4

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

D0000h–DFFFFh 68000h–6FFFFh

E0000h–EFFFFh

F0000h–F7FFFh

F8000h–F9FFFh

70000h–77FFFh

78000h–7BFFFh

7C000h–7CFFFh

8/4

FA000h–FBFFFh 7D000h–7DFFFh

FC000h–FFFFFh 7E000h–7FFFFh

16/8

12

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

Table 3. Am29LV800DB Bottom Boot Block Sector Addresses

Address Range (in hexadecimal)

Sector Size

(Kbytes/

Kwords)

(x8)

(x16)

Sector A18 A17 A16 A15 A14 A13 A12

Address Range Address Range

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

X

0

1

X

16/8

8/4

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

SA2

8/4

SA3

32/16

64/32

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

D0000h–DFFFFh 68000h–6FFFFh

E0000h–EFFFFh

F0000h–FFFFFh

70000h–77FFFh

78000h–7FFFFh

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte

Configuration” section.

verifying sector protection, the sector address

must appear on the appropriate highest order

address bits (see Tables 2 and 3). Table 4 shows

the remaining address bits that are don’t care.

When all necessary bits have been set as

required, the programming equipment may

then read the corresponding identifier code on

DQ7–DQ0.

Autoselect Mode

The autoselect mode provides manufacturer

and device identification, and sector protection

verification, through identifier codes output on

DQ7–DQ0. This mode is primarily intended for

programming equipment to automatically

match a device to be programmed with its cor-

responding programming algorithm. However,

the autoselect codes can also be accessed in-

system through the command register.

To access the autoselect codes in-system, the

host system can issue the autoselect command

via the command register, as shown in Table 5.

This method does not require V_ID. See “Com-

mand Definitions” for details on using the

autoselect mode.

When using programming equipment, the

autoselect mode requires V_ID(11.5 V to 12.5 V)

on address pin A9. Address pins A6, A1, and A0

must be as shown in Table 4. In addition, when

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

13

P R E L I M I N A R Y

Table 4. Am29LV800D Autoselect Codes (High Voltage Method)

A1 A1

8

1

to

A8

to

A5

to

DQ8

to

DQ7

to

WE A1 A1

Description

Mode CE# OE#

#

H

2

0

A9 A7 A6 A2 A1 A0 DQ15

DQ0

Manufacturer ID: AMD

L

X

V

X

L

X

L

X

01h

DAh

ID

Device ID:

Word

22h

Am29LV800B

(Top Boot Block)

X

V

X

L

X

L

H

ID

Byte

L

H

X

DAh

5Bh

Device ID:

Am29LV800B

(Bottom Boot

Block)

Word

22h

V

X

L

X

L

H

L

ID

Byte

L

H

X

5Bh

01h

(protected)

Sector Protection

Verification

L

H

SA

X

H

ID

00h

(unprotecte

d)

X

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

IL

IH

standard microprocessor bus cycle timing. For

sector unprotect, all unprotected sectors must

first be protected prior to the first sector unpro-

tect write cycle.

Sector Protection/Unprotection

The hardware sector protection feature disables

both program and erase operations in any

sector. The hardware sector unprotection

feature re-enables both program and erase

operations in previously protected sectors.

The alternate method intended only for pro-

gramming equipment requires V_IDon address

pin A9 and OE#. This method is compatible with

programmer routines written for earlier 3.0 volt-

only AMD flash devices. Publication number

20536 contains further details; contact an AMD

representative to request a copy.

The device is shipped with all sectors unpro-

tected. AMD offers the option of programming

and protecting sectors at its factory prior to

shipping the device through AMD’s Express-

Flash™ Service. Contact an AMD representative

for details.

Temporary Sector Unprotect

It is possible to determine whether a sector is

protected or unprotected. See “Autoselect

Mode” for details.

This feature allows temporary unprotection of

previously protected sectors to change data

in-system. The Sector Unprotect mode is acti-

vated by setting the RESET# pin to V_ID. During

this mode, formerly protected sectors can be

programmed or erased by selecting the sector

addresses. Once V_IDis removed from the

RESET# pin, all the previously protected sectors

are protected again. Figure 1 shows the algo-

Sector Protection/unprotection can be imple-

mented via two methods.

The primary method requires V_IDon the

RESET# pin only, and can be implemented

either in-system or via programming equip-

ment. Figure 2 shows the algorithms and Figure

1 shows the timing diagram. This method uses

14

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

rithm, and Figure 1 shows the timing diagrams,

for this feature.

START

RESET# = V

(Note 1)

ID

Perform Erase or

Program Operations

RESET# = V

IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected

once again.

Figure 1. Temporary Sector Unprotect

Operation

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

15

P R E L I M I N A R Y

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

PLSCNT = 1

RESET# = V_ID

Wait 1 ms

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Yes

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

Wait 150

s

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 01h?

Yes

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

from RESET#

Sector Unprotect

Algorithm

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/

Sector Unprotect Algorithms

16

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

the proper signals to the control pins to prevent

unintentional writes when V_CCis greater than

V_LKO

Hardware Data Protection

The command sequence requirement of unlock

cycles for programming or erasing provides data

protection against inadvertent writes (refer to

Table 5 for command definitions). In addition,

the following hardware data protection mea-

sures prevent accidental erasure or program-

ming, which might otherwise be caused by

spurious system level signals during V_CC

power-up and power-down transitions, or from

system noise.

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#,

CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of

OE# = V_IL, CE# = V_IHor WE# = V_IH. To initiate

a write cycle, CE# and WE# must be a logical

zero while OE# is a logical one.

Low V

Write Inhibit

CC

Power-Up Write Inhibit

When V_CCis less than V_LKO, the device does not

accept any write cycles. This protects data

during V_CCpower-up and power-down. The

command register and all internal pro-

gram/erase circuits are disabled, and the device

resets. Subsequent writes are ignored until V_CC

is greater than V_LKO. The system must provide

If WE# = CE# = V_ILand OE# = V_IHduring

power up, the device does not accept com-

mands on the rising edge of WE#. The internal

state machine is automatically reset to reading

array data on power-up.

Command Definitions

Writing specific address and data commands or

sequences into the command register initiates

device operations. Table 5 defines the valid reg-

ister command sequences. Writing incorrect

address and data values or writing them in

the improper sequence resets the device to

reading array data.

DQ5 goes high, or while in the autoselect mode.

See the “Reset Command” section, next.

See also “Requirements for Reading Array Data”

in the “Device Bus Operations” section for more

information. The Read Operations table provides

the read parameters, and Figure 1 shows the

timing diagram.

All addresses are latched on the falling edge of

WE# or CE#, whichever happens later. All data

is latched on the rising edge of WE# or CE#,

whichever happens first. Refer to the appro-

priate timing diagrams in the “AC Characteris-

tics” section.

Reset Command

Writing the reset command to the device resets

the device to reading array data. Address bits

are don’t care for this command.

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the device to

reading array data. Once erasure begins, how-

ever, the device ignores reset commands until

the operation is complete.

Reading Array Data

The device is automatically set to reading array

data after device power-up. No commands are

required to retrieve data. The device is also

ready to read array data after completing an

Embedded Program or Embedded Erase algo-

rithm.

The reset command may be written between the

sequence cycles in a program command

sequence before programming begins. This

resets the device to reading array data (also

applies to programming in Erase Suspend

mode). Once programming begins, however, the

device ignores reset commands until the opera-

tion is complete.

After the device accepts an Erase Suspend com-

mand, the device enters the Erase Suspend

mode. The system can read array data using the

standard read timings, except that if it reads at

an address within erase-suspended sectors, the

device outputs status data. After completing a

programming operation in the Erase Suspend

mode, the system may once again read array

data with the same exception. See “Erase Sus-

pend/Erase Resume Commands” for more infor-

mation on this mode.

The reset command may be written between the

sequence cycles in an autoselect command

sequence. Once in the autoselect mode, the

reset command must be written to return to

reading array data (also applies to autoselect

during Erase Suspend).

The system must issue the reset command to

re-enable the device for reading array data if

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

17

P R E L I M I N A R Y

If DQ5 goes high during a program or erase

“Write Operation Status” for information on

these status bits.

operation, writing the reset command returns

the device to reading array data (also applies

during Erase Suspend).

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note

that a hardware reset immediately terminates

the programming operation. The program

command sequence should be reinitiated once

the device has reset to reading array data, to

ensure data integrity.

Autoselect Command Sequence

The autoselect command sequence allows the

host system to access the manufacturer and

devices codes, and determine whether or not a

sector is protected. Table 5 shows the address

and data requirements. This method is an alter-

native to that shown in Table 4, which is

intended for PROM programmers and requires

V_IDon address bit A9.

Programming is allowed in any sequence and

across sector boundaries. A bit cannot be pro-

grammed from a “0” back to a “1”.

Attempting to do so may halt the operation and

set DQ5 to “1”, or cause the Data# Polling algo-

rithm to indicate the operation was successful.

However, a succeeding read will show that the

data is still “0”. Only erase operations can

convert a “0” to a “1”.

The autoselect command sequence is initiated

by writing two unlock cycles, followed by the

autoselect command. The device then enters

the autoselect mode, and the system may read

at any address any number of times, without

initiating another command sequence.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to

program bytes or words to the device faster

than using the standard program command

sequence. The unlock bypass command

sequence is initiated by first writing two unlock

cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h.

The device then enters the unlock bypass mode.

A two-cycle unlock bypass program command

sequence is all that is required to program in

this mode. The first cycle in this sequence con-

tains the unlock bypass program command,

A0h; the second cycle contains the program

address and data. Additional data is pro-

grammed in the same manner. This mode dis-

penses with the initial two unlock cycles

required in the standard program command

sequence, resulting in faster total programming

time. Table 5 shows the requirements for the

command sequence.

A read cycle at address XX00h retrieves the

manufacturer code. A read cycle at address

XX01h in word mode (or 02h in byte mode)

returns the device code. A read cycle containing

a sector address (SA) and the address 02h in

word mode (or 04h in byte mode) returns 01h if

that sector is protected, or 00h if it is unpro-

tected. Refer to Tables 2 and 3 for valid sector

addresses.

The system must write the reset command to

exit the autoselect mode and return to reading

array data.

Word/Byte Program Command Sequence

The system may program the device by word or

byte, depending on the state of the BYTE# pin.

Programming is a four-bus-cycle operation. The

program command sequence is initiated by

writing two unlock write cycles, followed by the

program set-up command. The program

address and data are written next, which in turn

initiate the Embedded Program algorithm. The

system is not required to provide further con-

trols or timings. The device automatically pro-

vides internally generated program pulses and

verifies the programmed cell margin. Table 5

shows the address and data requirements for

the byte program command sequence.

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset com-

mands are valid. To exit the unlock bypass

mode, the system must issue the two-cycle

unlock bypass reset command sequence. The

first cycle must contain the data 90h; the

second cycle the data 00h. Addresses are don’t

care for both cycles. The device then returns to

reading array data.

When the Embedded Program algorithm is com-

plete, the device then returns to reading array

data and addresses are no longer latched. The

system can determine the status of the program

operation by using DQ7, DQ6, or RY/BY#. See

Figure 1 illustrates the algorithm for the

program operation. See the Erase/Program

Operations table in “AC Characteristics” for

parameters, and to Figure 1 for timing dia-

grams.

18

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

tion. The Chip Erase command sequence should

be reinitiated once the device has returned to

reading array data, to ensure data integrity.

START

The system can determine the status of the

erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. See “Write Operation Status” for infor-

mation on these status bits. When the

Embedded Erase algorithm is complete, the

device returns to reading array data and

addresses are no longer latched.

Write Program

Command Sequence

Data Poll

from System

Figure 1 illustrates the algorithm for the erase

operation. See the Erase/Program Operations

tables in “AC Characteristics” for parameters,

and to Figure 1 for timing diagrams.

Embedded

Program

algorithm

in progress

Verify Data?

Yes

Sector Erase Command Sequence

No

Sector erase is a six bus cycle operation. The

sector erase command sequence is initiated by

writing two unlock cycles, followed by a set-up

command. Two additional unlock write cycles

are then followed by the address of the sector to

be erased, and the sector erase command. Table

5 shows the address and data requirements for

the sector erase command sequence.

No

Increment Address

Last Address?

Yes

The device does not require the system to pre-

program the memory prior to erase. The

Embedded Erase algorithm automatically pro-

grams and verifies the sector for an all zero data

pattern prior to electrical erase. The system is

not required to provide any controls or timings

during these operations.

Programming

Completed

Note: See Table 5 for program command sequence.

After the command sequence is written, a sector

erase time-out of 50 µs begins. During the time-

out period, additional sector addresses and

sector erase commands may be written.

Loading the sector erase buffer may be done in

any sequence, and the number of sectors may

be from one sector to all sectors. The time

between these additional cycles must be less

than 50 µs, otherwise the last address and

command might not be accepted, and erasure

may begin. It is recommended that processor

interrupts be disabled during this time to ensure

all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase

command is written. If the time between addi-

tional sector erase commands can be assumed

to be less than 50 µs, the system need not

monitor DQ3. Any command other than

Sector Erase or Erase Suspend during the

time-out period resets the device to

reading array data. The system must rewrite

the command sequence and any additional

sector addresses and commands.

Figure 1. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip

erase command sequence is initiated by writing

two unlock cycles, followed by a set-up com-

mand. Two additional unlock write cycles are

then followed by the chip erase command,

which in turn invokes the Embedded Erase algo-

rithm. The device does not require the system

to preprogram prior to erase. The Embedded

Erase algorithm automatically preprograms and

verifies the entire memory for an all zero data

pattern prior to electrical erase. The system is

not required to provide any controls or timings

during these operations. Table 5 shows the

address and data requirements for the chip

erase command sequence.

Any commands written to the chip during the

Embedded Erase algorithm are ignored. Note

that a hardware reset during the chip erase

operation immediately terminates the opera-

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

19

P R E L I M I N A R Y

The system can monitor DQ3 to determine if the

When the Erase Suspend command is written

during a sector erase operation, the device

requires a maximum of 20 µs to suspend the

erase operation. However, when the Erase

Suspend command is written during the sector

erase time-out, the device immediately termi-

nates the time-out period and suspends the

erase operation.

sector erase timer has timed out. (See the

“DQ3: Sector Erase Timer” section.) The time-

out begins from the rising edge of the final WE#

pulse in the command sequence.

Once the sector erase operation has begun, only

the Erase Suspend command is valid. All other

commands are ignored. Note that a hardware

reset during the sector erase operation imme-

diately terminates the operation. The Sector

Erase command sequence should be reinitiated

once the device has returned to reading array

data, to ensure data integrity.

After the erase operation has been suspended,

the system can read array data from or program

data to any sector not selected for erasure. (The

device “erase suspends” all sectors selected for

erasure.) Normal read and write timings and

command definitions apply. Reading at any

address within erase-suspended sectors pro-

duces status data on DQ7–DQ0. The system can

use DQ7, or DQ6 and DQ2 together, to deter-

mine if a sector is actively erasing or is erase-

suspended. See “Write Operation Status” for

information on these status bits.

When the Embedded Erase algorithm is com-

plete, the device returns to reading array data

and addresses are no longer latched. The

system can determine the status of the erase

operation by using DQ7, DQ6, DQ2, or RY/BY#.

Refer to “Write Operation Status” for informa-

tion on these status bits.

After an erase-suspended program operation is

complete, the system can once again read array

data within non-suspended sectors. The system

can determine the status of the program opera-

tion using the DQ7 or DQ6 status bits, just as in

the standard program operation. See “Write

Operation Status” for more information.

Figure 1 illustrates the algorithm for the erase

operation. Refer to the Erase/Program Opera-

tions tables in the “AC Characteristics” section

for parameters, and to Figure 1 for timing dia-

grams.

Erase Suspend/Erase Resume Commands

The system may also write the autoselect

command sequence when the device is in the

Erase Suspend mode. The device allows reading

autoselect codes even at addresses within

erasing sectors, since the codes are not stored

in the memory array. When the device exits the

autoselect mode, the device reverts to the Erase

Suspend mode, and is ready for another valid

operation. See “Autoselect Command

Sequence” for more information.

The Erase Suspend command allows the system

to interrupt a sector erase operation and then

read data from, or program data to, any sector

not selected for erasure. This command is valid

only during the sector erase operation, including

the 50 µs time-out period during the sector

erase command sequence. The Erase Suspend

command is ignored if written during the chip

erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command

during the Sector Erase time-out immediately

terminates the time-out period and suspends

the erase operation. Addresses are

“don’t-cares” when writing the Erase Suspend

command.

The system must write the Erase Resume

command (address bits are “don’t care”) to exit

the erase suspend mode and continue the sector

erase operation. Further writes of the Resume

command are ignored. Another Erase Suspend

command can be written after the device has

resumed erasing.

20

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

START

Write Erase

Command Sequence

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 1. Erase Operation

Table 5. Am29LV800D Command Definitions

Bus Cycles (Notes 2-5)

Third Fourth

Addr Data Addr Data Addr Data Addr Data

Command

Sequence

(Note 1)

First

Second

Fifth

Sixth

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

RD

F0

XXX

555

AAA

555

AAA

555

AAA

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

AAA

555

AAA

555

AAA

Manufacturer ID

4

AA

55

90

X00

01

X01 22DA

X02 DA

X01 225B

Device ID,

Top Boot Block

Device ID,

Bottom Boot Block

X02

5B

XX00

XX01

00

(SA)

X02

Word

Byte

555

AAA

2AA

555

AAA

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

01

Word

Byte

Word

Byte

555

AAA

555

AAA

2AA

555

2AA

555

AAA

555

AAA

Program

Unlock Bypass

A0

20

PA

PD

3

2

AA

A0

90

55

PD

00

Unlock Bypass Program (Note

10)

XXX

PA

Unlock Bypass Reset (Note

11)

XXX

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

21

P R E L I M I N A R Y

Word

Byte

Word

Byte

555

AAA

555

AAA

XXX

2AA

555

2AA

555

AAA

555

AAA

555

AAA

555

AAA

2AA

555

2AA

555

AAA

Chip Erase

6

AA

55

80

AA

55

10

30

Sector Erase

SA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens

first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any

sector.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write operations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.

5. Address bits A18–A11 are don’t cares for unlock and command cycles, unless PA or SA required.

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5

goes high (while the device is providing status data).

8. The fourth cycle of the autoselect command sequence is a read cycle.

9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for

more information.

10.The Unlock Bypass command is required prior to the Unlock Bypass Program command.

11.The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock

bypass mode.

12.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during a sector erase operation.

13.The Erase Resume command is valid only during the Erase Suspend mode.

Write Operation Status

The device provides several bits to determine

the status of a write operation: DQ2, DQ3, DQ5,

DQ6, DQ7, and RY/BY#. Table 6 and the fol-

lowing subsections describe the functions of

these bits. DQ7, RY/BY#, and DQ6 each offer a

method for determining whether a program or

erase operation is complete or in progress.

These three bits are discussed first.

datum programmed to DQ7. This DQ7 status

also applies to programming during Erase Sus-

pend. When the Embedded Program algorithm

is complete, the device outputs the datum pro-

grammed to DQ7. The system must provide the

program address to read valid status informa-

tion on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active

for approximately 1 µs, then the device returns

to reading array data.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is

in Erase Suspend. Data# Polling is valid after

the rising edge of the final WE# pulse in the

program or erase command sequence.

During the Embedded Erase algorithm, Data#

Polling produces a “0” on DQ7. When the

Embedded Erase algorithm is complete, or if the

device enters the Erase Suspend mode, Data#

Polling produces a “1” on DQ7. This is analogous

to the complement/true datum output described

for the Embedded Program algorithm: the erase

function changes all the bits in a sector to “1”;

During the Embedded Program algorithm, the

device outputs on DQ7 the complement of the

22

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

prior to this, the device outputs the “comple-

ment,” or “0.” The system must provide an

address within any of the sectors selected for

erasure to read valid status information on DQ7.

START

After an erase command sequence is written, if

all sectors selected for erasing are protected,

Data# Polling on DQ7 is active for approxi-

mately 100 µs, then the device returns to

reading array data. If not all selected sectors are

protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the

selected sectors that are protected.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

When the system detects DQ7 has changed

from the complement to true data, it can read

valid data at DQ7–DQ0 on the following read

cycles. This is because DQ7 may change asyn-

chronously with DQ0–DQ6 while Output Enable

(OE#) is asserted low. Figure 1, Data# Polling

Timings (During Embedded Algorithms), in the

“AC Characteristics” section illustrates this.

No

DQ5 = 1?

Table 6 shows the outputs for Data# Polling on

DQ7. Figure 1 shows the Data# Polling algo-

rithm.

Yes

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a

sector erase operation, a valid address is an

address within any sector selected for erasure.

During chip erase, a valid address is any

non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” be-

cause DQ7 may change simultaneously with DQ5.

Figure 1. Data# Polling Algorithm

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output

pin that indicates whether an Embedded Algo-

rithm is in progress or complete. The RY/BY#

status is valid after the rising edge of the final

WE# pulse in the command sequence. Since

RY/BY# is an open-drain output, several

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

23

P R E L I M I N A R Y

RY/BY# pins can be tied together in parallel with

Table 6 shows the outputs for Toggle Bit I on

DQ6. Figure 1 shows the toggle bit algorithm.

Figure 1 in the “AC Characteristics” section

shows the toggle bit timing diagrams. Figure 1

shows the differences between DQ2 and DQ6 in

graphical form. See also the subsection on

“DQ2: Toggle Bit II”.

a pull-up resistor to V_CC.

If the output is low (Busy), the device is actively

erasing or programming. (This includes pro-

gramming in the Erase Suspend mode.) If the

output is high (Ready), the device is ready to

read array data (including during the Erase

Suspend mode), or is in the standby mode.

DQ2: Toggle Bit II

Table 6 shows the outputs for RY/BY#. Figures

1, 1, 1 and 1 shows RY/BY# for read, reset, pro-

gram, and erase operations, respectively.

The “Toggle Bit II” on DQ2, when used with

DQ6, indicates whether a particular sector is

actively erasing (that is, the Embedded Erase

algorithm is in progress), or whether that sector

is erase-suspended. Toggle Bit II is valid after

the rising edge of the final WE# pulse in the

command sequence.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an

Embedded Program or Erase algorithm is in

progress or complete, or whether the device has

entered the Erase Suspend mode. Toggle Bit I

may be read at any address, and is valid after

the rising edge of the final WE# pulse in the

command sequence (prior to the program or

erase operation), and during the sector erase

time-out.

DQ2 toggles when the system reads at

addresses within those sectors that have been

selected for erasure. (The system may use

either OE# or CE# to control the read cycles.)

But DQ2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. DQ6,

by comparison, indicates whether the device is

actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for

erasure. Thus, both status bits are required for

sector and mode information. Refer to Table 6 to

compare outputs for DQ2 and DQ6.

During an Embedded Program or Erase algo-

rithm operation, successive read cycles to any

address cause DQ6 to toggle. (The system may

use either OE# or CE# to control the read

cycles.) When the operation is complete, DQ6

stops toggling.

Figure 1 shows the toggle bit algorithm in flow-

chart form, and the section “DQ2: Toggle Bit II”

explains the algorithm. See also the “DQ6:

Toggle Bit I” subsection. Figure 1 shows the

toggle bit timing diagram. Figure 1 shows the

differences between DQ2 and DQ6 in graphical

form.

After an erase command sequence is written, if

all sectors selected for erasing are protected,

DQ6 toggles for approximately 100 µs, then

returns to reading array data. If not all selected

sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and

ignores the selected sectors that are protected.

Reading Toggle Bits DQ6/DQ2

The system can use DQ6 and DQ2 together to

determine whether a sector is actively erasing

or is erase-suspended. When the device is

actively erasing (that is, the Embedded Erase

algorithm is in progress), DQ6 toggles. When

the device enters the Erase Suspend mode, DQ6

stops toggling. However, the system must also

use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on “DQ7:

Data# Polling”).

Refer to Figure 1 for the following discussion.

Whenever the system initially begins reading

toggle bit status, it must read DQ7–DQ0 at least

twice in a row to determine whether a toggle bit

is toggling. Typically, the system would note and

store the value of the toggle bit after the first

read. After the second read, the system would

compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device

has completed the program or erase operation.

The system can read array data on DQ7–DQ0 on

the following read cycle.

If a program address falls within a protected

sector, DQ6 toggles for approximately 1 µs after

the program command sequence is written,

then returns to reading array data.

However, if after the initial two read cycles, the

system determines that the toggle bit is still

toggling, the system also should note whether

the value of DQ5 is high (see the section on

DQ5). If it is, the system should then determine

again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as

DQ6 also toggles during the erase-suspend-

program mode, and stops toggling once the

Embedded Program algorithm is complete.

24

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

DQ5 went high. If the toggle bit is no longer tog-

gling, the device has successfully completed the

program or erase operation. If it is still toggling,

the device did not completed the operation suc-

cessfully, and the system must write the reset

command to return to reading array data.

START

Read DQ7–DQ0

The remaining scenario is that the system ini-

tially determines that the toggle bit is toggling

and DQ5 has not gone high. The system may

continue to monitor the toggle bit and DQ5

through successive read cycles, determining the

status as described in the previous paragraph.

Alternatively, it may choose to perform other

system tasks. In this case, the system must

start at the beginning of the algorithm when it

returns to determine the status of the operation

(top of Figure 1).

(Note 1)

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

Yes

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase

time has exceeded a specified internal pulse

count limit. Under these conditions DQ5 pro-

duces a “1.” This is a failure condition that indi-

cates the program or erase cycle was not

successfully completed.

No

DQ5 = 1?

Yes

(Notes

1, 2)

Read DQ7–DQ0

Twice

The DQ5 failure condition may appear if the

system tries to program a “1” to a location that

is previously programmed to “0.” Only an

erase operation can change a “0” back to a

“1.” Under this condition, the device halts the

operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

Toggle Bit

= Toggle?

No

Under both these conditions, the system must

issue the reset command to return the device to

reading array data.

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

DQ3: Sector Erase Timer

After writing a sector erase command sequence,

the system may read DQ3 to determine whether

or not an erase operation has begun. (The

sector erase timer does not apply to the chip

erase command.) If additional sectors are

selected for erasure, the entire time-out also

applies after each additional sector erase com-

mand. When the time-out is complete, DQ3

switches from “0” to “1.” The system may

ignore DQ3 if the system can guarantee that

the time between additional sector erase com-

mands will always be less than 50 µs. See also

the “Sector Erase Command Sequence” section.

Notes:

1. Read toggle bit twice to determine whether or not

it is toggling. See text.

2. Recheck toggle bit because it may stop toggling

as DQ5 changes to “1”. See text.

Figure 1. Toggle Bit Algorithm

further commands (other than Erase Suspend)

are ignored until the erase operation is com-

plete. If DQ3 is “0”, the device will accept addi-

tional sector erase commands. To ensure the

command has been accepted, the system soft-

ware should check the status of DQ3 prior to

and following each subsequent sector erase

command. If DQ3 is high on the second status

check, the last command might not have been

accepted. Table 6 shows the outputs for DQ3.

After the sector erase command sequence is

written, the system should read the status on

DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to

ensure the device has accepted the command

sequence, and then read DQ3. If DQ3 is “1”, the

internally controlled erase cycle has begun; all

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

25

P R E L I M I N A R Y

Table 6. Write Operation Status

DQ7

(Note

2)

DQ5

(Note 1)

DQ2

(Note 2)

RY/BY

#

Operation

DQ6

Toggle

DQ3

N/A

1

Embedded Program

Algorithm

DQ7#

0

No toggle

Toggle

0

1

Standard

Mode

Embedded Erase Algorithm

0

1

Toggle

Reading within Erase

Suspended Sector

No toggle

N/A

Toggle

Erase

Suspend

Mode

Reading within Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum

timing limits. See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection

for further details.

26

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

V_CC(Note 1). . . . . . . . . . . . . . . . –0.5 V to +4.0 V

ABSOLUTE MAXIMUM RATINGS

A9, OE#, and

Storage Temperature

RESET# (Note 2) . . . . . . . . . . . –0.5 V to +12.5 V

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

All other pins (Note 1). . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . . 200 mA

Notes:

Ambient Temperature

with Power Applied . . . . . . . . . . . . . . –65°C to +85°C

Voltage with Respect to Ground

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may

undershoot V to –2.0 V for periods of up to 20 ns. See Figure 2. Maximum DC voltage on input or I/O pins

SS

is V +0.5 V. During voltage transitions, input or I/O pins may overshoot to V +2.0 V for periods up to 20

CC

ns. See Figure 3.

2. Minimum DC input voltage on pins A9, OE#, and

RESET# is –0.5 V. During voltage transitions, A9,

OE#, and RESET# may undershoot V_SSto –2.0 V for

periods of up to 20 ns. See Figure 2. Maximum DC

input voltage on pin A9 is +12.5 V which may

overshoot to 14.0 V for periods up to 20 ns.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

3. No more than one output may be shorted to ground

at a time. Duration of the short circuit should not be

greater than one second.

Ambient Temperature (T_A) . . . . . . . . .–40°C to +85°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

V

Supply Voltages

CC

V_CCfor regulated voltage range . . . . +3.0 V to +3.6 V

V_CCfor full voltage range . . . . . . . . . +2.7 V to +3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed

20 ns

+0.8 V

V

CC

+2.0 V

–0.5 V

–2.0 V

V

CC

+0.5 V

2.0 V

20 ns

Figure 2. Maximum Negative Overshoot

Waveform

Figure 3. Maximum Positive Overshoot

Waveform

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

27

P R E L I M I N A R Y

DC Characteristics

CMOS Compatible

Paramete

r

Description

Test Conditions

Min

Typ

Max

1.0

35

Unit

µA

V

= V to V

,

IN

SS

CC

I

Input Load Current

LI

= V

CC

CC max

I

A9 Input Load Current

Output Leakage Current

V

= V

; A9 = 12.5 V

µA

LIT

CC

CC max

V

= V to V

,

OUT

SS

CC

I

1.0

µA

LO

= V

CC

CC max

CE# = V OE#

5 MHz

1 MHz

5 MHz

1 MHz

7

2

7

2

15

4

IL,

=

V

IH,

Byte Mode

V

Active Read Current

CC

I

mA

CC1

(Notes 1, 2)

CE# = V OE#

15

4

IL,

=

V

IH,

Word Mode

V

Active Write Current

CC

CE# = V OE#

V

15

30

CC2

IL,

IH

(Notes 2, 3, 5)

V

2)

Standby Current (Note

CC

I

CE#, RESET# = V

0.3 V

CC

0.2

5

µA

CC3

CC4

CC5

V

Reset Current (Note 2) RESET# = V

0.3 V

CC

SS

Automatic Sleep Mode

(Notes 2, 4)

V

= V

0.3 V;

0.3 V

IH

IL

CC

SS

5

V

Input Low Voltage

Input High Voltage

–0.5

0.8

V

IL

V

0.7 x V

V

+ 0.3

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 3.3 V

11.5

12.5

0.45

V

ID

CC

V

Output Low Voltage

I

= 4.0 mA, V

= V

V

OL

CC

CC min

V

= –2.0 mA, V = V

0.85 V

OH1

OH2

OH

CC

CC min

CC

Output High Voltage

= –100 µA, V = V

V

–0.4

CC

CC min

CC

Low V Lock-Out Voltage

(Note 4)

CC

V

2.3

2.5

V

LKO

Notes:

1. The I

current listed is typically less than 2 mA/MHz, with OE# at V . Typical V

is 3.0 V.

CC

IH

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax

.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns.

5. Not 100% tested.

28

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

DC Characteristics (Continued)

Zero Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 1. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

10

8

3.6 V

6

2.7 V

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 1. Typical I_CC1vs. Frequency

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

29

P R E L I M I N A R Y

Te st Cond iti on s

Table 7. Test Specifications

-90,

3.3

Test Condition

-70

-120

Unit

2.7 kΩ

Device

Under

Test

Output Load

1 TTL gate

Output Load Capacitance,

C

30

100

pF

L

C

6.2 kΩ

L

(including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

0.0–3.0

Input timing

measurement reference

levels

Note: Diodes are IN3064 or

1.5

V

Figure 1. Test Setup

Output timing

measurement reference

levels

1.5

Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 1. Input Waveforms and

Measurement Levels

30

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

AC Characteristics

Read Operations

Parameter

Speed Options

-70 -90 -120 Unit

70

JEDEC

Std

Description

Test Setup

Min

t

Read Cycle Time (Note 1)

Address to Output Delay

90

120

ns

AVAV

RC

CE# = V

IL

t

Max

70

AVQV

ACC

OE# = V

t

Chip Enable to Output Delay

OE# = V

Max

Min

70

30

25

90

35

30

0

120

50

ns

ELQV

GLQV

EHQZ

GHQZ

CE

IL

t

Output Enable to Output Delay

OE

t

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

30

DF

t

30

Read

Output Enable

Hold Time (Note 1)

t

OEH

Toggle and

Data# Polling

Min

10

0

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1)

t

OH

AXQX

Notes:

1. Not 100% tested.

2. See Figure 1 and Table 7 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 1. Read Operations Timings

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

31

P R E L I M I N A R Y

AC Characteristics

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

Max

All Speed Options

Unit

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

t

20

µs

READY

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

Max

Min

500

50

ns

READY

t

RESET# Pulse Width

RP

RESET# High Time Before Read (See

Note)

t

RH

t

RESET# Low to Standby Mode

RY/BY# Recovery Time

Min

20

0

µs

ns

RPD

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 1. RESET# Timings

32

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

AC Characteristics

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

Description

-70

-90

-120

Unit

t

CE# to BYTE# Switching Low or High

Max

5

ns

ELFL/ ELFH

BYTE# Switching Low to Output HIGH

Z

25

70

30

90

30

ns

FLQZ

FHQV

BYTE# Switching High to Output

Active

t

Min

120

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

33

P R E L I M I N A R Y

CE#

OE#

BYTE#

t

ELFL

Data Output

(DQ0–DQ14)

Data

BYTE#

Switching

from word

to byte

DQ0–DQ14

DQ15/A-1

Output

Address

Input

DQ15

Output

mode

t

FLQ

t

ELFH

BYTE#

Switching

from byte

to word

Data

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

Output

mode

Address

Input

DQ15

Output

t

FHQ

Figure 1. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE#

WE#

BYTE#

t

SET

(t

)

AS

t

HOLD

Note: Refer to the Erase/Program Operations table for t and t specifications.

AS

AH

Figure 1. BYTE# Timings for Write Operations

34

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

AC Characteristics

Erase/Program Operations

Parameter

Speed Options

JEDEC

Std

Description

-70

-90

90

0

-120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

120

AVAV

AVWL

WLAX

WC

t

ns

AS

AH

DS

DH

t

45

35

45

0

50

ns

t

ns

DVWH

WHDX

t

Data Hold Time

ns

t

Output Enable Setup Time

0

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHWL

t

CE# Setup Time

CE# Hold Time

Min

Typ

Min

0

ns

ELWL

WHEH

WLWH

WHWL

CS

CH

WP

t

Write Pulse Width

Write Pulse Width High

35

30

8

50

t

WPH

Byte

t

Programming Operation (Note 2)

Sector Erase Operation (Note 2)

µs

WHWH1

WHWH2

WHWH1

Word

16

1

sec

µs

WHWH2

t

V

Setup Time (Note 1)

50

0

VCS

CC

t

Recovery Time from RY/BY#

ns

RB

t

Program/Erase Valid to RY/BY# Delay

90

ns

BUSY

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

35

P R E L I M I N A R Y

AC Characteristics

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

Data

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. Illustration shows device in word mode.

Figure 1. Program Operation Timings

36

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

AC Characteristics

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation

Status”).

2. Illustration shows device in word mode.

Figure 1. Chip/Sector Erase Operation Timings

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

37

P R E L I M I N A R Y

AC Characteristics

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

t_OEH

WE#

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

Status Data

True

DQ0–DQ6

Valid Data

Status Data

True

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 1. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

VA

t_ACC

t_CE

VA

CE#

t_CH

t_OE

OE#

t_OEH

t_DF

t_OH

WE#

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 1. Toggle Bit Timings (During Embedded Algorithms)

38

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

AC Characteristics

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 1. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t

V

Rise and Fall Time (See Note)

Min

500

ns

VIDR

ID

RESET# Setup Time for Temporary

Sector Unprotect

t

4

µs

RSP

Note: Not 100% tested.

12 V

RESET#

0 or 3 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 1. Temporary Sector Unprotect

Timing Diagram

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

39

P R E L I M I N A R Y

AC Characteristics

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 1. Sector Protect/Unprotect

Timing Diagram

40

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

AC Characteristics

Alternate CE# Controlled

Erase/Program Operations

Parameter

Speed Options

JEDEC

Std

Description

-70

-90

90

0

-120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

120

AVAV

WC

t

ns

AVEL

AS

AH

DS

DH

t

45

35

45

0

50

ns

ELAX

t

ns

DVEH

EHDX

t

Data Hold Time

ns

t

Output Enable Setup Time

0

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHEL

t

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

WLEL

WS

t

EHWH

WH

t

CE# Pulse Width

CE# Pulse Width High

35

30

8

50

ELEH

EHEL

CP

t

CPH

Byte

Word

Programming Operation

(Note 2)

t

µs

WHWH1

16

1

Sector Erase Operation (Note 2)

sec

WHWH2

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance”

section for more information.

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

41

P R E L I M I N A R Y

AC Characteristics

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

Data

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D

data written to the device.

=

OUT

2. Figure indicates the last two bus cycles of command

sequence.

3. Word mode address used as an example.

Figure 1. Alternate CE# Controlled Write Operation Timings

42

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

Erase and Programming Performance

Typ (Note

1)

Parameter

Max (Note 2)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

1

14

8

10

Excludes 00h programming

prior to erasure

s

Byte Programming Time

Word Programming Time

300

360

25

µs

s

16

8.4

Excludes system level

overhead (Note 5)

Chip Programming

Time

Byte Mode

Word Mode

5.8

17

s

(Note 3)

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles.

CC

Additionally, programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most

bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See Table 5 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

Latchup Characteristics

Description

Min

Max

Input voltage with respect to V on all pins except I/O pins

(including A9, OE#, and RESET#)

SS

–1.0 V

12.5 V

Input voltage with respect to V on all I/O pins

–1.0 V

V

+ 1.0 V

CC

SS

V

Current

–100 mA

+100 mA

CC

Includes all pins except V . Test conditions: V

=

CC

3.0 V, one pin at a time.

TSOP and SO Pin Capacitance

Parameter

Symbol

Parameter Description

Test Setup

Typ

6

Max

7.5

12

Unit

pF

C

Input Capacitance

Output Capacitance

Control Pin Capacitance

V

= 0

IN

C

V

8.5

7.5

pF

OUT

C

V

9

pF

IN2

IN

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

Data Retention

Test

Parameter

Conditions

Min

10

Unit

150°C

Years

Minimum Pattern Data Retention Time

125°C

20

43

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

Physical Dimensions*

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for

Basic Space Centering.

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

44

P R E L I M I N A R Y

Physical Dimensions

TSR048—48-Pin Reverse TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for

Basic Space Centering.

45

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

Physical Dimensions

FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm

Dwg rev AF; 10/99

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

46

P R E L I M I N A R Y

Physical Dimensions

VBK 048 - 48 Ball Fine-Pitch Ball Grid Array (FBGA) 6.15 x 8.15 mm

0.10 (4X)

D1

A

D

6

5

4

3

2

1

7

e

SE

E1

E

H

G

F

E

D

C

B

A

INDEX MARK

10

6

B

A1 CORNER

PIN A1

CORNER

7

fb

SD

f 0.08 M

C

TOP VIEW

f 0.15 M C A B

BOTTOM VIEW

0.10 C

0.08 C

A2

A

SEATING PLANE

SIDE VIEW

C

A1

NOTES:

PACKAGE

JEDEC

VBK 048

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

6.15 mm x 8.15 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

---

NOM

MAX

1.00 OVERALL THICKNESS

--- BALL HEIGHT

NOTE

4.

e

REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

---

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.18

0.62

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

---

0.76 BODY THICKNESS

BODY SIZE

8.15 BSC.

6.15 BSC.

5.60 BSC.

4.00 BSC.

8

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

MD

ME

N

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

6

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

48

fb

0.33

---

0.43 BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

0.80 BSC.

0.40 BSC.

---

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3338 \ 16-038.25b

47

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

Physical Dimensions

SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/99

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

48

P R E L I M I N A R Y

Global

Revision Summary

Converted datasheet to Preliminary.

Revision A (January 19, 2004)

Ordering Information

Changed data sheet status to Advance Informa-

tion to indicate new 0.23 µm process tech-

nology. The base device part number has

changed from Am29LV800B to Am29LV800D.

Specifications for I_CC1, t_WHWH1, t_WHWH2have

changed. Extended temperature is no longer

available. All other specifications in the data

sheet remain unchanged. Deleted references to

KGD option in Connection Diagrams section.

(This document was formerly released as publi-

cation 21490, revision H.)

Added Pb-Free packages and updated Valid

Combinations tables to include changes.

Absolute Maximum Rating

Changed ambient with power applied from

125°C to 85°C.

Revision A+3 (June 23, 2004)

Global change

Changed all Helvetica/Times Roman fonts to Gill

Sans For AMD or Verdana.

Revision A+1 (February 3, 2004)

“Physical Dimensions” on page 47

Distinctive Characteristics, General Description,

Ordering Information

Added VBK048 Package Drawing.

“Ordering Information” on page 8

Deleted references to KGD option. (This docu-

ment was formerly released as publication

21490, revision H1.)

Added “WC =...” to Standard Products table.

Added “WCC, WCI, WCD, WCF” to Valid combi-

nations table.

Revision A+2 (April 2, 2004)

General Description

Added Colophon.

Removed unlock bypass section.

Revision A+4 (January 21, 2005)

Added migration statement.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that FASL will not be liable to you

and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices

have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures

into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating condi-

tions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Ex-

change and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior

authorization by the respective government entity will be required for export of those products.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

49

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005


型号：	AM29LV800DT-90WCI
厂家：	AMD
描述：	8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory 8兆位（ 1一M× 8位/ 512的K× 16位） CMOS 3.0伏只引导扇区闪存闪存内存集成电路
文件：	总51页 (文件大小：1726K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV800DT-90WCI [AMD]

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