AM29LV652DU35MAI [AMD]
128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO⑩ Control; 128兆位（ 16一M× 8位） CMOS 3.0伏只统一部门快闪记忆体与VersatileIO⑩控制
| 型号： | AM29LV652DU35MAI |
| 厂家： | 
AMD |
| 描述： | 128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO⑩ Control |
| 文件： | 总54页 (文件大小：1000K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am29LV652D
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new designs, S29GL128N
supersedes Am29LV652D. Please refer to the S29GL-N family data sheet for specifications and
ordering information. Availability of this document is retained for reference and historical purposes
only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 24961 Revision E Amendment 5 Issue Date May 5, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29LV652D
128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileIO™ Control
This product has been retired and is not recommended for designs. For new designs, S29GL128N supersedes Am29LV652D. Please refer to the S29GL-N family data sheet for specifica-
tions and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■
Two 64 Megabit (Am29LV065D) in a single 63-ball 11
x 12 mm FBGA package (Note: Features will be
described for each internal Am29LV065D)
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
■
Two Chip Enable inputs
— Each CE# controls selection of one internal
Am29LV065D device
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
■
■
Single power supply operation
■
■
Compatibility with JEDEC standards
— 3.0 to 3.6 volt read, erase, and program operations
— Except for the added CE2#, the FBGA is pinout and
software compatible with single-power supply Flash
VersatileIO™ control
— Device generates output voltages and tolerates input
voltages on DQ I/Os as determined by the voltage on
— Superior inadvertent write protection
Minimum 1 million erase cycle guarantee per sector
V
IO input
■
■
63-ball FBGA Package
■
High performance
Erase Suspend/Erase Resume
— Access times as fast as 90 ns
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
■
■
Manufactured on 0.23 µm process technology
CFI (Common Flash Interface) compliant
■
■
■
■
■
■
Data# Polling and toggle bits
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
— Provides a software method of detecting program or
erase operation completion
■
Ultra low power consumption (typical values at 3.0 V,
5 MHz) for the part
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
— 9 mA typical active read current
— 26 mA typical erase/program current
— 400 nA typical standby mode current
Ready/Busy# output (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
■
■
Flexible sector architecture
— Two hundred fifty-six 64 Kbyte sectors
Hardware reset input (RESET#)
— Hardware method to reset the device for reading array
data
Sector Protection
— A hardware method to lock a sector to prevent
program or erase operations within that sector
ACC input
— Sectors can be locked in-system or via programming
equipment
— Accelerates programming time for higher throughput
during system production
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Program and Erase Performance (VHH not applied to
the ACC input)
— Byte program time: 5 µs typical
— Sector erase time: 1.6 s typical for each 64 Kbyte
sector
■
20-year data retention at 125°C
— Reliable operation for the life of the system
Publication# 24961 Rev: A Amendment: 5
Issue Date: May 5, 2006
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Refer to AMD’s Website (www.amd.com) for the latest information.
D A T A S H E E T
GENERAL DESCRIPTION
The Am29LV652D is a 128 Mbit, 3.0 Volt (3.0 V to 3.6
V) single power supply flash memory device organized
as two Am29LV065D dice in a single 63-ball FBGA
package. Each Am29LV065D is a 64 Mbit, 3.0 Volt (3.0
V to 3.6 V) single power supply flash memory device
organized as 8,388,608 bytes. Data appears on
DQ0-DQ7. The device is designed to be programmed
in-system with the standard system 3.0 volt VCC sup-
ply. A 12.0 volt VPP is not required for program or erase
operations. The Am29LV652D is equipped with two
CE#s for flexible selection between the two internal 64
Mb devices. The device can also be programmed in
standard EPROM programmers.
at its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on
VIO. This allows the device to operate in a 3 V or 5 V
system environment as required. For voltage levels
below 3 V, contact an AMD representative for more in-
formation.
The host system can detect whether a program or
erase operation is complete by observing RY/BY#, by
reading the DQ7 (Data# Polling), or DQ6 (toggle) sta-
tus bits. After a program or erase cycle is completed,
the device is ready to read array data or accept an-
other command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
The Am29LV652D offers access times of 90 and 120
ns and is offered in a 63-ball FBGA package. To elimi-
nate bus contention the Am29LV652D device contains
two separate chip enables (CE# and CE2#). Each chip
enable (CE# or CE2#) is connected to only one of the
two dice in the Am29LV652D package. To the sys-
tem, this device is the same as two independent
Am29LV065D on the same board. The only differ-
ence is that they are now packaged together to re-
duce board space.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
Each device requires only a single 3.0 Volt power
supply (3.0 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The hardware RESET# terminates any operation in
progress and resets the internal state machine to
reading array data. RESET# may be tied to the system
reset circuitry. A system reset would thus also reset
the device, enabling the system microprocessor to
read boot-up firmware from the Flash memory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to VHH, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
The VersatileI/O™ (VIO) control allows the host sys-
tem to set the voltage levels that the device generates
2
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29LV652D Device Bus Operations ................................9
VersatileIO™ (VIO) Control ....................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences ............................ 10
Accelerated Program Operation .......................................... 10
Autoselect Functions ........................................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table for CE# ..........................................11
Table 3. Sector Address Table for CE2# ........................................15
Autoselect Mode ..................................................................... 19
Table 4. Am29LV652D Autoselect Codes, (High Voltage Method) 19
Sector Group Protection and Unprotection ............................. 20
Table 5. Sector Group Protection/Unprotection Address Table .....20
Temporary Sector Group Unprotect ....................................... 21
Figure 1. Temporary Sector Group Unprotect Operation................ 21
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 22
Hardware Data Protection ...................................................... 23
Low VCC Write Inhibit ......................................................... 23
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Common Flash Memory Interface (CFI). . . . . . . 23
Table 6. CFI Query Identification String.......................................... 23
System Interface String................................................................... 24
Table 8. Device Geometry Definition .............................................. 24
Table 9. Primary Vendor-Specific Extended Query ........................ 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................ 25
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Byte Program Command Sequence ....................................... 26
Unlock Bypass Command Sequence .................................. 26
Figure 3. Program Operation .......................................................... 27
Chip Erase Command Sequence ........................................... 27
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 28
Figure 4. Erase Operation............................................................... 29
Table 10. Am29LV652D Command Definitions ..............................30
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ................................................................. 31
Figure 5. Data# Polling Algorithm .................................................. 31
RY/BY#: Ready/Busy# ............................................................ 32
DQ6: Toggle Bit I .................................................................... 32
Figure 6. Toggle Bit Algorithm........................................................ 32
DQ2: Toggle Bit II ................................................................... 33
Reading Toggle Bits DQ6/DQ2 ............................................... 33
DQ5: Exceeded Timing Limits ................................................ 33
DQ3: Sector Erase Timer ....................................................... 33
Table 11. Write Operation Status ................................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 7. Maximum Negative Overshoot Waveform ..................... 35
Figure 8. Maximum Positive Overshoot Waveform....................... 35
DC Characteristics
(for two Am29LV065 devices) . . . . . . . . . . . . . . . 36
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents)............................................................. 37
Figure 10. Typical ICC1 vs. Frequency............................................ 37
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. Test Setup.................................................................... 38
Table 12. Test Specifications ......................................................... 38
Figure 12. Input Waveforms and Measurement Levels ................. 38
Key to Switching Waveforms. . . . . . . . . . . . . . . . 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Read-Only Operations ........................................................... 39
Figure 13. Read Operation Timings............................................... 39
Hardware Reset (RESET#) .................................................... 40
Figure 14. Reset Timings............................................................... 40
Erase and Program Operations .............................................. 41
Figure 15. Program Operation Timings.......................................... 42
Figure 16. Accelerated Program Timing Diagram.......................... 42
Figure 17. Chip/Sector Erase Operation Timings .......................... 43
Figure 18. Data# Polling Timings (During Embedded Algorithms). 44
Figure 19. Toggle Bit Timings (During Embedded Algorithms)...... 45
Figure 20. DQ2 vs. DQ6................................................................. 45
Temporary Sector Unprotect .................................................. 46
Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 46
Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 47
Figure 23. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 49
Erase And Programming Performance . . . . . . . 50
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 50
Input/Output Capacitance . . . . . . . . . . . . . . . . . . 50
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51
FSA063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 11 x 12 mm
package .................................................................................. 51
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52
May 5, 2006 24961A5
Am29LV652D
3
D A T A S H E E T
PRODUCT SELECTOR GUIDE
Part Number
Am29LV652D
90R
Speed Option
Regulated Voltage Range: VCC = 3.0–3.6 V
12R
120
120
50
Max Access Time (ns)
CE# Access Time (ns)
OE# Access Time (ns)
90
90
35
Note: See “AC Characteristics” on page 39 for full specifications.
4
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
BLOCK DIAGRAM
VCC
Sector Switches
VSS
RY/BY#
VIO
Erase Voltage
Generator
Input/Output
Buffers
DQ0–DQ7
RESET#
WE#
State
Control
ACC
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
X-Decoder
Y-Gating
STB
VCC Detector
A0–A22
Timer
Cell Matrix
Sector Switches
RY/BY#
VIO
Erase Voltage
Generator
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#2
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A0–A22
May 5, 2006 24961A5
Am29LV652D
5
D A T A S H E E T
CONNECTION DIAGRAM
63-Ball FBGA
Top View, Balls Facing
Down
L8
M8
A8
B8
NC*
NC*
NC*
NC*
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
A7
B7
A14
A13
A15
A16
A17
NC
A20
V
SS
NC*
NC*
NC*
NC*
C6
A9
D6
A8
E6
F6
G6
H6
J6
K6
A11
A12
A19
A10
DQ6
DQ7
C5
D5
E5
F5
G5
H5
J5
K5
WE# RESET# A22
NC
DQ5
NC
V
DQ4
CC
C4
D4
E4
F4
G4
H4
J4
K4
RY/BY# ACC
NC
NC
DQ2
DQ3
V
A21
IO
C3
A7
D3
E3
A6
F3
A5
G3
H3
J3
K3
A18
DQ0
NC
CE2#
DQ1
A2
L2
M2
C2
A3
D2
A4
E2
A2
F2
A1
G2
A0
H2
J2
K2
NC*
CE#
OE#
V
NC*
NC*
SS
A1
B1
L1
M1
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
NC*
NC*
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
Special Handling Instructions for FBGA
Package
Special handling is required for Flash Memory products
in FBGA packages.
6
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
PIN DESCRIPTION
LOGIC SYMBOL
A0–A22
= 23 Addresses inputs
23
DQ0–DQ7 = 8 Data inputs/outputs
A0–A22
8
CE#
= Chip Enable input
DQ0–DQ7
CE#
CE2#
OE#
= Chip Enable input for second die
= Output Enable input
= Write Enable input
CE2#
OE#
WE#
WE#
ACC
RESET#
VIO
ACC
= Acceleration Input
RESET#
RY/BY#
VCC
= Hardware Reset Pin input
= Ready/Busy output
RY/BY#
= 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VIO
VSS
NC
= Output Buffer power
= Device Ground
= Pin Not Connected Internally
May 5, 2006 24961A5
Am29LV652D
7
D A T A S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29LV652D
U
90R
MA
I
TEMPERATURE RANGE
I
=
=
=
=
Industrial (–40°C to +85°C)
E
F
K
Extended (–55°C to +125°C)
Industrial (-40oC to +85oC) with Pb-free Package
Extended (-55oC to +125oC) with Pb-free Package
PACKAGE TYPE
MA
=
63-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 11 x 12 mm package (FSA063)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE
U
=
Uniform sector device
DEVICE NUMBER/DESCRIPTION
Am29LV652D
128 Megabit (2 x 8 M x 8-Bit) CMOS Uniform Sector Flash Memory with VersatileIO™ Control
3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations for FBGA Packages
Package
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Speed/
VIO Range
Order Number
Marking
MAF,
MAI
F,
I
90 ns, VIO
3.0 V – 5.0 V
=
Am29LV652DU90R
L652DU90R
I,
E,
MAI,
MAE
MAF,
MAK
120 ns, VIO
3.0 V – 5.0 V
=
Am29LV652DU12R
L652DU12R
F,
K
8
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV652D Device Bus Operations
CE#
Addresses
Operation
(Note 1)
OE#
L
WE#
H
RESET#
ACC
X
(Note 2)
DQ0–DQ7
DOUT
Read
L
H
AIN
AIN
AIN
X
Write (Program/Erase)
Accelerated Program
Standby
L
H
L
H
X
(Note 3)
(Note 3)
High-Z
High-Z
High-Z
L
H
L
H
VHH
H
VCC ± 0.3 V
X
X
VCC ± 0.3 V
Output Disable
Reset
L
H
H
H
L
X
X
X
X
X
X
X
SA, A6 = L,
A1 = H, A0 = L
Sector Group Protect (Note 4)
L
L
H
H
X
L
L
VID
VID
VID
X
X
X
(Note 3)
(Note 3)
(Note 3)
Sector Group Unprotect
(Note 4)
SA, A6 = H,
A1 = H, A0 = L
Temporary Sector Group
Unprotect
X
X
AIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at
the same time.
2. Addresses are A22:A0. Sector addresses are A22:A16.
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
5. All sectors are unprotected when shipped from the factory.
VersatileIO™ (VIO) Control
Requirements for Reading Array Data
The VersatileIO (VIO) control allows the host system to
set the voltage levels that the device generates at its
data outputs and the voltages tolerated at its data in-
puts to the same voltage level that is asserted on VIO.
This allows the device to operate in a 3 V or 5 V sys-
tem environment as required. For voltage levels below
3 V, contact an AMD representative for more informa-
tion.
To read array data from the outputs, the system must
drive CE# or CE2# and OE# to VIL. CE# or CE2# is the
power control and selects the device. OE# is the out-
put control and gates array data to the outputs. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
For example, a VI/O of 4.5–5.0 volts allows for I/O at
the 5 volt level, driving and receiving signals to and
from other 5 V devices on the same data bus.
May 5, 2006 24961A5
Am29LV652D
9
D A T A S H E E T
enabled for read access until the command register
contents are altered.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
See “VersatileIO‰ (VIO) Control” for more informa-
tion. Refer to the AC “Read-Only Operations” on
page 39 table for timing specifications and to Figure
13, on page 39 for the timing diagram. ICC1 in the DC
Characteristics table represents the active current
specification for reading array data.
The device enters the CMOS standby mode when the
CE#, CE2#, and RESET# are all held at VCC 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE#, CE2#, and RESET# are held at VIH, but
not within VCC 0.3 V, the device is in the standby
mode, but the standby current is greater. The device
requires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# (or CE2#) to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” on page 26 section
contains details on programming data to the device
using both standard and Unlock Bypass command se-
quences.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics (for two Am29LV065 de-
vices) table represents the standby current specifica-
tion.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2, on page 11 indicates
the address space that each sector occupies.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
ICC2 in the DC Characteristics table represents the ac-
this mode when addresses remain stable for tACC +
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
30 ns. The automatic sleep mode is independent of
the CE#, CE2#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Accelerated Program Operation
I
CC4 in the DC Characteristics (for two Am29LV065 de-
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
vices) table represents the automatic sleep mode cur-
rent specification.
RESET#: Hardware Reset Pin
If the system asserts VHH on ACC, the device automat-
ically enters the aforementioned Unlock Bypass mode,
temporarily unprotects any protected sectors, and
uses the higher voltage to reduce the time required for
program operations. The system would use a two-cy-
cle program command sequence as required by the
Unlock Bypass mode. Removing VHH from ACC re-
turns the device to normal operation. Note that ACC
must not be at VHH for operations other than acceler-
ated programming, or device damage may result.
RESET# provides a hardware method of resetting the
device to reading array data. When RESET# is driven
low for at least a period of tRP, the device immediately
terminates any operation in progress, tristates all out-
puts, and ignores all read/write commands for the du-
ration of the RESET# pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated
once the device is ready to accept another command
sequence, to ensure data integrity.
Autoselect Functions
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS 0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL, but not within VSS 0.3 V, the standby current is
greater.
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the “Autoselect Mode” on page 19
and “Autoselect Command Sequence” on page 26
sections for more information.
RESET# may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
10
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
enabling the system to read the boot-up firmware from
the Flash memory.
of tREADY (not during Embedded Algorithms). The sys-
tem can read data tRH after RESET# returns to VIH.
If RESET# is asserted during a program or erase op-
eration, RY/BY# remains a “0” (busy) until the internal
reset operation is complete, which requires a time of
Refer to the “AC Characteristics” on page 39 tables for
RESET# parameters and to Figure 14, on page 40 for
the timing diagram.
t
READY (during Embedded Algorithms). The system can
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The outputs are placed in the high
impedance state.
thus monitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is not executing (RY/BY#
is “1”), the reset operation is completed within a time
Table 2. Sector Address Table for CE# (Sheet 1 of 4)
8-bit Address Range
(in hexadecimal)
Sector
SA0
A22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
May 5, 2006 24961A5
Am29LV652D
11
D A T A S H E E T
Table 2. Sector Address Table for CE# (Sheet 2 of 4)
8-bit Address Range
(in hexadecimal)
Sector
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
A22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A21
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A20
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
A18
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
A17
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A16
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
12
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
Table 2. Sector Address Table for CE# (Sheet 3 of 4)
8-bit Address Range
(in hexadecimal)
Sector
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
A22
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A21
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
A20
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
A19
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
A18
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
A17
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
May 5, 2006 24961A5
Am29LV652D
13
D A T A S H E E T
Table 2. Sector Address Table for CE# (Sheet 4 of 4)
8-bit Address Range
(in hexadecimal)
Sector
SA97
A22
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A21
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
650000–65FFFF
660000–66FFFF
670000–67FFFF
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
Note: All sectors are 64 Kbytes in size.
14
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
Table 3. Sector Address Table for CE2# (Sheet 1 of 4)
8-bit Address Range
(in hexadecimal)
Sector
SA0
A22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
May 5, 2006 24961A5
Am29LV652D
15
D A T A S H E E T
Table 3. Sector Address Table for CE2# (Sheet 2 of 4)
8-bit Address Range
(in hexadecimal)
Sector
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
A22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
A21
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
A19
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
A18
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
A17
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
16
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
Table 3. Sector Address Table for CE2# (Sheet 3 of 4)
8-bit Address Range
(in hexadecimal)
Sector
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
A22
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A20
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
A19
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
A18
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
650000–65FFFF
660000–66FFFF
670000–67FFFF
May 5, 2006 24961A5
Am29LV652D
17
D A T A S H E E T
Table 3. Sector Address Table for CE2# (Sheet 4 of 4)
8-bit Address Range
(in hexadecimal)
Sector
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
A22
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A21
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A20
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
Note: All sectors are 64 Kbytes in size.
18
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
protection, the sector address must appear on the ap-
Autoselect Mode
propriate highest order address bits (see Table 2, on
page 11 and Table 3, on page 15). Table 4 shows the
remaining address bits that are don’t care. When all
necessary bits have been set as required, the pro-
gramming equipment may then read the correspond-
ing identifier code on DQ7–DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10, on page 30.
This method does not require VID. Refer to the “Au-
toselect Command Sequence” on page 26 section for
more information.
When using programming equipment, the autoselect
mode requires VID (8.5 V to 12.5 V) on address A9.
Addresses A6, A1, and A0 must be as shown in
Table 4, on page 19. In addition, when verifying sector
Table 4. Am29LV652D Autoselect Codes, (High Voltage Method)
A22
to
A15
to
A8
to
A5
to
Description
CE# OE# WE# A16
A10 A9 A7 A6 A2 A1 A0
DQ7 to DQ0
01h
Manufacturer ID: AMD
Device ID: Am29LV652D
L
L
L
L
H
H
X
X
X
X
VID
VID
X
X
L
L
X
X
L
L
L
H
93h
Sector Protection
Verification
01h (protected),
00h (unprotected)
L
L
H
SA
X
VID
X
L
X
H
L
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Notes:
1. CE# can be replaced with CE2# when referring to the second die in the package.
2. The device ID’s used for the Am29LV652 are the same as the Am29LV065, because the Am29LV652 uses two Am29LV065
dice and appears to the system as two Am29LV065 devices.
May 5, 2006 24961A5
Am29LV652D
19
D A T A S H E E T
Table 5. Sector Group Protection/Unprotection
Address Table
Sector Group Protection and
Unprotection
Sector Group
A22–A18
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Table 5). The hardware sector
group unprotection feature re-enables both program
and erase operations in previously protected sector
groups. Sector group protection/unprotection can be
implemented via two methods.
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
The primary method requires VID on RESET# only,
and can be implemented either in-system or via pro-
gramming equipment. Figure 2, on page 22 shows the
algorithms and Figure 22, on page 47 shows the tim-
ing diagram. This method uses standard microproces-
sor bus cycle timing. For sector group unprotect, all
unprotected sector groups must first be protected prior
to the first sector group unprotect write cycle.
Some earlier 3.0 volt-only AMD flash devices used a
sector protection/unprotection method intended only
for programming equipment, and required VID on ad-
dress A9 and OE#. If this earlier method is required for
the intended application, contact AMD for further de-
tails.
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and pro-
tecting sector groups at its factory prior to shipping the
device through AMD’s ExpressFlash™ Service. Con-
tact an AMD representative for details.
It is possible to determine whether a sector group is
protected or unprotected. See the “Autoselect Mode”
on page 19 section for details.
Note: All sector groups are 256 Kbytes in size.
20
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 5, on page 20)).
START
This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated by
setting RESET# to VID (8.5 V – 12.5 V). During this
mode, formerly protected sector groups can be pro-
grammed or erased by selecting the sector group ad-
dresses. Once VID is removed from RESET#, all the
previously protected sector groups are
protected again. Figure 1, on page 21 shows the algo-
rithm, and Figure 21, on page 46 shows the timing dia-
grams, for this feature.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unprotect
Completed (Note 2)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group
Unprotect Operation
May 5, 2006 24961A5
Am29LV652D
21
D A T A S H E E T
START
START
PLSCNT = 1
PLSCNT = 1
RESET# = VID
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 μs
Wait 1 μs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Sector Group Protect:
Write 60h to sector
group address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector Group
Protect: Write 40h
to sector group
address twith A6 = 0,
A1 = 1, A0 = 0
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector group address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector group
address with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Am29LV652D
22
24961A5 May 5, 2006
D A T A S H E E T
inputs to prevent unintentional writes when VCC is
greater than VLKO
Hardware Data Protection
.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10, on
page 30 for command definitions). In addition, the fol-
lowing hardware data protection measures prevent ac-
cidental erasure or programming, which might
otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or
from system noise.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#,
CE2#, or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH, CE2# = VIH or WE# = VIH. To initiate a
write cycle, CE# (or CE2#), and WE# must be a logical
zero while OE# is a logical one.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
Power-Up Write Inhibit
If WE# = CE# = CE2# = VIL and OE# = VIH during
power up, the device does not accept commands on
the rising edge of WE#. The internal state machine is
automatically reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
care). The system can read CFI information at the ad-
dresses given in Table 6, on page 23 to Table 9, on
page 25. To terminate reading CFI data, the system
must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 6, on page 23
to Table 9, on page 25. The system must write the
reset command to return the device to the autoselect
mode.
The Am29LV652 is a two die solution which appears
as two 64 Mbit Am29LV065 devices in the system.
This allows the same CFI information to be used be-
cause the system “sees” two 64 Mbit devices, not a
single 128 Mbit device.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD represen-
tative for copies of these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, any time the
device is ready to read array data (addresses are don’t
Table 6. CFI Query Identification String
Description
Addresses (x8)
Data
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
00h
00h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
00h
00h
Address for Alternate OEM Extended Table (00h = none exists)
May 5, 2006 24961A5
Am29LV652D
23
D A T A S H E E T
Table 7. System Interface String
Addresses (x8)
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
27h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
36h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
00h
00h
04h
00h
0Ah
00h
05h
00h
04h
00h
VPP Min. voltage (00h = no VPP input present)
V
PP Max. voltage (00h = no VPP input present)
Typical timeout per single byte write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 8. Device Geometry Definition
Description
Addresses (x8)
Data
27h
17h
Device Size = 2N byte
28h
29h
00h
00h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
00h
00h
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch
01h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
7Fh
00h
00h
01h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
00h
00h
00h
00h
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
35h
36h
37h
38h
00h
00h
00h
00h
39h
3Ah
3Bh
3Ch
00h
00h
00h
00h
24
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
Table 9. Primary Vendor-Specific Extended Query
Addresses (x8)
Data
Description
40h
41h
42h
50h
52h
49h
Query-unique ASCII string “PRI”
43h
44h
31h
31h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
01h
Silicon Revision Number (Bits 7-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
02h
04h
01h
04h
00h
000h
00h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported
ACC (Acceleration) Supply Minimum
4Dh
4Eh
4Fh
B5h
C5h
00h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 10, on page 30 defines the valid
register command sequences. Writing incorrect ad-
dress and data values or writing them in the im-
proper sequence resets the device to reading array
data.
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See “Erase Suspend/Erase Resume Com-
mands” on page 28 for more information.
All addresses are latched on the falling edge of WE#
or CE# (or CE2#), whichever happens later. All data is
latched on the rising edge of WE# or CE# (or CE2#),
whichever happens first. Refer to “AC Characteristics”
on page 39 for timing diagrams.
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase op-
eration, or if the device is in the autoselect mode. See
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
May 5, 2006 24961A5
Am29LV652D
25
D A T A S H E E T
the next section, “Reset Command”, for more informa-
tion.
may read at any address any number of times without
initiating another autoselect command sequence:
See also “VersatileIO‰ (VIO) Control” on page 9 for
more information. The Read-Only Operations table
provides the read parameters, and Figure 13, on page
39 shows the timing diagram.
■ A read cycle at address XX00h returns the manu-
facturer code.
■ A read cycle at address XX01h returns the device
code.
■ A read cycle to an address containing a sector
group address (SA), and the address 02h on A7–A0
returns 01h if the sector group is protected, or 00h
if it is unprotected. (Refer to Table 5, on page 20 for
valid sector addresses).
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
Byte Program Command Sequence
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 10, on page 30 shows
the address and data requirements for the byte pro-
gram command sequence.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the “Write Operation
Status” on page 31 section for information on these
status bits.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device returns to the read
mode, to ensure data integrity.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 10, on page 30 shows the address and data re-
quirements. This method is an alternative to that
shown in Table 4, on page 19, which is intended for
PROM programmers and requires VID on address A9.
The autoselect command sequence may be written to
an address that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively pro-
gramming or erasing.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read shows that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
26
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 10, on page 30 shows the require-
ments for the command sequence.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
algorithm
in progress
Verify Data?
Yes
No
The device offers accelerated program operations
through ACC. When the system asserts VHH on ACC,
the device automatically enters the Unlock Bypass
mode. The system may then write the two-cycle Un-
lock Bypass program command sequence. The device
uses the higher voltage on ACC to accelerate the op-
eration. Note that ACC must not be at VHH for opera-
tions other than accelerated programming, or device
damage may result.
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 10, on page 30 for program command
sequence.
Figure 3, on page 27 illustrates the algorithm for the
program operation. Refer to the “Erase and Program
Operations” on page 41 table in the AC Characteristics
section for parameters, and Figure 15, on page 42 for
timing diagrams.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10, on
page 30 shows the address and data requirements for
the chip erase command sequence.
May 5, 2006 24961A5
Am29LV652D
27
D A T A S H E E T
When the Embedded Erase algorithm is complete, the ing edge of the final WE# pulse in the command
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” on page 31
for information on these status bits.
sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing sector. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing sector.
Refer to “Write Operation Status” on page 31 for infor-
mation on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device returns to reading array
data, to ensure data integrity.
Once the sector erase operation begins, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device returns to read-
ing array data, to ensure data integrity.
Figure 4, on page 29 illustrates the algorithm for the
erase operation. Refer to the “Erase and Program Op-
erations” on page 41 tables in the AC Characteristics
section for parameters, and Figure 17, on page 43
section for timing diagrams.
Sector Erase Command Sequence
Figure 4, on page 29 illustrates the algorithm for the
erase operation. Refer to the “Erase and Program Op-
erations” on page 41 tables in the AC Characteristics
section for parameters, and Figure 17, on page 43
section for timing diagrams.
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 10, on page 30
shows the address and data requirements for the sec-
tor erase command sequence.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sec-
tor erase operation, including the 50 µs time-out pe-
riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode. The system must re-
write the command sequence and any additional ad-
dresses and commands.
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation.
After the erase operation is suspended, the device en-
ters the erase-suspend-read mode. The system can
read data from or program data to any sector not se-
lected for erasure. (The device “erase suspends” all
sectors selected for erasure.) Reading at any address
within erase-suspended sectors produces status infor-
mation on DQ7–DQ0. The system can use DQ7, or
DQ6 and DQ2 together, to determine if a sector is ac-
tively erasing or is erase-suspended. Refer to “Write
Operation Status” on page 31 for information on these
status bits.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See “DQ3: Sector Erase
Timer” on page 33.). The time-out begins from the ris-
28
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard byte program operation.
Refer to “Write Operation Status” on page 31 for more
information.
START
Write Erase
Command Sequence
(Notes 1, 2)
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
“Autoselect Mode” on page 19 and “Autoselect Com-
mand Sequence” on page 26 sections for details.
Data Poll to Erasing
Bank from System
To resume the sector erase operation, the system
must write the Erase Resume command. The address
of the erase-suspended sector is required when writ-
ing this command. Further writes of the Resume com-
mand are ignored. Another Erase Suspend command
can be written after the chip resumes erasing.
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10, on page 30 for erase command
sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 4. Erase Operation
May 5, 2006 24961A5
Am29LV652D
29
D A T A S H E E T
Command Definitions
Table 10. Am29LV652D Command Definitions
Bus Cycles (Notes 2–4)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data
Addr
Data
Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
Device ID
1
1
4
4
RA
RD
F0
XXX
XXX
XXX
AA
AA
XXX
XXX
55
55
XXX
XXX
90
90
X00
X01
01
93
Sector Group Protect Verify
(Note 8)
4
XXX
AA
XXX
55
XXX
90 (SA)X02
00/01
PD
Program
4
3
2
XXX
XXX
XXX
AA
AA
A0
XXX
XXX
55
55
XXX
XXX
A0
20
PA
Unlock Bypass
Unlock Bypass Program (Note 9)
PA
PD
00
55
55
Unlock Bypass Reset (Note 10)
Chip Erase
XXX
XXX
XXX
BA
90
AA
AA
B0
30
98
XXX
XXX
XXX
2
6
6
1
1
1
XXX
XXX
80
80
XXX
XXX
AA
AA
XXX
XXX
55
55
XXX
SA
10
30
Sector Erase
Erase Suspend (Note 11)
Erase Resume (Note 12)
CFI Query (Note 13)
BA
XX
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# (or CE2#) pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A22–A16 uniquely select any sector.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# (or CE2#) pulse, whichever
happens later.
Notes:
1. See Table 1, on page 9 for description of bus operations.
8. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
2. All values are in hexadecimal.
9. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
10. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
4. Unless otherwise noted, address bits A22–A12 are don’t cares.
5. No unlock or command cycles required when device is in read
mode.
11. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
12. The Erase Resume command is valid only during the Erase
Suspend mode.
7. The fourth cycle of the autoselect command sequence is a read
cycle. See the Autoselect Command Sequence section for more
information.
13. Command is valid when device is ready to read array data or when
device is in autoselect mode.
30
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11, on page 34 and the following subsections
describe the function of these bits. DQ7 and DQ6 each offer
a method for determining whether a program or erase oper-
ation is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in
progress or is completed.
invalid. Valid data on DQ0–DQ7 appears on succes-
sive read cycles.
“Write Operation Status” on page 34 shows the out-
puts for Data# Polling on DQ7. Figure 5 shows the
Data# Polling algorithm. Figure 18, on page 44 in the
AC Characteristics section shows the Data# Polling
timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Yes
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device completes
the program or erase operation and DQ7 contains
valid data, the data outputs on DQ0–DQ6 may be still
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
May 5, 2006 24961A5
Am29LV652D
31
D A T A S H E E T
Table 11, on page 34 shows the outputs for Toggle Bit
RY/BY#: Ready/Busy#
I on DQ6. Figure 6 shows the toggle bit algorithm. Fig-
ure 19, on page 45 in the “AC Characteristics” section
shows the toggle bit timing diagrams. Figure 20, on
page 45 shows the differences between DQ2 and DQ6
in graphical form. See also the subsection “DQ2: Tog-
gle Bit II” on page 33.
The RY/BY# is a dedicated, open-drain output which
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY#s can be tied together in parallel with a
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or the device is in the erase-suspend-read
mode.
START
Read DQ7–DQ0
Table 11, on page 34 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Read DQ7–DQ0
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
No
Toggle Bit
= Toggle?
Yes
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# (or CE2#) to control the read cycles. When the
operation is complete, DQ6 stops toggling.
No
DQ5 = 1?
Yes
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
“DQ7: Data# Polling” on page 31).
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Figure 6. Toggle Bit Algorithm
32
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
the toggle bit and DQ5 through successive read cy-
DQ2: Toggle Bit II
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 6, on
page 32).
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# or
CE2# to control the read cycles.) But DQ2 cannot dis-
tinguish whether the sector is actively erasing or is
erase-suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are se-
lected for erasure. Thus, both status bits are required
for sector and mode information. Refer to Table 11, on
page 34 to compare outputs for DQ2 and DQ6.
DQ5 indicates whether the program or erase time ex-
ceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit is
exceeded, DQ5 produces a “1.”
Figure 6, on page 32 shows the toggle bit algorithm in
flowchart form, and the section “DQ2: Toggle Bit II” ex-
plains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 19, on page 45 shows the toggle bit
timing diagram. Figure 20, on page 45 shows the dif-
ferences between DQ2 and DQ6 in graphical form.
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if the device was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
Reading Toggle Bits DQ6/DQ2
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure began. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies
after each additional sector erase command. When
the time-out period is complete, DQ3 switches from a
“0” to a “1.” If the time between additional sector erase
commands from the system can be assumed to be
less than 50 µs, the system need not monitor DQ3.
See also “Sector Erase Command Sequence” on
page 28
Refer to Figure 6, on page 32 for the following discus-
sion. Whenever the system initially begins reading tog-
gle bit status, it must read DQ7–DQ0 at least twice in a
row to determine whether a toggle bit is toggling. Typi-
cally, the system would note and store the value of the
toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device accepted the
command sequence, and then read DQ3. If DQ3 is “1,”
the Embedded Erase algorithm has begun; all further
commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is “0,” the de-
vice accepts additional sector erase commands. To
ensure the command is accepted, the system software
should check the status of DQ3 prior to and following
each subsequent sector erase command. If DQ3 is
high on the second status check, the last command
might not have been accepted.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
Table 11, on page 34 shows the status of DQ3 relative
to the other status bits.
May 5, 2006 24961A5
Am29LV652D
33
D A T A S H E E T
Table 11. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend-
Read
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
1
No toggle
0
N/A
Toggle
1
Suspended Sector
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
34
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Industrial (I) Devices
Ambient Temperature (TA). . . . . . . . . .–40°C to +85°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Extended (E) Devices
Ambient Temperature (TA). . . . . . . . .–55°C to +125°C
Voltage with Respect to Ground
Supply Voltages
V
CC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V–3.6 V
VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V–5.0 V
VIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +5.5 V
A9, OE#, ACC, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
All others (Note 1). . . . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During
voltage transitions, input or I/Os may overshoot VSS to
–2.0 V for periods of up to 20 ns. Maximum DC voltage
on input or I/Os is VCC +0.5 V. See Figure 7, on page 35.
During voltage transitions, input or I/Os may overshoot to
VCC +2.0 V for periods up to 20 ns. See Figure 8, on
page 35.
2. Minimum DC input voltage on A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 7, on page 35.
Maximum DC input voltage on A9, OE#, ACC, and
RESET# is +12.5 V which may overshoot to +14.0 V for
periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
20 ns
20 ns
20 ns
VCC
+2.0 V
+0.8 V
VCC
+0.5 V
–0.5 V
–2.0 V
2.0 V
20 ns
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
Figure 7. Maximum Negative
Overshoot Waveform
May 5, 2006 24961A5
Am29LV652D
35
D A T A S H E E T
DC CHARACTERISTICS
(For Two Am29LV065 Devices)
CMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current
Test Conditions
IN = VSS to VCC
CC = VCC max
Min
Typ
Max
±1.0
70
Unit
µA
V
V
,
ILI
ILIT
A9, ACC Input Load Current
Output Leakage Current
VCC = VCC max; A9 = 12.5 V
VOUT = VSS to VCC
µA
,
ILO
±1.0
µA
VCC = VCC max
5 MHz
1 MHz
9
2
16
4
VCC Active Read Current
(Notes 1, 2)
CE# (or CE2#) = VIL,
OE# = VIH
ICC1
mA
mA
VCC Active Write Current (Notes 2, 3,
4)
ICC2
CE# (or CE2#) = VIL, OE# = VIH
26
30
ICC3
ICC4
ICC5
VCC Standby Current (Note 2)
VCC Reset Current (Note 2)
CE#, CE2#, RESET# = VCC ± 0.3 V
RESET# = VSS ± 0.3 V
0.4
0.4
0.4
5
10
10
µA
µA
µA
mA
mA
V
Automatic Sleep Mode (Notes 2, 5)
VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V
10
ACC
CE# = VIL, OE# = VIH
VCC
10
ACC Accelerated Program Current
(Note 4)
IACC
15
30
VIL
VIH
Input Low Voltage (Note 6)
Input High Voltage (Note 6)
–0.5
0.8
0.7 x VCC
VCC + 0.3
V
Voltage for ACC Program
Acceleration
VHH
VID
V
CC = 3.0 V 10%
11.5
8.5
12.5
V
V
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 3.0 V ± 10%
12.5
0.45
VOL
VOH1
VOH2
VLKO
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
IOH = –2.0 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
V
V
V
V
0.85 VIO
VIO–0.4
2.3
Output High Voltage (Note 7)
Low VCC Lock-Out Voltage (Note 7)
2.5
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Assumes only one Am29LV065 die being programmed at the same time.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
400 nA.
6. If VIO < VCC, maximum VIL for CE# (or CE2#) is 0.3 VIO. If VIO < VCC, minimum VIH for CE# (or CE2#) is 0.3 VIO.
7. Not 100% tested.
8. CE# can be replaced with CE2# when referring to the second device within the package.
9. Specifications in the table are for the Am29LV652 i.e. two Am29LV065 dice.
36
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
DC CHARACTERISTICS
Zero-Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
10
8
3.6 V
3.0 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
May 5, 2006 24961A5
Am29LV652D
37
D A T A S H E E T
TEST CONDITIONS
Table 12. Test Specifications
3.3 V
Test Condition
90R
12R
Unit
Output Load
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
C
L
6.2 kΩ
Input timing measurement
reference levels (See Note)
1.5
V
V
Output timing measurement
reference levels
0.5 VIO
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO.
3.0 V
1.5 V
0.5 VIO V
Input
Measurement Level
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 12. Input Waveforms and Measurement Levels
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
38
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
Test Setup
JEDEC
tAVAV
Std.
tRC
tACC
tCE
Description
(Note 1)
90R
90
90
90
35
30
30
12R
120
120
120
50
Unit
ns
Read Cycle Time (Note 2)
Address to Output Delay
Min
Max
Max
Max
Max
Max
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
CE#, OE# = VIL
OE# = VIL
ns
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z (Note 2)
Output Enable to Output High Z (Note 2)
ns
tOE
tDF
ns
30
ns
tDF
30
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
Time (Note 2)
tOEH
Toggle and
10
Data# Polling
Notes:
1. All test setups assume VIO = VCC
.
2. Not 100% tested.
3. See Figure 11, on page 38 and Table 12, on page 38 for
test specifications
4. CE# can be replaced with CE2# when referring to the second device within the package.
.
tRC
Addresses Stable
tACC
Addresses
CE# or CE2#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operation Timings
May 5, 2006 24961A5
Am29LV652D
39
D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
Max
20
μs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
μs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE# or CE2#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE# or CE2#, OE#
RESET#
tRP
Figure 14. Reset Timings
40
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
90R
12R
Unit
ns
Write Cycle Time (Note 1)
Min
Min
Min
Min
90
120
tAVWL
Address Setup Time
0
ns
tASO
tAH
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
ns
tWLAX
45
45
50
50
ns
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
Min
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
ns
ns
ns
Data Hold Time
0
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Min
Min
0
0
ns
ns
ns
ns
µs
µs
sec
ns
µs
ns
ns
CE# Hold Time
tWP
Write Pulse Width
35
50
tWPH
tWHWH1
tWHWH1
tWHWH2
tVHH
Write Pulse Width High
30
5
tWHWH1
tWHWH1
tWHWH2
Byte Programming Operation (Note 2)
Accelerated Byte Programming Operation (Note 2)
Sector Erase Operation (Note 2)
VHH Rise and Fall Time (Note 1)
VCC Setup Time (Note 1)
4
1.6
250
50
0
tVCS
tRB
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
tBUSY
90
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” on page 50 section for more information.
3. CE# can be replaced with CE2# when referring to the second device within the package.
May 5, 2006 24961A5
Am29LV652D
41
D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 15. Program Operation Timings
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Figure 16. Accelerated Program Timing Diagram
42
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE# or CE2#
OE#
2AAh
555 h for chip erase
tAH
tCH
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” on page 31
Figure 17. Chip/Sector Erase Operation Timings
May 5, 2006 24961A5
Am29LV652D
43
D A T A S H E E T
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE# or CE2#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
Complement
High Z
High Z
DQ7
Valid Data
Complement
Status Data
True
DQ0–DQ6
Valid Data
Status Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 18. Data# Polling Timings (During Embedded Algorithms)
44
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE# or CE2#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 19. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 20. DQ2 vs. DQ6
May 5, 2006 24961A5
Am29LV652D
45
D A T A S H E E T
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
4
µs
µs
RESET# Hold Time from RY/BY# High for
Temporary Sector Group Unprotect
tRRB
Min
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE# or CE2#
WE#
tRRB
tRSP
RY/BY#
Figure 21. Temporary Sector Group Unprotect Timing Diagram
46
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
60h
Valid*
Valid*
Status
Sector Group Protect/Unprotect
Verify
40h
Data
60h
1 µs
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
CE# or CE2#
WE#
OE#
* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 22. Sector Group Protect and Unprotect Timing Diagram
May 5, 2006 24961A5
Am29LV652D
47
D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
90R
12R
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
90
120
tAVWL
tELAX
tDVEH
tEHDX
0
ns
tAH
tDS
tDH
45
45
50
50
ns
ns
0
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
ns
tWLEL
tEHWH
tELEH
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
Typ
0
0
ns
ns
CE# Pulse Width
CE# Pulse Width High
45
50
ns
ns
µs
µs
sec
tEHEL
tCPH
30
5
tWHWH1
tWHWH1
tWHWH2
tWHWH1 Byte Programming Operation (Note 2)
tWHWH1 Accelerated Byte Programming Operation (Note 2)
tWHWH2 Sector Erase Operation (Note 2)
4
1.6
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. CE# can be replaced with CE2# when referring to the second device within the package.
48
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE# or CE2#
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings
May 5, 2006 24961A5
Am29LV652D
49
D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
Chip Erase Time
1.6
205
5
15
Excludes 00h programming
prior to erasure (Note 4)
Byte Program Time
Accelerated Byte Program Time
Chip Program Time (Note 3)
Notes:
150
120
126
Excludes system level
overhead (Note 5)
4
µs
42
sec
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 10, on page 30 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all device connections (including
A9, OE#, and RESET#) except I/Os
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/Os
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Note: Includes all connections except VCC. Test conditions: VCC = 3.0 V, one connection at a time.
INPUT/OUTPUT CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
12
12
6
Max
16
16
8
Unit
pF
CIN
COUT
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
pF
CE/CE2
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
50
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
PHYSICAL DIMENSIONS
FSA063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 11 x 12 mm package
May 5, 2006 24961A5
Am29LV652D
51
D A T A S H E E T
REVISION SUMMARY
Revision A (May 24, 2001)
Initial release.
Revision A+3 (January 10, 2002)
Global
Clarified description of VersatileIO (VIO) in the follow-
ing sections: Distinctive Characteristics; General De-
scription; VersatileIO (VIO) Control; Operating Ranges;
DC Characteristics; CMOS compatible.
Revision A+1 (July 31, 2001)
AC Characteristics—Alternate CE# Controlled
Erase and Program Table
t
WHWH1—Byte Programming Operation: Changed typi-
cal value from 11 µs to 5 µs.
Revision A+4 (October 29, 2004)
t
WHWH1—Accelerated Byte Programming Operation:
Global
Changed typical value from 7 µs to 4 µs.
Revision A+2 (August 14, 2001)
Global
Added Spansion Cover Sheet
Added reference links to page numbers
Added Colophon
Removed the speed options for 100 ns with VIO = 1.8
V – 2.9 V and 120 ns with VIO = 1.8 V – 2.9 V.
Changed the speed option for 120 ns with VIO = 3.0 V
– 5.0 V from 120R to 12R.
Ordering Information
Added two package types to temperature range.
Valid Combination for FBGA Packages
General Description and Device Bus Operations
Added MAF and MAK to order number.
Added “For voltage levels below 3 V, contact an AMD
representative for more information.” to VersatileI/O™
text.
Added F and K to Package Marking.
Revision A5 (May 5, 2006)
Added migration/obsolescence notices.
Ordering Information
Removed the Optional Processing from the order
number.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those product.
Trademarks
Copyright © 2000–2006 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies
52
Am29LV652D
24961A5 May 5, 2006
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128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO Control
SPANSION
AM29LV652DU90RMAF
128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO⑩ Control
AMD
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