AM29LV200BT-120EI [AMD]
2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory; 2兆位（ 256千×8位/ 128的K× 16位） CMOS 3.0伏只引导扇区闪存
| 型号： | AM29LV200BT-120EI |
| 厂家： | 
AMD |
| 描述： | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 文件： | 总7页 (文件大小：46K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
Am29LV200B
2 Megabit (256 K x 8-Bit/128 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Top or bottom boot block configurations
available
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
■ Embedded Algorithms
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
■ Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29LV200 device
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 write cycle guarantee per
■ High performance
sector
— Full voltage range: access times as fast as 80 ns
■ Package option
— 48-pin TSOP
— 44-pin SO
— Regulated voltage range: access times as fast as
70 ns
■ Ultra low power consumption (typical values at 5
MHz)
■ Compatibility with JEDEC standards
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
— 15 mA program/erase current
■ Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors (byte mode)
■ Ready/Busy# pin (RY/BY#)
— One 8 Kword, two 4 Kword, one 16 Kword, and
three 32 Kword sectors (word mode)
— Provides a hardware method of detecting
program or erase cycle completion
— Supports full chip erase
■ Erase Suspend/Erase Resume
— Sector Protection features:
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
A hardware method of locking a sector to prevent
any program or erase operations within that
sector
■ Hardware reset pin (RESET#)
Sectors can be locked in-system or via
programming equipment
— Hardware method to reset the device to reading
array data
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice. 1/23/98
Publication# 21521 Rev: A Amendment/0
Issue Date: January 1998
A D V A N C E I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV200B is a 2 Mbit, 3.0 volt-only Flash
memory organized as 262,144 bytes or 131,072 words.
The device is offered in 44-pin SO and 48-pin TSOP
packages. The word-wide data (x16) appears on
DQ15–DQ0; the byte-wide (x8) data appears on DQ7–
DQ0. This device is designed to be programmed in-
system using only a single 3.0 volt VCC supply. No VPP
is required for write or erase operations. The device
can also be programmed in standard EPROM pro-
grammers.
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
This device is manufactured using AMD’s 0.35 µm
process technology, and offers all the features and ben-
efits of the Am29LV200, which was manufactured using
0.5 µm process technology. In addition, the
Am29LV200B features unlock bypass programming
and in-system sector protection/unprotection.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
detector that automatically inhibits write opera-
VCC
The standard device offers access times of 70, 80, 90
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
1/23/98
Am29LV200B
2
A D V A N C E I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV200B
Regulated Voltage Range: V =3.0–3.6 V
-70R
CC
Speed Options
Max access time, ns (t
Full Voltage Range: V = 2.7–3.6 V
-80
-90
90
90
35
-120
120
120
50
CC
)
70
70
30
80
80
30
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
)
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A0–A16
21521A-1
3
Am29LV200B
1/23/98
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
VCC
WE#
RESET#
NC
NC
RY/BY#
NC
Standard TSOP
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
NC
A7
A6
A5
48
A16
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reverse TSOP
A4
A3
A2
A1
OE#
VSS
CE#
A0
21521A-2
1/23/98
Am29LV200B
4
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
NC
RY/BY#
NC
1
2
3
4
5
6
7
8
9
44 RESET#
43 WE#
42 A8
41 A9
A7
A6
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
32 VSS
A5
A4
A3
A2
A1 10
A0 11
CE# 12
VSS 13
SO
OE# 14
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
31 DQ15/A-1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
21521A-3
PIN CONFIGURATION
LOGIC SYMBOL
A0–A16
= 17 addresses
17
DQ0–DQ14 = 15 data inputs/outputs
A0–A16
16 or 8
DQ15/A-1
=
DQ15 (data input/output, word mode),
DQ0–DQ15
(A-1)
A-1 (LSB address input, byte mode)
Selects 8-bit or 16-bit mode
Chip enable
BYTE#
CE#
=
=
=
=
=
=
=
CE#
OE#
OE#
Output enable
WE#
WE#
Write enable
RESET#
BYTE#
RESET#
RY/BY#
VCC
Hardware reset pin, active low
Ready/Busy# output
RY/BY#
3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
21521A-4
VSS
NC
=
=
Device ground
Pin not connected internally
5
Am29LV200B
1/23/98
A D V A N C E I N F O R M A T I O N
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV200B
T
-70R
E
C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E
=
48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F
=
48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29LV200B
2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be sup-
Am29LV200BT-70R,
Am29LV200BB-70R
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
EC, EI, FC, FI, SC, SI
Am29LV200BT-80,
Am29LV200BB-80
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
Am29LV200BT-90,
Am29LV200BB-90
Am29LV200BT-120,
Am29LV200BB-120
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
1/23/98
Am29LV200B
6
A D V A N C E I N F O R M A T I O N
7
Am29LV200B
1/23/98
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