AM29LV116BT-120EEB_技术文档

PRELIMINARY

Am29LV116B

16 Megabit (2 M x 8-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Top or bottom boot block configurations

available

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

■ Embedded Algorithms

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with

high performance 3.3 volt microprocessors

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

■ Manufactured on 0.35 µm process technology

■ High performance

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

— Full voltage range: access times as fast as 90 ns

■ Minimum 1,000,000 write cycle guarantee per

sector

— Regulated voltage range: access times as fast

as 80 ns

■ Package option

— 40-pin TSOP

■ Ultra low power consumption (typical values at

5 MHz)

■ CFI (Common Flash Interface) compliant

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 9 mA read current

— Provides device-specific information to the

system, allowing host software to easily

reconfigure for different Flash devices

— 15 mA program/erase current

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

thirty-one 64 Kbyte sectors

— Superior inadvertent write protection

— Supports full chip erase

■ Data# Polling and toggle bits

— Sector Protection features:

— Provides a software method of detecting

program or erase operation completion

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

Sectors can be locked in-system or via

programming equipment

■ Erase Suspend/Erase Resume

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■ Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command sequences

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 21359 Rev: C Amendment/+2

Issue Date: March 1998

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29LV116B is a 16 Mbit, 3.0 Volt-only Flash

memory organized as 2,097,152 bytes. The device is

offered in a 40-pin TSOP package. The byte-wide (x8)

data appears on DQ7–DQ0. All read, program, and

erase operations are accomplished using only a single

power supply. The device can also be programmed in

standard EPROM programmers.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

has been completed, the device is ready to read array

data or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

The standard device offers access times of 80, 90, and

120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

V_CC

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically pre-

programs the array (if it is not already programmed) be-

fore executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within

a sector simultaneously via Fowler-Nordheim tun-

neling. The data is programmed using hot electron

injection.

Am29LV116B

2

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Family Part Number

Am29LV116B

Regulated Voltage Range: V =3.0–3.6 V

80R

CC

Speed Options

Max access time, ns (t

Full Voltage Range: V = 2.7–3.6 V

90

35

120

50

CC

)

80

30

ACC

Max CE# access time, ns (t

)

CE

Max OE# access time, ns (t

)

OE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ7

RY/BY#

V

CC

Sector Switches

V

SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

STB

V

Detector

Timer

CC

Cell Matrix

A0–A20

21359C-1

3

Am29LV116B

P R E L I M I N A R Y

CONNECTION DIAGRAMS

A17

V_SS

A16

A15

A14

A13

A12

A11

A9

1

2

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A20

A19

A10

DQ7

DQ6

DQ5

DQ4

V_CC

A8

WE#

RESET#

NC

RY/BY#

A18

A7

9

10

11

12

13

14

15

16

17

18

19

20

40-Pin Standard TSOP

NC

DQ3

DQ2

DQ1

DQ0

OE#

V_SS

A6

A5

A4

A3

A2

A1

CE#

A0

A17

V_SS

1

2

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A16

A15

A14

A13

A12

A11

A9

A20

A19

A10

DQ7

DQ6

DQ5

DQ4

V_CC

NC

DQ3

DQ2

DQ1

DQ0

A8

9

WE#

RESET#

NC

RY/BY#

A18

A7

A6

A5

A4

A3

10

11

12

13

14

15

16

17

18

19

20

40-Pin Reverse TSOP

OE#

V_SS

CE#

A0

A2

A1

21359C-2

Am29LV116B

4

P R E L I M I N A R Y

PIN CONFIGURATION

LOGIC SYMBOL

A0–A20

= 21 addresses

21

DQ0–DQ7 = 8 data inputs/outputs

A0–A20

8

CE#

=

Chip enable

DQ0–DQ7

OE#

Output enable

WE#

Write enable

CE#

OE#

RESET#

RY/BY#

V_CC

Hardware reset pin, active low

Ready/Busy output

WE#

RESET#

3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

RY/BY#

V_SS

NC

=

Device ground

Pin not connected internally

21359C-3

5

Am29LV116B

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29LV116B

T

80R

E

C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E

=

40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F

=

40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV116B

16 Megabit (2 M x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

Am29LV116BT80R,

Am29LV116BB80R

EC, FC

Am29LV116BT90,

Am29LV116BB90

EC, EI, EE,

FC, FI, FE

Am29LV116BT120,

Am29LV116BB120

Am29LV116B

6

P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register itself

does not occupy any addressable memory location.

The register is composed of latches that store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29LV116B Device Bus Operations

Operation

CE#

L

OE#

L

WE#

H

RESET#

Addresses

DQ0–DQ7

Read

Write

H

A

D

OUT

IN

L

H

L

D

IN

V

0.3 V

±

V

0.3 V

±

CC

Standby

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z

X

Sector Addresses,

A6 = L, A1 = H, A0 = L

Sector Protect (See Note)

L

H

L

V

D

, D

ID

IN

OUT

Sector Addresses

A6 = H, A1 = H, A0 = L

Sector Unprotect (See Note)

L

H

X

L

V

ID

IN

Temporary Sector Unprotect

X

A

D

IN

ID

IN

Legend:

L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Address In, D = Data In, D

= Data Out

IL

IH

ID

IN

OUT

Note: The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Requirements for Reading Array Data

Writing Commands/Command Sequences

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH.

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

The device features an Unlock Bypass mode to facil-

itate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a byte, instead of four. The “Byte

Program Command Sequence” section has details on

programming data to the device using both standard

and Unlock Bypass command sequences.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory con-

tent occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid addresses

on the device address inputs produce valid data on the

device data outputs. The device remains enabled for

read access until the command register contents are

altered.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. A “sector ad-

dress” consists of the address bits required to uniquely

select a sector. The “Command Definitions” section

has details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. I_CC1in

the DC Characteristics table represents the active cur-

rent specification for reading array data.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

7

Am29LV116B

P R E L I M I N A R Y

mode. Refer to the Autoselect Mode and Autoselect

signals. Standard address access timings provide new

data when addresses are changed. While in sleep

mode, output data is latched and always available to

the system. I_CC5in the DC Characteristics table

represents the automatic sleep mode current

specification.

Command Sequence sections for more information.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

RESET#: Hardware Reset Pin

Program and Erase Operation Status

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is ready

to accept another command sequence, to ensure data

integrity.

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I_CC

read specifications apply. Refer to “Write Operation

Status” for more information, and to “AC Characteris-

tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS±0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current will

be greater.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up

firmware from the Flash memory.

V

_CC± 0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device requires

standard access time (t_CE) for read access when the

device is in either of these standby modes, before it is

ready to read data.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

The device also enters the standby mode when the RE-

SET# pin is driven low. Refer to the next section, “RE-

SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

I_CC3in the DC Characteristics table represents the

standby current specification.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 for the timing diagram.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically

enables this mode when addresses remain stable for

t_ACC+ 30 ns. The automatic sleep mode is

independent of the CE#, WE#, and OE# control

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

Am29LV116B

8

P R E L I M I N A R Y

Table 2. Am29LV116BT Top Boot Sector Address Table

Sector Size

Address Range

(in hexadecimal)

Sector

SA0

A20

0

1

A19

0

1

0

1

A18

0

1

0

1

0

1

0

1

A17

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A15

X

0

A14

X

0

A13

X

0

(Kbytes)

64

32

8

000000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1F7FFF

1F8000–1F9FFF

1FA000–1FBFFF

1FC000–1FFFFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

1

0

1

8

1

X

16

9

Am29LV116B

P R E L I M I N A R Y

Table 3. Am29LV116BB Bottom Boot Sector Address Table

Sector Size

Address Range

(in hexadecimal)

Sector

SA0

A20

0

1

A19

0

1

0

1

A18

0

1

0

1

0

1

0

1

A17

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A15

A14

A13

X

0

(Kbytes)

16

8

0

000000–003FFF

004000–005FFF

006000–007FFF

008000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

SA1

0

1

SA2

0

1

8

SA3

1

X

32

64

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Am29LV116B

10

P R E L I M I N A R Y

Table 4. In addition, when verifying sector protection,

Autoselect Mode

the sector address must appear on the appropriate

highest order address bits (see Tables 2 and 3). Table

4 shows the remaining address bits that are don’t care.

When all necessary bits have been set as required, the

programming equipment may then read the corre-

sponding identifier code on DQ7-DQ0.

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 9. This method

does not require V_ID. See “Command Definitions” for

details on using the autoselect mode.

When using programming equipment, the autoselect

mode requires V_ID(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Table 4. Am29LV116B Autoselect Codes (High Voltage Method)

A20 A12

to to

OE# WE# A13 A10

A8

to

A7

A5

to

A2

DQ7

to

DQ0

Description

CE#

A9

A6

A1

A0

Manufacturer ID: AMD

L

H

X

V

X

L

X

L

01h

C7h

ID

Device ID: Am29LV116B

(Top Boot Block)

L

V

L

H

Device ID: Am29LV116B

(Bottom Boot Block)

L

H

X

V

X

4Ch

ID

01h

(protected)

Sector Protection Verification

L

SA

V

L

H

L

00h

(unprotected)

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

IL

IH

lication number 21586 contains further details; contact

an AMD representative to request a copy.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 1 shows the algo-

rithms and Figure 21 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect write

cycle.

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

sector addresses. Once V_IDis removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 2 shows the algorithm, and

Figure 20 shows the timing diagrams, for this feature.

The alternate method intended only for programming

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices. Pub-

11

Am29LV116B

P R E L I M I N A R Y

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 µs

unprotect address

No

First Write

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

21359C-4

Figure 1. In-System Sector Protect/Unprotect Algorithms

Am29LV116B

12

P R E L I M I N A R Y

against inadvertent writes (refer to Table 9 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up

and power-down transitions, or from system noise.

START

RESET# = V

(Note 1)

ID

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until V_CC

is greater than V_LKO. The system must provide the

proper signals to the control pins to prevent uninten-

Perform Erase or

Program Operations

RESET# = V

IH

tional writes when V_CCis greater than V_LKO

.

Temporary Sector

Unprotect Completed

(Note 2)

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

21359C-5

Logical Inhibit

Notes:

1. All protected sectors unprotected.

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

2. All previously protected sectors are protected once

again.

Power-Up Write Inhibit

Figure 2. Temporary Sector Unprotect Operation

If WE# = CE# = V_ILand OE# = V_IHduring power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

13

Am29LV116B

P R E L I M I N A R Y

data. The system can read CFI information at the

COMMON FLASH MEMORY INTERFACE

(CFI)

addresses given in Tables 5–8. To terminate reading

CFI data, the system must write the reset command.

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 5–8. The

system must write the reset command to return the

device to the autoselect mode.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/products/nvd/over-

view/cfi.html. Alternatively, contact an AMD represent-

ative for copies of these documents.

This device enters the CFI Query mode when the

system writes the CFI Query command, 98h, to

address 55h, any time the device is ready to read array

Table 5. CFI Query Identification String

Description

Addresses

Data

10h

11h

12h

51h

52h

59h

Query Unique ASCII string “QRY”

Primary OEM Command Set

13h

14h

02h

00h

15h

16h

40h

00h

Address for Primary Extended Table

17h

18h

00h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

00h

Table 6. System Interface String

Description

Addresses

Data

V

Min. (write/erase)

CC

1Bh

27h

D7–D4: volt, D3–D0: 100 millivolt

V

Max. (write/erase)

CC

1Ch

36h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

00h

04h

00h

0Ah

00h

05h

00h

04h

00h

V

Min. voltage (00h = no V pin present)

PP

Max. voltage (00h = no V pin present)

PP

N

Typical timeout per single byte/word write 2 µs

N

Typical timeout for Min. size buffer write 2 µs (00h = not supported)

N

Typical timeout per individual block erase 2 ms

N

Typical timeout for full chip erase 2 ms (00h = not supported)

N

Max. timeout for byte/word write 2 times typical

N

Max. timeout for buffer write 2 times typical

N

Max. timeout per individual block erase 2 times typical

N

Max. timeout for full chip erase 2 times typical (00h = not supported)

Am29LV116B

14

P R E L I M I N A R Y

Table 7. Device Geometry Definition

Addresses

Data

Description

N

27h

15h

Device Size = 2 byte

28h

29h

00h

Flash Device Interface description (refer to CFI publication 100)

N

2Ah

2Bh

00h

Max. number of byte in multi-byte write = 2

(00h = not supported)

2Ch

04h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

00h

40h

00h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

01h

00h

20h

00h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

00h

80h

00h

39h

3Ah

3Bh

3Ch

1Eh

00h

01h

Table 8. Primary Vendor-Specific Extended Query

Data Description

Addresses

40h

41h

42h

50h

52h

49h

Query-unique ASCII string “PRI”

43h

44h

31h

30h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock

0 = Required, 1 = Not Required

45h

46h

00h

02h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

47h

48h

01h

Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

49h

04h

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

4Ah

4Bh

00h

Simultaneous Operation: 00 = Not Supported, 01 = Supported

Burst Mode Type: 00 = Not Supported, 01 = Supported

Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,

02 = 8 Word Page

4Ch

00h

15

Am29LV116B

P R E L I M I N A R Y

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 9 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence resets

the device to reading array data.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 9 shows the address and data requirements. This

method is an alternative to that shown in Table 4, which

is intended for PROM programmers and requires V_ID

on address bit A9.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect com-

mand. The device then enters the autoselect mode,

and the system may read at any address any number

of times, without initiating another command sequence.

A read cycle at address XX00h retrieves the manufac-

turer code. A read cycle at address XX01h returns the

device code. A read cycle containing a sector address

(SA) and the address 02h returns 01h if that sector is

protected, or 00h if it is unprotected. Refer to Tables 2

and 3 for valid sector addresses.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data.

After completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See “Erase Sus-

pend/Erase Resume Commands” for more information

on this mode.

The system must issue the reset command to re-ena-

ble the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Byte Program Command Sequence

The device programs one byte of data for each pro-

gram operation. The command sequence requires four

bus cycles, and is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically generates the program

pulses and verifies the programmed cell margin. Table

9 shows the address and data requirements for the

byte program command sequence.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Figure 13 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

for information on these status bits.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The Byte Program command se-

Am29LV116B

16

P R E L I M I N A R Y

quence should be reinitiated once the device has reset

to reading array data, to ensure data integrity.

START

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1,” or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Write Program

Command Sequence

Data Poll

from System

Unlock Bypass Command Sequence

Embedded

Program

algorithm

in progress

The unlock bypass feature allows the system to pro-

gram bytes to the device faster than using the standard

program command sequence. The unlock bypass com-

mand sequence is initiated by first writing two unlock

cycles. This is followed by a third write cycle containing

the unlock bypass command, 20h. The device then en-

ters the unlock bypass mode. A two-cycle unlock by-

pass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program ad-

dress and data. Additional data is programmed in the

same manner. This mode dispenses with the initial two

unlock cycles required in the standard program com-

mand sequence, resulting in faster total programming

time. Table 9 shows the requirements for the command

sequence.

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

21359C-6

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

don’t cares for both cycles. The device then returns to

reading array data.

Note: See Table 9 for program command sequence.

Figure 3. Program Operation

Figure 3 illustrates the algorithm for the program oper-

ation. See the Erase/Program Operations table in “AC

Characteristics” for parameters, and to Figure 15 for

timing diagrams

17

Am29LV116B

P R E L I M I N A R Y

ensure all commands are accepted. The interrupts can

Chip Erase Command Sequence

be re-enabled after the last Sector Erase command is

written. If the time between additional sector erase

commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 9 shows

the address and data requirements for the chip erase

command sequence.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the op-

eration. The Sector Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Note that a hardware

reset during the chip erase operation immediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device has

returned to reading array data, to ensure data integrity.

The system can determine the status of the erase op-

eration by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these sta-

tus bits. When the Embedded Erase algorithm is com-

plete, the device returns to reading array data and

addresses are no longer latched.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. (Refer to “Write Operation Status” for informa-

tion on these status bits.)

Figure 4 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to Figure 16 for

timing diagrams.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

Figure 16 for timing diagrams.

Sector Erase Command Sequence

Erase Suspend/Erase Resume Commands

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock write cycles are then followed by the ad-

dress of the sector to be erased, and the sector erase

command. Table 9 shows the address and data re-

quirements for the sector erase command sequence.

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the time-out period 50 µs

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase Sus-

pend command.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time be-

tween these additional cycles must be less than 50 µs,

otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended

that processor interrupts be disabled during this time to

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

Am29LV116B

18

P R E L I M I N A R Y

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on these

status bits.

START

Write Erase

Command Sequence

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine the

status of the program operation using the DQ7 or DQ6

status bits, just as in the standard program operation.

See “Write Operation Status” for more information.

Data Poll

from System

Embedded

Erase

algorithm

in progress

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

No

Data = FFh?

Yes

Erasure Completed

21359C-7

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

Notes:

1. See Table 9 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

19

Am29LV116B

P R E L I M I N A R Y

Table 9. Am29LV116B Command Definitions

Bus Cycles (Notes 2–4)

Command Sequence

(Note 1)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 5)

Reset (Note 6)

Manufacturer ID

1

4

RA

XXX

555

RD

F0

AA

2AA

55

555

90

X00

X01

01

Device ID,

Top Boot Block

C7

4

555

AA

Device ID,

Bottom Boot Block

4C

00

01

Sector Protect

Verify (Note 8)

SA

X02

4

555

AA

2AA

55

555

90

Byte Program

Unlock Bypass

4

3

555

AA

2AA

55

555

A0

20

PA

PD

Unlock Bypass Program

(Note 9)

2

XXX

A0

90

PA

PD

00

Unlock Bypass Reset

(Note 10)

XXX

Chip Erase

6

1

555

AA

B0

30

2AA

55

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Erase Suspend (Note 11)

Erase Resume (Note 12)

XXX

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data is latched

on the rising edge of WE# or CE# pulse.

RA = Address of the memory location to be read.

SA = Address of the sector to be erased or verified. Address

bits A20–A13 uniquely select any sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses are latched on the falling edge of the WE# or CE#

pulse.

Notes:

1. See Table 1 for descriptions of bus operations.

8. The data is 00h for an unprotected sector and 01h for a

protected sector.

2. All values are in hexadecimal.

9. The Unlock Bypass command is required prior to the

Unlock Bypass Program command.

3. Except when reading array or autoselect data, all bus

cycles are write operations.

10. The Unlock Bypass Reset command is required to return

to reading array data when the device is in the Unlock

Bypass mode.

4. Address bits A20–A11 are don’t care for unlock and

command cycles, except when PA or SA is required.

5. No unlock or command cycles required when device is in

read mode.

11. The system may read and program functions in non-

erasing sectors, or enter the autoselect mode, when in the

Erase Suspend mode. The Erase Suspend command is

valid only during a sector erase operation.

6. The Reset command is required to return to the read

mode when the device is in the autoselect mode or if DQ5

goes high.

12. The Erase Resume command is valid only during the

Erase Suspend mode.

7. The fourth cycle of the autoselect command sequence is

a read cycle.

Am29LV116B

20

P R E L I M I N A R Y

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,

and RY/BY#. Table 10 and the following subsections

describe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

START

Read DQ7–DQ0

Addr = VA

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Algorithm is in progress or

completed, or whether the device is in Erase Suspend.

Data# Polling is valid after the rising edge of the final

WE# pulse in the program or erase command se-

quence.

Yes

DQ7 = Data?

No

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for ap-

proximately 1 µs, then the device returns to reading

array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21359C-8

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

Figure 5. Data# Polling Algorithm

following read cycles. This is because DQ7

DQ0 on the

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 17, Data#

Polling Timings (During Embedded Algorithms), in the

“AC Characteristics” section illustrates this.

Table 10 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm.

21

Am29LV116B

P R E L I M I N A R Y

Table 10 shows the outputs for Toggle Bit I on DQ6. Fig-

RY/BY#: Ready/Busy#

ure 6 shows the toggle bit algorithm in flowchart form,

and the section “Reading Toggle Bits DQ6/DQ2” ex-

plains the algorithm. Figure 18 in the “AC Characteris-

tics” section shows the toggle bit timing diagrams.

Figure 19 shows the differences between DQ2 and

DQ6 in graphical form. See also the subsection on

DQ2: Toggle Bit II.

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC. (The RY/BY# pin is not availa-

ble on the 44-pin SO package.)

DQ2: Toggle Bit II

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

Table 10 shows the outputs for RY/BY#. Figures 13, 15

and 16 shows RY/BY# for reset, program, and erase

operations, respectively.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for eras-

ure. (The system may use either OE# or CE# to control

the read cycles.) But DQ2 cannot distinguish whether

the sector is actively erasing or is erase-suspended.

DQ6, by comparison, indicates whether the device is

actively erasing, or is in Erase Suspend, but cannot

distinguish which sectors are selected for erasure.

Thus, both status bits are required for sector and mode

information. Refer to Table 10 to compare outputs for

DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle (The system may use either OE# or CE#

to control the read cycles). When the operation is com-

plete, DQ6 stops toggling.

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “Reading Toggle Bits DQ6/DQ2”

explains the algorithm. See also the DQ6: Toggle Bit I

subsection. Figure 18 shows the toggle bit timing dia-

gram. Figure 19 shows the differences between DQ2

and DQ6 in graphical form.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, DQ6 toggles for

approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected sec-

tors, and ignores the selected sectors that are

protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has com-

pleted the program or erase operation. The system can

read array data on DQ7–DQ0 on the following read cy-

cle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that

is, the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on DQ7: Data# Polling).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is toggling,

since the toggle bit may have stopped toggling just as

DQ5 went high. If the toggle bit is no longer toggling,

the device has successfully completed the program or

erase operation. If it is still toggling, the device did not

completed the operation successfully, and the system

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Am29LV116B

22

P R E L I M I N A R Y

must write the reset command to return to reading

array data.

START

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 6).

Read DQ7–DQ0

(Note 1)

Read DQ7–DQ0

Table 10 shows the outputs for Toggle Bit I on DQ6. Fig-

ure 6 shows the toggle bit algorithm. Figure 18 in the

“AC Characteristics” section shows the toggle bit timing

diagrams. Figure 19 shows the differences between

DQ2 and DQ6 in graphical form. See also the subsec-

tion on DQ2: Toggle Bit II.

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

(Notes

1, 2)

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

21359C-9

Figure 6. Toggle Bit Algorithm

23

Am29LV116B

P R E L I M I N A R Y

tional sectors are selected for erasure, the entire time-

DQ5: Exceeded Timing Limits

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” If the time between additional sector

erase commands from the system can be assumed to

be less than 50 µs, the system need not monitor DQ3.

See also the “Sector Erase Command Sequence” sec-

tion.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence, and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all further commands (other than Erase Suspend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 10 shows the outputs for DQ3.

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

Table 10. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend Reading within Non-Erase

Data

0

Data

N/A

Data

N/A

1

0

Mode

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Am29LV116B

24

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V

20 ns

All other pins (Note 1) . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

21359C-10

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may undershoot V

Figure7. MaximumNegativeOvershootWaveform

SS

to –2.0 V for periods of up to 20 ns. See Figure 7.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

During voltage transitions, input or I/O pins may overshoot

to V +2.0 V for periods up to 20 ns. See Figure 8.

CC

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

20 ns

RESET# may undershoot V to –2.0 V for periods of up

V

SS

CC

+2.0 V

to 20 ns. See Figure 7. Maximum DC input voltage on pin

A9 is +12.5 V which may overshoot to 14.0 V for periods

up to 20 ns.

V

CC

+0.5 V

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

2.0 V

20 ns

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

21359C-11

Figure 8. Maximum Positive Overshoot Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . –55°C to +125°C

V_CCSupply Voltages

V_CCfor regulated voltage range. . . . . .+3.0 V to 3.6 V

V_CCfor full voltage range . . . . . . . . . . .+2.7 V to 3.6 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

25

Am29LV116B

P R E L I M I N A R Y

Test Conditions

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Min

Typ

Max

±1.0

35

Unit

µA

V

= V to V

,

CC

IN

SS

I

Input Load Current

LI

= V

CC

CC max

I

A9 Input Load Current

Output Leakage Current

V

= V

; A9 = 12.5 V

µA

LIT

CC

CC max

V

= V to V

,

CC

OUT

SS

I

±1.0

µA

LO

= V

CC

CC max

5 MHz

1 MHz

9

2

16

4

V

Active Read Current

V

= V

;

CC max

CC

I

mA

CC1

(Note 1)

CE# = V OE#

V

IL,

=

IH

V

Active Write Current

V

= V

;

CC max

CC

I

15

0.2

30

5

mA

µA

CC2

CC3

CC4

CC5

(Notes 2 and 4)

CE# = V OE#

IL,

IH

V

= V

;

CC max

CC

V

Standby Current

Reset Current

CC

CE#, RESET# = V ±0.3 V

CC

V

= V

;

CC max

CC

5

CC

RESET# = V ± 0.3 V

SS

V

= V

; V = V ± 0.3 V;

CC max IH CC

CC

Automatic Sleep Mode (Note 3)

5

= V ± 0.3 V

IL

SS

V

Input Low Voltage

Input High Voltage

–0.5

0.8

V

IL

V

0.7 x V

V

+ 0.3

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 3.3 V

11.5

12.5

0.45

V

ID

CC

V

Output Low Voltage

I

= 4.0 mA, V = V

V

OL

OH

CC

CC min

V

= –2.0 mA, V = V

0.85 V

OH1

OH2

CC

CC min

CC

Output High Voltage

V

= –100 µA, V = V

V

–0.4

CC

Low V Lock-Out Voltage

(Note 4)

CC

V

2.3

2.5

V

LKO

Notes:

1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical specifications are for V = 3.0 V.

CC

IH

CC

2. I active while Embedded Erase or Embedded Program is in progress.

CC

3. Automatic sleep mode enables the low power mode when addresses remain stable for t

4. Not 100% tested.

+ 30 ns.

ACC

Am29LV116B

26

P R E L I M I N A R Y

DC CHARACTERISTICS (Continued)

Zero Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

21359C-12

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

21359C-13

Figure 10. Typical I_CC1vs. Frequency

27

Am29LV116B

P R E L I M I N A R Y

TEST CONDITIONS

Table 11. Test Specifications

3.3 V

Test Condition

Output Load

80R

90, 120 Unit

1 TTL gate

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C

(including jig capacitance)

L

30

100

pF

C

L

Input Rise and Fall Times

Input Pulse Levels

5

0.0–3.0

ns

6.2 kΩ

V

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

21359C-14

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

KS000010-PAL

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

21359C-15

Figure 12. Input Waveforms and Measurement Levels

Am29LV116B

28

P R E L I M I N A R Y

AC CHARACTERISTICS

Read Operations

Parameter

Speed Option

JEDEC

Std

Description

Test Setup

80R

90

120

Unit

t

Read Cycle Time (Note 1)

Min

80

90

120

ns

AVAV

RC

CE# = V

OE# = V

IL

t

Address to Output Delay

Max

90

ns

AVQV

ACC

t

Chip Enable to Output Delay

OE# = V

Max

Min

80

30

25

90

35

30

0

120

50

ns

ELQV

GLQV

EHQZ

GHQZ

CE

IL

t

Output Enable to Output Delay

OE

t

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

30

DF

t

30

Read

Output Enable

t

OEH

Toggle and

Data# Polling

Hold Time (Note 1)

Min

10

0

ns

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First (Note 1)

t

OH

AXQX

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 11 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

21359C-16

Figure 13. Read Operations Timings

29

Am29LV116B

P R E L I M I N A R Y

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

Max

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read or Write (See Note)

t

20

µs

READY

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t

Max

500

ns

READY

t

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

RP

RESET# High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

RH

t

RPD

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

21359C-17

Figure 14. RESET# Timings

Am29LV116B

30

P R E L I M I N A R Y

AC CHARACTERISTICS

Erase/Program Operations

Parameter

JEDEC

Std.

Description

80R

90

0

120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

80

120

AVAV

WC

t

ns

AVWL

WLAX

DVWH

WHDX

AS

AH

DS

DH

t

45

35

45

0

50

ns

t

ns

t

ns

t

Output Enable Setup Time (Note 1)

0

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHWL

t

CE# Setup Time

Min

Typ

Min

0

ns

µs

sec

µs

ns

ELWL

WHEH

WLWH

WHWL

CS

CH

WP

t

CE# Hold Time

t

Write Pulse Width

35

30

9

50

t

Write Pulse Width High

Programming Operation (Note 2)

Sector Erase Operation (Note 2)

WPH

t

WHWH1

WHWH2

WHWH1

WHWH2

t

0.7

50

0

t

V

Setup Time (Note 1)

VCS

CC

t

Recovery Time from RY/BY#

RB

t

Program/Erase Valid to RY/BY# Delay

90

BUSY

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

31

Am29LV116B

P R E L I M I N A R Y

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_GHWL

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

21359C-18

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

Figure 15. Program Operation Timings

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_GHWL

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

21359C-19

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

Figure 16. Chip/Sector Erase Operation Timings

Am29LV116B

32

P R E L I M I N A R Y

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

t_OEH

WE#

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

Status Data

True

DQ0–DQ6

Status Data

True

Valid Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

21359C-20

Figure 17. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

21359C-21

Figure 18. Toggle Bit Timings (During Embedded Algorithms)

33

Am29LV116B

P R E L I M I N A R Y

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

21359C-22

Figure 19. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std.

Description

Rise and Fall Time (See Note)

All Speed Options

Unit

t

V

Min

500

ns

VIDR

ID

RESET# Setup Time for Temporary Sector

Unprotect

t

4

µs

RSP

Note: Not 100% tested.

12 V

RESET#

0 or 3 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

21359C-23

Figure 20. Temporary Sector Unprotect Timing Diagram

Am29LV116B

34

P R E L I M I N A R Y

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Protect: 100 µs

Sector Unprotect: 10 ms

1 µs

CE#

WE#

OE#

Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

21359C-24

Figure 21. Sector Protect/Unprotect Timing Diagram

35

Am29LV116B

P R E L I M I N A R Y

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

JEDEC

Std.

Description

80R

90

0

120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

80

120

AVAV

AVEL

ELAX

WC

t

ns

AS

AH

DS

DH

t

45

35

45

0

50

ns

t

ns

DVEH

EHDX

t

Data Hold Time

ns

t

Output Enable Setup Time

0

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHEL

t

WE# Setup Time

Min

Typ

0

ns

WLEL

WS

t

WE# Hold Time

EHWH

WH

t

CE# Pulse Width

35

30

9

50

ns

ELEH

EHEL

CP

t

CE# Pulse Width High

Programming Operation (Note 2)

Sector Erase Operation (Note 2)

ns

CPH

t

µs

WHWH1

WHWH2

WHWH1

WHWH2

t

0.7

sec

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29LV116B

36

P R E L I M I N A R Y

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Note: PA = program address, PD = program data, DQ7# = complement of the data written to the device, D

the device. Figure indicates the last two bus cycles of the command sequence.

= data written to

21359C-25

OUT

Figure 22. Alternate CE# Controlled Write Operation Timings

37

Am29LV116B

P R E L I M I N A R Y

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

s

Comments

Sector Erase Time

0.7

25

9

15

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

s

Byte Programming Time

Chip Programming Time (Note 3)

300

µs

s

Excludes system level

overhead (Note 5)

18

54

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four- or two-bus-cycle sequence for the program command. See

Table 9 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles per sector.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V on all pins except I/O pins

(including A9, OE#, and RESET#)

SS

–1.0 V

12.5 V

Input voltage with respect to V on all I/O pins

–1.0 V

V

+ 1.0 V

CC

SS

V

Current

–100 mA

+100 mA

CC

Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.

CC

TSOP PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

Typ

6

Max

7.5

12

Unit

pF

C

V

= 0

IN

C

Output Capacitance

Control Pin Capacitance

V

= 0

8.5

7.5

pF

OUT

C

V

= 0

IN

9

pF

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

Am29LV116B

38

P R E L I M I N A R Y

PHYSICAL DIMENSIONS*

TS 040—40-Pin Standard TSOP (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

40

9.90

10.10

0.50 BSC

20

21

0.05

0.15

18.30

18.50

19.80

20.20

0.08

0.20

0.10

0.21

16-038-TSOP-1_AC

TS 040

4-25-96 lv

1.20

MAX

0˚

5˚

0.25MM (0.0098") BSC

0.50

0.70

* For reference only. BSC is an ANSI standard for Basic Space Centering.

TSR040—40-Pin Reverse TSOP (measured in millimeters)

1.05

Pin 1 I.D.

1

40

9.90

10.10

0.50 BSC

20

21

0.05

0.15

18.30

18.50

19.80

20.20

16-038-TSOP-1_AC

TSR040

4-25-96 lv

0.08

0.20

1.20

MAX

0.10

0.21

0˚

5˚

0.25MM (0.0098") BSC

0.50

0.70

* For reference only. BSC is an ANSI standard for Basic Space Centering.

39

Am29LV116B

P R E L I M I N A R Y

REVISION SUMMARY

AC Characteristics

Revision B

Erase/Program Operations; Alternate CE# Controlled

Erase/Program Operations: Corrected the notes refer-

ence for t_WHWH1and t_WHWH2. These parameters are

Global

Deleted SO package from data sheet.

100% tested. Corrected the note reference for t_VCS

This parameter is not 100% tested.

.

Revision C

Alternate CE# Controlled Erase/Program

Operations

Temporary Sector Unprotect Table

Added note reference for t_VIDR. This parameter is not

100% tested.

Changed t_CPfrom 45 to 35 ns on 80R and 90 speed

options.

Figure 21, Sector Protect/Unprotect Timing

Diagram

Revision C+1

Global

A valid address is not required for the first write cycle;

only the data 60h.

Changed data sheet status to Preliminary.

Erase and Programming Performance

Reset Command

Deleted the last paragraph in this section.

In Note 2, the worst case endurance is now 1 million

cycles.

Revision C+2

Figure 1, In-System Sector Protect/Unprotect

Algorithms

In the sector protect algorithm, added a “Reset

PLSCNT=1” box in the path from “Protect another sec-

tor?” back to setting up the next sector address.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29LV116B

40


型号：	AM29LV116BT-120EEB
厂家：	AMD
描述：	16 Megabit (2 M x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory 16兆位（2M ×8位） CMOS 3.0伏只引导扇区闪存闪存
文件：	总40页 (文件大小：508K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV116BT-120EEB [AMD]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E