AM29LV102BT-90EIB [AMD]

2 Megabit (256 K x 8-Bit) CMOS 3.0 Volt-only, Boot Sector 32-Pin Flash Memory; 2兆位（ 256千×8位） CMOS 3.0伏只，引导扇区32个引脚闪存


型号：	AM29LV102BT-90EIB
厂家：	AMD
描述：	2 Megabit (256 K x 8-Bit) CMOS 3.0 Volt-only, Boot Sector 32-Pin Flash Memory 2兆位（ 256千×8位） CMOS 3.0伏只，引导扇区32个引脚闪存闪存
文件：	总7页 (文件大小：41K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADVANCE INFORMATION

Am29LV102B

2 Megabit (256 K x 8-Bit)

CMOS 3.0 Volt-only, Boot Sector 32-Pin Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Unlock Bypass Program Command

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Reduces overall programming time when

issuing multiple program command sequences

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations and for compatibility with high

performance 3.3 volt microprocessors

■ Embedded Algorithms

— Embedded Erase algorithms automatically

preprogram and erase the entire chip or any

combination of designated sectors

■ Manufactured on 0.35 µm process technology

■ High performance

— Embedded Program algorithms automatically

writes and verifies data at specified addresses

— Full voltage range: access times as fast as 70 ns

— Regulated voltage range: access times as fast

as 55 ns

■ Minimum 1,000,000 write/erase cycles

guaranteed

■ Package option

■ Ultra low power consumption

— 32-pin PLCC

— Automatic sleep mode: 1 µA (typical values at

5 MHz)

— 32-pin TSOP

— Standby mode: 1 µA

— Read mode: 7 mA

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Program/erase mode: 15 mA

— Superior inadvertent write protection

■ Flexible sector architecture

■ Data# Polling and toggle bits

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

three 64 Kbyte sectors

— Provides a software method of detecting

program or erase cycle completion

— Any combination of sectors can be erased;

supports full chip erase

■ Erase Suspend/Resume

— Sector Protection features:

— Supports reading data from or programming

data to a sector not being erased

Hardware method of locking a sector to prevent

any program or erase operations within that

sector

Sectors can be locked via programming

equipment

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice. 2/9/98

Publication# 21259 Rev: A Amendment/0

Issue Date: January 1998

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29LV102B is a single power supply, 2 Mbit, 3.0

Volt-only Flash memory device organized as 262,144

bytes. The data appears on DQ0-DQ7. The device is

available in 32-pin PLCC and 32-pin TSOP packages.

All read, erase, and program operations are accom-

plished using only a single power supply. The device

can also be programmed in standard EPROM pro-

grammers.

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the device is ready

to read array data or accept another command.

The device offers access times of 55, 70, 90, and 120

ns allowing high speed microprocessors to operate

without wait states. To eliminate bus contention, the

device has separate control pins—chip enable (CE#),

write enable (WE#), and output enable (OE#)—to

control normal read and write operations.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

V_CC

The device requires only a single power supply (2.7

V–3.6V) for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This is achieved via programming equipment.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tun-

neling. The data is programmed using hot electron

injection.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

Am29LV102B

2/9/98

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Family Part Number

Am29LV102B

Regulated Voltage Range: V =3.0–3.6 V

-55R

Speed Options

Full Voltage Range: V = 2.7–3.6 V

-70

-90

-120

120

Max access time, ns (t

)

ACC

Max CE# access time, ns (t

)

Max OE# access time, ns (t

)

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ7

Sector Switches

Erase Voltage

Generator

Input/Output

Buffers

State

Control

WE#

Command

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

Detector

Timer

Cell Matrix

X-Decoder

A0–A17

2/9/98

Am29LV102B

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

3 2 1 32 31 30

A14

A13

A11

OE#

A10

CE#

DQ7

DQ0

16 17

19 20

32-Pin PLCC

21259A-2

Am29LV102B

2/9/98

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

A11

OE#

A10

CE#

A13

A14

A17

WE#

V_CC

A16

A15

A12

DQ7

DQ6

DQ5

DQ4

DQ3

V_SS

DQ2

DQ1

DQ0

32-pin Standard TSOP

A11

OE#

A10

CE#

A13

A14

A17

WE#

V_CC

A16

A15

A12

DQ7

DQ6

DQ5

DQ4

DQ3

V_SS

DQ2

DQ1

DQ0

32-Pin Reverse TSOP

21259A-3

2/9/98

Am29LV102B

A D V A N C E I N F O R M A T I O N

PIN CONFIGURATION

LOGIC SYMBOL

A0–A17

= 18 address inputs

DQ0–DQ7 = 8 data inputs/outputs

A0–A17

CE#

OE#

WE#

V_CC

Chip enable

Output enable

Write enable

DQ0–DQ7

CE#

OE#

3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

WE#

V_SS

Device ground

Am29LV102B

2/9/98

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29LV102B

-55R

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

32-Pin Plastic Leaded Chip Carrier (PL 032)

32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV102B

2 Megabit (256 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

JC, JI, EC, EI, FC, FI

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

Am29LV102B-55R

Am29LV102B-70

Am29LV102B-90

Am29LV102B-120

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

2/9/98

Am29LV102B

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