AM29LV008B-100_技术文档

PRELIMINARY

Am29LV008T/Am29LV008B

8 Megabit (1,048,576 x 8-Bit) CMOS 3.0 Volt-only,

Sectored Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Embedded Algorithms

— Extended voltage range: 2.7 to 3.6 volt read and

write operations for battery-powered

applications

— Embedded Erase algorithms automatically

preprogram and erase the entire chip or any

combination of designated sectors

— Standard voltage range: 3.0 to 3.6 volt read and

write operations and for compatibility with high

performance 3.3 volt microprocessors

— Embedded Program algorithms automatically

write and verify bytes or words at speciﬁed

addresses

■ High performance

■ Minimum 100,000 write cycle guarantee per

sector

— Extended voltage range:access times as fast as

100 ns

■ Package option

— Standard voltage range: access times as fast as

90 ns

— 40-pin TSOP

■ Compatibility with JEDEC standards

■ Ultra low power consumption

— Automatic Sleep Mode: 200 nA typical

— Standby mode: 200 nA typical

— Read mode: 2 mA/MHz typical

— Program/erase mode: 20 mA typical

■ Flexible sector architecture

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

ﬁfteen 64 Kbyte sectors

■ Ready/Busy pin

— Provides a hardware method of detecting

program or erase cycle completion

— Supports control code and data storage on a

single device

■ Erase suspend/resume feature

— Sector Protection features:

— Provides the ability to suspend the erase

operation in any sector, read data from or

program data to any other sector, then return to

the original sector and complete the initial erase

operation

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■ Hardware reset pin (RESET)

■ Top or bottom boot block conﬁgurations

— Hardware method to reset the device to the read

mode

available

GENERAL DESCRIPTION

The Am29LV008 is an 8 Mbit, 3.0 Volt-only Flash mem-

ory organized as 512 Kbytes of 8 bits each. For ﬂexible

erase and program capability, the 512 Kbits of data is

divided into 19 sectors of one 16 Kbyte, two 8 Kbyte,

one 32 Kbyte, and ﬁfteen 64 Kbytes. The data appears

on DQ0–DQ7. The Am29LV008 is offered in a 40-pin

TSOP package. This device is designed to be pro-

grammed in-system with the standard system 3.0 volt

V

supply. The device can also be reprogrammed in

CC

standard EPROM programmers.

The Am29LV008 provides two levels of performance.

The ﬁrst level offers access times as fast as 100 ns with

a V

range as low as 2.7 volts, which is optimal for

CC

battery powered applications.The second level offers a

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 20511 Rev: C Amendment/+1

Issue Date: May 1997

P R E L I M I N A R Y

90 ns access time, optimizing performance in systems

The Am29LV008 device also features hardware sector

protection, implemented via external programming

equipment, which disables both program and erase op-

erations in any combination of the memory sectors.

where the power supply is in the regulated range of 3.0

to 3.6 volts.To eliminate bus contention, the device has

separate chip enable (CE), write enable (WE), and

output enable (OE) controls.

The Erase Suspend feature enables the user to pause

the erase operation, for any period of time, to read data

from or program data to a sector that was not being

erased. Thus, true background erase can be achieved.

The Am29LV008 is entirely command set-compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write cy-

cles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The device features 3.0 volt, single-power-supply oper-

ation for both read and write functions. Internally gen-

erated and regulated voltages are provided for the

program and erase operations. A low V detector au-

CC

tomatically inhibits write operations during power tran-

sitions. The end of program or erase is detected by the

RY/BY pin. Data Polling of DQ7, or by the Toggle Bit

(DQ6). Once the end of a program or erase cycle has

been completed, the device automatically resets to the

read mode.

The Am29LV008 is programmed by executing the pro-

gram command sequence.This invokes the Embedded

Program Algorithm, which is an internal algorithm that

automatically times the program pulse widths and veri-

ﬁes proper cell margin.The device is erased by execut-

ing the erase command sequence. This invokes the

Embedded Erase Algorithm, which is an internal algo-

rithm that automatically preprograms the array, if it is

not already programmed, before executing the erase

operation. During erase, the device automatically times

the erase pulse widths and veriﬁes proper cell margin.

The Am29LV008 also has a hardware RESET pin.

When this pin is driven low, execution of any Embed-

ded Program or Erase Algorithm will be terminated.

The internal state machine is then be reset into the

read mode. Resetting the device will enable the sys-

tem’s microprocessor to read the boot-up ﬁrmware

from the Flash memory.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The Am29LV008 memory electrically erases

all bits within a sector simultaneously via Fowler-

Nordheim tunneling. The bytes are programmed one

byte at a time using the EPROM programming mecha-

nism of hot electron injection.

This device also features a sector erase architecture.

This allows for sectors of memory to be erased and re-

programmed without affecting the data contents of

other sectors. A sector is typically erased and veriﬁed

within 1.0 second. The Am29LV008 is fully erased

when shipped from the factory.

2

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Family Part Number

Am29LV008T/Am29LV008B

Ordering Part Number:

V

= 3.0–3.6 V

= 2.7–3.6 V

-90R

CC

V

-100

100

40

-120

120

50

-150

150

55

CC

Max access time (ns)

CE access time (ns)

OE access time (ns)

90

40

BLOCK DIAGRAM

RY/BY

DQ0–DQ7

Sector

V

CC

Switches

SS

Input/Output

Buffers

Erase Voltage

Generator

RESET

State

Control

WE

BYTE

Command

Register

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

Data Latch

STB

CE

OE

Y-Decoder

Y-Gating

STB

V

Detector

Timer

CC

X-Decoder

Cell Matrix

A0–A19

20511C-1

Am29LV008T/Am29LV008B

3

P R E L I M I N A R Y

CONNECTION DIAGRAMS

A17

V_SS

NC

A16

A15

A14

A13

A12

A11

A9

1

2

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A19

A10

DQ7

DQ6

DQ5

DQ4

V_CC

A8

WE

RESET

NC

RY/BY

A18

A7

9

10

11

12

13

14

15

16

17

18

19

20

NC

DQ3

DQ2

DQ1

DQ0

OE

V_SS

A6

A5

A4

A3

A2

A1

CE

A0

Standard 40-Pin TSOP

A17

V_SS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

A16

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A15

A14

A13

A12

A11

A9

NC

A19

A10

DQ7

DQ6

DQ5

DQ4

V_CC

NC

DQ3

DQ2

DQ1

DQ0

A8

WE

RESET

NC

RY/BY

A18

A7

A6

A5

A4

A3

CE

V_SS

CE

A0

A2

A1

Reverse 40-Pin TSOP

20511C-2

4

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

PIN CONFIGURATION

LOGIC SYMBOL

A0–A19

= 20 addresses

20

A0–A19

DQ0–DQ7 = 8 data inputs/outputs

8

DQ0–DQ7

CE

= Chip enable

OE

= Output enable

CE (E)

OE (G)

WE

= Write enable

RESET

RY/BY

= Hardware reset pin, active low

= Ready/Busy output

WE (W)

RESET

RY/BY

V

= Standard voltage range

(3.0 V to 3.6 V) for -90R

CC

Extended voltage range

(2.7 to 3.6 V) for -100, -120, -150

20511C-3

V

= Device ground

SS

NC

= Pin not connected internally

Am29LV008T/Am29LV008B

5

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29LV008

T

-90R

E

C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

SPEED OPTION

-xxx = 2.7 to 3.6 V V

-xxR= 3.0 to 3.6 V V

CC

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV008

8 Megabit (1 M x 8-Bit) CMOS Flash Memory

3.0 Volt-only Program and Erase

Valid Combinations

Valid Combinations list conﬁgurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

ofﬁce to conﬁrm availability of speciﬁc valid combinations and

to check on newly released combinations.

Am29LV008T-90R,

Am29LV008B-90R

EC, EI, FC, FI

V

= 3.0–3.6 V

CC

Am29LV008T-100,

Am29LV008B-100

Am29LV008T-120,

Am29LV008B-120

EC, EI, EE, EEB,

FC, FI, FE, FEB

Am29LV008T-150,

Am29LV008B-150

6

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

Table 1. Am29LV008 User Bus Operations

Operation

CE

OE

WE

A0

A1

A6

A9

DQ0–DQ7

RESET

Autoselect, Manufacturer Code

(Note 1)

L

H

L

V

Code

H

ID

Autoselect, Device Code (Note 1)

Read

L

H

A0

X

L

A1

X

L

A6

X

V

Code

RD

H

ID

H

A9

X

Standby

H

L

X

H

X

HIGH Z

PD (Note 2)

Code

Output Disable

H

X

Write

L

A0

L

A1

H

A6

L

A9

Enable Sector Protect (Note 3)

Verify Sector Protect (Note 4)

Temporary Sector Unprotect

Reset

L

V

Pulse/H

V

ID

L

H

X

L

H

L

V

Code

ID

X

V

ID

X

HIGH Z

L

Legend:

L = V , H = V , V = 12.0 V ± 5%, X = Don’t care. See “DC Characteristics” on page 26 for voltage levels.

IL

IH ID

PD = program data, RD = read data. Refer to Table 3 on page 10 for more information.

Notes:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5 on page 13.

2. Refer to Table 5 for valid PD during a write operation.

3. Set V = 3.0 volts ± 10%.

CC

4. Refer to “Sector Protection” on page 12.

Am29LV008T/Am29LV008B

7

P R E L I M I N A R Y

USER BUS OPERATIONS

Read Mode

Deselecting CE (CE and RESET = V

± 0.3 V) puts

CC

the device into the I

standby mode. If the device is

CC3

The Am29LV008 has three control functions which

must be satisﬁed in order to obtain data at the outputs:

deselected during an Embedded Algorithm operation,

it continues to draw active power (I ) prior to entering

CC2

■ CE is the power control and should be used for de-

the standby mode, until the operation is complete.

vice selection (CE = V )

When the device is again selected (CE = V ), active

IL

operations occur in accordance with the AC timing

speciﬁcations.

■ OE is the output control and should be used to gate

data to the output pins if the device is selected

(OE = V )

IL

Automatic Sleep Mode

■ WE remains at V

IH

Advanced power management features such as the

automatic sleep mode minimize Flash device energy

consumption. This is extremely important in

battery-powered applications. The Am29LV008 auto-

matically enables the low-power, automatic sleep

mode when addresses remain stable for 200 ns. Auto-

matic sleep mode is independent of the CE, WE, and

OE control signals. Typical sleep mode current draw is

200 nA (for CMOS-compatible operation). Standard

address access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

Address access time (T

stable addresses to valid output data. The chip enable

) is equal to the delay from

ACC

access time (T ) is the delay from stable addresses

CE

and stable CE to valid data at the output pins. The out-

put enable access time (T ) is the delay from the fall-

ing edge of OE to valid data at the output pins

(assuming the addresses have been stable at least

OE

T

– T time).

ACC

OE

Standby Mode

The Am29LV008 is designed to accommodate low

standby power consumption by applying the following

voltages to the CE and RESET pins: I

compatible I/Os (current consumption <5 µA max.) is

enabled when a CMOS logic level ‘1’ (V ± 0.3 V) is

applied to the CE control pin with RESET = V ± 0.3

Output Disable

for CMOS

CC3

If the OE input is at a logic high level (V ), output from

IH

the device is disabled.This will cause the output pins to

be in a high impedance state.

CC

V.While in the I

standby mode, the data I/O pins re-

CC3

main in the high impedance state independent of the

voltage level applied to the OE input. See the DC Char-

acteristics section for more details on Standby Modes.

8

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

Am29LV008 is erased or programmed in a system with-

Autoselect

out access to high voltage on the A9 pin.The command

sequence is illustrated in Table 5 on page 13.

The Autoselect mode allows the reading out of a binary

code from the device and will identify its manufacturer

and type.The intent is to allow programming equipment

to automatically match the device to be programmed

with its corresponding programming algorithm.The Au-

toselect command may also be used to check the sta-

tus of write-protected sectors (see Table 2). This mode

is functional over the entire temperature range of the

device.

Byte 0 (A0 = V ) represents the manufacturer’s code

IL

and byte 1 (A0 = V ) the device identiﬁer code. For the

IH

Am29LV008 these two bytes are given in Table 2. All

identiﬁers for manufacturer and device will exhibit odd

parity with DQ7 deﬁned as the parity bit. In order to

read the proper device codes when executing Autose-

lect, A1 must be V (see Table 2). The device code is

IL

3EH (for top boot block) or 37H (for bottom boot block).

To activate this mode, the programming equipment

must force V (12.0 V ± 5%) on address pin A9. Two

In order to determine which sectors are write protected,

ID

identiﬁer bytes may then be sequenced from the device

A1 must be at V while running through the sector ad-

IH

outputs by toggling address A0 from V to V . All ad-

dresses are don’t cares except A0, A1, and A6 see

Table 2.

dresses; if the selected sector is protected, a logical ‘1’

will be output on DQ0 (DQ0 = 1).

IL

IH

The manufacturer and device codes may also be read

via the command register, for instances when the

Table 2. Autoselect/Sector Protection Codes

Code DQ DQ DQ DQ DQ DQ DQ DQ

Type

A13–A19

A6

A1

A0

(HEX)

7

6

5

4

3

2

1

0

Manufacturer Code: AMD

X

L

01H

3EH

0

1

29LV008 Device

(Top Boot Block)

X

L

H

L

0

1

0

1

0

1

0

1

0

1

0

1

29LV008 Device

(Bottom Boot Block)

37H

Set Sector

Addresses

Sector Protection

H

01H*

X = Don’t care.

* Outputs 01H at protected sector addresses.

Am29LV008T/Am29LV008B

9

P R E L I M I N A R Y

Table 3. Sector Address Tables (Am29LV008T)

A19

0

A18

0

A17

0

A16

0

A15

X

0

A14

X

0

A13

X

0

Sector Size

64 Kbytes

32 Kbytes

8 Kbytes

Address Range

00000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

40000h-4FFFFh

50000h-5FFFFh

60000h-6FFFFh

70000h-7FFFFh

80000h-8FFFFh

90000h-9FFFFh

A0000h-AFFFFh

B0000h-BFFFFh

C0000h-CFFFFh

D0000h-DFFFFh

E0000h-EFFFFh

F0000h-F7FFFh

F8000h-F9FFFh

FA000h-FBFFFh

FC000h-FFFFFh

SA0

SA1

0

1

SA2

0

1

0

SA3

0

1

SA4

0

1

0

SA5

0

1

0

1

SA6

0

1

0

SA7

0

1

SA8

1

0

SA9

1

0

1

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8 Kbytes

1

X

16 Kbytes

10

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

Table 4. Sector Address Tables (Am29LV008B)

A19

0

A18

0

A17

0

A16

0

A15

0

A14

0

A13

X

0

Sector Size

16 Kbytes

8 Kbytes

Address Range

00000h-03FFFh

04000h-05FFFh

06000h-07FFFh

08000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

40000h-4FFFFh

50000h-5FFFFh

60000h-6FFFFh

70000h-7FFFFh

80000h-8FFFFh

90000h-9FFFFh

A0000h-AFFFFh

B0000h-BFFFFh

C0000h-CFFFFh

D0000h-DFFFFh

E0000h-EFFFFh

F0000h-FFFFFh

SA0

SA1

0

1

SA2

0

1

8 Kbytes

SA3

0

1

X

32 Kbytes

64 Kbytes

SA4

0

1

X

SA5

0

1

0

SA6

0

1

SA7

0

1

0

SA8

0

1

0

1

SA9

0

1

0

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Am29LV008T/Am29LV008B

11

P R E L I M I N A R Y

ing them in the improper sequence will reset the

Write

device to the read mode. Table 5 on page 13 deﬁnes

the valid register command sequences. Note that the

Erase Suspend (B0H) and Erase Resume (30H) com-

mands are valid only while the Sector Erase operation

is in progress.

Device erasure and programming are accomplished

via the command register. The command register is

written by bringing WE to V , while CE is at V and OE

IL

is at V . Addresses are latched on the falling edge of

IH

CE or WE, whichever occurs later, while data is latched

on the rising edge of the CE or WE pulse, whichever

occurs ﬁrst. Standard microprocessor write timings are

used.

Read/Reset Command

The device will automatically power up in the read/

reset state. In this case, a command sequence is

not required to read data. Standard microproces-

sor cycles will retrieve array data. This default

value ensures that no spurious alteration of the

memory content occurs during the power transi-

tion. Refer to the AC Characteristics section for the

speciﬁc timing parameters.

Refer to AC Write Characteristics and the Erase/

Programming Waveforms for speciﬁc timing parameters.

Sector Protection

Sectors of the Am29LV008 may be hardware protected

at the user’s factory with external programming equip-

ment.The protection circuitry will disable both program

and erase functions for the protected sectors, making

the protected sectors read-only. Requests to program

or erase a protected sector will be ignored by the de-

vice. If the user attempts to write to a protected sector,

DATA Polling will be activated for about 1 µs; the device

will then return to read mode, with data from the pro-

tected sector unchanged. If the user attempts to erase

a protected sector, Toggle Bit will be activated for about

50 µs; the device will then return to read mode, without

having erased the protected sector.

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data

from the memory. The device remains enabled for

reads until the command register contents are altered.

Autoselect Command

Flash memories are intended for use in applications

where the local CPU alters memory contents. As such,

manufacturer and device codes must be accessible

while the device resides in the target system. The

Am29LV008 contains an autoselect command opera-

tion that provides device information and sector protec-

tion status to the system. The operation is initiated by

writing the autoselect command sequence into the

command register. Following the command write, a

read cycle from address XX00H retrieves the manufac-

turer code of 01H. A read cycle from address XX01H

returns the device code 3EH (for top boot device) or

37H (for bottom boot device); see Table 2 on page 9.

All manufacturer and device codes will exhibit odd par-

ity with the MSB of the lower byte (DQ7) deﬁned as the

parity bit. Scanning the sector addresses (A13, A14,

A15, A16, A17, A18, and A19) while (A6, A1, A0) = (0,

1, 0) will produce a logical ‘1’ code at device output

DQ0 for a write protected sector (See Table 2).

It is possible to determine if a sector is protected in the

system by writing an Autoselect command. Performing

a read operation at the address location XX02H, where

the higher order address A18–A12 represents the sec-

tor address, will produce a logical ‘1’ at DQ0 for a pro-

tected sector.

Temporary Sector Unprotect

The sectors of the Am29LV008 may be temporarily un-

protected by raising the RESET pin to 12.0 volts (V ).

ID

During this mode, formerly protected sectors can be

programmed or erased with standard command se-

quences by selecting the appropriate byte or sector ad-

dresses. Once the RESET pin goes to V , all the

IH

previously protected sectors will be protected again.

To terminate the Autoselect operation, it is neces-

sary to write the read/reset command sequence

into the register.

Command Deﬁnitions

Device operations are selected by writing speciﬁc ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writ-

12

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

Table 5. Am29LV008 Command Deﬁnitions

Second Bus

Read/Write

Cycle

Fourth Bus

Read/Write

Cycle

Command

Sequence

Read/Reset

(Note 2)

Bus

Write

Cycles

First Bus

Write Cycle

Third Bus

Write Cycle

Fifth Bus

Write Cycle Write Cycle

Sixth Bus

Req’d Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset/Read

1

3

XXX

555

F0

RA

RD

55

Autoselect

Manufacturer ID

AA

2AA

555

90

X00

X01

01

3E

Autoselect

Device ID

(Top Boot Block)

3

555

AA

2AA

55

Autoselect

Device ID

(Bottom Boot Block)

555

90

X01

37

Autoselect

Sector Protect Verify

(Note 3)

00

01

SA

X02

Byte Program

Chip Erase

4

6

555

AA

2AA

55

555

A0

80

PA

PD

AA

555

2AA

55

555

SA

10

30

Sector Erase

Erase Suspend

(Note 4)

1

XXX

B0

30

Erase Resume

(Note 5)

Legend:

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WEor CE pulse.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WEor CE pulse.

SA = Address of the sector to be erased or veriﬁed. Address bits A19–A13 uniquely select any sector.

Notes:

1. All values are in hexadecimal.

2. See Table 1 for description of bus operations.

3. The data is 00h for an unprotected sector and 01h for a protected sector.The complete bus address is composed of the sector

address on A19–A13 and 02h on A7–A0.

4. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode. The Erase Suspend command

is valid only during a sector erase operation.

5. The Erase Resume command is valid only during the Erase Suspend mode.

6. Unless otherwise noted, address bits A19–A11 = X = don’t care.

bedded Program Algorithm. Upon executing the

Byte Programming

write command, the system is not required to pro-

The device is programmed on a byte-by-byte basis.

vide further controls or timing. The device will auto-

Programming is a four-bus-cycle operation. There

matically provide adequate internally generated

are two “unlock” write cycles. These are followed by

program pulses and verify the programmed cell

the program command and address/data write cy-

margin.

cles. Addresses are latched on the falling edge of

CE or WE, whichever occurs later, while the data is

latched on the rising edge of CE or WE, whichever

occurs ﬁrst. The rising edge of CE or WE, whichever

occurs ﬁrst, initiates programming using the Em-

The status of the Embedded Program Algorithm op-

eration can be determined three ways:

■ DATA Polling of DQ7

Am29LV008T/Am29LV008B

13

P R E L I M I N A R Y

then following it by additional writes of the Sector Erase

■ Checking the status of the toggle bit DQ6

■ Checking the status of the RY/BY pin

command to addresses of other sectors to be erased.

The time between Sector Erase command writes must

be less than 80 µs, otherwise that command will not be

accepted. It is recommended that processor interrupts

be disabled during this time to guarantee this condition.

The interrupts can be re-enabled after the last Sector

Erase command is written. A time-out of 80 µs from the

rising edge of the last WE (or CE) will initiate the exe-

cution of the Sector Erase command(s). If another fall-

ing edge of the WE (or CE) occurs within the 80 µs

time-out window, the timer is reset. During the 80 µs

window, any command other than Sector Erase or

Erase Suspend written to the device will reset the de-

vice back to Read mode. Once the 80 µs window has

timed out, only the Erase suspend command is recog-

nized. Note that although the Reset command is not

recognized in the Erase Suspend mode, the device is

available for read or program operations in sectors that

are not erase suspended. The Erase Suspended and

Erase Resume commands may be written as often as

required during a sector erase operation. Hence, once

erase has begun, it must ultimately complete unless

Hardware Reset is initiated. Loading the sector erase

registers may be done in any sequence and with any

number of sectors (0 to 18).

Any commands written to the chip during the Em-

bedded Program Algorithm will be ignored. If a

hardware reset occurs during a programming oper-

ation, the data at that location will be corrupted.

Programming is allowed in any sequence and

across sector boundaries. Beware that a data ‘0’

cannot be programmed back to a ‘1’. Attempting to

do so will cause the device to exceed programming

time limits (DQ5 = 1) or result in an apparent suc-

cess according to the data polling algorithm. How-

ever, reading the device after executing the Read/

Reset operation will show that the data is still ‘0’.

Only erase operations can convert ‘0’s to ‘1’s.

Figure 4 illustrates the Embedded Program Algorithm,

using typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two

“unlock” write cycles, followed by writing the erase “set

up” command. Two more “unlock” write cycles are fol-

lowed by the chip erase command.

Chip erase does not require the user to preprogram the

device to all ‘0’s prior to erase. Upon executing the Em-

bedded Erase Algorithm command sequence, the de-

vice automatically programs and veriﬁes the entire

memory to an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations.

Sector erase does not require the user to program the

device prior to erase. The device automatically prepro-

grams all memory locations, within sectors to be

erased, prior to electrical erase. When erasing a sector

or sectors, the remaining unselected sectors or the

write protected sectors are unaffected. The system is

not required to provide any controls or timings during

sector erase operations. The Erase Suspend and

Erase Resume commands may be written as often as

required during a sector erase operation.

The Embedded Erase Algorithm erase begins on the

rising edge of the last WE or CE (whichever occurs

ﬁrst) pulse in the command sequence.The status of the

Embedded Erase Algorithm operation can be deter-

mined three ways:

Automatic sector erase operations begin on the rising

edge of the WE (or CE) pulse of the last sector erase

command issued, and once the 80 µs time-out window

has expired. The status of the sector erase operation

can be determined three ways:

■ DATA Polling of DQ7

■ Checking the status of the toggle bit DQ6

■ Checking the status of the RY/BY pin

Figure 5 illustrates the Embedded Erase Algorithm,

using a typical command sequence and bus opera-

tions.

■ DATA Polling of DQ7

■ Checking the status of the toggle bit DQ6

■ Checking the status of the RY/BY pin

Sector Erase

Further status of device activity during the sector erase

operation can be determined using toggle bits DQ2 and

DQ3.

Sector erase is a six bus cycle operation.There are two

“unlock” writes.These are followed by writing the erase

“set up” command. Two more “unlock” writes are fol-

lowed by the Sector Erase command (30H).The sector

address (any address location within the desired sec-

tor) is latched on the falling edge of WE or CE (which-

ever occurs last) while the command (30H) is latched

on the rising edge of WE or CE (whichever occurs ﬁrst).

Figure 5 illustrates the Embedded Erase Algorithm,

using a typical command sequence and bus opera-

tions.

Erase Suspend

The Erase Suspend command allows the user to inter-

rupt a Sector Erase operation and then perform data

Multiple sectors can be speciﬁed for erase by writing

the six bus cycle operation as described above and

14

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

read or programs in a sector not being erased. This

■ Checking the status of the toggle bit DQ2

■ Checking the status of the RY/BY pin

command is applicable only during the Sector Erase

operation, which includes the time-out period for Sector

Erase. The Erase Suspend command will be ignored if

written during the execution of the Chip Erase opera-

tion or Embedded Program Algorithm (but will reset the

chip if written improperly during the command se-

quences.) Writing the Erase Suspend command during

the Sector Erase time-out results in immediate termina-

tion of the time-out period and suspension of the erase

operation. Once in Erase Suspend, the device is avail-

able for read (note that in the Erase Suspend mode, the

Reset/Read command is not required for read opera-

tions and is ignored) or program operations in sectors

not being erased. Any other command written during

the Erase Suspend mode will be ignored, except for the

Erase Resume command. Writing the Erase Resume

command resumes the sector erase operation.The ad-

dresses are “don’t cares” when writing the Erase Sus-

pend or Erase Resume command.

To resume the operation of Sector Erase, the Resume

command (30H) should be written. Any further writes of

the Resume command at this point will be ignored.

However, another Erase Suspend command can be

written after the device has resumed sector erase op-

erations.

When the erase operation has been suspended, the

device defaults to the erase-suspend-read mode.

Reading data in this mode is the same as reading from

the standard read mode except that the data must be

read from sectors that have not been

erase-suspended.

To resume the operation of Sector Erase, the Resume

command (30H) should be written. Any further writes of

the Resume command at this point will be ignored. An-

other Erase Suspend command can be written after the

chip has resumed erasing.

When the Erase Suspend command is written during a

Sector Erase operation, the chip will take between 0.1

µs and 20 µs to actually suspend the operation and go

into erase suspended read mode (pseudo-read mode),

at which time the user can read or program from a sec-

tor that is not erase suspended. Reading data in this

mode is the same as reading from the standard read

mode, except that the data must be read from sectors

that have not been erase suspended.

Write Operation Status

Address Sensitivity of Write Status Flags

Detailed in Table 6 are all the status ﬂags that can be

used to check the status of the device for current mode

operation. During Sector Erase, the part provides the

status ﬂags automatically to the I/O ports.The informa-

tion on DQ2 is address sensitive. This means that if an

address from an erasing sector is consecutively read,

then the DQ2 bit will toggle. However, DQ2 will not tog-

gle if an address from a non-erasing sector is consec-

utively read. This allows the user to determine which

sectors are erasing and which are not.

Successively reading from the erase-suspended sector

while the device is in the erase-suspend-read mode will

cause DQ2 to toggle. Polling DQ2 on successive reads

from a given sector provides the system the ability to

determine if a sector is in Erase Suspend.

Once Erase Suspend is entered, address sensitivity

still applies. If the address of a non-erasing sector (that

is, one available for read) is provided, then stored data

can be read from the device. If the address of an eras-

ing sector (that is, one unavailable for read) is applied,

the device will output its status bits. Conﬁrmation of sta-

tus bits can be done by doing consecutive reads to tog-

gle DQ2, which is active throughout the Embedded

Erase mode, including Erase Suspend.

After entering the erase-suspend-read mode, the user

can program the device by writing the appropriate com-

mand sequence for Byte Program. This program mode

is known as the erase suspend-program mode. Again,

programming in this mode is the same as programming

in the regular Byte Program mode, except that the data

must be programmed to sectors that are not erase sus-

pended. Successively reading from the erase sus-

pended sector while the device is in the erase

suspend-program mode will cause DQ2 to toggle.

Completion of the erase suspend operation can be de-

termined two ways:

In order to effectively use DATA Polling to determine if

the device has entered into erase-suspended mode, it

is necessary to apply a sector address from a sector

being erased.

Am29LV008T/Am29LV008B

15

P R E L I M I N A R Y

Table 6. Hardware Sequence Flags

Status

DQ7

0

DQ6

DQ5

DQ3

DQ2

RY/BY

Programming

Toggle

0

1

No Toggle

(Note 1)

0

Program/Erase in Auto-Erase

Toggle

(Note 1)

Erase Sector Address

Erase

Suspend

1

No Toggle

Data

0

Data

0

Data

0

1

0

In Progress

Data(Note

2)

Mode

Non-Erase Sector Address

Data

DQ7

(Note 2)

1

Program in Erase Suspend

Toggle

(Note 2)

Programming

DQ7

0

Toggle

1

0

1

0

No Toggle

(Note 3)

0

Exceeded

Time Limits

Program/Erase in Auto-Erase

Program in Erase Suspend

DQ7

No Toggle

Notes:

1. DQ2 can be toggled when the sector address applied is that of an erasing or erase suspended sector.Conversely, DQ2 cannot

be toggled when the sector address applied is that of a non-erasing or non-erase suspended sector. DQ2 is therefore used

to determine which sectors are erasing or erase suspended and which are not.

2. These status ﬂags apply when outputs are read from the address of a non-erase-suspended sector.

3. If DQ5 is high (exceeded timing limits), successive reads from a problem sector will cause DQ2 to toggle.

DQ7: Data Polling

device is driving status information on DQ7 at one in-

stant of time and in the next instance of time, that byte

has valid data. Depending on when the system sam-

ples the DQ7 output, it may read the status or valid

data. Even if the device has completed the Embedded

Algorithm operations and DQ7 has valid data, DQ0–

DQ6 may still provide write operation status. The valid

data on DQ0–DQ7 can be read on the next successive

read attempt.

The Am29LV008 features DATA Polling as a method to

indicate to the host system that the embedded algo-

rithms are in progress or completed.

During the Embedded Program Algorithm, an attempt

to read the device will produce the compliment of the

data last written to DQ7. Upon completion of the Em-

bedded Program Algorithm, an attempt to read the de-

vice will produce the true data last written to DQ7. Note

that just at the instant when DQ7 switches to true data,

the other bits, DQ6–DQ0, may not yet be true data.

However, they will all be true data on the next read from

the device. Please note that Data Polling (DQ7) may

give an inaccurate result when an attempt is made

to write to a protected sector. During an Embedded

Erase Algorithm, an attempt to read the device will pro-

duce a ‘0’ at the DQ7 output. Upon completion of the

Embedded Erase Algorithm, an attempt to read

the device will produce a ‘1’ at DQ7.

The DATA Polling feature is only active during the Em-

bedded Programming Algorithm, Embedded Erase Al-

gorithm, Erase Suspend, erase suspend-program

mode, or sector erase time-out (see Table 6).

If the user attempts to write to a protected sector, DATA

Polling will be activated for about 1 µs; the device will

then return to read mode, with data from the protected

sector unchanged. If the user attempts to erase a pro-

tected sector, Toggle Bit will be activated for about 50

µs; the device will then return to read mode, without

having erased the protected sector.

For chip erase, the DATA Polling is valid (DQ7 = 1) after

the rising edge of the sixth WE pulse in the six write

pulse sequence. For sector erase, the DATA Polling is

valid after the last rising edge of the sector erase WE

pulse. DATA Polling must be performed at sector ad-

dresses within any of the sectors being erased and not

a sector that is within a protected sector. Otherwise, the

status may not be valid.

See Figure 6 for the DATA Polling timing speciﬁcations

and diagrams.

DQ6:Toggle Bit

The Am29LV008 also features a “Toggle Bit” as a

method to indicate to the host system whether the em-

bedded algorithms are in progress or completed.

Just prior to the completion of Embedded Algorithm op-

erations, DQ7 may change asynchronously while the

output enable (OE) is asserted low.This means that the

During an Embedded Program or Erase Algorithm,

successive attempts to read data from the device will

result in DQ6 toggling between one and zero. Once the

16

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

Embedded Program or Erase Algorithm is completed,

If DATA Polling or the Toggle Bit indicates the device

has been written with a valid Sector Erase command,

DQ3 may be used to determine if the sector erase timer

window is still open. If DQ3 is high (‘1’), the internally

controlled erase cycle has begun; attempts to write

subsequent commands to the device will be ignored

until the erase operation is completed as indicated by

the DATA Polling or Toggle Bit. If DQ3 is low (‘0’), the

device will accept additional sector erase commands.

To be certain the command has been accepted, the

software should check the status of DQ3 following each

Sector Erase command. If DQ3 was high on the sec-

ond status check, the command may not have been ac-

cepted.

DQ6 will stop toggling and valid data can be read on

the next successive attempts. During programming, the

Toggle Bit is valid after the rising edge of the fourth WE

pulse in the four-write-pulse sequence. During Chip

erase, the Toggle Bit is valid after the rising edge of the

sixth WE pulse in the six-write-pulse sequence. During

Sector erase, the Toggle Bit is valid after the last rising

edge of the sector erase WE pulse. The Toggle Bit is

active during the Sector Erase time-out.

Either CE or OE toggling will cause DQ6 to toggle. If

the user attempts to write to a protected sector, DATA

Polling will be activated for about 1 µs; the device will

then return to read mode, with data from the protected

sector unchanged. If the user attempts to erase a pro-

tected sector, Toggle Bit will be activated for about 50

µs; the device will then return to read mode, without

having erased the protected sector.

It is recommended that the user guarantee the time be-

tween sector erase command writes be less than 80 µs

by disabling the processor interrupts just for the dura-

tion of the Sector Erase (30H) commands. This ap-

proach will ensure that sequential sector erase

command writes will be written to the device while the

sector erase timer window is still open.

DQ5: Exceeded Timing Limits

DQ5 will indicate if the program or erase time has ex-

ceeded the speciﬁed limits (internal pulse count).

Under these conditions, DQ5 will produce a ‘1’ indicat-

ing that the program or erase cycle was not success-

fully completed. Write operation status and reset

command are the only operating functions under this

condition. The device will draw active power under this

condition.

DQ2:Toggle Bit 2

This toggle bit, along with DQ6, can be used to deter-

mine whether the device is in the Embedded Erase Al-

gorithm or in Erase Suspend.

Successive reads from the erasing sector will cause

DQ2 to toggle during the Embedded Erase Algorithm.

If the device is in the erase-suspend-read mode, suc-

cessive reads from the erase-suspended sector will

cause DQ2 to toggle. When the device is in the erase

suspend-program mode, successive reads from the

byte address of the non-erase suspended sector will in-

dicate a logic‘1’at the DQ2 bit. Note that a sector which

is selected for erase is not available for read in Erase

Suspend mode. Other sectors which are not selected

for Erase can be read in Erase Suspend.

The DQ5 failure condition will also appear if the user at-

tempts to write a data ‘1’ to a bit that has already been

programmed to a data ‘0’. In this case, the DQ5 failure

condition is not guaranteed to happen, since the device

was incorrectly used. Please note that programming a

data ‘0’ to a data ‘1’ should never be attempted, and

only erasure should be used for this purpose. If pro-

gramming to a data ‘1’ is attempted, the device should

be reset.

DQ6 is different from DQ2 in that DQ6 toggles only

when the standard program or erase, or erase

suspend-program operation is in progress.

If the DQ5 failure condition is observed while in Sector

Erase mode (that is, exceeded timing limits), then DQ2

can be used to determine which sector had the prob-

lem. This is especially useful when multiple sectors

have been loaded for erase.

If the DQ5 failure condition is observed while in Sector

Erase mode (that is, exceeded timing limits), the DQ2

toggle bit can give extra information. In this case, the

normal function of DQ2 is modiﬁed. If DQ5 is at logic

‘1’, then DQ2 will toggle with consecutive reads only at

the sector address that caused the failure condition.

DQ2 will toggle at the sector address where the failure

occurred and will not toggle at other sector addresses.

DQ3: Sector Erase Timer

After the completion of the initial Sector Erase com-

mand sequence, the Sector Erase time-out will begin.

DQ3 will remain low until the time-out is complete.

DATA Polling (DQ7) and Toggle Bit (DQ6) are also valid

after the ﬁrst sector erase command sequence.

Am29LV008T/Am29LV008B

17

P R E L I M I N A R Y

Suspend mode, the RY/BY output will be high. For pro-

RY/BY: Ready/Busy Pin

gramming, the RY/BY is valid (RY/BY=0) after the ris-

ing edge of the fourth WE pulse in the four write pulse

sequence. For chip erase, the RY/BY is valid after the

rising edge of the sixth WE pulse in the six write pulse

sequence. For sector erase, the RY/BY is also valid

after the rising edge of the sixth WE pulse.

The Am29LV008 provides a RY/BY open-drain output

pin as a way to indicate to the host system that the Em-

bedded Algorithms are either in progress or have been

completed. If the output is low, the device is busy with

either a program or erase operation. If the output is

high, the device is ready to accept any read/write or

erase operation.When the RY/BY pin is low, the device

will not accept any additional program or erase com-

mands with the exception of the Erase Suspend com-

mand. If the Am29LV008 is placed in an Erase

Since the RY/BY pin is an open-drain output, several

RY/BY pins can be tied together in parallel with a

pull-up resistor to V

.

CC

Table 7. Toggle Bit Status

Mode

DQ7

DQ6

Toggles

1

DQ2

1

Program

Erase

DQ7

0

Toggles

1 (Note 2)

Erase-Suspend Read (Note 1) (Erase-Suspended Sector)

Erase Suspend Program

1

DQ7 (Note 2)

Toggles

Notes:

1. These status ﬂags apply when outputs are read from a sector that has been erase suspended.

2. These status ﬂags apply when outputs are read from the addresses of the non-erase suspended sector.

CE

LAST_BUS_CYCLE

WE

RY/BY

t_BUSY

20511C-4

Figure 1. RY/BY Timing Diagram

18

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

ecuting (RY/BY pin is high), the reset operation will be

RESET: Hardware Reset Pin

complete within 500 ns.

The RESET pin is an active low signal. A logic ‘0’ on

this pin will force the device out of any mode that is cur-

rently executing back to the reset state. This allows a

system reset to take effect immediately without having

to wait for the device to ﬁnish a long execution cycle.To

avoid a potential bus contention during a system reset,

the device is isolated from the data I/O bus by tri-stating

the data output pins for the duration of the RESET

pulse.

Asserting RESET during a program or erase operation

leaves erroneous data stored in the address locations

being operated on at the time of device reset.These lo-

cations need updating after the reset operation is com-

plete. See Figure 2 for timing speciﬁcations.

The device enters I

standby mode (200 nA) when

CC4

V

± 0.3V is applied to the RESET pin.The device can

SS

enter this mode at any time, regardless of the logical

condition of the CE pin. Furthermore, entering I

If RESET is asserted during a program or erase oper-

ation, the RY/BY pin will remain low until the reset op-

eration is internally complete.This will require between

1 µs and 20 µs. Hence the RY/BY pin can be used to

signal that the reset operation is complete. Otherwise,

allow for the maximum reset time of 20 µs. If RESET is

asserted when a program or erase operation is not ex-

CC4

during a program or erase operation leaves erroneous

data in the address locations being operated on at the

time of the RESET pulse. These locations need updat-

ing after the device resumes standard operations. After

the RESET pin goes high, a minimum latency period of

50 ns must occur before a valid read can take place.

t_RL

RESET

RY/BY

t_RRB

20511C-5

Figure 2. Device Reset During a Program or Erase Operation

t_RP

RESET

RY/BY

0 V

20511C-6

Figure 3. Device Reset During Read Mode

Am29LV008T/Am29LV008B

19

P R E L I M I N A R Y

Data Protection

Write Pulse “Glitch” Protection

The Am29LV008 is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tions. During power-up, the device automatically resets

the internal state machine to the read mode. Also, with

its control register architecture, alteration of the mem-

ory contents only occurs after successful completion of

the command sequences.

Noise pulses of less than 5 ns (typical) on OE, CE, or

WE will not change the command registers.

Logical Inhibit

Writing is inhibited by holding any one of OE = V , CE

IL

= V , or WE = V .To initiate a write, CE and WE must

IH

be logical zero while OE is a logical one.

Power-Up Write Inhibit

The Am29LV008 incorporates several features to pre-

Power up of the device with WE = CE = V and OE =

IL

vent inadvertent write cycles resulting from V

CC

V

will not accept commands on the rising edge of WE.

IH

power-up and power-down transitions or system noise.

The internal state machine is automatically reset to

read mode on power up.

Low V Write Inhibit

CC

To avoid initiation of a write cycle during V power-up

CC

and power-down, a write cycle is locked out for V

CC

less than V

(lock-out voltage). If V

< V

, the

LKO

CC

LKO

command register is disabled and all internal program/

erase circuits are disabled. Under this condition, the

device will reset to read mode. Subsequent writes will

be ignored until the V level is greater than V

. It is

CC

LKO

the user’s responsibility to ensure that the control levels

are logically correct when V is above V

(unless

CC

LKO

the RESET pin is asserted).

20

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

EMBEDDED ALGORITHMS

Embedded Program Algorithm

START

Write Program Cmd Sequence

Data Poll Device

No

Verify Byte?

Yes

No

Increment Address

Last Address?

Yes

Programming Completed

20511C-7

Figure 4. Embedded Program Algorithm

Bus Operation

Standby*

Write

Command Sequence

Comments

Program

Valid Address/Data

Read

DATA Polling to Verify Programming

Compare Data Output to Data Expected

Standby*

* Device is either powered-down, erase inhibit, or program inhibit.

Am29LV008T/Am29LV008B

21

P R E L I M I N A R Y

Embedded Erase Algorithm

START

Write Erase Cmd Sequence

Data Poll from Device

No

Data = FFH?

Yes

Erasure Completed

20511C-8

Figure 5. Embedded Erase Algorithm

Bus Operation

Standby

Write

Command Sequence

Comments

Erase

Read

DATA Polling to Verify Erasure

Compare Output to FFH

Standby

22

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

Data Polling Algorithm

START

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

DQ7 = Data?

No

FAIL

PASS

20511C-9

Figure 6. Data Polling Algorithm

Am29LV008T/Am29LV008B

23

P R E L I M I N A R Y

Toggle Bit Algorithm

START

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

No

DQ6 = Toggle?

Yes

FAIL

PASS

20511C-10

Figure 7. Toggle Bit Algorithm

Temporary Sector Unprotect Algorithm

Start

RESET = V

(Note 1)

ID

Perform Erase or

Program Operations

RESET = V

IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

20511C-11

Figure 8. Temporary Sector Unprotect Algorithm

24

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature

Commercial (C) Devices

Plastic Packages . . . . . . . . . . . . . . . -65°C to +150°C

Ambient Temperature (T ). . . . . . . . . . . . 0˚C to +70˚C

A

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . -55°C to +125°C

Industrial (I) Devices

Ambient Temperature (T ). . . . . . . . . . –40˚C to +85˚C

A

Voltage with Respect to Ground

All pins except A9, OE and RESET

Extended (E) Devices

(Note 1) . . . . . . . . . . . . . . . . . . . . -0.5 V to V +0.5 V

Ambient Temperature (T ). . . . . . . . . –55˚C to +125˚C

A

CC

V

(Note 1). . . . . . . . . . . . . . . . . . . . -0.5 V to +3.6 V

V

Supply Voltages

CC

A9, OE, and RESET (Note 2). . . . . . -0.5 V to +13.0 V

for Am29LV008T/B-90R. . . . . . . . +3.0 V to 3.6 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

for Am29LV008T/B-100,

-120, -150 . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5 V. During

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

voltage transitions, input or I/O pins may undershoot V

SS

to -2.0 V for periods of up to 20 ns. Maximum DC voltage

on input or I/O pins is V_CC+0.5 V. During voltage

transitions, input or I/O pins may overshoot to V +2.0 V

CC

for periods up to 20 ns. See Tables 10 and 11.

2. Minimum DC input voltage on pins A9, OE, and RESET is

-0.5 V. During voltage transitions, A9, OE, and RESET

may undershoot V to -2.0 V for periods of up to 20 ns.

SS

Maximum DC input voltage on pin A9 is +12.5 V which

may overshoot to 14.0 V for periods up to 20 ns. See

Tables 10 and 11.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

4. Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the de-

vice at these or any other conditions above those indi-

cated in the operational sections of this data sheet is not

implied. Exposure of the device to absolute maximum rat-

ing conditions for extended periods may affect device re-

liability.

Am29LV008T/Am29LV008B

25

P R E L I M I N A R Y

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

= V to V , V = V

CC max

Min

Max

Unit

I

Input Load Current

V

±1.0

µA

LI

IN

SS

CC CC

V

= V

;

CC

CC max

I

A9 Input Load Current

Output Leakage Current

35

µA

LIT

A9 = 13.0 V

= V to V , V = V

CC max

I

V

±1.0

16

4

µA

mA

LO

OUT

SS

CC CC

CE = V OE

V

at 5 MHz

IL,

=

IH

V

Active Current

CC

I

CC1

(Note 1)

CE = V OE

V

at 1 MHz

IL,

V

Active Current

CC

I

CE = V OE

30

5

mA

µA

CC2

IL,

=

IH

(Notes 1, 2, and 4)

V

= V

;

CC

CC max

V

Standby Current

CC3

CC

CE, RESET = V ± 0.3 V

CC

V

= V

; CE = V ± 0.3 V;

CC

CC max CC

I

V

Standby Current During Reset

5

CC4

RESET = V ± 0.3 V

SS

Automatic Sleep Mode (Note 3)

Input Low Voltage

V

= V ± 0.3 V; V = V ± 0.3 V

5

µA

V

CC5

IH

CC

IL

SS

V

-0.5

0.8

IL

V

Input High Voltage

0.7 x V

V + 0.3

CC

V

IH

CC

Voltage for Autoselect andTemporary

Sector Unprotect

V

= 3.3 V

11.5

12.5

0.45

V

ID

CC

V

Output Low Voltage

I

= 4.0 mA, V = V

V

OL

CC

CC min

V

I

= -2.0 mA, V = V

0.85 V

OH1

OH

CC

CC min

CC

Output High Voltage

V

= -100 µA, V = V

V

-0.4

OH2

CC

CC min

CC

V

Low V Lock-Out Voltage (Note 4)

2.3

2.5

V

LKO

CC

Notes:

1. The I current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The

CC

frequency component typically is less than 2 mA/MHz, with OEat V

.

IH

2. I active while Embedded Erase or Embedded Program is in progress.

CC

3. Automatic sleep mode enables the low power mode when addresses remain stable for 200 ns. Typical sleep mode current is

200 nA.

4. Not 100% tested.

26

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

DC CHARACTERISTICS (CONTINUED)

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

20511C-11A

Figure 8A.

I

Current vs.Time

CC

15

10

5

0

1

2

3

Frequency in MHz

4

5

Note: T = 25 °C

20511C-11B

Figure 8B.

I

vs. Frequency

CC

Am29LV008T/Am29LV008B

27

P R E L I M I N A R Y

AC CHARACTERISTICS

Read-Only Operations Characteristics

Parameter Symbols

Speed Option (Note 1)

JEDEC Standard Description

Test Setup

Min

-90R -100

-120

-150

Unit

t

Read Cycle Time (Note 3)

Address to Output Delay

90

100

120

150

ns

AVAV

RC

CE = V

IL

t

Max

120

150

ns

AVQV

ACC

OE = V

IL

t

Chip Enable to Output Delay

OE = V

Max

90

40

30

100

40

120

50

150

55

ns

ELQV

GLQV

EHQZ

GHQZ

CE

OE

DF

IL

Output Enable to Output Delay

Chip Enable to Output High Z (Notes 2, 3)

Output Enable to Output High Z (Notes 2, 3)

30

40

30

40

Output Hold Time From Addresses, CE or

OE, Whichever Occurs First (Note 3)

t

Min

0

ns

AXQX

OH

RESET Pin Low to Read Mode (Note 3)

Max

20

µs

Ready

Notes:

1. Test Conditions

Input Rise and Fall Times: 5 ns

Input Pulse Levels: 0.0 V to 3.0 V

Timing Measurement Reference Level:

Input: 1.5 V

Output: 1.5 V

2. Output Driver Disable Time

3. Not 100% tested.

3.3 V

IN3064

or Equivalent

2.7 kΩ

Device

Under

Test

C

L

6.2 kΩ

IN3064 or Equivalent

Notes:

C = 30 pF for 90 and 100 ns

L

C = 100 pF for 120 and 150 ns

L

20511C-12

Figure 9. Test Conditions

28

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

AC CHARACTERISTICS

Write (Erase/Program) Operations

Parameter Symbols

JEDEC

Standard Description

-90R

90

0

-100

100

0

-120

120

0

-150

150

0

Unit

ns

t

Write Cycle Time (Note 2)

Min

AVAV

WC

AS

Address Setup Time

Address Hold Time

ns

AVWL

WLAX

DVWH

WHDX

50

0

50

0

50

0

65

0

ns

AH

Data Setup Time

ns

DS

Data Hold Time

ns

DH

OES

Output Enable Setup Time (Note 2)

0

ns

Read (Note 2)

Output

0

ns

t

Enable Hold

Time

OEH

Toggle and Data Polling

(Note 2)

Min

10

0

10

0

10

0

10

0

ns

Read Recovery Time Before Write

(OE High to WE Low)

t

GHWL

t

CE Setup Time

Min

Typ

Min

Max

0

ns

µs

sec

µs

ns

µs

ns

µs

ELWL

CS

CE Hold Time

WHEH

WLWH

WHWL

WHWH1

WHWH2

CH

Write Pulse Width

50

30

9

50

30

9

50

30

9

65

35

9

WP

Write Pulse Width High

Programming Operation

Sector Erase Operation (Note 1)

WPH

WHWH1

WHWH2

VCS

RB

1

V

Setup Time

50

0

50

0

50

0

50

0

CC

Write Recovery Time from RY/BY

RESET High Time Before Read

RESET To Power Down Time

50

20

90

500

20

50

20

90

500

20

50

20

90

500

20

50

20

90

500

20

RH

RPD

BUSY

VIDR

RP

Program/Erase Valid to RY/BY Delay

Rise Time to V

ID

RESET Pulse Width

RESET Low to RY/BY High

RRB

RESET Setup Time for Temporary Sector

Unprotect

t

Min

4

µs

RSP

Notes:

1. The duration of the program or erase operation is variable and is calculated in the internal algorithms.

2. Note 100% tested.

Am29LV008T/Am29LV008B

29

P R E L I M I N A R Y

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Must be

Steady

Will be

Steady

May

Change

from H to L

Will be

Changing

from H to L

May

Change

from L to H

Will be

Changing

from L to H

Don’t Care,

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center

Line is High-

Impedance

“Off” State

KS000010-PAL

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

20511C-13

Figure 10. Maximum Negative Overshoot Waveform

20 ns

V

+ 2.0 V

CC

V

+ 0.5 V

CC

2.0 V

20 ns

20511C-14

Figure 11. Maximum Positive Overshoot Waveform

30

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

SWITCHING WAVEFORMS

t_RC

Addresses Stable

t_ACC

Addresses

CE

t_DF

t_OE

OE

t_OEH

t_CE

WE

t_OH

HIGH Z

Output Valid

Outputs

20511C-15

Figure 12. AC Waveforms for Read Operations

Data Polling

t_AS

t_WC

ADDRESSES

555H

PA

t_AH

t_RC

CE

OE

t_GHWL

t_WP

t_{WHWH1_or_2}

WE

t_DF

t_CS

t_WPH

t_DS

t_OE

t_DH

DQ7

D_OUT

A0H

PD

DATA

V_CC

t_OH

t_CE

t_VCS

Notes:

1. DQ7 is the output of the complement of the data written to the device.

2. D is the output of the data written to the device.

OUT

3. PA is the address of the memory location to be programmed.

4. PD is the data to be programmed at the byte address.

5. Illustration shows the last two cycles of a four-bus-cycle sequence..

20511C-16

Figure 13. AC Waveforms for Program Operations

Am29LV008T/Am29LV008B

31

P R E L I M I N A R Y

SWITCHING WAVEFORMS

t_WC

t_AS

555H for chip erase

ADDRESSES

555H

AAAH

555H

AAAH

SA

t_AH

CE

OE

WE

t_GHWL

t_WP

t_CS

t_DS

t_WPH

10H for Chip Erase

t_DH

DATA

V_CC

55H

80H

AAH

55H

30H

AAH

Note:

1. SA is the sector address for Sector Erase.

20511C-17

Figure 14. AC Waveforms for Chip/Sector Erase Operations

t_CH

CE

OE

t_DF

t_OE

t_OEH

WE

t_CE

t_OH

*

HIGH Z

DQ7=Valid Data

DQ7

t_{WHWH1_or_2}

DQ0-DQ6=Invalid Data

DQ0-DQ6

DQ0-DQ6 Valid Data

* DQ7 = Valid Data (The device has completed the embedded operation.)

20511C-18

Figure 15. AC Waveforms for Data Polling During Embedded Algorithm Operations

32

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

SWITCHING WAVEFORMS

CE

t_OEH

WE

t_OES

OE

*

DQ0-DQ7

Data Valid

Data (DQ0-DQ7)

DQ6=Toggle

DQ6=Stop Toggling

t_OE

DQ6 stops toggling (The device has completed the embedded operation.)

20511C-19

Figure 16. AC Waveforms for Toggle Bit During Embedded Algorithm Operations

CE

The rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

t

BUSY

DQ7 = Valid Data (The device has completed the embedded operation.)

20511C-20

Figure 17. RY/BY Timing Diagram During Program/Erase Operations

RESET

t

RP

t

Ready

20511C-21

Figure 18. RESET Timing Diagram

Am29LV008T/Am29LV008B

33

P R E L I M I N A R Y

SWITCHING WAVEFORMS

t

VIDR

12 V

RESET

0 V or 3 V

CE

WE

t

RSP

Program or Erase Command Sequence

20511C-22

Figure 19. Temporary Sector Unprotect Timing Diagram

34

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

AC CHARACTERISTICS

Write (Erase/Program) Operations

Alternate CE Controlled Writes

Parameter Symbols

JEDEC

Standard Description

-90R

90

0

-100

100

0

-120

120

0

-150

150

0

Unit

ns

t

Write Cycle Time (Note 1)

Min

AVAV

AVEL

ELAX

DVEH

EHDX

WC

AS

Address Setup Time

Address Hold Time

Data Setup Time

ns

50

0

50

0

50

0

65

0

ns

AH

ns

DS

Data Hold Time

ns

DH

OES

Output Enable Setup Time

0

ns

Read (Note 1)

0

ns

Output Enable

Hold Time

t

OEH

Toggle and Data Polling

(Note 1)

Min

10

0

10

0

10

0

10

0

ns

Read Recovery Time Before Write

(OE High to WE Low)

t

GHEL

t

WE Setup Time

Min

Typ

0

ns

WLEL

WS

WE Hold Time

EHWH

ELEH

WH

CE Pulse Width

50

30

9

50

30

9

50

30

9

65

35

9

ns

CP

CE Pulse Width High

Programming Operation

Sector Erase Operation (Note 3)

ns

EHEL

CPH

µs

sec

WHWH1

WHWH2

WHWH1

WHWH2

1

Notes:

1. Not 100% tested.

2. The duration of the program or erase operation is variable and is calculated in the internal algorithms.

3. Does not include the preprogramming time.

Am29LV008T/Am29LV008B

35

P R E L I M I N A R Y

SWITCHING WAVEFORMS

Data Polling

t_WC

555H

t_AS

PA

ADDRESSES

PA

t_AH

WE

OE

t_GHWL

t_CP

t_{WHWH1_or_2}

CE

t_WS

t_CPH

t_DS

t_DH

DQ7

D_OUT

A0H

PD

DATA

V_CC

t_VCS

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ7 is the complement of the data written to the device.

4. D

is the data written to the device.

OUT

5. Figure indicates last two bus cycles of four bus cycle sequence.

20511C-23

Figure 20. Alternate CE Controlled Write Operation Timings

36

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 2)

Max (Note 3)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

1

19

9

15

Excludes 00h programming

prior to erasure (Note 4)

s

Byte Programming Time

Chip Programming Time

300

27

µs

s

Excludessystemleveloverhead

(Note 5)

9

Minimum 100,000 cycles

guaranteed

Erase/Program Endurance

1,000,000

cycles

Notes:

1. The typical program and erase times are considerably less than the maximum times since most bytes program or erase

signiﬁcantly faster than the worst case byte.The device enters the failure mode (DQ5=“1”) only after the maximum times given

are exceeded. See the section on DQ5 for further information.

2. Except for erase and program endurance, the typical program and erase times assume the following conditions: 25°C, 3.0 V

V

, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern.

CC

3. Under worst case conditions of 90˚C, V = 2.7 V, 100,000 cycles.

CC

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5

for further information on command deﬁnitions.

LATCHUP CHARACTERISTICS

Min

Max

Input voltage with respect to V on all pins except I/O pins

(including A9, OE, and RESET)

SS

-1.0 V

13.0 V

Input voltage with respect to V on all I/O pins

-1.0 V

V

+ 1.0 V

SS

CC

V

Current

-100 mA

+100 mA

CC

Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.

CC

TSOP PIN CAPACITANCE (Notes 1–2)

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

Typ

6

Max

7.5

12

Unit

pF

C

V

= 0

IN

C

Output Capacitance

Control Pin Capacitance

V

= 0

8.5

7.5

pF

OUT

C

V

= 0

9

pF

IN2

IN

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25˚C, f = 1.0 MHz.

A

Am29LV008T/Am29LV008B

37

P R E L I M I N A R Y

sector protect verify. Added note 3 to explain sector

protect codes. In Note 8, changed A13 to A11, added

“unless otherwise noted”; is now new Note 6.

DATA SHEET REVISION SUMMARY FOR

AM29LV008

Distinctive Characteristics:

RESET: Hardware Reset Pin:

Rearranged bullets. Renamed “2.7 to 3.6 volt, ex-

tended voltage range...” to “Single power supply opera-

tion.” Under “Single power supply operation” and “High

performance” bullets, deﬁned standard and extended

voltage ranges and added 90 ns speed option. Com-

bined “Advanced power management” and “Low cur-

rent consumption” bullets into new “Ultra low power

consumption” bullet. Under that bullet, revised the typ-

ical standby and automatic sleep mode current speciﬁ-

cations from 1 µA to 200 nA; revised read current

speciﬁcation from 10 mA to 2 mA/MHz. Combined

“Sector protection” and “Flexible sector architecture”

bullets. Under ﬂexible sector architecture bullet, added

temporary sector unprotect feature description. Com-

bined Embedded Program and Embedded Erase bul-

lets under new “Embedded Algorithms” bullet; removed

™ designations. Clariﬁed descriptions of sector protec-

tion, erase suspend/resume, hardware reset pin,

ready/busy pin, and data polling and toggle bits.

Fourth paragraph: Revised standby mode speciﬁcation

to 200 nA.

Operating Ranges:

V

Supply Voltages: Added 3.0 to 3.6 V voltage range

CC

and -90R speed option.

DC Characteristics:

CMOS Compatible: Changed I

from 30 mA maxi-

CC1

mum at 6 MHz to 16 mA maximum at 5 MHz and 4 mA

maximum at 1 MHz. Changed I from 35 mA to 30

CC2

mA maximum. In the V speciﬁcation, changed the

OL

I

test condition from 5.8 to 4.0 mA. In Note 1,

OL

changed 6 MHz to 5 MHz. In Note 3, changed address

stable time from 300 ns to 200 ns; changed typical au-

tomatic sleep mode current from 1 µA to 200 nA.

Figure 8A, I Current vs.Time, and Figure 8B, I

CC

vs. Frequency:

Figure 8A illustrates current draw during the Automatic

Sleep Mode after the addresses are stable. Figure 8B

shows how frequency affects the current draw curves

for both voltage ranges.

General Description:

Added text on new speed option and voltage range to

the second paragraph.

Product Selector Guide:

AC Characteristics:

Added -90R voltage range and speed option.

Read Only Operations Characteristics: Added -90R

column.

Pin Conﬁguration:

Added new voltage range for -90R to V speciﬁcation.

Test Conditions, Figure 9:

CC

Ordering Information, Standard Products:

Added 90 ns speed to C note.

L

The -90R speed option is now listed in the example.

Revised “Speed Option” section to indicate both volt-

age ranges.

AC Characteristics:

Write/Erase/Program Operations: Added the -90R col-

umn.

Valid Combinations: Added -90R speed option and

voltage range.

Figure 13, AC Waveforms for Program Operations:

Changed 5555H to 555H in addresses waveform to

match command deﬁnitions (Table 5).

Automatic Sleep Mode:

Revised addresses stable time to 200 ns and current

draw to 200 nA.

Figure 14, AC Waveforms for Chip/Sector Erase

Operations:

Table 5, Command Deﬁnitions:

Changed 5555H to 555H in addresses waveform to

match command deﬁnitions (Table 5).

Grouped address designators PA, PD, RA, RD, and SA

under the legend heading. Modiﬁed SA deﬁnition to ac-

commodate the sector protect verify command. Since

unlock addresses only require address bits A0–A10 to

be valid, the number of hexadecimal digits in the unlock

addresses were changed from four to three. The re-

maining upper address bits are don’t care. Removed

“H” designation from hexadecimal values in table and

replaced with new Note 1. Revised Notes 5 and 6 to in-

dicate when commands are valid; are now new Notes

4 and 5. Expanded autoselect section to show each

function separately: manufacturer ID, device ID, and

Figure 19,Temporary Sector Unprotect Diagram:

Corrected callouts on RESET waveform to “0 V or 3 V”.

AC Characteristics:

Alternate CE Controlled Writes: Added the -90R col-

umn. Changed t from 45 to 50 ns for -100, from 50 to

AH

65 ns for -150. Changed t from 50 to 65 ns for -150.

DS

Changed t from 45 to 50 ns for -100, from 50 to 65

CP

ns for -150. Changed t

from 20 to 30 ns for -100, -

CPH

120; from 20 to 35 ns for -150.

38

Am29LV008T/Am29LV008B

P R E L I M I N A R Y

Figure 20, Alternate CE Controlled Write Operation

cycle endurance is minimum, not typical. Revised Note

1 to include write endurance; moved Note 1 references

in table to table head. Consolidated and moved Note 1

and Note 3 references in table to table head. Combined

Note 2 and Note 5 into new Note 1, which applies to the

entire table; revised to indicate that DQ5=1 after any

maximum time. Comments for program and erase now

straddle parameter rows. Separated the two sentences

in Note 4 into new Notes 4 and 5; added corresponding

note references to comment section.

Timings:

Changed 5555H to 555H in addresses waveform to

match command deﬁnitions (Table 5).

Erase and Programming Performance:

Added typical chip erase speciﬁcation. Renamed

erase/program cycles speciﬁcation to erase/program

endurance. Corrected to indicate 1,000,000 cycle en-

durance is typical, not maximum, and that 100,000

Am29LV008T/Am29LV008B

39


型号：	AM29LV008B-100
厂家：	AMD
描述：	8 Megabit (1,048,576 x 8-Bit) CMOS 3.0 Volt-only, Sectored Flash Memory 8兆位（ 1,048,576 ×8位） CMOS 3.0伏只，扇形闪存闪存
文件：	总39页 (文件大小：143K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV008B-100 [AMD]

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