AM29F800BT-55FEB [AMD]
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory; 8兆位（ 1一M× 8位/ 512的K× 16位） CMOS 5.0伏只，引导扇区闪存
| 型号： | AM29F800BT-55FEB |
| 厂家： | 
AMD |
| 描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| 文件： | 总39页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Top or bottom boot block configurations
available
— 5.0 Volt-only operation for read, erase, and
program operations
■ Embedded Algorithms
— Minimizes system level requirements
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
■ Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29F800 device
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ High performance
— Access times as fast as 55 ns
■ Minimum 1,000,000 program/erase cycles per
■ Low power consumption (typical values at 5
sector guaranteed
MHz)
■ Package option
— 48-pin TSOP
— 44-pin SO
— 1 µA standby mode current
— 20 mA read current (byte mode)
— 28 mA read current (word mode)
— 30 mA program/erase current
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power-supply Flash
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Provides a software method of detecting
program or erase operation completion
— Supports full chip erase
■ Ready/Busy# pin (RY/BY#)
— Sector Protection features:
— Provides a hardware method of detecting
program or erase cycle completion
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
■ Erase Suspend/Erase Resume
Sectors can be locked via programming
equipment
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
Publication# 21504 Rev: C Amendment/+1
Issue Date: April 1998
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29F800B is an 8 Mbit, 5.0 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 44-pin SO and 48-pin
TSOP packages. The word-wide data (x16) appears on
DQ15–DQ0; the byte-wide (x8) data appears on DQ7–
DQ0. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply.
A 12.0 V VPP is not required for write or erase opera-
tions. The device can also be programmed in standard
EPROM programmers.
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
This device is manufactured using AMD’s 0.35 µm
process technology, and offers all the features and ben-
efits of the Am29F800, which was manufactured using
0.5 µm process technology.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 55, 70, 90,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
Hardware data protection measures include a low
detector that automatically inhibits write opera-
VCC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost
effectiveness. The device electrically erases all
b i t s w i t h i n a s e c t o r s i m u l t a n e o u s l y v i a
Fo w l e r -No r d h e i m tu n n e l i n g . T h e d a t a i s
programmed using hot electron injection.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
2
Am29F800B
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F800B
V
= 5.0 V ± 5%
= 5.0 V ± 10%
-55
CC
Speed Option
V
-70
-90
90
90
35
-120
120
120
50
-150
150
150
55
CC
Max access time, ns (t
)
55
55
30
70
70
30
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
)
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A0–A18
21504C-1
Am29F800B
3
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
VCC
WE#
RESET#
NC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
48-Pin TSOP—Standard Pinout
1
2
3
4
5
6
7
8
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
OE#
VSS
CE#
A0
48-Pin TSOP—Reverse Pinout
21504C-2
4
Am29F800B
P R E L I M I N A R Y
CONNECTION DIAGRAMS
SO
RY/BY#
1
2
3
4
5
6
7
8
9
44 RESET#
43 WE#
42 A8
A18
A17
A7
41 A9
A6
40 A10
A5
39 A11
A4
38 A12
A3
37 A13
A2
36 A14
A1 10
A0 11
35 A15
34 A16
CE# 12
VSS 13
33 BYTE#
32 VSS
OE# 14
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
31 DQ15/A-1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
21504C-3
PIN CONFIGURATION
LOGIC SYMBOL
A0–A18
= 19 addresses
19
DQ0–DQ14 = 15 data inputs/outputs
A0–A18
16 or 8
DQ15/A-1
=
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
DQ0–DQ15
(A-1)
BYTE#
CE#
=
=
=
=
=
=
=
Selects 8-bit or 16-bit mode
Chip enable
CE#
OE#
OE#
Output enable
WE#
WE#
Write enable
RESET#
BYTE#
RESET#
RY/BY#
VCC
Hardware reset pin, active low
Ready/Busy# output
RY/BY#
+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
21504C-4
VSS
NC
=
=
Device ground
Pin not connected internally
Am29F800B
5
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am29F800B
T
-70
E
C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E
F
S
=
=
=
48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to be sup-
Valid Combinations
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29F800BT-55,
Am29F800BB-55
EC, EI, FC, FI, SC, SI
Am29F800BT-70,
Am29F800BB-70
Am29F800BT-90,
Am29F800BB-90
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
Am29F800BT-120,
Am29F800BB-120
Am29F800BT-150,
Am29F800BB-150
6
Am29F800B
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F800B Device Bus Operations
DQ8–DQ15
BYTE# BYTE#
Operation
CE#
L
OE# WE#
RESET#
A0–A18
DQ0–DQ7
= V
= V
IH
IL
Read
Write
L
H
X
X
H
X
H
L
H
H
A
A
D
D
High-Z
High-Z
IN
IN
OUT
OUT
L
D
D
IN
IN
CMOS Standby
TTL Standby
V
± 0.5 V
X
X
H
X
V
± 0.5 V
CC
X
High-Z
High-Z
High-Z
High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
CC
H
L
H
H
L
X
X
X
Output Disable
Hardware Reset
X
Temporary Sector Unprotect
(See Note)
X
X
X
V
A
D
D
IN
X
ID
IN
IN
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, D = Data In, D
= Data Out, A = Address In
IN
IL
IH
ID
IN
OUT
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and control-
led by CE# and OE#.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables in-
dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the en-
tire chip, or suspending/resuming the erase operation.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
Am29F800B
7
P R E L I M I N A R Y
After the system writes the autoselect command se-
In the DC Characteristics tables, ICC3 represents the
standby current specification.
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of tRP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac-
teristics section for timing diagrams.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS
0.5 V, the device enters the CMOS standby mode.
±
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at VCC ± 0.5 V. (Note
that this is a more restricted voltage range than VIH.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device re-
quires standard access time (tCE) for read access when
the device is in either of these standby modes, before it
is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, “RE-
SET#: Hardware Reset Pin”.
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
Output Disable Mode
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
8
Am29F800B
P R E L I M I N A R Y
Table 2. Am29F800BT Top Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector Size
(Kbytes/
(x16)
(x8)
Sector A18
A17
0
A16
0
A15
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Kwords)
Address Range
Address Range
SA0
SA1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7BFFFh
7C000h–7CFFFh
7D000h–7DFFFh
7E000h–7FFFFh
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–EFFFFh
F0000h–F7FFFh
F8000h–F9FFFh
FA000h–FBFFFh
FC000h–FFFFFh
0
0
1
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
SA7
1
1
1
SA8
0
0
0
SA9
0
0
1
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
8/4
1
1
1
1
1
X
16/8
Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.
Am29F800B
9
P R E L I M I N A R Y
Table 3. Am29F800BB Bottom Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector Size
(Kbytes/
(x16)
(x8)
Sector A18
A17
0
A16
0
A15
0
A14
0
A13
0
A12
X
0
Kwords)
Address Range
Address Range
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
16/8
8/4
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–EFFFFh
F0000h–FFFFFh
0
0
0
0
1
SA2
0
0
0
0
1
1
8/4
SA3
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA4
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
0
1
0
SA6
0
1
1
SA7
1
0
0
SA8
1
0
1
SA9
1
1
0
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require VID. See
“Command Definitions” for details on using the autose-
lect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi-
tion, when verifying sector protection, the sector ad-
10
Am29F800B
P R E L I M I N A R Y
Table 4. Am29F800B Autoselect Codes (High Voltage Method)
A18 A11
to to
Mode CE# OE# WE# A12 A10 A9
A8
to
A7
A5
to
A2
DQ8
to
DQ15
DQ7
to
DQ0
Description
A6
A1
A0
Manufacturer ID: AMD
L
L
L
L
H
H
X
X
V
X
X
L
X
X
L
L
X
01h
D6h
ID
Device ID:
Am29F800B
(Top Boot Block)
Word
Byte
Word
Byte
22h
X
X
V
L
L
L
L
H
H
ID
L
L
L
L
L
L
H
H
H
X
22h
X
D6h
58h
58h
Device ID:
Am29F800B
(Bottom Boot Block)
X
X
X
V
V
X
X
X
X
ID
01h
(protected)
X
X
Sector Protection Verification
L
L
H
SA
L
H
L
ID
00h
(unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously pro-
tected sectors.
START
RESET# = V
(Note 1)
ID
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 20374. Contact an
AMD representative to obtain a copy of the appropriate
document.
Perform Erase or
Program Operations
RESET# = V
IH
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Temporary Sector
Unprotect
Completed (Note 2)
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
21504C-5
Notes:
1. All protected sectors unprotected.
Temporary Sector Unprotect
2. All previously protected sectors are protected once
again.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system.
The Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly pro-
tected sectors can be programmed or erased by se-
lecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algo-
rithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
Figure 1. Temporary Sector Unprotect Operation
Am29F800B
11
P R E L I M I N A R Y
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO
Hardware Data Protection
.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Sus-
pend/Erase Resume Commands” for more information
on this mode.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
12
Am29F800B
P R E L I M I N A R Y
the operation and set DQ5 to “1”, or cause the Data#
Autoselect Command Sequence
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires VID on address bit A9.
START
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
Write Program
Command Sequence
Data Poll
from System
A read cycle at address XX00h or retrieves the manu-
facturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) re-
turns 01h if that sector is protected, or 00h if it is un-
protected. Refer to the Sector Address tables for valid
sector addresses.
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
The system must write the reset command to exit the
autoselect mode and return to reading array data.
No
Increment Address
Last Address?
Yes
Word/Byte Program Command Sequence
The system may program the device by byte or word,
on depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically provides internally gen-
erated program pulses and verify the programmed cell
margin. The Command Definitions take shows the ad-
dress and data requirements for the byte program com-
mand sequence.
Programming
Completed
21504C-6
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the device has reset to read-
ing array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
Am29F800B
13
P R E L I M I N A R Y
reset during the chip erase operation immediately ter-
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no longer latched.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa-
tion on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
14
Am29F800B
P R E L I M I N A R Y
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
START
Write Erase
Command Sequence
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
21504C-7
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
Am29F800B
15
P R E L I M I N A R Y
Table 5. Am29F800B Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data Addr Data Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
RD
F0
Word
Byte
Word
Byte
Word
Byte
2AA
555
2AA
555
2AA
555
555
AAA
555
Manufacturer ID
4
4
4
AA
AA
AA
55
55
55
90
90
90
X00
01
AAA
555
X01 22D6
Device ID,
Top Boot Block
AAA
555
AAA
555
X02
X01
X02
D6
2258
58
Device ID,
Bottom Boot Block
AAA
AAA
XX00
XX01
00
(SA)
X02
Word
Byte
555
2AA
555
555
Sector Protect Verify
(Note 9)
4
AA
55
90
(SA)
X04
AAA
AAA
01
Word
Byte
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
2AA
555
555
AAA
555
Program
4
6
6
AA
AA
AA
55
55
55
A0
80
80
PA
PD
AA
AA
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
55
55
10
30
AAA
555
AAA
555
AAA
Sector Erase
SA
AAA
XXX
XXX
AAA
AAA
Erase Suspend (Note 10)
Erase Resume (Note 11)
1
1
B0
30
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17–A12 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
8. The fourth cycle of the autoselect command sequence is a
read cycle.
2. All values are in hexadecimal.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles.
10. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
5. Address bits A17–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array
data.
11. The Erase Resume command is valid only during the Erase
Suspend mode.
7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
16
Am29F800B
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 6 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
START
Read DQ7–DQ0
Addr = VA
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
Yes
DQ7 = Data?
No
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 µs, then the device returns to reading
array data.
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
21504C-8
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
Figure 4. Data# Polling Algorithm
following read cycles. This is because DQ7
DQ0 on the
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
Am29F800B
17
P R E L I M I N A R Y
The Write Operation Status table shows the outputs for
RY/BY#: Ready/Busy#
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC
.
DQ2: Toggle Bit II
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
Table 6 shows the outputs for RY/BY#. The timing dia-
grams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can read array data on DQ7–DQ0 on the following
read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
18
Am29F800B
P R E L I M I N A R Y
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).
START
Read DQ7–DQ0
DQ5: Exceeded Timing Limits
Read DQ7–DQ0
(Note 1)
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
No
Toggle Bit
= Toggle?
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Yes
No
DQ5 = 1?
Yes
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
(Notes
1, 2)
Read DQ7–DQ0
Twice
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50 µs. See also the “Sector Erase Command Se-
quence” section.
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 6 shows the outputs for DQ3.
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
21504C-9
Figure 5. Toggle Bit Algorithm
Am29F800B
19
P R E L I M I N A R Y
Table 6. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 1)
DQ6
(Note 2)
DQ3
N/A
1
(Note 1)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
20
Am29F800B
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
+0.8 V
Voltage with Respect to Ground
–0.5 V
–2.0 V
VCC (Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V
20 ns
All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
21504C-10
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot V
to –2.0 V for periods of up to 20 ns. See Figure 6.
Figure 6. Maximum Negative Overshoot
Waveform
SS
Maximum DC voltage on input or I/O pins is V
+0.5 V.
CC
During voltage transitions, input or I/O pins may overshoot
to V +2.0 V for periods up to 20 ns. See Figure 7.
CC
20 ns
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
V
CC
RESET# may undershoot V to –2.0 V for periods of up
SS
+2.0 V
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to +13.5 V for periods
up to 20 ns.
V
CC
+0.5 V
2.0 V
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
20 ns
20 ns
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to absolute maximum rating conditions for extend-
ed periods may affect device reliability.
21504C-11
Figure 7. Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for ± 5% devices. . . . . . . . . . .+4.75 V to +5.25 V
VCC for± 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Am29F800B
21
P R E L I M I N A R Y
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Description
Input Load Current
Test Conditions
= V to V , V = V
CC max
Min
Typ
Max
±1.0
35
Unit
µA
I
V
V
V
LI
IN
SS
CC CC
I
A9 Input Load Current
Output Leakage Current
= V ; A9 = 12.5 V
CC max
µA
LIT
CC
OUT
I
= V to V , V = V
CC max
±1.0
µA
LO
SS
CC CC
CE# = V OE#
V
V
= V
,
,
IL,
=
IH, CC
CC max
19
19
36
0.4
40
50
60
mA
mA
mA
mA
f = 5 MHz, Byte Mode
CE# = V OE# V V
IH, CC
V
Active Read Current
CC
I
CC1
(Note 1)
= V
IL,
=
CC max
f = 5 MHz, Word Mode
V
Active Write Current
CC
I
I
CE# = V OE# V
V
= V
CC2
CC3
IL,
=
IH, CC
CC max
(Notes 2 and 3)
CE#, OE#, and RESET# = V
IH,
V
Standby Current
1
CC
V
= V
,
CC
CC max
V
Input Low Voltage
Input High Voltage
–0.5
2.0
0.8
V
V
IL
V
CC
V
V
IH
+ 0.5
12.5
0.45
Voltage for Autoselect and
Temporary Sector Unprotect
V
= 5.0 V
= 5.8 mA, V = V
CC min
11.5
V
ID
CC
V
Output Low Voltage
Output High Voltage
I
I
V
V
OL
OL
CC
V
= –2.5 mA, V = V
CC min
2.4
3.2
OH
OH
CC
Low V Lock-Out Voltage
CC
V
4.2
V
LKO
(Note 3)
Notes:
1. The I current listed is typically less than 2 mA/MHz, with OE# at V
.
IH
CC
2. I active while Embedded Erase or Embedded Program is in progress.
CC
3. Not 100% tested.
22
Am29F800B
P R E L I M I N A R Y
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
= V to V
Min
Typ
Max
Unit
V
V
,
IN
SS
CC
I
Input Load Current
±1.0
µA
LI
= V
CC
CC max
V
= V
;
CC max
CC
I
A9 Input Load Current
Output Leakage Current
35
µA
µA
LIT
A9 = 12.5 V
V
V
= V to V
= V
,
CC
OUT
CC
SS
I
±1.0
LO
CC max
CE# = V OE#
V
IH,
IL,
=
V
= V
, f = 5 MHz
20
28
40
mA
mA
CC
CC max
Byte Mode
I
V
V
Active Read Current
Active Write Current
CC1
CC
CE# = V OE#
V
IH,
IL,
=
V
= V
, f = 5 MHz
50
50
CC
CC max
Word Mode
CE# = V OE#
V ,
IH
CC
IL,
=
I
I
30
mA
µA
CC2
CC3
(Notes 1 and 2)
V
= V
CC CC max
CE# and RESET# = V ±0.5 V,
OE# = V , V = V
CC
CC max
V
Standby Current
0.3
5
CC
IH
CC
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
V
0.7 x V
V
+ 0.3
CC
IH
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
= 5.0 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 5.8 mA, V = V
CC min
V
V
V
OL
OL
OH
OH
CC
V
= –2.5 mA, V = V
0.85 V
CC
OH1
OH2
CC
CC min
CC min
Output High Voltage
V
= –100 µA, V = V
V
–0.4
CC
CC
Low V Lock-Out Voltage
(Note 2)
CC
V
3.2
4.2
V
LKO
Notes:
1. I active while Embedded Erase or Embedded Program is in progress.
CC
2. Not 100% tested.
Am29F800B
23
P R E L I M I N A R Y
TEST CONDITIONS
Table 7. Test Specifications
All
5.0 V
Test Condition
-55
others
Unit
2.7 kΩ
Device
Under
Test
Output Load
1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
L
30
5
100
20
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
ns
0.0–3.0 0.45–2.4
V
Input timing measurement
reference levels
1.5
1.5
0.8, 2.0
0.8, 2.0
V
V
Note:
Output timing measurement
reference levels
Diodes are IN3064 or equivalents.
21504C-12
Figure 8. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
24
Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std Description
Test Setup
-55
-70
-90
-120 -150 Unit
t
t
Read Cycle Time (Note 1)
Address to Output Delay
Min
55
70
70
90
120
120
150
150
ns
ns
AVAV
RC
CE# = V
OE# = V
IL
IL
t
t
Max
55
90
AVQV
ACC
t
t
t
Chip Enable to Output Delay
Output Enable to Output Delay
OE# = V
Max
Max
55
30
70
30
90
35
120
50
150
55
ns
ns
ELQV
GLQV
CE
IL
t
t
OE
Chip Enable to Output High Z (Note
1)
t
Max
20
20
20
20
20
30
30
35
35
ns
EHQZ
GHQZ
DF
DF
Output Enable to Output High Z
(Note 1)
t
t
Max
Min
Min
20
0
ns
ns
ns
Read
Output Enable
t
Hold Time
(Note 1)
OEH
Toggle and
Data# Polling
10
Output Hold Time From Addresses,
CE# or OE#, Whichever Occurs
First (Note 1)
t
t
Min
0
ns
AXQX
OH
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
21504C-13
Figure 9. Read Operations Timings
Am29F800B
25
P R E L I M I N A R Y
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
t
Max
20
µs
READY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
t
Max
500
ns
READY
t
t
t
RESET# Pulse Width
Min
Min
Min
500
50
0
ns
ns
ns
RP
RH
RB
RESET# High Time Before Read (See Note)
RY/BY# Recovery Time
Note:
Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
21504C-14
Figure 10. RESET# Timings
26
Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Std.
Description
-55
-70
-90
5
-120 -150 Unit
t
t
t
t
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
Max
Max
Min
ns
ELFL/ ELFH
20
55
20
70
20
90
30
35
ns
ns
FLQZ
FHQV
120
150
CE#
OE#
BYTE#
t
ELFL
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
BYTE#
Switching
from word
to byte
DQ0–DQ14
DQ15/A-1
Address
Input
DQ15
Output
mode
t
FLQZ
t
ELFH
BYTE#
BYTE#
Switching
from byte
to word
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
DQ15/A-1
mode
Address
Input
DQ15
Output
t
FHQV
21504C-15
Figure 11. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
t
SET
(t
)
AS
t
(t
)
HOLD AH
Note:
Refer to the Erase/Program Operations table for t and t specifications.
AS
AH
21504C-16
Figure 12. BYTE# Timings for Write Operations
Am29F800B
27
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase/Program Operations
Parameter
JEDEC
Std.
Description
-55
-70
-90
90
0
-120 -150 Unit
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
55
70
120
150
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
AVWL
WLAX
DVWH
WHDX
AS
AH
DS
DH
t
t
45
25
45
30
45
45
0
50
50
50
50
t
t
t
t
t
t
Data Hold Time
t
Output Enable Setup Time
0
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
Min
0
ns
GHWL
GHWL
t
t
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Min
0
0
ns
ns
ns
ns
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
CE# Hold Time
t
t
t
Write Pulse Width
Write Pulse Width High
30
35
45
20
7
50
50
t
WPH
Byte
t
t
Programming Operation (Note 2)
µs
WHWH1
WHWH2
WHWH1
Word
12
1
t
t
Sector Erase Operation (Note 2)
sec
µs
WHWH2
t
V
Setup Time (Note 1)
50
0
VCS
CC
t
Recovery Time from RY/BY#
ns
RB
t
Program/Erase Valid to RY/BY# Delay
30
30
35
50
55
ns
BUSY
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
28
Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
21504C-17
Notes:
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Figure 13. Program Operation Timings
Am29F800B
29
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tGHWL
tCH
OE#
WE#
tWP
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
21504C-13
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 14. Chip/Sector Erase Operation Timings
30
Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
Complement
High Z
High Z
DQ7
Valid Data
Complement
Status Data
True
DQ0–DQ6
Status Data
True
Valid Data
tBUSY
RY/BY#
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
21504C-18
Figure 15. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
RY/BY#
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
21504C-19
Figure 16. Toggle Bit Timings (During Embedded Algorithms)
Am29F800B
31
P R E L I M I N A R Y
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the
erase-suspended sector.
21504C-20
Figure 17. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std.
Description
Rise and Fall Time (See Note)
All Speed Options
Unit
t
V
Min
Min
500
ns
VIDR
ID
RESET# Setup Time for Temporary Sector
Unprotect
t
4
µs
RSP
Note: Not 100% tested.
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
21504C-21
Figure 18. Temporary Sector Unprotect Timing Diagram
32
Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
Std.
Description
-55
-70
-90
90
0
-120
-150
Unit
ns
t
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
55
70
120
150
AVAV
AVEL
ELAX
DVEH
EHDX
WC
t
ns
AS
AH
DS
DH
t
t
45
25
45
30
45
45
0
50
50
50
50
ns
t
t
t
ns
t
Data Hold Time
ns
t
Output Enable Setup Time
0
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
WLEL
GHEL
t
t
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
Typ
0
0
ns
ns
ns
ns
WS
t
EHWH
WH
t
t
CE# Pulse Width
CE# Pulse Width High
30
35
45
20
7
50
50
ELEH
EHEL
CP
t
t
CPH
Byte
Word
Programming Operation
(Note 2)
t
t
µs
WHWH1
WHWH1
12
1
t
t
Sector Erase Operation (Note 2)
sec
WHWH2
WHWH2
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Am29F800B
33
P R E L I M I N A R Y
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D
= Array Data.
21504C-22
OUT
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
Figure 19. Alternate CE# Controlled Write Operation Timings
34
Am29F800B
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 3)
Unit
s
Comments
Sector Erase Time
1.0
19
7
8
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time (Note 2)
Byte Programming Time
Word Programming Time
s
300
500
µs
µs
s
12
7.2
6.3
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
21.6
18.6
Chip Programming Time
(Note 2)
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V V , 1,000,000 cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 4.5 V (4.75 V for -55), 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to V on all pins except I/O pins
(including A9, OE#, and RESET#)
SS
–1.0 V
12.5 V
Input voltage with respect to V on all I/O pins
–1.0 V
V
+ 1.0 V
CC
SS
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 5.0 V, one pin at a time.
CC
CC
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
Typ
6
Max
7.5
12
Unit
pF
C
V
= 0
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8.5
7.5
pF
OUT
OUT
C
V
= 0
IN
9
pF
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
Am29F800B
35
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package (measured in millimeters)
44
23
13.10
13.50
15.70
16.30
1
22
1.27 NOM.
TOP VIEW
28.00
28.40
0.10
0.21
2.17
2.45
2.80
MAX.
0°
8°
SEATING
PLANE
0.60
1.00
0.35
0.50
0.10
0.35
END VIEW
SIDE VIEW
16-038-SO44-2
SO 044
DF83
8-8-96 lv
36
Am29F800B
P R E L I M I N A R Y
PHYSICAL DIMENSIONS (continued)
TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
16-038-TS48-2
TS 048
DT95
0.08
0.20
0.10
0.21
1.20
MAX
8-8-96 lv
0°
5°
0.25MM (0.0098") BSC
0.50
0.70
TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
SEATING PLANE
16-038-TS48
TSR048
DT95
0.08
0.20
8-8-96 lv
1.20
MAX
0.10
0.21
0°
5°
0.25MM (0.0098") BSC
0.50
0.70
Am29F800B
37
P R E L I M I N A R Y
Erase and Programming Performance
REVISION SUMMARY FOR AM29F800B
Corrected word and chip programming times.
Revision B
Revision C
Global
Global
Added -55 speed option. Changed data sheet designa-
tion from Advance Information to Preliminary.
Formatted for consistency with other 5.0 volt-only data
sheets.
Sector Protection/Unprotection
Revision C+1
Corrected text to indicate that these functions can only
be implemented using programming equipment.
Distinctive Characteristics
Table 1, Device Bus Operations
Changed typical program/erase current to 30 mA to
match the CMOS DC Characteristics table.
Revised to indicate inputs for both CE# and RESET#
are required for standby mode.
Changed minimum endurance to 1 million write cycles
per sector guaranteed.
Program Command Sequence
Changed to indicate Data# Polling is active for 2 µs
after a program command sequence if the sector spec-
ified is protected.
AC Characteristics
Erase/Program Operations: Corrected the notes refer-
ence for tWHWH1 and tWHWH2. These parameters are
100% tested. Changed tDS and tCP specifications for 55
ns device. Changed tWHWH1 word mode specification
to 12 µs.
Sector Erase Command Sequence and DQ3: Sector
Erase Timer
Corrected sector erase timeout to 50 µs.
Alternate CE# Controlled Erase/Program Operations:
Erase Suspend Command
Corrected the notes reference for tWHWH1 and tWHWH2
.
Changed to indicate that the device suspends the
erase operation a maximum of 20 µs after the rising
edge of WE#.
These parameters are 100% tested. Changed tDS and
tCP specifications for 55 ns device. Changed tWHWH1
word mode specification to 12 µs.
DC Characteristics
Temporary Sector Unprotect Table
Changed to indicate VID min and max values are 11.5
to 12.5 V, with a VCC test condition of 5.0 V. Added
typical values to TTL table. Revised CMOS typical
standby current (ICC3).
Added note reference for tVIDR. This parameter is not
100% tested.
Erase and Programming Performance
In Notes 1 and 6, changed the endurance specification
to 1 million cycles.
Figure 14: Chip/Sector Erase Operation Timings;
Figure 19: Alternate CE# Controlled Write
Operation TImings
Corrected hexadecimal values in address and data
waveforms. In Figure 19, corrected data values for chip
and sector erase.
38
Am29F800B
P R E L I M I N A R Y
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29F800B
39
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