AM29F800BB-120EK_技术文档

Am29F800B

Data Sheet

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 21504 Revision E Amendment 5 Issue Date November 2, 2006

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29F800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Embedded Algorithms

— 5.0 Volt-only operation for read, erase, and

program operations

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Minimizes system level requirements

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29F800 device

■ Minimum 1,000,000 program/erase cycles per

■ High performance

sector guaranteed

— Access times as fast as 55 ns

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package option

■ Low power consumption (typical values at

5 MHz)

— 1 µA standby mode current

— 48-pin TSOP

— 20 mA read current (byte mode)

— 28 mA read current (word mode)

— 30 mA program/erase current

— 44-pin SO

— 48-ball FBGA

— Known Good Die (KGD)

(see publication number 21631)

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power-supply Flash

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)

— Superior inadvertent write protection

— Supports full chip erase

■ Data# Polling and toggle bits

— Sector Protection features:

— Provides a software method of detecting

program or erase operation completion

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

— Sectors can be locked via programming

equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■ Top or bottom boot block configurations

available

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21504 Rev: E Amendment: 5

Issue Date: November 2, 2006

D A T A S H E E T

GENERAL DESCRIPTION

The Am29F800B is an 8 Mbit, 5.0 volt-only Flash

memory organized as 1,048,576 bytes or 524,288

words. The device is offered in 44-pin SO, 48-pin

TSOP, and 48-ball FBGA packages. The device is also

available in Known Good Die (KGD) form. For more

information, refer to publication number 21631. The

word-wide data (x16) appears on DQ15–DQ0; the

byte-wide (x8) data appears on DQ7–DQ0. This device

is designed to be programmed in-system with the stan-

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data

or accept another command.

dard system 5.0 volt V

supply. A 12.0 V V is not

CC

PP

required for write or erase operations. The device can

also be programmed in standard EPROM program-

mers.

This device is manufactured using AMD’s 0.32 µm

process technology, and offers all the features and ben-

efits of the Am29F800, which was manufactured using

0.5 µm process technology.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

The standard device offers access times of 55, 70, 90,

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus contention

the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

Hardware data protection measures include a low

V

detector that automatically inhibits write opera-

CC

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved via programming equipment.

The device requires only a single 5.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

serve as input to an internal state-machine that con-

trols the erase and programming circuitry. Write cycles

also internally latch addresses and data needed for the

programming and erase operations. Reading data out

of the device is similar to reading from other Flash or

EPROM devices.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The system can place the device into the standby

mode. Power consumption is greatly reduced in

this mode.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

2

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5

Special Handling Instructions for FBGA Package .................... 6

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9

Table 1. Am29F800B Device Bus Operations ..................................9

Word/Byte Configuration .......................................................... 9

Requirements for Reading Array Data ..................................... 9

Writing Commands/Command Sequences .............................. 9

Program and Erase Operation Status .................................... 10

Standby Mode ........................................................................ 10

RESET#: Hardware Reset Pin ............................................... 10

Output Disable Mode .............................................................. 10

Table 2. Am29F800BT Top Boot Block Sector Address Table .......11

Table 3. Am29F800BB Bottom Boot Block Sector Address Table ..12

Autoselect Mode ..................................................................... 12

Table 4. Am29F800B Autoselect Codes (High Voltage Method) ....13

Sector Protection/Unprotection ............................................... 13

Temporary Sector Unprotect .................................................. 13

Figure 1. Temporary Sector Unprotect Operation........................... 13

Hardware Data Protection ...................................................... 14

Command Definitions . . . . . . . . . . . . . . . . . . . . . .14

Reading Array Data ................................................................ 14

Reset Command ..................................................................... 14

Autoselect Command Sequence ............................................ 15

Word/Byte Program Command Sequence ............................. 15

Figure 2. Program Operation .......................................................... 15

Chip Erase Command Sequence ........................................... 15

Sector Erase Command Sequence ........................................ 16

Erase Suspend/Erase Resume Commands ........................... 16

Figure 3. Erase Operation............................................................... 17

Command Definitions ............................................................. 18

Table 5. Am29F800B Command Definitions ...................................18

Write Operation Status . . . . . . . . . . . . . . . . . . . . .19

DQ7: Data# Polling ................................................................. 19

Figure 4. Data# Polling Algorithm ................................................... 19

RY/BY#: Ready/Busy# ........................................................... 20

DQ6: Toggle Bit I .................................................................... 20

DQ2: Toggle Bit II ................................................................... 20

Reading Toggle Bits DQ6/DQ2 .............................................. 20

DQ5: Exceeded Timing Limits ................................................ 21

DQ3: Sector Erase Timer ....................................................... 21

Figure 5. Toggle Bit Algorithm......................................................... 21

Table 6. Write Operation Status ......................................................22

Absolute Maximum Ratings . . . . . . . . . . . . . . . . .23

Figure 6. Maximum Negative Overshoot Waveform ....................... 23

Figure 7. Maximum Positive Overshoot Waveform......................... 23

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 23

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24

TTL/NMOS Compatible .......................................................... 24

CMOS Compatible .................................................................. 25

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 8. Test Setup....................................................................... 26

Table 7. Test Specifications ........................................................... 26

Key to Switching Waveforms. . . . . . . . . . . . . . . . 26

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27

Read Operations .................................................................... 27

Figure 9. Read Operations Timings ............................................... 27

Hardware Reset (RESET#) .................................................... 28

Figure 10. RESET# Timings .......................................................... 28

Word/Byte Configuration (BYTE#) ........................................ 29

Figure 11. BYTE# Timings for Read Operations............................ 29

Figure 12. BYTE# Timings for Write Operations............................ 29

Erase/Program Operations ..................................................... 30

Figure 13. Program Operation Timings.......................................... 31

Figure 14. Chip/Sector Erase Operation Timings .......................... 32

Figure 15. Data# Polling Timings (During Embedded Algorithms). 33

Figure 16. Toggle Bit Timings (During Embedded Algorithms)...... 33

Figure 17. DQ2 vs. DQ6................................................................. 34

Temporary Sector Unprotect .................................................. 34

Figure 18. Temporary Sector Unprotect Timing Diagram .............. 34

Figure 19. Alternate CE# Controlled Write Operation Timings ...... 36

Erase and Programming Performance . . . . . . . 37

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 37

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 37

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38

SO 044—44-Pin Small Outline Package ................................ 38

TS 048—48-Pin Standard Pinout Thin Small

Outline Package (TSOP) ........................................................ 39

FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm

package .................................................................................. 40

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 41

Revision A (August 1997) ....................................................... 41

Revision B (October 1997) ..................................................... 41

Revision C (January 1998) ..................................................... 41

Revision C+1 (April 1998) ....................................................... 41

Revision C+2 (April 1998) ....................................................... 41

Revision D (January 1999) ..................................................... 42

Revision D+1 (March 23, 1999) .............................................. 42

Revision D+2 (July 2, 1999) ................................................... 42

Revision E (November 16, 1999) ............................................ 42

Revision E+1 (August 4, 2000) ............................................... 42

Revision E+2 (June 4, 2004) .................................................. 42

Revision E3 (December 22, 2005) .......................................... 42

Revision E4 (May 19, 2006) ................................................... 42

Revision E5 (November 2, 2006) ............................................ 42

November 2, 2006 21504E5

Am29F800B

3

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Family Part Number

Am29F800B

Speed Option

V_CC= 5.0 V 10%

-55

55

30

-70

70

30

-90

90

35

-120

120

50

Max access time, ns (t_ACC

)

Max CE# access time, ns (t_CE

)

Max OE# access time, ns (t_OE

)

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

A0–A18

4

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21631 for

more information.

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

A8

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

48-Pin TSOP—Standard Pinout

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

RY/BY#

A18

A17

A7

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

41 A9

A6

40 A10

A5

39 A11

A4

38 A12

A3

37 A13

A2

36 A14

A1 10

A0 11

35 A15

SO

34 A16

CE# 12

V_SS13

33 BYTE#

32 V_SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

November 2, 2006 21504E5

Am29F800B

5

D A T A S H E E T

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21631 for

more information.

FBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

DQ5

DQ12

V_CC

DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY#

NC

A18

NC

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V_SS

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be

compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of

time.

Special Handling Instructions for FBGA

Package

Special handling is required for Flash Memory products

in FBGA packages.

6

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

PIN CONFIGURATION

LOGIC SYMBOL

A0–A18

= 19 addresses

19

DQ0–DQ14 = 15 data inputs/outputs

A0–A18

16 or 8

DQ15/A-1

=

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

DQ0–DQ15

(A-1)

BYTE#

CE#

=

Selects 8-bit or 16-bit mode

Chip enable

CE#

OE#

Output enable

WE#

Write enable

RESET#

BYTE#

RESET#

RY/BY#

Hardware reset pin, active low

Ready/Busy# output

RY/BY#

V

+5.0 V single power supply

(see Product Selector Guide for

device speed ratings and voltage

supply tolerances)

CC

V

=

Device ground

SS

NC

Pin not connected internally

November 2, 2006 21504E5

Am29F800B

7

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the elements below.

Am29F800B

T

-70

E

C

TEMPERATURE RANGE

C

D

I

=

Commercial (0°C to +70°C)

Commercial (0°C to +70°C) with Pb-Free Package

Industrial (–40°C to +85°C)

Industrial (–40°C to +85°C) with Pb-Free Package

Extended (–55°C to +125°C)

F

E

K

Extended (–55°C to +125°C) with Pb-Free Package

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

S

=

44-Pin Small Outline Package (SO 044)

WB

48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 9 mm package (FBB048)

This device is also available in Known Good Die (KGD) form. See publication number

21536 for more information.

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29F800B

8 Megabit (1 M x 8-Bit/512K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Read, Program and Erase

Valid Combinations

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29F800BT-55, F800BT55V,

AM29F800BT-55,

AM29F800BB-55

AM29F800BT-70,

AM29F800BB-70

AM29F800BB-55

F800BB55V

WBC,

WBI,

WBE,

WBD,

WBF,

WBK

EC, EI, EE, ED, EF, EK

SC, SI, SE, SD, SF, SK

AM29F800BT-70,

AM29F800BB-70

F800BT70V,

F800BB70V

AM29F800BT-90,

AM29F800BB-90

C, I, E,

D, F, K

AM29F800BT-90,

AM29F800BB-90

F800BT90V,

F800BB90V

AM29F800BT-120,

AM29F800BB-120

AM29F800BT-120,

AM29F800BB-120

F800BT12V,

F800BB12V

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

8

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control levels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29F800B Device Bus Operations

DQ8–DQ15

BYTE# BYTE#

Operation

CE#

OE# WE#

RESET#

A0–A18

DQ0–DQ7

D_OUT

= V_IH

D_OUT

D_IN

= V_IL

High-Z

Read

Write

L

H

X

H

X

H

L

H

A_IN

X

L

H

D_IN

CMOS Standby

TTL Standby

V_CC0.5 V

X

H

X

V_CC0.5 V

High-Z

High-Z High-Z

H

L

H

L

X

Output Disable

Hardware Reset

X

Temporary Sector Unprotect

(See Note)

X

V_ID

A_IN

D_IN

X

Legend:

L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 12.0 ± 0.5 V, X = Don’t Care, D_IN= Data In, D_OUT= Data Out, A_IN= Address In

Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.

command is necessary in this mode to obtain array

Word/Byte Configuration

data. Standard microprocessor read cycles that as-

The BYTE# pin controls whether the device data I/O

sert valid addresses on the device address inputs

pins DQ15–DQ0 operate in the byte or word configura-

produce valid data on the device data outputs. The

tion. If the BYTE# pin is set at logic ‘1’, the device is in

device remains enabled for read access until the

word configuration, DQ15–DQ0 are active and con-

command register contents are altered.

trolled by CE# and OE#.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

an input for the LSB (A-1) address function.

the timing waveforms. I

in the DC Characteristics

CC1

table represents the active current specification for

reading array data.

Requirements for Reading Array Data

To read array data from the outputs, the system must

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

drive the CE# and OE# pins to V . CE# is the power

IL

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should re-

CE# to V , and OE# to V .

IL

IH

main at V .

IH

An erase operation can erase one sector, multiple sec-

tors, or the entire device. The Sector Address Tables in-

dicate the address space that each sector occupies. A

“sector address” consists of the address bits required

to uniquely select a sector. See the “Command Defini-

The internal state machine is set for reading array

data upon device power-up, or after a hardware reset.

This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No

November 2, 2006 21504E5

Am29F800B

9

D A T A S H E E T

tions” section for details on erasing a sector or the en-

tire chip, or suspending/resuming the erase operation.

In the DC Characteristics tables, I

standby current specification.

represents the

CC3

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the system

drives the RESET# pin low for at least a period of t ,

RP

the device immediately terminates any operation in

progress, tristates all data output pins, and ignores all

read/write attempts for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is ready

to accept another command sequence, to ensure data

integrity.

I

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V , the device enters

IL

the TTL standby mode; if RESET# is held at V

0.5 V, the device enters the CMOS standby mode.

SS

bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac-

teristics section for timing diagrams.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operation is complete, which requires a

time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

The device enters the CMOS standby mode when CE#

and RESET# pins are both held at V ± 0.5 V. (Note

CC

that this is a more restricted voltage range than V .)

IH

within a time of t

(not during Embedded Algo-

READY

The device enters the TTL standby mode when CE#

rithms). The system can read data t

after the RE-

RH

and RESET# pins are both held at V . The device re-

IH

SET# pin returns to V .

IH

quires standard access time (t ) for read access when

CE

the device is in either of these standby modes, before it

is ready to read data.

Refer to the AC Characteristics tables for RESET# pa-

rameters and timing diagram.

The device also enters the standby mode when the RE-

SET# pin is driven low. Refer to the next section, “RE-

SET#: Hardware Reset Pin”.

Output Disable Mode

When the OE# input is at V , output from the device is

IH

disabled. The output pins are placed in the high imped-

ance state.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

10

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

Table 2. Am29F800BT Top Boot Block Sector Address Table

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x16)

(x8)

Sector A18

A17

0

A16

0

A15

0

A14

X

0

A13

X

0

A12

X

0

Kwords)

Address Range

SA0

SA1

0

1

64/32

32/16

8/4

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7BFFFh

7C000h–7CFFFh

7D000h–7DFFFh

7E000h–7FFFFh

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

D0000h–DFFFFh

E0000h–EFFFFh

F0000h–F7FFFh

F8000h–F9FFFh

FA000h–FBFFFh

FC000h–FFFFFh

0

1

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

SA6

1

0

SA7

1

SA8

0

SA9

0

1

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

0

1

0

1

0

1

0

1

0

1

0

1

8/4

1

X

16/8

Note:

Address range is A18:A-1 in byte mode and A18:A0 in word mode. See the “Word/Byte Configuration” section for more

information.

November 2, 2006 21504E5

Am29F800B

11

D A T A S H E E T

Table 3. Am29F800BB Bottom Boot Block Sector Address Table

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x16)

(x8)

Sector A18

A17

0

A16

0

A15

0

A14

0

A13

0

A12

X

0

Kwords)

Address Range

SA0

SA1

0

1

16/8

8/4

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

D0000h–DFFFFh

E0000h–EFFFFh

F0000h–FFFFFh

0

1

SA2

0

1

8/4

SA3

0

1

X

32/16

64/32

SA4

0

1

X

SA5

0

1

0

SA6

0

1

SA7

1

0

SA8

1

0

1

SA9

1

0

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

1

0

1

0

1

0

1

0

1

0

1

0

1

Note:

Address range is A18:A-1 in byte mode and A18:A0 in word mode. See the “Word/Byte Configuration” sectionfor more

information.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

dress must appear on the appropriate highest order

address bits. Refer to the corresponding Sector Ad-

dress Tables. The Command Definitions table shows

the remaining address bits that are don’t care. When all

necessary bits have been set as required, the program-

ming equipment may then read the corresponding

identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

When using programming equipment, the autoselect

mode requires V (11.5 V to 12.5 V) on address pin

ID

A9. Address pins A6, A1, and A0 must be as shown in

Autoselect Codes (High Voltage Method) table. In addi-

tion, when verifying sector protection, the sector ad-

tions table. This method does not require V . See

“Command Definitions” for details on using the autose-

lect mode.

ID

12

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

Table 4. Am29F800B Autoselect Codes (High Voltage Method)

A18 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Description

A6

A1

Manufacturer ID: AMD

L

H

X

V_ID

X

L

X

L

X

01h

D6h

Device ID:

Am29F800B

(Top Boot Block)

Word

Byte

Word

Byte

22h

X

V_ID

L

H

L

H

X

22h

X

D6h

58h

Device ID:

Am29F800B

(Bottom Boot Block)

X

V_ID

X

H

L

01h

(protected)

X

Sector Protection Verification

L

H

SA

V_ID

L

H

00h

(unprotected)

L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

sectors are protected again. Figure 1 shows the algo-

rithm, and the Temporary Sector Unprotect diagram

shows the timing waveforms, for this feature.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The

hardware sector unprotection feature re-enables both

program and erase operations in previously pro-

tected sectors.

START

Sector protection/unprotection must be implemented

using programming equipment. The procedure re-

RESET# = V_ID

(Note 1)

quires a high voltage (V ) on address pin A9 and the

ID

control pins. Details on this method are provided in a

supplement, publication number 20374. Contact an

AMD representative to obtain a copy of the appropriate

document.

Perform Erase or

Program Operations

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

RESET# = V_IH

Temporary Sector

Unprotect

Completed (Note 2)

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system.

The Sector Unprotect mode is activated by setting the

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

RESET# pin to V . During this mode, formerly pro-

ID

tected sectors can be programmed or erased by se-

lecting the sector addresses. Once V is removed

from the RESET# pin, all the previously protected

ID

Figure 1. Temporary Sector Unprotect Operation

November 2, 2006 21504E5

Am29F800B

13

D A T A S H E E T

proper signals to the control pins to prevent uninten-

Hardware Data Protection

tional writes when V is greater than V

.

CC

LKO

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection measures prevent accidental erasure or pro-

gramming, which might otherwise be caused by spuri-

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

ous system level signals during V

power-down transitions, or from system noise.

power-up and

Write cycles are inhibited by holding any one of OE# =

CC

V , CE# = V or WE# = V . To initiate a write cycle,

IL

IH

CE# and WE# must be a logical zero while OE# is a

logical one.

Low V Write Inhibit

CC

When V

is less than V

, the device does not ac-

LKO

CC

Power-Up Write Inhibit

cept any write cycles. This protects data during V

CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

If WE# = CE# = V and OE# = V during power up, the

IL

IH

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

device resets. Subsequent writes are ignored until V

CC

is greater than V

. The system must provide the

LKO

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the im-

proper sequence resets the device to reading array

data.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Read Operation Timings diagram shows the

timing diagram.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data.

After completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See “Erase Sus-

pend/Erase Resume Commands” for more information

on this mode.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

The system must issue the reset command to re-en-

able the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

14

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

from a “0” back to a “1”. Attempting to do so may halt

Autoselect Command Sequence

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements. This method is an alternative to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

mers and requires V on address bit A9.

ID

START

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

Write Program

Command Sequence

A read cycle at address XX00h or retrieves the manu-

facturer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) returns the device code.

A read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode) re-

turns 01h if that sector is protected, or 00h if it is un-

protected. Refer to the Sector Address tables for valid

sector addresses.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

No

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Yes

No

Word/Byte Program Command Sequence

Increment Address

Last Address?

Yes

The system may program the device by byte or word,

on depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically provides internally gen-

erated program pulses and verify the programmed cell

margin. The Command Definitions take shows the ad-

dress and data requirements for the byte program com-

mand sequence.

Programming

Completed

Note: See the appropriate Command Definitions table for

program command sequence.

Figure 2. Program Operation

Chip Erase Command Sequence

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using DQ7,

DQ6, or RY/BY#. See “Write Operation Status” for in-

formation on these status bits.

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The program command sequence

should be reinitiated once the device has reset to read-

ing array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

November 2, 2006 21504E5

Am29F800B

15

D A T A S H E E T

Any commands written to the chip during the Embed-

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the op-

eration. The Sector Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

ded Erase algorithm are ignored. Note that a hardware

reset during the chip erase operation immediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device has

returned to reading array data, to ensure data integrity.

The system can determine the status of the erase

operation by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data

and addresses are no longer latched.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. Refer to “Write Operation Status” for informa-

tion on these status bits.

Figure 3 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to the Chip/Sector

Erase Operation Timings for timing waveforms.

Figure 3 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

the Sector Erase Operations Timing diagram for timing

waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two un-

lock cycles, followed by a set-up command. Two addi-

tional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the sec-

tor erase command sequence.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase Sus-

pend command.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time be-

tween these additional cycles must be less than 50 µs,

otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended

that processor interrupts be disabled during this time to

ensure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. If the time between additional sector erase

commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on these

status bits.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

16

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

DQ6 status bits, just as in the standard program oper-

ation. See “Write Operation Status” for more informa-

tion.

START

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

Write Erase

Command Sequence

Data Poll

from System

Embedded

Erase

algorithm

in progress

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See the appropriate Command Definitions table for erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

November 2, 2006 21504E5

Am29F800B

17

D A T A S H E E T

Command Definitions

Table 5. Am29F800B Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data Addr Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

RD

F0

Word

2AA

555

2AA

555

2AA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

01

Byte

Word

Byte

Word

Byte

AAA

555

X01 22D6

Device ID,

Top Boot Block

AAA

555

AAA

555

X02

X01

X02

D6

2258

58

Device ID,

Bottom Boot Block

AAA

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

2AA

555

2AA

555

2AA

555

AAA

555

Program

4

6

AA

55

A0

80

PA

PD

AA

555

AAA

555

2AA

555

2AA

555

Chip Erase

55

10

30

AAA

555

AAA

555

AAA

Sector Erase

SA

AAA

XXX

AAA

Erase Suspend (Note 10)

Erase Resume (Note 11)

1

B0

30

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A18–A12 uniquely select any sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

8. The fourth cycle of the autoselect command sequence is a

read cycle.

2. All values are in hexadecimal.

9. The data is 00h for an unprotected sector and 01h for a

protected sector. See “Autoselect Command Sequence” See

“Autoselect Command Sequence” for more information.

3. Except when reading array or autoselect data, all bus cycles

are write operations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and

command cycles.

10. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during a

sector erase operation.

5. Address bits A18–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

6. No unlock or command cycles required when reading array data.

11. The Erase Resume command is valid only during the Erase

Suspend mode.

7. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes

high (while the device is providing status data).

18

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,

and RY/BY#. Table 6 and the following subsections de-

scribe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

Read DQ7–DQ0

Addr = VA

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is in

Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the program or erase

command sequence.

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for ap-

proximately 2 µs, then the device returns to reading

array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

DQ0 on the following read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. The Data# Poll-

ing Timings (During Embedded Algorithms) figure in

the “AC Characteristics” section illustrates this.

Figure 4. Data# Polling Algorithm

November 2, 2006 21504E5

Am29F800B

19

D A T A S H E E T

The Write Operation Status table shows the outputs for

RY/BY#: Ready/Busy#

Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

The DQ2 vs. DQ6 figure shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on “DQ2: Toggle Bit II”.

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to V

.

CC

DQ2: Toggle Bit II

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

Table 6 shows the outputs for RY/BY#. The timing dia-

grams for read, reset, program, and erase shows the

relationship of RY/BY# to other signals.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 6 to compare outputs

for DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

Figure 5 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the “DQ6: Toggle Bit I” subsection.

Refer to the Toggle Bit Timings figure for the toggle bit

timing diagram. The DQ2 vs. DQ6 figure shows the dif-

ferences between DQ2 and DQ6 in graphical form.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, a

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The sys-

tem can read array data on DQ7–DQ0 on the following

read cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not complete the operation successfully, and

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

20

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

the system must write the reset command to return to

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 6 shows the outputs for DQ3.

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 5).

START

Read DQ7–DQ0

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

Read DQ7–DQ0

(Note 1)

No

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”

Toggle Bit

= Toggle?

Yes

No

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ5 = 1?

Yes

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the system can guarantee that the time between ad-

ditional sector erase commands will always be less

than 50 µs. See also the “Sector Erase Command Se-

quence” section.

(Notes

1, 2)

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence, and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all further commands (other than Erase Suspend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

Figure 5. Toggle Bit Algorithm

November 2, 2006 21504E5

Am29F800B

21

D A T A S H E E T

Table 6. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 1)

DQ6

(Note 2)

DQ3

N/A

1

(Note 1)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend Reading within Non-Erase

Data

0

Data

N/A

Data

N/A

1

0

Mode

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

22

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

20 ns

+0.8 V

Voltage with Respect to Ground

V

(Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

–0.5 V

–2.0 V

CC

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V

All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

Figure 6. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may undershoot V_SS

to –2.0 V for periods of up to 20 ns. See Figure 6.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

During voltage transitions, input or I/O pins may overshoot

to V_CC+2.0 V for periods up to 20 ns. See Figure 7.

20 ns

V_CC

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may undershoot V_SSto –2.0 V for periods of up

to 20 ns. See Figure 6. Maximum DC input voltage on pin

A9 is +12.5 V which may overshoot to +13.5 V for periods

up to 20 ns.

+2.0 V

V_CC

+0.5 V

2.0 V

20 ns

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Figure 7. Maximum Positive

Overshoot Waveform

Note: Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C

A

Industrial (I) Devices

Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C

A

Extended (E) Devices

Ambient Temperature (T ) . . . . . . . . –55°C to +125°C

A

V

Supply Voltages

CC

V

for all devices . . . . . . . . . . . . . . .+4.5 V to +5.5 V

CC

Note: Operating ranges define those limits between which

the functionality of the device is guaranteed.

November 2, 2006 21504E5

Am29F800B

23

D A T A S H E E T

DC CHARACTERISTICS

TTL/NMOS Compatible

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

I_LI

Input Load Current

V_IN= V_SSto V_CC, V_CC= V_{CC max}

±1.0

µA

V_CC= V_{CC max}

A9 = OE# = RESET# = 12.5 V

;

I_LIT

I_LO

A9, OE#, RESET Input Load Current

Output Leakage Current

35

±1.0

40

µA

V_OUT= V_SSto V_CC

CE# = V_IL, OE# = V_IH,

f = 5 MHz, Byte Mode

19

mA

V_CCActive Read Current

(Notes 1, 2)

I_CC1

CE# = V_IL, OE# = V_IH,

50

60

mA

f = 5 MHz, Word Mode

V_CCActive Write Current

(Notes 2, 3 and 4)

I_CC2

CE# = V_IL,OE# = V_IH

36

I_CC3

V_IL

V_CCStandby Current (Notes 2, 5)

Input Low Voltage

CE#, OE#, and RESET# = V_IH,

0.4

1

mA

V

–0.5

2.0

0.8

V_CC

+ 0.5

V_IH

V_ID

Input High Voltage

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_CC= 5.0 V

11.5

12.5

0.45

V_OL

V_OH

V_LKO

Output Low Voltage

I_OL= 5.8 mA, V_CC= V_{CC min}

I_OH= –2.5 mA, V_CC= V_{CC min}

V

Output High Voltage

2.4

3.2

Low V_CCLock-Out Voltage (Note 4)

4.2

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

2. Maximum I_CCspecifcations are tested with V_CC= V_CCmax

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Not 100% tested.

5. I_CC3= 20 µA max at extended temperature (>+85°C)

24

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

Test Conditions

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Min

Typ

Max

Unit

V_IN= V_SSto V_CC

V_CC= V_{CC max}

,

I_LI

Input Load Current

±1.0

µA

A9, OE#, RESET Input Load

Current

V_CC= V_{CC max},

A9 = OE# = RESET = 12.5 V

I_LIT

35

µA

V_OUT= V_SSto V_CC

V_CC= V_{CC max}

,

I_LO

Output Leakage Current

±1.0

CE# = V_IL, OE# = V_IH,

f = 5 MHz

Byte Mode

20

28

40

50

mA

V_CCActive Read Current

(Note 2)

I_CC1

CE# = V_IL, OE# = V_IH,

f = 5 MHz

Word Mode

V_CCActive Write Current

(Notes 1, 2, 3)

I_CC2

CE# = V_IL, OE# = V_IH

30

50

5

mA

µA

CE# and RESET# = V_CC±0.5 V,

OE# = V_IH

I_CC3

V_CCStandby Current (Note 2)

0.3

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.5

0.8

V

0.7 x V_CC

V_CC+ 0.3

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V_CC= 5.0 V

11.5

12.5

0.45

V

V_OL

V_OH1

V_OH2

Output Low Voltage

I_OL= 5.8 mA, V_CC= V_{CC min}

I_OH= –2.5 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

0.85 V_CC

V_CC–0.4

Output High Voltage

Low V_CCLock-Out Voltage

(Note 3)

V_LKO

3.2

4.2

V

Notes:

1. I_CCactive while Embedded Erase or Embedded Program is in progress.

2. Maximum I_CCspecifcations are tested with V_CC= V_CCmax

3. Not 100% tested.

November 2, 2006 21504E5

Am29F800B

25

D A T A S H E E T

TEST CONDITIONS

Table 7. Test Specifications

All

5.0 V

Test Condition

-55

others

Unit

2.7 kΩ

Output Load

1 TTL gate

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

5

100

20

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

ns

V

0.0–3.0 0.45–2.4

Input timing measurement

reference levels

1.5

0.8, 2.0

V

Note:

Output timing measurement

reference levels

Diodes are IN3064 or equivalents.

Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

26

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

AC CHARACTERISTICS

Read Operations

Parameter

Speed Options

JEDEC

Std Description

Test Setup

-55

-70

-90

-120

Unit

t_AVAV

t_RCRead Cycle Time (Note 1)

Min

55

70

90

120

ns

CE# = V_IL

OE# = V_IL

t_AVQV

t_ACCAddress to Output Delay

Max

55

70

90

120

ns

t_ELQV

t_GLQV

t_EHQZ

t_CEChip Enable to Output Delay

OE# = V_IL

Max

55

30

20

70

30

20

90

35

20

120

50

ns

t_OEOutput Enable to Output Delay

t_DFChip Enable to Output High Z (Note 1)

30

Output Enable to Output High Z

(Note 1)

t_GHQZ

t_DF

Max

Min

20

30

ns

Read

0

Output Enable

t_OEHHold Time

Toggle and

Data# Polling

10

(Note 1)

Output Hold Time From Addresses,

t_OHCE# or OE#, Whichever Occurs First

(Note 1)

t_AXQX

Min

0

ns

Notes:

1. Not 100% tested.

2. See Figure 8 and Table 7 for test specifications.

t_RC

Addresses Stable

Addresses

CE#

t_ACC

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 9. Read Operations Timings

November 2, 2006 21504E5

Am29F800B

27

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std Description

Test Setup

All Speed Options

Unit

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

t_READY

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t_READY

500

ns

t_RP

t_RH

t_RB

RESET# Pulse Width

Min

500

50

0

ns

RESET# High Time Before Read (See Note)

RY/BY# Recovery Time

Note:

Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 10. RESET# Timings

28

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

t_{ELFL/ ELFH}

t_FLQZ

t_FHQV

Description

-55

-70

-90

-120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

20

55

20

70

20

90

30

ns

120

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

Switching

from word

to byte

DQ0–DQ14

Address

Input

DQ15

Output

mode

DQ15/A-1

BYTE#

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t_FHQV

Figure 11. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 12. BYTE# Timings for Write Operations

Am29F800B

November 2, 2006 21504E5

29

D A T A S H E E T

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

-55

-70

-90

-120

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

55

70

90

120

t_AVWL

t_WLAX

t_DVWH

t_WHDX

0

ns

t_AH

45

25

45

30

45

50

ns

t_DS

ns

t_DH

t_OES

Data Hold Time

0

ns

Output Enable Setup Time

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHWL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

Max

0

ns

CE# Hold Time

t_WP

Write Pulse Width

Write Pulse Width High

30

35

45

50

t_WPH

20

7

Byte

t_WHWH1

t_WHWH2

t_WHWH1Programming Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

µs

Word

12

1

sec

µs

t_VCS

t_RB

V_CCSetup Time (Note 1)

50

0

Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

30

35

50

ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

30

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 13. Program Operation Timings

November 2, 2006 21504E5

Am29F800B

31

D A T A S H E E T

AC CHARACTERISTICS

t_AS

SA

t_WC

2AAh

VA

Addresses

CE#

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Note: SA = Sector Address. VA = Valid Address for reading status data.

Figure 14. Chip/Sector Erase Operation Timings

32

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

Status Data

True

DQ0–DQ6

Valid Data

Status Data

True

t_BUSY

RY/BY#

Note:

VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 15. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

RY/BY#

Note:

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,

and array data read cycle.

Figure 16. Toggle Bit Timings (During Embedded Algorithms)

November 2, 2006 21504E5

Am29F800B

33

D A T A S H E E T

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the

erase-suspended sector.

Figure 17. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

Note: Not 100% tested.

12 V

RESET#

0 or 5 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 18. Temporary Sector Unprotect Timing Diagram

34

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

-55

-70

-90

-120

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

55

70

90

120

t_AVEL

0

ns

t_ELAX

t_DVEH

t_EHDX

t_AH

45

25

45

30

45

50

ns

t_DS

ns

t_DH

t_OES

Data Hold Time

0

ns

Output Enable Setup Time

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

30

35

45

50

t_CPH

20

7

Byte

Programming Operation

(Note 2)

t_WHWH1

t_WHWH2

t_WHWH1

µs

Word

12

1

t_WHWH2Sector Erase Operation (Note 2)

sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

November 2, 2006 21504E5

Am29F800B

35

D A T A S H E E T

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D_OUT= Array Data.

2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

Figure 19. Alternate CE# Controlled Write Operation Timings

36

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 3)

Unit

s

Comments

Sector Erase Time

1.0

19

7

8

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time (Note 2)

Byte Programming Time

Word Programming Time

s

300

500

µs

s

12

7.2

6.3

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

21.6

18.6

Chip Programming Time

(Note 2)

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 5.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 4.5 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Includes all pins except V_CC. Test conditions: V_CC= 5.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

November 2, 2006 21504E5

Am29F800B

37

D A T A S H E E T

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/99

38

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

PHYSICAL DIMENSIONS (continued)

TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP)

Dwg rev AA; 10/99

November 2, 2006 21504E5

Am29F800B

39

D A T A S H E E T

PHYSICAL DIMENSIONS (continued)

FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm package

Dwg rev AF; 10/99

40

Am29F800B

21504E5 November 2, 2006

D A T A S H E E T

REVISION SUMMARY

Revision A (August 1997)

Revision C+1 (April 1998)

Initial release.

Distinctive Characteristics

Changed typical program/erase current to 30 mA to

match the CMOS DC Characteristics table.

Revision B (October 1997)

Global

Changed minimum endurance to 1 million write cycles

per sector guaranteed.

Added -55 speed option. Changed data sheet designa-

tion from Advance Information to Preliminary.

AC Characteristics

Sector Protection/Unprotection

Erase/Program Operations: Corrected the notes refer-

Corrected text to indicate that these functions can only

be implemented using programming equipment.

ence for t

and t

. These parameters are

WHWH1

WHWH2

100% tested. Changed t and t specifications for 55

DS

CP

ns device. Changed t

to 12 µs.

word mode specification

WHWH1

Table 1, Device Bus Operations

Revised to indicate inputs for both CE# and RESET#

are required for standby mode.

Alternate CE# Controlled Erase/Program Operations:

Corrected the notes reference for t and t

These parameters are 100% tested. Changed t and

.

WHWH2

WHWH1

Program Command Sequence

DS

Changed to indicate Data# Polling is active for 2 µs

after a program command sequence if the sector spec-

ified is protected.

t

specifications for 55 ns device. Changed t

CP WHWH1

word mode specification to 12 µs.

Temporary Sector Unprotect Table

Sector Erase Command Sequence and DQ3: Sector

Erase Timer

Added note reference for t

100% tested.

. This parameter is not

VIDR

Corrected sector erase timeout to 50 µs.

Erase and Programming Performance

Erase Suspend Command

In Notes 1 and 6, changed the endurance specification

to 1 million cycles.

Changed to indicate that the device suspends the

erase operation a maximum of 20 µs after the rising

edge of WE#.

Revision C+2 (April 1998)

Product Selector Guide

DC Characteristics

Deleted the -55 speed option for V

= 5.0 V 5%.

Changed to indicate V min and max values are 11.5

CC

ID

Added the -55 speed option for V = 5.0 V 10%.

to 12.5 V, with a V

test condition of 5.0 V. Added

CC

typical values to TTL table. Revised CMOS typical

standby current (I ).

Ordering Information

CC3

Valid Combinations for Am29F800BT-55 and

Am29F800BB-55: Added the extended temperature

range for all package types.

Figure 14: Chip/Sector Erase Operation Timings;

Figure 19: Alternate CE# Controlled Write

Operation TImings

Operating Ranges

Corrected hexadecimal values in address and data

waveforms. In Figure 19, corrected data values for chip

and sector erase.

V

Supply Voltages: Deleted “V for 5% devices .

CC

. . . +4.75 V to +5.25 V”. Changed “V

devices . . . . +4.5 V to +5.5 V” to “V for all devices .

. . . +4.5 V to +5.5 V”.

for 10%

CC

Erase and Programming Performance

Corrected word and chip programming times.

Erase and Programming Performance

Note 2: Deleted “(4.75 V for -55)”.

Revision C (January 1998)

Global

Formatted for consistency with other 5.0 volt-only

data sheets.

November 2, 2006 21504E5

Am29F800B

41

D A T A S H E E T

REVISION SUMMARY (Continued)

Revision D (January 1999)

Distinctive Characteristics

Revision E (November 16, 1999)

AC Characteristics—Figure 13. Program

Operations Timing and Figure 14. Chip/Sector

Erase Operations

Added the 20-year data retention subbullet.

Ordering Information

Deleted t

high.

and changed OE# waveform to start at

GHWL

Optional Processing: Deleted “B = Burn-in”.

DC Characteristics—TTL/NMOS Compatible

Physical Dimensions

I

: Added OE# and RESET to the Description column.

Replaced figures with more detailed illustrations.

LIT

Changed “A9 = 12.5 V” to “A9 = OE# = RESET = 12.5

V” in the Test Conditions column.

Revision E+1 (August 4, 2000)

Global

I

, I

: Deleted “V

= V

max” in

CC

LO

CC1

CC2

CC

Test Conditions.

Added FBGA package.

I

: Added Note 4, “I

= 20 µA max at extended

CC3

Revision E+2 (June 4, 2004)

Ordering Information

temperatures (>+85°C)”.

DC Characteristics—CMOS Compatible

: Added OE# and RESET to the Description column.

Added Pb-Free OPNs.

I

LIT

Changed “A9 = 12.5 V” to “A9 = OE# = RESET = 12.5

V” in the Test Conditions column.

Revision E3 (December 22, 2005)

Global

I

, I

: Deleted “V

= V max”; added

CC CC

CC1 CC2 CC3

Deleted reverse TSOP package option and 150 ns

speed option.

Note 2 “Maximum I

specifications are tested with

CC

V

= V max”.

CC

Revision E4 (May 19, 2006)

Added “Not recommended for new designs” note.

AC Characteristics

Revision D+1 (March 23, 1999)

Command Definitions table

Corrected SA definition in legend; range should be

A18–A12. In Note 4, A17 should be A18.

Changed t

specification to maximium value.

BUSY

Revision D+2 (July 2, 1999)

Global

Revision E5 (November 2, 2006)

Deleted “Not recommended for new designs” note.

Added references to availability of device in Known

Good Die (KGD) form.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are

for identification purposes only and may be trademarks of their respective companies.

42

Am29F800B

21504E5 November 2, 2006


型号：	AM29F800BB-120EK
厂家：	AMD
描述：	8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory 8兆位（ 1一M× 8位/ 512的K× 16位） CMOS 5.0伏只，引导扇区闪存闪存
文件：	总44页 (文件大小：1486K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29F800BB-120EK [AMD]

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