AM29F400AB-120EIB [AMD]
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory; 4兆位( 524,288 ×8位/ 262,144 x 16位) CMOS 5.0伏只,扇区擦除闪存型号: | AM29F400AB-120EIB |
厂家: | AMD |
描述: | 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
文件: | 总35页 (文件大小:139K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
Am29F400AT/Am29F400AB
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10% for read and write operations
■ Embedded Program Algorithms
— Minimizes system level power requirements
— Automatically programs and verifies data at
specified address
■ Compatible with JEDEC-standards
■ Data Polling andToggle Bit feature for detection
— Pinout and software compatible with
single-power-supply flash
of program or erase cycle completion
■ Ready/Busy output (RY/BY)
— Superior inadvertent write protection
— Hardware method for detection of program or
erase cycle completion
■ Package options
— 44-pin SO
■ Erase Suspend/Resume
— 48-pin TSOP
— Supports reading data from a sector not being
erased
■ Minimum 100,000 write/erase cycles guaranteed
■ High performance
■ Low power consumption
— 60 ns maximum access time
— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current
■ Sector erase architecture
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
seven 64 Kbytes
■ Enhanced power management for standby
— Any combination of sectors can be erased. Also
supports full chip erase.
mode
— 1 µA typical standby current
■ Sector protection
■ Boot Code Sector Architecture
— T = Top sector
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
— B = Bottom sector
■ Hardware RESET pin
■ Embedded Erase Algorithms
— Resets internal state machine to the read mode
— Automatically preprograms and erases the chip
or any sector
GENERAL DESCRIPTION
The Am29F400A is a 4 Mbit, 5.0Volt-only Flash memory
organized as 512 Kbytes of 8 bits each or 256 Kwords
of 16 bits each. The 4 Mbits of data is divided into 11
sectors of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte,
and seven 64 Kbytes, for flexible erase capability. The
8 bits of data will appear on DQ0–DQ7 or 16 bits on
DQ0–DQ15. The Am29F400A is offered in 44-pin SO
and 48-pin TSOP packages. This device is designed
to be programmed in-system with the standard system
The standard Am29F400A offers access times of
60 ns, 70 ns, 90 ns, 120 ns and 150 ns, allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has sepa-
rate chip enable (CE), write enable (WE) and output
enable (OE) controls.
The Am29F400A is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine
which controls the erase and programming circuitry.
5.0 Volt V
supply. 12.0 Volt V is not required for
CC
PP
program or erase operations.The device can also be re-
programmed in standard EPROM programmers.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 20380 Rev: B Amendment/0
Issue Date: April 1997
P R E L I M I N A R Y
Write cycles also internally latch addresses and data
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness.The Am29F400A memory electrically erases all
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from 12.0 Volt Flash or EPROM devices.
bits within
a sector simultaneously via
The Am29F400A is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm which is an
internal algorithm that automatically preprograms the
array if it is not already programmed before executing
the erase operation. During erase, the device automat-
ically times the erase pulse widths and verifies proper
cell margin.
Fowler-Nordhiem tunneling.The bytes/words are pro-
grammed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.
Flexible Sector-Erase Architecture
■ One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
seven 64 Kbyte sectors
■ Individual-sector or multiple-sector erase capability
■ Sector protection is user definable
(x8)
(x16)
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and re-
programmed without affecting the data contents of
other sectors. A sector is typically erased and verified
within 1.5 seconds. The Am29F400A is erased when
shipped from the factory.
7FFFFh 3FFFFh
7BFFFh 3DFFFh
79FFFh 3CFFFh
77FFFh 3BFFFh
6FFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
00000h 00000h
20380B-1
16 Kbyte
8 Kbyte
8 Kbyte
32 Kbyte
64 Kbyte
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
The Am29F400A device also features hardware sector
protection. This feature will disable both program and
erase operations in any combination of eleven sectors
of memory.
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from a sector that was not being
erased. Thus, true background erase can be achieved.
The device features single 5.0 Volt power supply oper-
ation for both read and write functions. Internally gen-
erated and regulated voltages are provided for the
program and erase operations. A low V detector au-
CC
Am29F400AT Sector Architecture
(x8)
tomatically inhibits write operations during power tran-
sitions. The end of program or erase is detected by the
RY/BY pin. Data Polling of DQ7, or by the Toggle Bit
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.
(x16)
7FFFFh 3FFFFh
6BFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
07FFFh 03FFFh
05FFFh 02FFFh
03FFFh 01FFFh
00000h 00000h
20380B-2
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
32 Kbyte
8 Kbyte
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
The Am29F400A also has a hardware RESET pin.
When this pin is driven low, execution of any Embed-
ded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal state machine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be auto-
matically reset to the read mode and will have errone-
ous data stored in the address locations being
operated on. These locations will need rewriting after
the Reset. Resetting the device will enable the sys-
tem’s microprocessor to read the boot-up firmware
from the Flash memory.
8 Kbyte
16 Kbyte
Am29F400AB Sector Architecture
2
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part No:
Am29F400A
Ordering Part No:V
CC
= 5.0 V ± 5%
-65
V
= 5.0 V ± 10%
-70
-90
90
90
35
-120
120
120
50
-150
150
150
55
CC
Max Access Time (ns)
CE (E) Access (ns)
OE (G) Access (ns)
60
60
30
70
70
30
BLOCK DIAGRAM
DQ0–DQ15
RY/BY
Buffer
RY/BY
V
V
CC
Input/Output
Buffers
SS
Erase Voltage
Generator
State
Control
WE
BYTE
Command
Register
RESET
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE
OE
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
X-Decoder
Cell Matrix
A0-A17
A-1
20380B-3
Am29F400AT/Am29F400AB
3
P R E L I M I N A R Y
CONNECTION DIAGRAMS
SO
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
NC
RY/BY
A17
A7
1
2
A8
3
A9
4
A10
A11
A12
A13
A14
A15
A16
BYTE
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
CE
V
V
SS
SS
DQ15/A-1
DQ7
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
20380B-4
4
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A16
1
2
3
4
5
6
7
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
8
9
10
11
12
13
14
15
16
17
18
19
20
DQ12
DQ4
WE
RESET
NC
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
21
22
23
24
V
SS
CE
A0
20380B-5
Standard TSOP
A16
1
2
3
4
5
6
7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
8
9
DQ12
DQ4
10
11
12
13
14
15
16
17
18
19
20
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
21
22
23
24
V
SS
CE
A0
20380B-6
Reverse TSOP
Am29F400AT/Am29F400AB
5
P R E L I M I N A R Y
PIN CONFIGURATION
LOGIC SYMBOL
A1, A0–A17 = 18 Addresses
BYTE
CE
= Selects 8-bit or 16-bit mode
= Chip Enable
A-1
18
16 or 8
A0–A17
DQ0–DQ15 = 16 Data Inputs/Outputs
DQ0–DQ15
NC
= Pin Not Connected Internally
= Output Enable
CE (E)
OE (G)
OE
RESET
RY/BY
= Hardware Reset Pin, Active Low
= Ready/Busy Output
WE (W)
RESET
V
= +5.0 Volt Single-Power Supply
SS
BYTE
(±10% for -90, -120, -150) or (±5% for -75)
RY/BY
V
= Device Ground
= Write Enable
SS
20380B-7
WE
6
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the following:
AM29F400A
T
-65
E
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I
= Industrial (-40°C to +85°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F400A
4 Megabit (512K x 8-Bit/256K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
EC, EI, FC, FI, SC, SI
AM29F400AT/B-65
AM29F400AT/B-70
AM29F400AT/B-90
AM29F400AT/B-120
AM29F400AT/B-150
EC, EI, EE, EEB,
FC, FI, FE, FEB,
SC, SI, SE, SEB
Am29F400AT/Am29F400AB
7
P R E L I M I N A R Y
Table 1. Am29F400A User Bus Operations (BYTE = V )
IH
Operation
Autoselect, AMD Manuf. Code (Note 1)
Autoselect Device Code (Note 1)
Read
CE
L
OE
L
WE
H
H
H
X
A0
L
A1
L
A6
L
A9
DQ0–DQ15
Code
RESET
V
H
H
H
H
H
H
H
ID
L
L
H
L
L
V
Code
ID
L
L
A0
X
A1
X
A6
X
A9
X
D
OUT
Standby
H
L
X
H
H
L
HIGH Z
HIGH Z
Output Disable
H
L
X
X
X
X
Write
L
A0
L
A1
H
A6
L
A9
D
IN
Verify Sector Protect (Note 2)
Temporary Sector Unprotect
Hardware Reset
L
H
X
V
Code
X
ID
X
X
X
X
X
X
X
X
V
ID
X
X
X
X
X
HIGH Z
L
Table 2. Am29F400A User Bus Operations (BYTE = V )
IL
Operation
CE
OE
WE
A0
A1
A6
A9
DQ0–DQ7 DQ8–DQ15 RESET
Autoselect, AMD Manuf. Code
(Note 1)
L
L
H
L
L
L
V
Code
Code
HIGH Z
H
ID
Autoselect Device Code (Note 1)
Read
L
L
L
L
H
H
X
H
L
H
A0
X
L
A1
X
L
A6
X
V
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
H
H
H
H
H
H
ID
A9
X
D
OUT
Standby
H
L
X
H
H
L
HIGH Z
HIGH Z
Output Disable
X
X
X
X
Write
L
A0
L
A1
H
A6
L
A9
D
IN
Verify Sector Protect (Note 2)
Temporary Sector Unprotect
Hardware Reset
L
H
X
X
V
Code
X
ID
X
X
X
X
X
X
X
X
V
ID
X
X
X
X
HIGH Z
L
Legend:
L = logic 0, H = logic 1, X = Don’t Care. See Characteristics for voltage levels.
Notes:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.
2. Refer to the section on Sector Protection.
suming the addresses have been stable for at least
-t time).
Read Mode
t
ACC OE
The Am29F400A has two control functions which must
be satisfied in order to obtain data at the outputs. CE is
the power control and should be used for device selec-
tion. OE is the output control and should be used to
gate data to the output pins if a device is selected.
Standby Mode
There are two ways to implement the standby mode on
the Am29F400A device, both using the CE pin.
A CMOS standby mode is achieved with the CE input
Address access time (t
stable addresses to valid output data. The chip enable
) is equal to the delay from
ACC
held at V ± 0.5 V. Under this condition the current is
CC
typically reduced to less than 5 µA. A TTL standby
access time (t ) is the delay from stable addresses
CE
mode is achieved with the CE pin held at V . Under
IH
and stable CE to valid data at the output pins.
The output enable access time is the delay from the
falling edge of OE to valid data at the output pins (as-
this condition the current is typically reduced to 1 mA.
In the standby mode the outputs are in the high imped-
ance state, independent of the OE input.
8
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
Am29F400A is erased or programmed in a system
Output Disable
without access to high voltage on the A9 pin.The com-
mand sequence is illustrated in Table 4 (see Autoselect
Command Sequence).
With the OE input at a logic high level (V ), output from
IH
the device is disabled.This will cause the output pins to
be in a high impedance state.
Byte 0 (A0 = V ) represents the manufacturer’s code
IL
Autoselect
(AMD=01H) and byte 1 (A0 = V ) the device identifier
IH
The autoselect mode allows the reading of a binary
code from the device and will identify its manufacturer
and type. This mode is intended for use by program-
ming equipment for the purpose of automatically
matching the device to be programmed with its corre-
sponding programming algorithm. This mode is func-
tional over the entire temperature range of the device.
code (Am29F400AT = 23H and Am29F400AB = ABH
for x8 mode; Am29F400AT = 2223H and Am29F400AB
= 22ABH for x16 mode). These two bytes/words are
given in the table below. All identifiers for manufacturer
and device will exhibit odd parity with DQ7 defined as
the parity bit. In order to read the proper device codes
when executing the Autoselect, A1 must be V
(see Tables 3 and 4).
IL
To activate this mode, the programming equipment
must force V (11.5 V to 12.5 V) on address pin A9.
Two identifier bytes may then be sequenced from the
The autoselect mode also facilitates the determination
of sector protection in the system. By performing a read
operation at the address location XX02H with the
higher order address bits A12–A17 set to the desired
sector address, the device will return 01H for a pro-
tected sector and 00H for a non-protected sector.
ID
device outputs by toggling address A0 from V to V .
IL
IH
All addresses are don’t cares except A0, A1, and A6
(see Table 3).
The manufacturer and device codes may also be read
via the command register, for instances when the
Table 3. Am29F400A Sector Protection Verify Autoselect Codes
Type
A12-A17
A6
A1
A0
Code (HEX)
01H
Manufacturer Code-AMD
X
V
V
V
IL
IL
IL
Byte
Word
Byte
23H
Am29F400AT
Am29F400AB
X
X
V
V
V
IL
IL
IH
IH
2223H
ABH
Am29F400A Device
V
V
V
V
IL
IL
Word
22ABH
Sector
Address
Sector Protection
V
V
01H*
IL
IH
IL
*Outputs 01H at protected sector addresses
Table 4. Expanded Autoselect Code Table
DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ
Code
Type
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Manufacturer Code-AMD
01H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
23H
A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
Am29F400AT(B)
(W)
2223H
0
0
1
0
0
0
1
0
Am29F400A
Device
A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
Am29F400AB(B) ABH
(W) 22ABH
0
0
1
0
0
0
1
0
Sector Protection
01H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B) - Byte mode
(W) - Word mode
Am29F400AT/Am29F400AB
9
P R E L I M I N A R Y
Table 5. Sector Address Tables (Am29F400AT)
(x8) Address
(x16) Address
Range
A17
0
A16
0
A15
0
A14
X
X
X
X
X
X
X
0
A13
X
A12
X
Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-77FFFh
78000h-79FFFh
7A000h-7BFFFh
7C000h-7FFFFh
00000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3BFFFh
3C000h-3CFFFh
3D000h-3DFFFh
3E000h-3FFFFh
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
X
Table 6. Sector Address Tables (Am29F400AB)
(x8) Address
(x16) Address
Range
A17
0
A16
0
A15
A14
A13
A12
Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
0
0
0
X
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
00000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
X
X
0
0
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
Write
Device erasure and programming are accomplished via
the command register.The contents of the register serve
as inputs to the internal state machine. The state ma-
chine outputs dictate the function of the device.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.
Sector Protection
The Am29F400A features hardware sector protection.
This feature will disable both program and erase opera-
tions in any combination of ten sectors of memory. The
sector protect feature is enabled using programming
equipment at the user’s site. The device is shipped with
all sectors unprotected. Alternatively, AMD may program
and protect sectors in the factory prior to shipping the
device (AMD’s ExpressFlash Service).
The command register itself does not occupy any ad-
dressable memory location. The register is a latch used
to store the commands, along with the address and data
information needed to execute the command. The com-
mand register is written to by bringing WE to V , while
IL
CE is at V and OE is at V . Addresses are latched on
IL
IH
the falling edge of WE or CE, whichever happens later;
while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write
timings are used.
10
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
It is possible to determine if a sector is protected in the
the RESET pin, all the previously protected sectors will
be protected again. Refer to Figures 16 and 17.
system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where
the higher order address bits A12–A17 is the desired
sector address, will produce a logical “1” at DQ0 for a
protected sector. See Table 3 for Autoselect codes.
Command Definitions
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values
or writing them in the improper sequence will reset
the device to the read mode.Table 7 defines the valid
register command sequences. Note that the
Erase Suspend (B0H) and Erase Resume (30H) com-
mands are valid only while the Sector Erase operation
is in progress. Moreover, both Reset/Read commands
are functionally equivalent, resetting the device to the
read mode.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors of the Am29F400A device in
order to change data in-system. The Sector Unprotect
mode is activated by setting the RESET pin to high volt-
age (12V). During this mode, formerly protected sec-
tors can be programmed or erased by selecting the
sector addresses. Once the 12 V is taken away from
Am29F400AT/Am29F400AB
11
P R E L I M I N A R Y
Table 7. Am29F400A Command Definitions (Notes 1–7)
Bus
First Bus
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Command
Sequence
Read/Reset
Write Write Cycle
Cycles
Req’d
Addr Data Addr Data Addr Data Addr
Data
Addr Data Addr Data
Reset/Read
1
XXXXH F0H
Word
5555H AAH 2AAAH 55H 5555H
Reset/
Read
3
3
F0H
RA
RD
Byte
AAAAH
5555H
AAAAH
Word
5555H AAH 2AAAH 55H 5555H 90H
01H 2223H
(T Device ID)
22ABH
(B Device ID)
Byte
AAAAH
5555H
AAAAH
23H
(T Device ID)
ABH
Autoselect
(B Device ID)
Word
/Byte
01H (T/B
Manuf. ID)
00H
PA
Word
Byte
Word
Byte
Word
Byte
4
6
6
5555H AAH 2AAAH 55H 5555H A0H
AAAAH 5555H AAAAH
5555H AAH 2AAAH 55H 5555H 80H 5555H
AAAAH 5555H AAAAH AAAAH
5555H AAH 2AAAH 55H 5555H 80H 5555H
PD
Program
AAH
AAH
2AAAH 55H 5555H 10H
Chip Erase
5555H
AAAAH
SA
2AAAH 55H
5555H
30H
Sector
Erase
AAAAH
5555H
AAAAH
AAAAH
Erase Suspend
Erase Resume
1
1
XXXXH B0H
XXXXH 30H
Notes:
1. Bus operations are defined in Tables 1 and 2.
2. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A17–A12 will uniquely select any sector.
3. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
4. Reading from non-erasing sectors is allowed in the Erase Suspend mode.
5. Address bits A17–A15 are don’t care for unlock and command cycles.
6. The system should generate the following address patterns:
Word Mode: 5555H or 2AAAH to addresses A0–A14
Byte Mode: AAAAH or 5555H to addresses A-1–A14.
The device will automatically power-up in the read/
reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value en-
sures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific
timing parameters.
Read/Reset Command
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for
reads until the command register contents are altered.
12
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
Any commands written to the chip during the Embed-
Autoselect Command
ded Program Algorithm will be ignored. If a hardware
reset occurs during the programming operation, the
data at that particular location will be corrupted.
Flash memories are intended for use in applications
where the local CPU can alter memory contents. As
such, manufacture and device codes must
be accessible while the device resides in the target
system. PROM programmers typically access the sig-
nature codes by raising A9 to a high voltage. However,
multiplexing high voltage onto the address lines is not
generally a desirable system design practice.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success according
to the data polling algorithm but a read from reset/read
mode will show that the data is still “013”. Only erase
operations can convert “0”s to “1”s.
The device contains an autoselect command operation
to supplement traditional PROM programming method-
ology. The operation is initiated by writing the autose-
lect command sequence into the command register.
Following the command write, a read cycle from ad-
dress XX00H retrieves the manufacture code of 01H. A
read cycle from address XX01H returns the device
code (Am29F400AT = 23H and Am29F400AB = ABH
for x8 mode; Am29F400AT = 2223H and Am29F400AB
= 22ABH for x16 mode) (see Tables 3 and 4).
Figure 1 illustrates the Embedded Programming Algo-
rithm using typical command strings and
bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“setup” command. Two more “unlock” write cycles are
then followed by the chip erase command.
All manufacturer and device codes will exhibit odd par-
ity with DQ7 defined as the parity bit.
Chip erase does not require the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device will
automatically program and verify the entire memory for
an all zero data pattern prior to electrical erase. The
erase is performed sequentially on all sectors at the
same time (see Table “Erase and Programming Perfor-
mance”). The system is not required to provide any
controls or timings during these operations.
Furthermore, the write protect status of sectors can be
read in this mode. Scanning the sector addresses
(A17, A16, A15, A14, A13, and A12) while (A6, A1, A0)
= (0, 1, 0) will produce a logical “1” at device output
DQ0 for a protected sector.
To terminate the operation, it is necessary to write the
read/reset command sequence into the register.
Byte/Word Programming
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and termi-
nates when the data on DQ7 is “1” (see Write Operation
Status section) at which time the device returns to read
the mode.
The device is programmed on a byte-by-byte (or
word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These
are followed by the program setup command and data
write cycles. Addresses are latched on the falling edge
of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever hap-
pens first.The rising edge of CE or WE (whichever hap-
pens first) begins programming using the Embedded
Program Algorithm. Upon executing the algorithm, the
system is not required to provide further controls or tim-
ings.The device will automatically provide adequate in-
ternally generated program pulses and verify the
programmed cell margin.
Figure 1 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation.There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed by the sector erase command.The sector
address (any address location within the
desired sector) is latched on the falling edge of WE,
while the command (30H) is latched on the rising edge
of WE. After a time-out of 100 µs from the rising edge
of the last sector erase command, the sector erase op-
eration will begin.
The automatic programming operation is completed
when the data on DQ7 (also used as Data Polling) is
equivalent to the data written to this bit at which time
the device returns to the read mode and addresses are
no longer latched (see Table 8, Write Operation Sta-
tus).Therefore, the device requires that a valid address
to the device be supplied by the system at this particu-
lar instance of time for Data Polling operations. Data
Polling must be performed at the memory location
which is being programmed.
Multiple sectors may be erased sequentially by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be
sequentially erased. The time between writes must be
less than 100 µs otherwise that command will not be
Am29F400AT/Am29F400AB
13
P R E L I M I N A R Y
accepted and erasure will start. It is recommended that
Erase Suspend
processor interrupts be disabled during this time to
guarantee this condition. The interrupts can be
re-enabled after the last Sector Erase command
is written. A time-out of 100 µs from the rising edge of
the last WE will initiate the execution of the Sector
Erase command(s). If another falling edge of the WE
occurs within the 100 µs time-out window the timer is
reset. (Monitor DQ3 to determine if the sector erase
timer window is still open, see section DQ3, Sector
Erase Timer.) Any command other than Sector Erase
or Erase Suspend during this period will reset the de-
vice to the read mode, ignoring the previous command
string. In that case, restart the erase on those sectors
and allow them to complete.
The Erase Suspend command allows the user to inter-
rupt a Sector Erase operation and then perform data
reads from a sector not being erased.This command is
applicable ONLY during the Sector Erase operation
which includes the time-out period for sector erase.The
Erase Suspend command will be ignored if written dur-
ing the Chip Erase operation or Embedded
Program Algorithm. Writing the Erase Suspend com-
mand during the Sector Erase time-out results in imme-
diate termination of the time-out period and suspension
of the erase operation.
Any other command written during the Erase Suspend
mode will be ignored except the Erase
Resume command. Writing the Erase Resume com-
mand resumes the erase operation.The addresses are
“don’t-cares” when writing the Erase Suspend or Erase
Resume command.
(Refer to the Write Operation Status section for DQ3,
Sector Erase Timer operation.) Loading the sector
erase buffer may be done in any sequence and with
any number of sectors (0 to10).
When the Erase Suspend command is written during
the Sector Erase operation, the device will take a max-
imum of 15 µs to suspend the erase operation. When
the device has entered the erase-suspended mode,
DQ6 will stop toggling. The user must use the address
of a sector being erased for reading DQ6 to determine
if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
Sector erase does not require the user to program the
device prior to erase. The device automatically pro-
grams all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not af-
fected. The system is not required to provide any con-
trols or timings during these operations.
The automatic sector erase begins after the 100 µs
time out from the rising edge of the WE pulse for the
last sector erase command pulse and terminates when
the data on DQ7, Data Polling, is “1” (see Write Opera-
tion Status section) at which time the device returns to
the read mode. Data Polling must be performed at an
address within any of the sectors being erased.
When the erase operation has been suspended, the
device defaults to the erase-suspend-read mode.
Reading data in this mode is the same as reading from
the standard read mode except that the data must be
read from sectors that have not been
erase-suspended.
To resume the operation of Sector Erase, the Resume
command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. An-
other Erase Suspend command can be written after the
chip has resumed erasing.
Figure 1 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Write Operation Status
Table 8. Write Operation Status
Status
DQ7
DQ7
0
DQ6
DQ5
DQ3
Auto-Programming
Program/Erase in Auto-Erase
Auto-Programming
Program/Erase in Auto-Erase
Toggle
Toggle
Toggle
Toggle
0
0
1
1
0
1
0
1
In Progress
DQ7
0
Exceeded
Time Limits
Notes:
1. D8–D15 = Don’t Care for x16 mode.
2. DQ4 for AMD internal use only.
14
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
Toggle Bit is valid after the rising edge of the sixth WE
DQ7
pulse in the six write pulse sequence. For Sector erase,
the Toggle Bit is valid after the last rising edge of the
sector erase WE pulse. The Toggle Bit is active during
the sector time-out.
Data Polling
The Am29F400A device features Data Polling as a
method to indicate to the host that the embedded algo-
rithms are in progress or completed. During
the Embedded Program Algorithm an attempt to read
the device will produce the complement of the data last
written to DQ7. Upon completion of the Embedded Pro-
gram Algorithm, an attempt to read the device will pro-
duce the true data last written to DQ7. During the
Embedded Erase Algorithm, an attempt to read
the device will produce a “0” at the DQ7 output.
Upon completion of the Embedded Erase Algorithm an
attempt to read the device will produce a “1” at the DQ7
output. The flowchart for Data Polling (DQ7) is shown
in Figure 2.
Either CE or OE toggling will cause DQ6 to toggle. In
addition, an Erase Suspend/Resume command will
cause DQ6 to toggle. See Figure 11 for the Toggle Bit
timing specifications and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count).
Under these conditions DQ5 will produce a “1”. This is
a failure condition which indicates that the program or
erase cycle was not successfully completed. Data Poll-
ing is the only operating function of the device under
this condition. The CE circuit will partially power down
the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output dis-
able functions as described in Table 1.
For chip erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse se-
quence. For sector erase, the Data Polling is valid after
the last rising edge of the sector erase WE pulse. Data
Polling must be performed at sector addresses within
any of the sectors being erased and not a protected
sector. Otherwise, the status may not be valid.
The DQ5 failure condition will also appear if a user tries
to program a 1 to a location that is previously pro-
grammed to 0. In this case the device locks out and
never completes the Embedded Program Algorithm.
Hence, the system never reads a valid data on DQ7 bit
and DQ6 never stops toggling. Once the device has ex-
ceeded timing limits, the DQ5 bit will indicate a “1.”
Please note that this is not a device failure condition
since the device was incorrectly used. If this occurs,
reset the device.
Just prior to the completion of Embedded Algorithm
operations DQ7 may change asynchronously while
the output enable (OE) is asserted low. This means
that the device is driving status information on DQ7 at
one instant of time and then that byte’s valid data at
the next instant of time. Depending on when the sys-
tem samples the DQ7 output, it may read the status or
valid data. Even if the device has completed the Em-
bedded Algorithm operations and DQ7 has a valid
data, the data outputs on DQ0–DQ6 may be still in-
valid. The valid data on DQ0–DQ7 will be read on the
successive read attempts.
DQ3
Sector Erase Timer
After the completion of the initial sector erase com-
mand sequence the sector erase time-out will begin.
DQ3 will remain low until the time-out is complete. Data
Polling and Toggle Bit are valid after the initial sector
erase command sequence.
The Data Polling feature is only active during the Em-
bedded Programming Algorithm, Embedded Erase Al-
gorithm, or sector erase time-out (see Table 7).
See Figure 10 for the Data Polling timing specifications
and diagrams.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, DQ3 may be
used to determine if the sector erase timer window is
still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent
commands (other than Erase Suspend) to the device
will be ignored until the erase operation is completed as
indicated by Data Polling or Toggle Bit. If DQ3 is low
(“0”), the device will accept additional sector erase
commands. To insure the command has been ac-
cepted, the system software should check the status of
DQ3 prior to and following each subsequent sector
erase command. If DQ3 were high on the second sta-
tus check, the command may not have been accepted.
DQ6
Toggle Bit
The Am29F400A also features the “Toggle Bit” as a
method to indicate to the host system that the embed-
ded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cy-
cle, successive attempts to read (OE toggling) data
from the device at any address will result in DQ6 tog-
gling between one and zero. Once the Embedded Pro-
gram or Erase Algorithm cycle is completed, DQ6 will
stop toggling and valid data will be read on the next
successive attempt. During programming, the Toggle
Bit is valid after the rising edge of the fourth WE pulse
in the four write pulse sequence. For chip erase, the
Refer to Table 8: Write Operation Status.
Am29F400AT/Am29F400AB
15
P R E L I M I N A R Y
bit) mode. The data is read and programmed
RY/BY
Ready/Busy
at DQ0–DQ15. When this pin is driven low, the de-
vice operates in byte (8 bit) mode. Under this mode,
the DQ15/A-1 pin becomes the lowest address bit
and DQ8–DQ14 bits are tri-stated. However, the
command bus cycle is always an 8-bit operation and
hence commands are written at DQ0–DQ7 and the
DQ8–DQ15 bits are ignored. Refer to Figures 14 and
15 for the timing diagram.
The Am29F400A provides a RY/BY open-drain output
pin as a way to indicate to the host system that the Em-
bedded Algorithms are either in progress or have been
completed. If the output is low, the device is busy with
either a program or erase operation. If the output is
high, the device is ready to accept any read/write or
erase operation.When the RY/BY pin is low, the device
will not accept any additional program or erase com-
mands with the exception of the Erase Suspend com-
mand. If the Am29F400A is placed in an Erase
Suspend mode, the RY/BY output will be high.
Data Protection
The Am29F400A is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tions. During power up the device automatically resets
the internal state machine in the Read mode. Also, with
its control register architecture, alteration of the mem-
ory contents only occurs after successful completion of
specific multi-bus cycle command sequences.
During programming, the RY/BY pin is driven low after
the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising
edge of the sixth WE pulse. The RY/BY pin should be
ignored while RESET is at V . Refer to Figure 12 for a
IL
detailed timing diagram.
The device also incorporates several features to pre-
Since this is an open-drain output, several RY/BYpins
can be tied together in parallel with a pull-up resistor
vent inadvertent write cycles resulting from V
power-up and power-down transitions or system noise.
CC
to V
.
CC
Low VCC Write Inhibit
RESET
Hardware Reset
To avoid initiation of a write cycle during V
power-up
CC
and power-down, the Am29F400A locks out write cy-
cles for V < V (see DC Characteristics section for
The Am29F400A device may be reset by driving the
RESET pin to V . The RESET pin must be kept low
CC
LKO
IL
voltages). When V
< V
, the command register is
CC
LKO
(V ) for at least 500 ns. Any operation in progress will
IL
disabled, all internal program/erase circuits
are disabled, and the device resets to the read mode.
be terminated and the internal state machine will be
reset to the read mode 20 µs after the RESET pin is
driven low. Furthermore, once the RESET pin goes
high, the device requires an additional 50 ns before it
will allow read access. When the RESET pin is low, the
device will be in the standby mode for the duration of
the pulse and all the data output pins will be tri-stated.
If a hardware reset occurs during a program or erase
operation, the data at that particular location will
be indeterminate.
The Am29F400A ignores all writes until V
The user must ensure that the control pins are in the
> V
.
CC
LKO
correct logic state when V
tentional writes.
> V
to prevent unin-
CC
LKO
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or
WE will not initiate a write cycle.
Logical Inhibit
The RESET pin may be tied to the system reset input.
Therefore, if a system reset occurs during the Embed-
ded Program or Erase Algorithm, the device will be au-
tomatically reset to read mode and this will enable the
system’s microprocessor to read the boot-up firmware
from the Flash memory.
Writing is inhibited by holding any one of OE = V ,CE
IL
= V , or WE = V . To initiate a write cycle CE and WE
IH
IH
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and OE =
Byte/Word Configuration
V
will not accept commands on the rising edge of WE.
IH
The internal state machine is automatically reset to the
read mode on power-up.
The BYTE pin selects the byte (8-bit) mode or word
(16 bit) mode for the Am29F400A device. When this
pin is driven high, the device operates in the word (16
16
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence
(see below)
Data Poll Device
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
20380B-8
Figure 1. Embedded Programming Algorithm
Am29F400AT/Am29F400AB
17
P R E L I M I N A R Y
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence
(see below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Individual Sector/Multiple Sector
Chip Erase Command Sequence
Erase Command Sequence
(Address/Command):
(Address/Command):
5555H/AAH
2AAAH/55H
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional
Sector Address/30H
20380B-9
Note:
To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub-
sequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted.
Figure 2. Embedded Erase Algorithm
18
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
Start
VA =Byte address for programming
Read Byte
(DQ0-DQ7)
Addr=VA
=any of the sector addresses within the
sector being erased during sector erase
operation
=Valid address equals any non-protected
sector group address during chip erase
Yes
DQ7=Data
?
No
No
DQ5=1
?
Yes
Read Byte
(DQ0-DQ7)
Addr=VA
Yes
DQ7=Data
?
Pass
No
Fail
20380B-10
Note:
DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 3. Data Polling Algorithm
Am29F400AT/Am29F400AB
19
P R E L I M I N A R Y
Start
Read Byte
(DQ0–DQ7)
Addr=Don’t Care
No
DQ6=Toggle
?
Yes
No
DQ5=1
?
Yes
Read Byte
(DQ0–DQ7)
Addr=Don’t Care
No
DQ6=Toggle
?
Yes
Pass
Fail
20380B-11
Note:
DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.
Figure 4. Toggle Bit Algorithm
20 ns
20 ns
+0.8 V
-0.5 V
-2.0 V
20380B-12
20 ns
Figure 5. Maximum Negative Overshoot Waveform
20 ns
V
+ 2.0 V
CC
V
+ 0.5 V
2.0 V
CC
20380B-13
20 ns
20 ns
Figure 6. Maximum Positive Overshoot Waveform
20
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
Plastic Packages . . . . . . . . . . . . . . . -65°C to +125°C
Ambient Temperature (T ). . . . . . . . . . . . 0˚C to +70˚C
A
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . -55°C to +125°C
Industrial (I) Devices
Ambient Temperature (T ). . . . . . . . . . -40˚C to +85˚C
A
Voltage with Respect to Ground
All pins except A9, OE and RESET
Extended (E) Devices
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . -2.0 V to +7.0 V
Ambient Temperature (T ). . . . . . . . . -55˚C to +125˚C
A
V
(Note 1). . . . . . . . . . . . . . . . . . . . -2.0 V to +7.0 V
V
V
V
Supply Voltages
CC
CC
CC
CC
A9, OE, and RESET (Note 2). . . . . . -2.0 V to +13.0 V
for Am29F400T/B-65, . . . . . . +4.75 V to +5.25 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
for Am29F400T/B-70, -90,
-120, -150 . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V. During
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
voltage transitions, input or I/O pins may undershoot V
SS
to -2.0 V for periods of up to 20 ns. Maximum DC voltage
on input or I/O pins is VCC +0.5 V. During voltage
transitions, input or I/O pins may overshoot to V +2.0 V
CC
for periods up to 20 ns. See Figure 7 and Figure 8.
2. Minimum DC input voltage on pins A9, OE, and RESET is
-0.5 V. During voltage transitions, A9, OE, and RESET
may undershoot V to -2.0 V for periods of up to 20 ns.
SS
Maximum DC input voltage on pin A9 is +12.5 V which
may overshoot to 14.0 V for periods up to 20 ns. See
Figure 7 and Figure 8.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device
reliability.
Am29F400AT/Am29F400AB
21
P R E L I M I N A R Y
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
= V to V , V = V Max
Min
Max
±1.0
50
Unit
µA
I
Input Load Current
V
IN
LI
SS
CC CC
CC
I
A9, OE, RESET Input Load Current
Output Leakage Current
V
= V Max, A9, OE, RESET = 12.5 V
µA
LIT
CC
CC
I
V
= V to V , V = V Max
±1.0
40
µA
LO
OUT
SS
CC CC
CC
Byte
I
V
Active Read Current (Note 1)
Active Program/Erase Current
CE = V , OE = V
mA
mA
CC1
CC
IL
IH
Word
50
V
CC
I
I
CE = V , OE = V
60
CC2
IL
IH
(Notes 2, 3)
V
Standby Current
V
= V Max, CE = V , OE = V
1.0
0.8
mA
V
CC3
CC
CC
CC
IH
IH
V
Input Low Voltage
Input High Voltage
–0.5
2.0
IL
V
V
+ 0.5
V
IH
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
= 5.0 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
Output High Voltage
I
= 5.8 mA, V = V Min
V
V
V
OL
OL
CC
CC
V
I
= -2.5 mA, V = V Min
2.4
3.2
OH
OH
CC
CC
V
Low V Lock-Out Voltage
4.2
LKO
CC
Notes:
1. The I current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
CC
The frequency component typically is less than 2 mA/MHz, with OEat V .
IH
2. I active while Embedded Program or Erase Algorithm is in progress.
CC
3. Not 100% tested.
22
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
DC CHARACTERISTICS (continued)
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
= V to V , V = V Max
Min
Typ
Max
Unit
I
Input Load Current
V
±1.0
µA
LI
IN
SS
CC CC
CC
V
= V Max, A9, OE,
CC
A9, OE, RESET Input Load
Current
CC
I
50
µA
µA
LIT
RESET = 12.5 V
I
Output Leakage Current
V
= V to V , V = V Max
±1.0
40
LO
OUT
SS
CC CC
CC
Byte
20
28
I
V
Active Read Current (Note 1) CE = V , OE = V
mA
mA
CC1
CC
IL
IH
Word
50
V
Active Program/Erase
CC
I
I
CE = V , OE = V
30
1
50
CC2
IL
IH
Current (Notes 2, 3)
V
= V Max, CE = V ,
CC IH
CC
V
Standby Current (Note 4)
5
µA
V
CC3
CC
OE = V
IH
V
Input Low Voltage
Input High Voltage
-0.5
0.8
IL
0.7 x
V
+
CC
0.3
V
V
V
IH
V
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
= 5.0 V
11.5
12.5
0.45
V
V
V
ID
CC
V
Output Low Voltage
I
= 5.8 mA, V = V Min
OL
OL CC CC
0.85
V
I
I
= –2.5 mA, V = V Min
CC CC
OH1
OH
OH
V
CC
Output Low Voltage
V
= –100 µA, V = V Min
V -0.4
CC
V
V
OH2
CC
CC
V
Low V Lock-Out Voltage
3.2
4.2
LKO
CC
Notes:
1. The I current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
CC
The frequency component typically is less than 2 mA/MHz, with OEat V .
IH
2. I active while Embedded Program or Erase Algorithm is in progress.
CC
3. Not 100% tested.
4. I
= 20 µA max at extended temperatures (> +85°C).
CC3
Am29F400AT/Am29F400AB
23
P R E L I M I N A R Y
AC CHARACTERISTICS
Read-Only Operations Characteristics
Parameter
Symbols
Speed Option (Notes 1 and 2)
JEDEC Standard Description
Test Setup
Min
-65
-70
-90
-120
-150
Unit
t
t
t
t
t
t
t
t
Read Cycle Time (Note 4)
60
70
90
120
150
ns
AVAV
AVQV
ELQV
GLQV
RC
CE = V
IL
Address to Output Delay
Max
Max
Max
60
60
30
70
70
30
90
90
35
120
120
50
150
150
55
ns
ns
ns
ACC
CE
OE = V
IL
Chip Enable to Output Delay OE = V
IL
Output Enable to Output
Delay
OE
Chip Enable to Output High Z
(Notes 3, 4)
t
t
t
Max
Max
20
20
20
20
20
20
30
30
35
35
ns
ns
EHQZ
GHQZ
DF
DF
Output Enable to Output
High Z (Notes 3, 4)
t
Output Hold Time From
Addresses, CE or OE,
Whichever Occurs First
t
t
Min
0
0
0
0
0
ns
AXQX
OH
RESET Pin Low to Read
Mode (Note 4)
t
Max
Max
20
5
20
5
20
5
20
5
20
5
µs
Ready
t
t
CE to BYTE Switching Low
or High
ELFL
ELFH
ns
Notes:
1. Test Conditions (for -65 only)
Output Load: 1 TTL gate and 30 pF
Input Rise and Fall Times: 5 ns
Input Pulse Levels:0.0 V to 3.0 V
Timing Measurement Reference Level: 1.5 V input
and output
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2.0 V
input and output
3. Output Driver Disable Time
4. Not 100% tested.
2. Test Conditions (for -70, -90, -120, -150)
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 20 ns
5.0 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
C
L
6.2 kΩ
IN3064 or Equivalent
IN3064 or Equivalent
IN3064 or Equivalent
Notes:
For -65: C = 30 pF including jig capacitance
L
For all others: C = 100 pF including jig capacitance
L
20380B-14
Figure 7. Test Conditions
Am29F400AT/Am29F400AB
24
P R E L I M I N A R Y
AC CHARACTERISTICS
Write (Erase/Program) Operations
Parameter Symbols
Speed Option (Notes 1 and 2)
JEDEC
Standard Description
-65
-70
70
0
-90
90
0
-120
120
0
-150
150
0
Unit
ns
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
Min
60
0
AVAV
WC
AS
AH
DS
DH
ns
AVWL
WLAX
DVWH
WHDX
45
30
0
45
30
0
45
45
0
50
50
0
150
50
0
ns
ns
ns
Read (Note 2)
0
0
0
0
0
ns
Output
t
Enable
Hold Time
OEH
Toggle and Data Polling
(Note 2)
Min
Min
10
0
10
0
10
0
10
0
10
0
ns
ns
Read Recovery Time Before Write
(OE High to WE Low)
t
t
GHWL
GHWL
t
t
t
t
t
t
t
t
CE Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Max
Min
Min
0
0
0
0
0
0
0
0
0
0
ns
ns
ELWL
CS
CE Hold Time
WHEH
WLWH
WHDL
CH
Write Pulse Width
Write Pulse Width High
35
20
7
35
20
7
45
20
7
50
20
7
50
20
7
ns
WP
WPH
ns
Byte
Programming Operation
Word
µs
t
t
t
WHWH1
WHWH2
WHWH1
14
1.0
8
14
1.0
8
14
1.0
8
14
1.0
8
14
1.0
8
µs
sec
sec
µs
t
Sector Erase Operation (Note 1)
WHWH2
t
t
V
Setup Time (Note 2)
50
500
50
500
50
500
50
500
50
500
VCS
CC
Rise Time to V (Notes 2, 3)
ns
VIDR
ID
OE Setup Time to WE Active
(Notes 2, 3)
t
Min
4
4
4
4
4
µs
OESP
t
t
RESET Pulse Width
Min
500
20
500
20
500
30
500
30
500
30
ns
ns
RP
BYTE Switching Low to Output High Z
(Notes 3, 4)
Max
FLQZ
Program/Erase Valid to RY/BY Delay
(Note 2)
t
t
Min
Min
30
4
30
4
35
4
50
4
55
4
ns
BUSY
RESET Setup Time to WE Active
µs
RESSP
Notes:
1. This does not include the preprogramming time.
2. Not 100% tested.
3. These timings are for Temporary Sector Unprotect operation.
4. Output Driver Disable Time.
Am29F400AT/Am29F400AB
25
P R E L I M I N A R Y
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010
SWITCHING WAVEFORMS
t
RC
Addresses
Addresses Stable
t
ACC
CE
OE
(t
)
DF
t
OE
t
OEH
WE
(t
)
CE
(t
)
OH
High Z
High Z
Output Valid
Outputs
20380B-15
Figure 8. AC Waveforms for Read Operations
26
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
SWITCHING WAVEFORMS
3rd Bus Cycle
Data Polling
PA
PA
5555H
t
Addresses
CE
t
t
RC
AH
WC
t
AS
t
GHWL
OE
t
t
WHWH1
WP
WE
t
WPH
t
CS
t
DF
t
t
DH
OE
D
Data
5.0 V
PD
DQ7
A0H
OUT
t
DS
t
OH
t
CE
20380B-16
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. D is the output of the data written to the device.
OUT
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
Figure 9. Program Operation Timings
t
AH
Addresses
2AAAH
5555H
5555H
5555H
2AAAH
SA
t
AS
CE
OE
t
GHWL
t
WP
WE
t
WPH
t
CS
t
DH
Data
t
55H
80H
55H
10H/30H
AAH
AAH
DS
V
t
CC
VCS
20380B-17
Notes:
1. SA is the sector address for Sector Erase. Addresses = don’t care for Chip Erase.
2. These waveforms are for the x16 mode.
Figure 10. AC Waveforms Chip/Sector Erase Operations
Am29F400AT/Am29F400AB
27
P R E L I M I N A R Y
SWITCHING WAVEFORMS
t
CH
CE
t
DF
t
OE
OE
t
OEH
WE
t
CE
t
OH
*
High Z
DQ7=
DQ7
DQ7
Valid Data
t
WHWH 1 or 2
DQ0-DQ6
Valid Data
DQ0-DQ6=Invalid
DQ0-DQ6
20380B-18
Note:
*DQ7=Valid Data (The device has completed the Embedded operation).
Figure 11. AC Waveforms for Data Polling During Embedded Algorithm Operations
CE
t
OEH
WE
OE
*
Data
(DQ0-DQ7)
DQ6=
Stop Toggling
DQ0-DQ7
Valid
DQ6=Toggle
DQ6=Toggle
t
OE
20380B-19
Note:
*DQ6 stops toggling (The device has completed the Embedded operation).
Figure 12. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
28
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
SWITCHING WAVEFORMS
CE
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
t
BUSY
20380B-20
Figure 13. RY/BY Timing Diagram During Program/Erase Operations
RESET
t
RP
t
Ready
20380B-21
Figure 14. RESET Timing Diagram
Am29F400AT/Am29F400AB
29
P R E L I M I N A R Y
SWITCHING WAVEFORMS
CE
OE
BYTE
t
t
ELFL
ELFH
Data Output
(DQ0-DQ7)
Data Output
(DQ0-DQ14)
DQ0-DQ14
DQ15/A-1
DQ15
Output
Address
Input
t
FLQZ
20380B-22
Figure 15. BYTE Timing Diagram for Read Operation
CE
The falling edge of the last WE signal
WE
BYTE
t
SET
(t
)
AS
t
(t
)
HOLD AH
20380B-23
Figure 16. BYTE Timing Diagram for Write Operations
30
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
Start
RESET = V
(Note 1)
ID
Perform Erase or
Program Operations
RESET = V
IH
Temporary Sector Group
Unprotect Completed
(Note 2)
20380B-24
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 17. Temporary Sector Unprotect Algorithm
5 V
12 V
RESET
CE
t
VIDR
WE
Program or Erase Command Sequence
RY/BY
20380B-25
Figure 18. Temporary Sector Unprotect Timing Diagram
Am29F400AT/Am29F400AB
31
P R E L I M I N A R Y
AC CHARACTERISTICS
Write/Erase/Program Operations
Alternate CE Controlled Writes
Parameter Symbols
Speed Option (Notes 1 and 2)
JEDEC Standard Description
-65
60
0
-70
70
0
-90
90
0
-120
120
0
-150
150
0
Unit
ns
t
t
Write Cycle Time (Note 2)
Min
Min
Min
Min
Min
Min
Min
AVAV
AVEL
ELAX
DVEH
EHDX
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
ns
AS
AH
DS
DH
t
t
45
30
0
45
30
0
45
45
0
50
50
0
50
50
0
ns
t
t
ns
t
t
Data Hold Time
ns
t
Output Enable Setup Time
0
0
0
0
0
ns
OES
Read (Note 2)
0
0
0
0
0
ns
Output Enable
Hold Time
t
OEH
Toggle and Data
Polling (Note 2)
Min
10
10
10
10
10
ns
t
t
t
Read Recover Time Before Write
WE Setup Time
Min
Min
Min
Min
Min
Typ
Typ
Typ
Max
0
0
0
0
0
0
0
0
0
0
ns
ns
GHEL
GHEL
t
WLEL
WS
WH
t
t
WE Hold Time
0
0
0
0
0
ns
EHWH
t
t
CE Pulse Width
35
20
7
35
20
7
45
20
7
50
20
7
50
20
7
ns
ELEH
EHEL
CP
t
t
CE Pulse Width High
ns
CPH
Byte
ProgrammingOperation
Word
µs
t
t
t
t
WHWH1
WHWH1
14
1.0
8
14
1.0
8
14
1.0
8
14
1.0
8
14
1.0
8
µs
sec
sec
Sector Erase Operation (Note 1)
WHWH2
WHWH2
BYTE Switching Low to Output High Z
(Note 2)
t
Max
20
20
30
30
30
ns
FLQZ
Notes:
1. This does not include the preprogramming time.
2. Not 100% tested.
32
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
SWITCHING WAVEFORMS
Data Polling
PA
Addresses
PA
5555H
t
AH
t
WC
t
AS
WE
OE
t
GHEL
t
t
CP
WHWH1
CE
t
CPH
t
WS
t
DH
Data
D
A0H
PD
DQ7
OUT
t
DS
5.0 Volt
20380B-26
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. D is the output of the data written to the device.
OUT
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
Figure 19. Alternate CE Controlled Program Operation Timings
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Typ (Note 1)
Max
Unit
sec
sec
µs
Comments
Sector Erase Time
1.0
11
7
8
88
Excludes 00H programming prior to erasure
Excludes 00H programming prior to erasure
Excludes system-level overhead (Note 4)
Excludes system-level overhead (Note 4)
Excludes system-level overhead (Note 4)
Chip Erase Time
Byte Programming Time
Word Programming Time
Chip Programming Time
300 (Note 3)
600
14
3.6
µs
10.8 (Notes 3, 5)
sec
Notes:
1. 25°C, 5.0 V V , 100,000 cycles.
CC
2. Although Embedded Algorithms allow for longer chip program and erase time, the actual time will be considerably less since
bytes program or erase significantly faster than the worst case byte.
3. Under worst case condition of 90°C, 4.5 V V , 100,000 cycles.
CC
4. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each
byte. In the preprogramming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure.
5. The Embedded Algorithms allow for 2.5 ms byte program time. DQ5 = “1” only after a byte takes the theoretical maximum time
to program. A minimal number of bytes may require significantly more programming pulses than the typical byte.The majority
of the bytes will program within one or two pulses. This is demonstrated by the Typical and Maximum Programming Times
listed above.
Am29F400AT/Am29F400AB
33
P R E L I M I N A R Y
LATCHUP CHARACTERISTICS
Min
Max
V + 1.0 V
CC
Input Voltage with respect to V on all I/O pins
–1.0 V
SS
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 5.0 V, one pin at a time.
CC
CC
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
V = 0
IN
Typ
6
Max
7.5
12
Unit
pF
C
Input Capacitance
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8.5
8
pF
OUT
OUT
C
V
= 0
10
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
= 0
Typ
Max
Unit
pF
C
V
6
8.5
8
7.5
12
10
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
= 0
pF
OUT
OUT
C
V
pF
IN2
PP
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
34
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
Erase Suspend:
REVISION SUMMARY
Third paragraph, third sentence: Deleted the word “NOT.”
Distinctive Characteristics:
High Performance: The fastest speed option available
is now 60 ns.
Operating Ranges:
V
Supply Voltages: Added -65 and deleted -75 speed
CC
options in the list. Changed A9 maximum to +13.0 V.
Enhanced power management for standby mode:
Changed typical standby current to 1µA.
DC Characteristics:
General Description:
CMOS Compatible: Revised I specifications. Added
CC
Note 4 (refers to I
).
First paragraph, first sentence should read, “...orga-
nized as 512 Kbytes of 8 bits each or 256 Kwords of 16
bits each.” Added 60 ns speed option.
CC3
AC Characteristics:
Read Only Operations Characteristics: Added the -65
column and test conditions.
Product Selector Guide:
Added -65 column (60 ns, ±5% V ). Added -70 (70 ns,
CC
Replaced -75 column with -70 column.
±10% V ) and deleted -75 speed option.
CC
Test Conditions, Figure 7:
Ordering Information, Standard Products:
Changed speed option in first C statement from -75
L
The -65 speed option is now listed in the example.
to -65.
Valid Combinations: Added -65 and -70, and deleted -
75 speed options.
AC Characteristics:
Write/Erase/Program Operations, Alternate CE Con-
trolled Writes: Added the -65 column. Replaced -75
column with -70 column. Revised sector erase and
programming specifications.
Tables 1 and 2, User Bus Operations:
Corrected WE for read operations; was don’t care (X),
is now H.
Erase and Programming Performance:
Standby Mode:
Revised specifications in table. Clarified table and notes.
Corrected standby mode current; was 100 µA, is now
5 µA.
Table 7, Command Definitions
Table 5, Sector Address Tables (Am29F400AB):
Revised Note 5 to cover all upper address bits that are
don’t care.
Corrected x16 starting address for SA5; was 1C000h,
is now 28000h.
Deleted Note 6.
Am29F400AT/Am29F400AB
35
相关型号:
AM29F400AB-120FC
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
AMD
AM29F400AB-120FCB
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
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AM29F400AB-120FI
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
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AM29F400AB-120FIB
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
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AM29F400AB-120SC
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
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AM29F400AB-120SCB
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
AMD
AM29F400AB-120SI
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
AMD
AM29F400AB-120SIB
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
AMD
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