AM29F160DB90EC_技术文档

Am29F160D

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 5.0 Volt single power supply operation

■ Compatibile with JEDEC standards

— Minimizes system-level power requirements

— Pinout and software compatible with single-

power supply Flash

■ High performance

— Superior inadvertent write protection

— Access times as fast as 70 ns

■ Embedded Algorithms

■ Manufactured on 0.25 µm process technology

■ CFI (Common Flash Interface) compliant

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Provides device-specific information to the

system, allowing host software to easily

reconfigure for different Flash devices

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Ultra low power consumption (typical values at

■ Erase Suspend/Erase Resume

5 MHz)

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

— 15 mA typical active read current

— 35 mA typical erase/program current

— 300 nA typical standby mode current

■ Data# Polling and toggle bits

■ Flexible sector architecture

— Provides a software method of detecting

program or erase operation completion

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

thirty-one 64 Kbyte sectors (byte mode)

■ Unlock Bypass Program command

— One 8 Kword, two 4 Kword, one 16 Kword, and

thirty-one 32 Kword sectors (word mode)

— Reduces overall programming time when

issuing multiple program command sequences

— Supports full chip erase

■ Ready/Busy# pin (RY/BY#)

— Sector Protection features:

— Provides a hardware method of detecting

program or erase cycle completion

— Hardware method of locking a sector to prevent

program or erase operations within that sector

■ Hardware reset pin (RESET#)

— Sectors can be locked in-system or via

programming equipment

— Hardware method to reset the device for reading

array data

— Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■ WP# input pin

■ Top boot or bottom boot configurations

— At _VIL, protects the 16 Kbyte boot sector,

regardless of sector protect/unprotect status

available

■ Minimum 1,000,000 write cycle guarantee

— At V_IH, allows removal of boot sector protection

per sector

■ Program and Erase Performance

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package options

— Sector erase time: 1 s typical for each 64 Kbyte

sector

— Byte program time: 7 µs typical

— 48-pin TSOP

Publication# 22288 Rev: D Amendment/0

Issue Date: December 4, 2000

GENERAL DESCRIPTION

The Am29F160D is a 16 Mbit, 5.0 Volt-only Flash

memory device organized as 2,097,152 bytes or

1,048,576 words. Data appears on DQ0-DQ7 or DQ0-

DQ15 depending on the data width selected. The

device is designed to be programmed in-system with

the standard system 5.0 volt V_CCsupply. A 12.0 volt

V_PPis not required for program or erase operations.

The device can also be programmed in standard

EPROM programmers.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, by reading the DQ7 (Data# Polling), or DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data

or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

The device offers access times of 70, 90, and 120 ns,

allowing high speed microprocessors to operate

without wait states. The device is offered in a 48-pin

TSOP package. To eliminate bus contention each

device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

Hardware data protection measures include a low

VCC detector that automatically inhibits write operations

during power transitions. The hardware sector protec-

tion feature disables both program and erase operations

in any combination of sectors of memory. This can be

achieved in-system or via programming equipment.

Each device requires only a single 5.0 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The Write Protect (WP#) feature protects the 16

Kbyte boot sector by asserting a logic low on the WP#

pin, whether or not the sector had been previously pro-

tected.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timing. Register contents

serve as inputs to an internal state-machine that con-

trols the erase and programming circuitry. Write cycles

also internally latch addresses and data needed for the

programming and erase operations. Reading data out

of the device is similar to reading from other Flash or

EPROM devices.

The Erase Suspend/Erase Resume feature enables

the user to put erase on hold for any period of time to

read data from, or program data to, any sector that is

not selected for erasure. True background erase can

thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read boot-up firmware from the Flash memory device.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

The device offers a standby mode as a power-saving

feature. Once the system places the device into the

standby mode power consumption is greatly reduced.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunnelling.

The data is programmed using hot electron injection.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automati-

cally preprograms the array (if it is not already pro-

grammed) before executing the erase operation.

During erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

2

Am29F160D

TABLE OF CONTENTS

Figure 5. Data# Polling Algorithm .................................................. 23

RY/BY#: Ready/Busy#............................................................ 24

DQ6: Toggle Bit I .................................................................... 24

DQ2: Toggle Bit II ................................................................... 24

Reading Toggle Bits DQ6/DQ2............................................... 24

DQ5: Exceeded Timing Limits ................................................ 25

DQ3: Sector Erase Timer ....................................................... 25

Figure 6. Toggle Bit Algorithm........................................................ 25

Table 10. Write Operation Status................................................... 26

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 27

Figure 7. Maximum Negative Overshoot Waveform ...................... 27

Figure 8. Maximum Positive Overshoot Waveform........................ 27

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 27

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

TTL/NMOS Compatible .......................................................... 28

CMOS Compatible.................................................................. 29

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 9. Test Setup....................................................................... 30

Table 11. Test Specifications......................................................... 30

Key to Switching Waveforms. . . . . . . . . . . . . . . . 30

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 10. Read Operations Timings ............................................. 31

Figure 11. RESET# Timings .......................................................... 32

Figure 12. BYTE# Timings for Read Operations............................ 33

Figure 13. BYTE# Timings for Write Operations............................ 33

Figure 14. Program Operation Timings.......................................... 35

Figure 15. Chip/Sector Erase Operation Timings .......................... 36

Figure 16. Data# Polling Timings (During Embedded Algorithms). 37

Figure 17. Toggle Bit Timings (During Embedded Algorithms)...... 37

Figure 18. DQ2 vs. DQ6................................................................. 38

Figure 19. Temporary Sector Unprotect Timing Diagram .............. 38

Figure 20. Sector Protect/Unprotect Timing Diagram .................... 39

Figure 21. Alternate CE# Controlled Write Operation Timings ...... 41

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 42

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Am29F160D Device Bus Operations .................................. 8

Word/Byte Configuration .......................................................... 8

Requirements for Reading Array Data ..................................... 8

Writing Commands/Command Sequences .............................. 9

Program and Erase Operation Status ...................................... 9

Standby Mode .......................................................................... 9

Automatic Sleep Mode ............................................................. 9

RESET#: Hardware Reset Pin ................................................. 9

Output Disable Mode................................................................ 9

Table 2. Am29F160DT Sector Address Table (Top Boot) .............. 10

Table 3. Am29F160DB Sector Address Table (Bottom Boot)......... 11

Autoselect Mode..................................................................... 12

Table 4. Am29F160D Autoselect Codes (High Voltage Method).... 12

Sector Protection/Unprotection............................................... 12

Write Protect (WP#)................................................................ 13

Temporary Sector Unprotect .................................................. 13

Figure 1. Temporary Sector Unprotect Operation........................... 13

Common Flash Memory Interface (CFI) . . . . . . . 15

Table 5. CFI Query Identification String.......................................... 15

Table 6. System Interface String..................................................... 16

Table 7. Device Geometry Definition .............................................. 16

Table 8. Primary Vendor-Specific Extended Query ........................ 17

Hardware Data Protection ...................................................... 18

Low V Write Inhibit...................................................................... 18

CC

Write Pulse “Glitch” Protection........................................................ 18

Logical Inhibit .................................................................................. 18

Power-Up Write Inhibit .................................................................... 18

Reading Array Data................................................................ 18

Reset Command..................................................................... 18

Autoselect Command Sequence............................................ 19

Word/Byte Program Command Sequence ............................. 19

Unlock Bypass Command Sequence.............................................. 19

Figure 3. Program Operation .......................................................... 20

Chip Erase Command Sequence........................................... 20

Sector Erase Command Sequence........................................ 20

Erase Suspend/Erase Resume Commands........................... 21

Figure 4. Erase Operation............................................................... 21

Command Definitions ............................................................. 22

Table 9. Am29F160D Command Definitions................................... 22

DQ7: Data# Polling................................................................. 23

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 42

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 43

TSR048—48-Pin Reverse Thin Small Outline Package......... 44

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 45

Revision A (January 1999) ..................................................... 45

Revision B (June 14, 1999) .................................................... 45

Revision B+1 (July 7, 1999).................................................... 45

Revision B+2 (July 14, 1999).................................................. 45

Revision B+3 (July 30, 1999).................................................. 45

Revision B+4 (September 10, 1999) ...................................... 45

Revision C (November 16, 1999) ........................................... 45

Revision D (December 4, 2000) ............................................. 45

Am29F160D

3

PRODUCT SELECTOR GUIDE

Family Part Number

Am29F160D

V

= 5.0 V ± 5%

= 5.0 V ± 10%

75

CC

Speed Option

V

90

35

120

50

Max access time, ns (t

)

70

30

ACC

Max CE# access time, ns (t

)

CE

Max OE# access time, ns (t

)

OE

Note:See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V

CC

Sector Switches

V

SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

WP#

Command

Register

BYTE#

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V

Detector

Timer

CC

Cell Matrix

X-Decoder

A0–A19

4

Am29F160D

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

A19

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ4

V_CC

48-Pin TSOP

Standard Pinout

WE#

RESET#

NC

WP#

RY/BY#

A18

A17

A7

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

A6

A5

A4

A3

A2

A1

1

2

3

4

5

6

7

8

9

A15

A14

A13

A12

A11

A10

A9

A8

A19

NC

WE#

RESET#

NC

WP#

RY/BY#

A18

A17

A7

A6

A5

A4

A3

48

A16

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48-Pin TSOP

Reverse Pinout

OE#

V_SS

CE#

A0

A2

A1

Am29F160D

5

PIN CONFIGURATION

LOGIC SYMBOL

A0–A19

= 20 address inputs

20

DQ0–DQ14 = 15 data inputs/outputs

A0–A19

16 or 8

DQ15/A-1

=

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

DQ0–DQ15

(A-1)

BYTE#

CE#

=

Select input for 8-bit or 16-bit mode

Chip Enable input

CE#

OE#

Output Enable input

Write Enable input

WE#

WP#

Write Protect input

RESET#

RY/BY#

RESET#

RY/BY#

V_CC

Hardware reset input

Ready/Busy# output

BYTE#

+5.0 V single power supply

(see Product Selector Guide for

device speed ratings and voltage

supply tolerances)

V_SS

NC

=

Device ground

Pin not connected internally

6

Am29F160D

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the elements below.

Am29F160D

T

75

E

C

TEMPERATURE RANGE

C

=

Commercial (0°C to +70°C)

I

=

Industrial (–40°C to +85°C)

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F

=

48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29F160D

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Boot Sector Flash Memory

5.0 Volt-only Read, Program and Erase

Valid Combinations

Order Number

Speed

(ns)

Voltage

Range

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

AM29F160DT75,

AM29F160DB75

5.0 V

± 5%

70

90

AM29F160DT90,

AM29F160DB90

EC, EI,

FC, FI

5.0 V

± 10%

AM29F160DT120,

AM29F160DB120

120

Am29F160D

7

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control levels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29F160D Device Bus Operations

DQ8–DQ15

BYTE#

= V

Addresses

(Note 1)

DQ0– BYTE#

Operation

Read

CE# OE# WE#

WP#

X

RESET#

DQ7

= V

IH

IL

L

H

A

D

DQ8–DQ14 = High-Z,

DQ15 = A-1

IN

OUT

Write

L

H

L

(Note 3)

H

A

D

IN

V

0.5 V

±

V

0.5 V

±

CC

Standby

X

(Note 4)

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect

(Note 2)

L

H

L

X

V

D

X

ID

IN

Sector Address,

A6 = H, A1 = H,

A0 = L

Sector Unprotect

(Note 2)

L

H

X

L

X

V

D

X

ID

IN

Temporary Sector

Unprotect

X

(Note 3)

A

D

High-Z

ID

IN

Legend:

L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out

IL

IH

ID

IN

OUT

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = V ), A19:A-1 in byte mode (BYTE# = V ).

IH

IL

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

3. The 16 Kbyte boot sector is protected when WP# = V .

IL

4. In CMOS mode, WP# must be at V ±0.5 V or left floating.

CC

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should re-

main at V_IH.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and control-

led by CE# and OE#.

The internal state machine is set for reading array

data upon device power-up, or after a hardware reset.

This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs

produce valid data on the device data outputs. The

device remains enabled for read access until the

command register contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

an input for the LSB (A-1) address function.

Requirements for Reading Array Data

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

8

Am29F160D

tions and to the Read Operations Timings diagram for

the timing waveforms. I_CC1in the DC Characteristics

table represents the active current specification for

reading array data.

The device also enters the standby mode when the RE-

SET# pin is driven low. Refer to the next section, “RE-

SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

In the DC Characteristics tables, I_CC3represents the

standby current specification.

Automatic Sleep Mode

An erase operation can erase one sector, multiple sec-

tors, or the entire device. The Sector Address Tables in-

dicate the address space that each sector occupies. A

“sector address” consists of the address bits required

to uniquely select a sector. See the “Command Defini-

tions” section for details on erasing a sector or the en-

tire chip, or suspending/resuming the erase operation.

The automatic sleep mode minimizes flash device

energy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC+ 30

ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address

access timings provide new data when addresses are

changed. While in sleep mode, output data is latched

and always available to the system.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the system

drives the RESET# pin low for at least a period of t_RP

,

the device immediately terminates any operation in

progress, tristates all data output pins, and ignores all

read/write attempts for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is ready

to accept another command sequence, to ensure data

integrity. Current is reduced for the duration of the RE-

SET# pulse.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I_CC

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac-

teristics section for timing diagrams.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# are held at V_CC± 0.5 V. (Note that

this is a more restricted voltage range than V_IH.) WP#

must also either be held at V_CC± 0.5 V or left floating.

The device enters the TTL standby mode when CE#

and RESET# pins are both held at V_IH. The device re-

quires standard access time (t_CE) for read access when

the device is in either of these standby modes, before it

is ready to read data.

Refer to the AC Characteristics tables for RESET# pa-

rameters and timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

Am29F160D

9

Table 2. Am29F160DT Sector Address Table (Top Boot)

Sector Size

(Kbytes/

Address Range (in hexadecimal)

Sector A19 A18 A17 A16 A15 A14 A13 A12

Kwords)

Byte Mode (x8)

000000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1F7FFF

1F8000–1F9FFF

1FA000–1FBFFF

1FC000–1FFFFF

Word Mode (x16)

00000–07FFF

08000–0FFFF

10000–17FFF

18000–1FFFF

20000–27FFF

28000–2FFFF

30000–37FFF

38000–3FFFF

40000–47FFF

48000–4FFFF

50000–57FFF

58000–5FFFF

60000–67FFF

68000–6FFFF

70000–77FFF

78000–7FFFF

80000–87FFF

88000–8FFFF

90000–97FFF

98000–9FFFF

A0000–A7FFF

A8000–AFFFF

B0000–B7FFF

B8000–BFFFF

C0000–C7FFF

C8000–CFFFF

D0000–D7FFF

D8000–DFFFF

E0000–E7FFF

E8000–EFFFF

F0000–F7FFF

F8000–FBFFF

FC000–FCFFF

FD000–FDFFF

FE000–FFFFF

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

64/32

32/16

8/4

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

1

0

1

8/4

1

X

16/8

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.

10

Am29F160D

Table 3. Am29F160DB Sector Address Table (Bottom Boot)

Sector Size

(Kbytes/

Address Range (in hexadecimal)

Sector A19 A18 A17 A16 A15 A14 A13 A12

Kwords)

Byte Mode (x8)

000000–003FFF

004000–005FFF

006000–007FFF

008000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

Word Mode (x16)

00000–01FFF

02000–02FFF

03000–03FFF

04000–07FFF

08000–0FFFF

10000–17FFF

18000–1FFFF

20000–27FFF

28000–2FFFF

30000–37FFF

38000–3FFFF

40000–47FFF

48000–4FFFF

50000–57FFF

58000–5FFFF

60000–67FFF

68000–6FFFF

70000–77FFF

78000–7FFFF

80000–87FFF

88000–8FFFF

90000–97FFF

98000–9FFFF

A0000–A7FFF

A8000–AFFFF

B0000–B7FFF

B8000–BFFFF

C0000–C7FFF

C8000–CFFFF

D0000–D7FFF

D8000–DFFFF

E0000–E7FFF

E8000–EFFFF

F0000–F7FFF

F8000–FFFFF

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

16/8

8/4

SA2

0

1

8/4

SA3

1

X

32/16

64/32

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.

Am29F160D

11

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

dress must appear on the appropriate highest order

address bits. Refer to the corresponding Sector Ad-

dress Tables. The Command Definitions table shows

the remaining address bits that are don’t care. When all

necessary bits have been set as required, the program-

ming equipment may then read the corresponding

identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

tions table. This method does not require V_ID. See

“Command Definitions” for details on using the autose-

lect mode.

When using programming equipment, the autoselect

mode requires V_ID(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Autoselect Codes (High Voltage Method) table. In addi-

tion, when verifying sector protection, the sector ad-

Table 4. Am29F160D Autoselect Codes (High Voltage Method)

A19 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

DQ15

DQ7

to

DQ0

Description

A6

A1

A0

Manufacturer ID: AMD

L

H

X

V

X

L

X

L

X

01h

D2h

ID

Device ID:

Am29F160D

(Top Boot Block)

Word

Byte

Word

Byte

22h

X

V

L

H

ID

L

H

X

22h

X

D2h

D8h

Device ID:

Am29F160D

(Bottom Boot Block)

X

V

X

ID

01h

(protected)

X

Sector Protection Verification

L

H

SA

L

H

L

ID

00h

(unprotected)

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

IL

IH

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 20 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect write

cycle.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

The alternate method intended only for programming

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 5.0 volt-only AMD flash devices. De-

tails on this method are provided in a supplement, pub-

lication number 22289. Contact an AMD representative

to request a copy.

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

Sector protection/unprotection can be implemented via

two methods.

12

Am29F160D

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting the 16 Kbyte boot sector without

using V_ID.

START

RESET# = V

(Note 1)

If the system asserts V_ILon the WP# pin, the device

disables program and erase functions for the 16 Kbyte

boot sector (SA34 for top boot device and SA0 for bot-

tom boot device) independently of whether those sec-

tors were protected or unprotected using the method

described in “Sector Protection/Unprotection”.

ID

Perform Erase or

Program Operations

If the system asserts V_IHon the WP# pin, the device

reverts to whether the 16 Kbyte boot sector was previ-

ously set to be protected or unprotected using the

method described in “Sector Protection/Unprotection”.

RESET# = V

IH

Temporary Sector

Unprotect Completed

(Note 2)

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

sector addresses. Note, however, that the boot sector

will still be protected if WP# is asserted low. Once V_ID

is removed from the RESET# pin, all the previously pro-

tected sectors are protected again. Figure shows the

algorithm, and Figure 19 shows the timing diagrams,

for this feature.

Notes:

1. All protected sectors unprotected. Boot sector remains

protected if WP# is low.

2. All previously protected sectors are protected once

again.

Figure 1. Temporary Sector Unprotect Operation

Am29F160D

13

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 µs

unprotect address

No

First Write

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/Unprotect Algorithms

Am29F160D

14

The system can read CFI information at the addresses

given in Tables 5–8. In word mode, the upper address

bits (A7–MSB) must be all zeros. To terminate reading

CFI data, the system must write the reset command.

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-indepen-

dent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families.

Flash vendors can standardize their existing interfaces

for long-term compatibility.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 5–8. The

system must write the reset command to return the

device to the autoselect mode.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/products/nvd/over-

view/cfi.html. Alternatively, contact an AMD represen-

tative for copies of these documents.

This device enters the CFI Query mode when the

system writes the CFI Query command, 98h, to

address 55h in word mode (or address AAh in byte

mode), any time the device is ready to read array data.

Table 5. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

Am29F160D

15

Table 6. System Interface String

Data Description

Addresses

(Word Mode)

Addresses

(Byte Mode)

V

Min. (write/erase)

CC

1Bh

36h

0045h

D7–D4: volt, D3–D0: 100 millivolt

V

Max. (write/erase)

CC

1Ch

38h

0055h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V

Min. voltage (00h = no V pin present)

PP

Max. voltage (00h = no V pin present)

PP

N

Typical timeout per single byte/word write 2 µs

N

Typical timeout for Min. size buffer write 2 µs (00h = not supported)

N

Typical timeout per individual block erase 2 ms

N

Typical timeout for full chip erase 2 ms (00h = not supported)

N

Max. timeout for byte/word write 2 times typical

N

Max. timeout for buffer write 2 times typical

N

Max. timeout per individual block erase 2 times typical

N

Max. timeout for full chip erase 2 times typical (00h = not supported)

Table 7. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

N

27h

4Eh

0015h

Device Size = 2 byte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

N

2Ah

2Bh

54h

56h

0000h

Max. number of byte in multi-byte write = 2

(00h = not supported)

2Ch

58h

0004h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0000h

0040h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

0001h

0000h

0020h

0000h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

0080h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

001Eh

0000h

0001h

16

Am29F160D

Table 8. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock

0 = Required, 1 = Not Required

45h

46h

47h

48h

8Ah

8Ch

8Eh

90h

0000h

0002h

0001h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

49h

92h

0004h

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

Simultaneous Operation

00 = Not Supported, 01 = Supported

4Ah

4Bh

4Ch

94h

96h

98h

0000h

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh

4Eh

9Ah

9Ch

0000h

ACC Supply Minimum

ACC Supply Maximum

Top/Bottom Boot Sector Flag

02 = bottom, 03 = top

0002h,

0003h

4Fh

9Eh

Am29F160D

17

proper signals to the control pins to prevent uninten-

tional writes when V_CCis greater than V_LKO

Hardware Data Protection

.

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection measures prevent accidental erasure or pro-

gramming, which might otherwise be caused by spuri-

ous system level signals during V_CCpower-up and

power-down transitions, or from system noise.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until V_CC

is greater than V_LKO. The system must provide the

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the im-

proper sequence resets the device to reading array

data.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Read Operation Timings diagram shows the

timing diagram.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data.

After completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See “Erase Sus-

pend/Erase Resume Commands” for more information

on this mode.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

The system must issue the reset command to re-en-

able the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

18

Am29F160D

margin. The Command Definitions take shows the ad-

dress and data requirements for the byte program com-

mand sequence.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements. This method is an alternative to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

mers and requires V_IDon address bit A9.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using DQ7,

DQ6, or RY/BY#. See “Write Operation Status” for in-

formation on these status bits.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The program command sequence

should be reinitiated once the device has reset to read-

ing array data, to ensure data integrity.

A read cycle at address XX00h retrieves the manufac-

turer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) returns the device code.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

A read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode) re-

turns 01h if that sector is protected, or 00h if it is un-

protected. Refer to the Sector Address tables for valid

sector addresses. When a read occurs at an address

within the 16 Kbyte boot sector (SA34 for top boot de-

vices and SA0 for bottom boot devices), the input on

WP# may determine what code will be returned.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram words to the device faster than using the stan-

dard program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 9 shows the requirements for the

command sequence.

16Kb Sector

Protection

WP#

input

Autoselect

Code

protected

V

01 (protected)

00 (unprotected)

01 (protected)

IH

V

IL

unprotected

V

IH

V

IL

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by byte or word,

on depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically provides internally gen-

erated program pulses and verify the programmed cell

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h. The second cycle must contain the data 00h. The

device then returns to the read mode.

Am29F160D

19

The system can determine the status of the erase

operation by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data

and addresses are no longer latched.

START

Write Program

Command Sequence

Figure 4 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to the Chip/Sector

Erase Operation Timings for timing waveforms.

Data Poll

from System

Sector Erase Command Sequence

Embedded

Program

algorithm

in progress

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two un-

lock cycles, followed by a set-up command. Two addi-

tional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the sec-

tor erase command sequence.

Verify Data?

Yes

No

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Increment Address

Last Address?

Yes

Programming

Completed

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time be-

tween these additional cycles must be less than 50 µs,

otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended

that processor interrupts be disabled during this time to

ensure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. If the time between additional sector erase

commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

Note: See the appropriate Command Definitions table for

program command sequence.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Note that a hardware

reset during the chip erase operation immediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device has

returned to reading array data, to ensure data integrity.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the op-

eration. The Sector Erase command sequence should

20

Am29F160D

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard program oper-

ation. See “Write Operation Status” for more informa-

tion.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. Refer to “Write Operation Status” for informa-

tion on these status bits.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

the Sector Erase Operations Timing diagram for timing

waveforms.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase Sus-

pend command.

START

Write Erase

Command Sequence

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on these

status bits.

Data = FFh?

Yes

Erasure Completed

1. See the appropriate Command Definitions table for erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine

Figure 4. Erase Operation

Am29F160D

21

Command Definitions

Table 9. Am29F160D Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data Addr Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

AAA

555

AAA

555

AAA

RD

F0

Word

2AA

555

2AA

555

2AA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

01

Byte

Word

Byte

Word

Byte

X01

X02

X01

X02

22D2

D2

Device ID,

Top Boot Block

AAA

555

22D8

D8

Device ID,

Bottom Boot Block

AAA

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

CFI Query (Note 10)

1

4

3

98

AA

2AA

555

2AA

555

PA

555

AAA

555

Program

55

A0

20

PA

PD

AAA

555

Unlock Bypass

AAA

XXX

555

AAA

Unlock Bypass Program (Note 11)

Unlock Bypass Reset (Note 12)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

6

AA

55

80

AA

55

10

30

Byte

Word

Byte

AAA

555

AAA

Sector Erase

SA

AAA

XXX

AAA

Erase Suspend (Note 13)

Erase Resume (Note 14)

1

B0

30

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A19–A12 uniquely select any sector.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever

happens later.

Notes:

1. See Table 1 for description of bus operations.

9. The data is 00h for an unprotected sector and 01h for a protected

sector. See “Autoselect Command Sequence” for more

information.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are

write operations.

10. Command is valid when device is ready to read array data or

when device is in autoselect mode.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command

cycles.

11. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

5. Address bits A19–A11 are don’t cares for unlock and command

cycles, unless SA or PA required.

12. The Unlock Bypass Reset command is required to return to

reading array data when the device is in the unlock bypass mode.

6. No unlock or command cycles required when reading array data.

13. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

7. The Reset command is required to return to reading array data

when device is in the autoselect mode, CFI query mode, or if

DQ5 goes high (while the device is providing status data).

8. The fourth cycle of the autoselect command sequence is a read

cycle.

14. The Erase Resume command is valid only during the Erase

Suspend mode.

22

Am29F160D

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,

and RY/BY#. Table 10 and the following subsections

describe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

Table 10 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

Read DQ7–DQ0

Addr = VA

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is in

Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the program or erase

command sequence.

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for ap-

proximately 2 µs, then the device returns to reading

array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

DQ0 on the following read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. The Data# Poll-

ing Timings (During Embedded Algorithms) figure in

the “AC Characteristics” section illustrates this.

Figure 5. Data# Polling Algorithm

Am29F160D

23

The Write Operation Status table shows the outputs for

Toggle Bit I on DQ6. Refer to Figure 6 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

The DQ2 vs. DQ6 figure shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on “DQ2: Toggle Bit II”.

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC

.

DQ2: Toggle Bit II

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

Table 10 shows the outputs for RY/BY#. The timing di-

agrams for read, reset, program, and erase shows the

relationship of RY/BY# to other signals.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 10 to compare out-

puts for DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the “DQ6: Toggle Bit I” subsection.

Refer to the Toggle Bit Timings figure for the toggle bit

timing diagram. The DQ2 vs. DQ6 figure shows the dif-

ferences between DQ2 and DQ6 in graphical form.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, a

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The sys-

tem can read array data on DQ7–DQ0 on the following

read cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not complete the operation successfully, and

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

24

Am29F160D

the system must write the reset command to return to

reading array data.

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 10 shows the outputs for DQ3.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 6).

START

Read DQ7–DQ0

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

Read DQ7–DQ0

(Note 1)

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

(Notes

1, 2)

Read DQ7–DQ0

Twice

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the system can guarantee that the time between ad-

ditional sector erase commands will always be less

than 50 µs. See also the “Sector Erase Command Se-

quence” section.

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence, and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all further commands (other than Erase Suspend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

Figure 6. Toggle Bit Algorithm

Am29F160D

25

Table 10. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 1)

DQ6

(Note 2)

DQ3

N/A

1

(Note 1)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend Reading within Non-Erase

Data

0

Data

N/A

Data

N/A

1

0

Mode

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

26

Am29F160D

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

20 ns

+0.8 V

Voltage with Respect to Ground

V_CC(Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

–0.5 V

–2.0 V

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V

All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

Figure 7. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may undershoot V

SS

to –2.0 V for periods of up to 20 ns. See Figure 7.

Maximum DC voltage on input or I/O pins is V +0.5 V.

CC

During voltage transitions, input or I/O pins may overshoot

to V +2.0 V for periods up to 20 ns. See Figure 8.

CC

20 ns

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

V

CC

RESET# may undershoot V to –2.0 V for periods of up

+2.0 V

SS

to 20 ns. See Figure 7. Maximum DC input voltage on pin

A9 is +12.5 V which may overshoot to +13.5 V for periods

up to 20 ns.

V

CC

+0.5 V

2.0 V

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

Note: Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . –55°C to +125°C

V_CCSupply Voltages

V_CCfor ±5% devices . . . . . . . . . . .+4.75 V to +5.25 V

V_CCfor ±10% devices . . . . . . . . . . . .+4.5 V to +5.5 V

Note: Operating ranges define those limits between which

the functionality of the device is guaranteed.

Am29F160D

27

DC CHARACTERISTICS

TTL/NMOS Compatible

Parameter

Description

Test Conditions

= V to V , V = V

CC max

Min

Typ

Max

Unit

I

Input Load Current

V

±1.0

µA

LI

IN

SS

CC CC

V

= V

;

CC max

CC

I

A9, OE#, RESET Input Load Current

Output Leakage Current

35

±1.0

40

µA

LIT

A9 = OE# = RESET# = 12.5 V

I

V

OUT

= V to V

LO

SS

CC

CE# = V , OE# = V

f = 5 MHz, Byte Mode

,

IL

IH

15

mA

V

Active Read Current

CC

I

CC1

(Notes 1, 2)

CE# = V , OE# = V

,

IH

IL

50

mA

f = 5 MHz, Word Mode

V

Active Write Current

CC

I

CE# = V OE# = V

35

CC2

CC3

IL,

IH

(Notes 2, 3 and 4)

V

Standby Current (Notes 2, 5)

CE#, OE#, and RESET# = V

0.4

1

mA

V

CC

IH

V

Input Low Voltage

Input High Voltage

–0.5

2.0

0.8

IL

V

CC

V

IH

+ 0.5

12.5

0.45

Voltage for Autoselect and Temporary

Sector Unprotect

V

= 5.0 V

CC

11.5

ID

V

Output Low Voltage

Output High Voltage

I

= 5.8 mA, V = V

CC min

V

OL

CC

V

= –2.5 mA, V = V

CC min

2.4

3.2

OH

CC

V

Low V Lock-Out Voltage (Note 4)

4.2

LKO

CC

Notes:

1. The I current listed is typically less than 2 mA/MHz, with OE# at V

.

IH

CC

2. Maximum I specifcations are tested with V = V max

CC

3. I active while Embedded Erase or Embedded Program is in progress.

CC

4. Not 100% tested.

5. I

= 20 µA max at extended temperature (>+85°C)

CC3

28

Am29F160D

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Conditions

= V to V

Min

Typ

Max

Unit

V

,

IN

SS

CC

I

Input Load Current

±1.0

µA

LI

= V

CC

CC max

A9, OE#, RESET Input Load

Current

V

= V

,

CC

CC max

I

35

µA

LIT

A9 = OE# = RESET = 12.5 V

V

= V to V

,

OUT

CC

SS

CC

I

Output Leakage Current

±1.0

LO

= V

CC max

CE# = V , OE# = V ,

IL

IH

f = 5 MHz

15

40

mA

Byte Mode

V

Active Read Current

CC

I

CC1

(Note 2)

CE# = V , OE# = V ,

IL

IH

f = 5 MHz

Word Mode

15

35

50

mA

µA

V

Active Write Current

CC

I

CE# = V , OE# = V

IL

CC2

CC3

IH

(Notes 1, 2, 3)

CE# and RESET# = V ±0.5 V,

CC

V

Standby Current (Note 2)

WP# = V ±0.5 V or floating,

0.3

5

CC

OE# = V

IH

V

Input Low Voltage

Input High Voltage

–0.5

0.8

V

IL

V

0.7 x V

V

+ 0.3

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 5.0 V

CC

11.5

12.5

0.45

V

ID

V

Output Low Voltage

I

= 5.8 mA, V = V

CC min

V

OL

OH

CC

V

= –2.5 mA, V = V

0.85 V

OH1

OH2

CC

CC min

CC

Output High Voltage

V

= –100 µA, V = V

V

–0.4

CC

Low V Lock-Out Voltage (Note

3)

CC

V

3.2

4.2

V

LKO

Notes:

1. I active while Embedded Erase or Embedded Program is in progress.

CC

2. Maximum I specifcations are tested with V = V max

CC

3. Not 100% tested.

Am29F160D

29

TEST CONDITIONS

Table 11. Test Specifications

5.0 V

Test Condition

75

90, 120 Unit

Output Load

1 TTL gate

100

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C

(including jig capacitance)

L

30

5

pF

C

L

Input Rise and Fall Times

Input Pulse Levels

20

ns

6.2 kΩ

0.0–3.0 0.45–2.4

V

Input timing measurement

reference levels

1.5

0.8, 2.0

V

Output timing measurement

reference levels

Note:

Diodes are IN3064 or equivalents.

Figure 9. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

30

Am29F160D

AC CHARACTERISTICS

Read Operations

Parameter

Speed Option

90

JEDEC

Std Description

Test Setup

75

120

Unit

t

Read Cycle Time (Note 1)

Address to Output Delay

Min

70

90

120

ns

AVAV

RC

CE# = V

OE# = V

IL

t

Max

70

ns

AVQV

ACC

t

Chip Enable to Output Delay

OE# = V

Max

70

30

20

90

35

20

120

50

ns

ELQV

GLQV

EHQZ

CE

IL

t

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

OE

t

30

DF

Output Enable to Output High Z

(Note 1)

t

Max

Min

20

0

30

ns

GHQZ

Read

Output Enable

t

Hold Time

(Note 1)

OEH

Toggle and

Data# Polling

10

Output Hold Time From Addresses, CE#

or OE#, Whichever Occurs First (Note 1)

t

Min

0

ns

AXQX

OH

Notes:

1. Not 100% tested.

2. See Figure 9 and Table 11 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

Figure 10. Read Operations Timings

Am29F160D

31

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std Description

Test Setup

All Speed Options

Unit

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

t

Max

20

µs

READY

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t

Max

500

ns

READY

t

RESET# Pulse Width

Min

500

50

0

ns

RP

RH

RB

RESET# High Time Before Read (See Note)

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 11. RESET# Timings

32

Am29F160D

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std.

Description

75

90

5

120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

ELFL/ ELFH

20

70

20

90

30

ns

FLQZ

120

ns

FHQV

CE#

OE#

BYTE#

t

ELFL

Data Output

BYTE#

Switching

from word

to byte

DQ0–DQ14

DQ15/A-1

(DQ0–DQ14)

(DQ0–DQ7)

Address

Input

DQ15

Output

mode

t

FLQZ

t

ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t

FHQV

Figure 12. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

SET

(t

)

AS

t

(t

)

HOLD AH

Note: Refer to the Erase/Program Operations table for t and t specifications.

AS

AH

Figure 13. BYTE# Timings for Write Operations

Am29F160D

33

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

JEDEC

Std.

Description

75

90

0

120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

120

AVAV

WC

t

ns

AVWL

WLAX

DVWH

WHDX

AS

AH

DS

DH

t

45

30

45

0

50

ns

t

ns

t

Data Hold Time

ns

t

Output Enable Setup Time

0

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHWL

t

CE# Setup Time

Min

Typ

Min

0

ns

ELWL

WHEH

WLWH

WHWL

CS

CH

WP

t

CE# Hold Time

t

Write Pulse Width

Write Pulse Width High

35

45

20

7

50

t

WPH

Byte

t

Programming Operation (Note 2)

µs

WHWH1

WHWH2

WHWH1

Word

12

1

t

Sector Erase Operation (Note 2)

sec

µs

WHWH2

t

V

Setup Time (Note 1)

CC

50

0

VCS

t

Recovery Time from RY/BY#

ns

RB

t

Program/Erase Valid to RY/BY# Delay

30

35

50

ns

BUSY

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

34

Am29F160D

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. Illustration shows device in word mode.

Figure 14. Program Operation Timings

Am29F160D

35

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 15. Chip/Sector Erase Operation Timings

36

Am29F160D

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note:

VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 16. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

RY/BY#

Note:

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,

and array data read cycle.

Figure 17. Toggle Bit Timings (During Embedded Algorithms)

Am29F160D

37

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the

erase-suspended sector.

Figure 18. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std.

Description

Rise and Fall Time (See Note)

All Speed Options

Unit

t

V

Min

500

ns

VIDR

ID

RESET# Setup Time for Temporary Sector

Unprotect

t

4

µs

RSP

Note: Not 100% tested.

12 V

RESET#

0 or 5 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 19. Temporary Sector Unprotect Timing Diagram

38

Am29F160D

AC CHARACTERISTICS

V

ID

IH

V

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Protect/Unprotect

Verify

40h

Data

60h

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 20. Sector Protect/Unprotect Timing Diagram

Am29F160D

39

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

Std.

Description

75

90

0

120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

120

AVAV

AVEL

ELAX

DVEH

EHDX

WC

t

ns

AS

AH

DS

DH

t

45

30

45

0

50

ns

t

ns

t

Data Hold Time

ns

t

Output Enable Setup Time

0

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHEL

WLEL

GHEL

t

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

WS

t

EHWH

WH

t

CE# Pulse Width

CE# Pulse Width High

35

45

20

7

50

ELEH

EHEL

CP

t

CPH

Byte

Programming Operation

(Note 2)

t

µs

WHWH1

Word

12

1

t

Sector Erase Operation (Note 2)

sec

WHWH2

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

40

Am29F160D

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

= Array Data.

OUT

2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

Figure 21. Alternate CE# Controlled Write Operation Timings

Am29F160D

41

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 3)

Unit

s

Comments

Sector Erase Time

1.0

25

7

8

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time (Note 2)

Byte Programming Time

Word Programming Time

s

300

360

45

µs

s

11

15

12

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

Chip Programming Time

(Note 2)

35

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 5.0 V V , 1,000,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 4.5 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 9

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V on all pins except I/O pins

(including A9, OE#, and RESET#)

SS

–1.0 V

12.5 V

Input voltage with respect to V on all I/O pins

–1.0 V

V

+ 1.0 V

CC

SS

V

Current

–100 mA

+100 mA

CC

Includes all pins except V . Test conditions: V = 5.0 V, one pin at a time.

CC

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

Typ

6

Max

7.5

12

Unit

pF

C

V

= 0

IN

C

Output Capacitance

Control Pin Capacitance

V

= 0

8.5

7.5

pF

OUT

C

V

= 0

IN

9

pF

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

42

Am29F160D

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package

Dwg rev AA; 10/99

Am29F160D

43

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse Thin Small Outline Package

Dwg rev AA; 10/99

44

Am29F160D

REVISION SUMMARY

DC Characteristics

Revision A (January 1999)

TTL/NMOS Compatible table: Changed the maximum

current specification for I_CC2to 50 mA.

Initial release.

Revision B (June 14, 1999)

Revision B+4 (September 10, 1999)

Global

Device Bus Operations

Expanded data sheet into document with full specifica-

tions.

Write Protect (WP#): Clarified explanatory text.

Command Definitions

Deleted the 55 ns speed options.

Autoselect Command Sequence: Added text and table

explaining effect of WP# input on autoselect code

output for 16 Kbyte boot sector.

Distinctive Characteristics

In the Ultra Low Power Consumption bullets, changed

the typical current to match the DC specifications

(CMOS Compatible) table.

Revision C (November 16, 1999)

AC Characteristics—Figure 14. Program

Operations Timing and Figure 15. Chip/Sector

Erase Operations

Revision B+1 (July 7, 1999)

Connection Diagrams

Corrected the signals on pins 39 and 40 of the reverse

TSOP package.

Deleted t_GHWLand changed OE# waveform to start at

high.

Physical Dimensions

Revision B+2 (July 14, 1999)

Replaced figures with more detailed illustrations.

Global

Changed the V_CCoperating range of the 70 ns speed

option to 5.0 V ± 5%. Deleted all references to uniform

sector.

Revision D (December 4, 2000)

Removed Advance Information status from document.

Ordering Information

Command Definitions table

Deleted optional processing.

In Note 7, added a reference to CFI query mode.

Table 9, Command Definitions

Revision B+3 (July 30, 1999)

In Note 5, changed the lower address bit in don’t care

Global

range to A11.

Changed the part number designator for the 70 ns

speed option to 75 (with V_CCrated at 5.0 V ± 5%).

Table 11, Test Specifications

Changed capacitive loading on 70 ns speed option to

30 pF

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29F160D

45


型号：	AM29F160DB90EC
厂家：	AMD
描述：	16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory 16兆位（2M ×8位/ 1的M× 16位） CMOS 5.0伏只，引导扇区闪存闪存内存集成电路光电二极管
文件：	总46页 (文件大小：867K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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