AM29F040-55PIB [AMD]
4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory; 4兆位（ 524,288 ×8位） CMOS 5.0伏只，扇区擦除闪存
| 型号： | AM29F040-55PIB |
| 厂家： | 
AMD |
| 描述： | 4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| 文件： | 总33页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
Am29F040
4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
■ Compatible with JEDEC-standards
■ Embedded Erase Algorithms
— Automatically preprograms and erases the chip
or any combination of sectors
■ Embedded Program Algorithms
— Pinout and software compatible with single-
power-supply Flash
— Automatically programs and verifies data at
specified address
— Superior inadvertent write protection
■ Package options
■ Data Polling andToggle Bit feature for detection
of program or erase cycle completion
— 32-pin PLCC
■ Erase suspend/resume
— 32-pin TSOP
— Supports reading data from a sector not being
erased
— 32-pin PDIP
■ Minimum 100,000 write/erase cycles guaranteed
■ High performance
■ Low power consumption
— 20 mA typical active read current
— 30 mA typical program/erase current
— 55 ns maximum access time
■ Sector erase architecture
— Uniform sectors of 64 Kbytes each
■ Enhanced power management for standby
mode
— Any combination of sectors can be erased.
Also supports full chip erase.
— <1 µA typical standby current
— Standard access time from standby mode
■ Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations
GENERAL DESCRIPTION
The Am29F040 is a 4 Mbit, 5.0 Volt-only Flash memory
organized as 512 Kbytes of 8 bits each. The Am29F040
is offered in a 32-pin package. This device is designed
to be programmed in-system with the standard system
which controls the erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from 12.0 Volt Flash or EPROM devices.
5.0 V V
supply. A 12.0 V V
is not required for
CC
PP
write or erase operations. The device can also be
reprogrammed in standard EPROM programmers.
The Am29F040 is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Typically, each sector can
be programmed and verified in less than one second.
Erase is accomplished by executing the erase com-
mand sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automati-
cally preprograms the array if it is not already pro-
grammed before executing the erase operation. During
erase, the device automatically times the erase pulse
widths and verifies proper cell margin.
The standard Am29F040 offers access times between
55 ns and 150 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus
contention the device has separate chip enable (CE),
write enable (WE) and output enable (OE) controls.
The Am29F040 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state machine
Publication# 17113 Rev: E Amendment/0
Issue Date: November 1996
Any individual sector is typically erased and verified in
1.0 seconds (if already completely preprogrammed).
Flexible Sector-Erase Architecture
■ Eight 64 Kbyte sectors
This device also features a sector erase architecture.
The sector mode allows for 64K byte blocks of memory
to be erased and reprogrammed without affecting
other blocks. The Am29F040 is erased when shipped
from the factory.
■ Individual-sector, multiple-sector, or bulk-erase
capability
■ Individual or multiple-sector protection is user
definable
7FFFFh
6FFFFh
The device features single 5.0 V power supply opera-
tion for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
5FFFFh
64 Kbytes per Sector
program and erase operations. A low V
detector
CC
automatically inhibits write operations on the loss of
power.The end of program or erase is detected by Data
Polling of DQ7 or by the Toggle Bit feature on DQ6.
Once the end of a program or erase cycle has been
completed, the device internally resets to the read
mode.
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
00000h
17113E-1
AMD’s Flash technology combines years of EPROM
2
and E PROM experience to produce the highest levels
of quality, reliability and cost effectiveness. The
Am29F040 memory electrically erases the entire chip
or all bits within a sector simultaneously via Fowler-
Nordheim tunneling. The bytes are programmed one
byte at a time using the EPROM programming
mechanism of hot electron injection.
2
Am29F040
PRODUCT SELECTOR GUIDE
Family Part No:
Am29F040
Ordering Part No:
V
= 5.0 V ± 5%
= 5.0 V ± 10%
-55
CC
V
-70
70
70
30
-90
90
90
35
-120
120
120
50
-150
150
150
55
CC
Max Access Time (ns)
CE (E) Access (ns)
OE (G) Access (ns)
55
55
25
BLOCK DIAGRAM
DQ0–DQ7
V
V
CC
Input/Output
Buffers
SS
Erase Voltage
Generator
State
Control
WE
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data Latch
STB
CE
OE
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
X-Decoder
Cell Matrix
A0–A18
17113E-2
Am29F040
3
CONNECTION DIAGRAMS
PDIP
PLCC
A18
A16
A15
A12
A7
1
2
3
4
5
6
7
8
9
32
V
CC
31 WE
30 A17
29 A14
28 A13
27 A8
4
3
2
1 32 31 30
A7
A6
5
29
28
27
26
25
24
23
22
21
A14
A13
A8
6
A6
A5
7
A5
26 A9
A4
8
A9
A4
25 A11
24 OE
23 A10
22 CE
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
A3
9
A11
OE
A3
A2
10
11
12
13
A2 10
A1 11
A1
A10
CE
A0
A0 12
DQ0
DQ7
DQ0 13
DQ1 14
DQ2 15
14 15 16 17 18 19 20
V
16
SS
17113E-3
17113E-4
TSOP
A11
A9
A8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
9
10
11
12
13
14
15
16
A6
A5
A4
A1
A2
A3
29F040 Standard Pinout
OE
A10
CE
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
9
10
11
12
13
14
15
16
A1
A2
A3
A6
A5
A4
29F040 Reverse Pinout
Am29F040
17113E-5
4
PIN CONFIGURATION
A0–A18 = Address Inputs
DQ0–DQ7 = Data Input/Output
LOGIC SYMBOL
19
CE
OE
WE
= Chip Enable
= Output Enable
= Write Enable
= Device Ground
8
A0–A18
DQ0–DQ7
CE (E)
OE (G)
V
V
SS
CC
= Device Power Supply
(5.0 V ±10% or ±5%)
WE (W)
17113E-6
Am29F040
5
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges.The order number (Valid Combination) is formed
by a combination of:
AM29F040
-55
E
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide
and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F040
4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM29F040-55
JC, JI, JE, EC, EI, EE, FC, FI, FE
AM29F040-70
AM29F040-90
AM29F040-120
PC, PCB, PI, PIB, PE, PEB,
JC, JCB, JI, JIB, JE, JEB,
EC, ECB, EI, EIB, EE, EEB,
FC, FCB, FI, FIB, P11
AM29F040-150
FE, FEB
6
Am29F040
Table 1. Am29F040 User Bus Operations
Operation
Autoselect Manufacturer Code (Note 1)
Autoselect Device Code (Note 1)
Read (Note 4)
CE
L
OE
L
WE
H
A0
L
A1
L
A6
L
A9
I/O
Code
V
ID
L
L
H
H
L
L
V
Code
ID
L
L
H
A0
X
A1
X
A6
X
A9
X
RD
Standby
H
L
X
H
H
L
X
HIGH Z
HIGH Z
PD (Note 2)
Code
Output Disable
H
X
X
X
X
Write
L
L
A0
L
A1
H
A6
L
A9
Verify Sector Protect (Note 3)
Autoselect Device Unprotect Code
L
H
V
ID
L
L
H
H
H
L
V
Code
ID
Legend:
L = Logic 0, H = Logic 1, X = Don’t Care. See DC Characteristics for voltage levels.
Notes:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Tables 2 and 4.
2. Refer to Table 3 for valid PD (Program Data) during a write operation.
3. Refer to the section on Sector Protection.
4. WE can be V if OE is V , OE at V initiates the write operations.
IL
IL
IH
Read Mode
Output Disable
The Am29F040 has two control functions which must
be satisfied in order to obtain data at the outputs. CE is
the power control and should be used for device selec-
tion. OE is the output control and should be used to
gate data to the output pins if a device is selected.
With the OE input at a logic high level (V ), output from
the device is disabled.This will cause the output pins to
be in a high impedance state.
IH
Autoselect
The autoselect mode allows the reading out of a binary
code from the device and will identify its manufacturer
and type.This mode is intended for use by programming
equipment for the purpose of automatically matching the
device to be programmed with its corresponding pro-
gramming algorithm. This mode is functional over the
entire temperature range of the device.
Address access time (t
stable addresses to valid output data. The chip enable
) is equal to the delay from
ACC
access time (t ) is the delay from stable addresses and
CE
stable CE to valid data at the output pins.The output en-
able access time is the delay from the falling edge of OE
to valid data at the output pins (assuming the addresses
have been stable for at least t
–t time).
ACC OE
To activate this mode, the programming equipment
Standby Mode
must force V (11.5 V to 12.5 V) on address pin A9.
ID
The Am29F040 has two standby modes, a CMOS
Two identifier bytes may then be sequenced from the
standby mode (CE input held at V ± 0.5 V), when the
device outputs by toggling address A0 from V to V .
CC
IL IH
current consumed is less than 5 µA; and a TTL standby
All addresses are don’t cares except A0, A1, and A6.
mode (CE is held at V ) when the current required is
IH
The manufacturer and device codes may also be read
via the command register, for instances when the
Am29F040 is erased or programmed in a system with-
out access to high voltage on the A9 pin.The command
sequence is illustrated in Table 4 (refer to Autoselect
Command section).
reduced to approximately 1 mA. In the standby mode
the outputs are in a high impedance state, independent
of the OE input.
If the device is deselected during erasure or program-
ming, the device will draw active current until the
operation is completed.
Byte 0 (A0 = V ) represents the manufacturer’s code
IL
(AMD = 01H) and byte 1 (A0 = V ) the device identifier
IH
code (Am29F040 = A4H). All identifiers for manufac-
turer and device exhibit odd parity with the MSB (DQ7)
defined as the parity bit. See Table 2.
Am29F040
7
Table 2. Am29F040 Autoselect Codes
Code
Type
A18 A17 A16
A6
A1
A0 (HEX) DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacturer
ID
X
X
X
X
X
X
V
V
V
01H
A4H
01H*
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
IL
IL
IL
IL
IH
IL
Am29F040
Device ID
V
V
V
IH
Sector
Protection
Sector Addresses
V
V
V
IL
IL
*Outputs 01H at protected sector addresses
Table 3. Sector Addresses
Sector Protection
The Am29F040 features hardware sector protection.
This feature will disable both program and erase
operations in any number of sectors (0 through 8). The
sector protect feature is enabled using programming
equipment at the user’s site.The device is shipped with
all sectors unprotected. Alternatively, AMD may pro-
gram and protect sectors in the factory prior to shipping
the device (AMD’s ExpressFlash™ Service).
A18
0
A17
0
A16
0
Address Range
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
0
1
0
1
0
0
1
1
1
0
0
It is also possible to determine if a sector is protected
in the system by writing an Autoselect command.
Performing a read operation at the address location
XX02H, where the higher order addresses (A16,
A17, and A18) are used to select the desired sector.
The device produces a logical “1” at DQ0 for a pro-
tected sector and a logical “0” for an unprotected
sector. See Table 2 for Autoselect codes.
1
0
1
1
1
0
1
1
1
Write
Device erasure and programming are accomplished
via the command register. The contents of the register
serve as inputs to the internal state machine.The state
machine outputs dictate the function of the device.
Sector Unprotect
The Am29F040 also features a sector unprotect mode
so that a protected sector may be unprotected to
incorporate any changes in the code. The sector unpro-
tect is enabled using programming equipment at the
user’s site.
The command register itself does not occupy any
addressable memory location. The register is a latch
used to store the commands, along with the address
and data information needed to execute the command.
The command register is written by bringing WE to V ,
IL
Command Definitions
while CE is at V and OE is at V . Addresses are
IL
IH
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device to
read mode.Table 4 defines the valid register command
sequences. Note that the Erase Suspend (B0) and
Erase Resume (30) commands are valid only while the
Sector Erase operation is in progress. Either of the two
reset commands will reset the device (when applicable).
latched on the falling edge of WE or CE, whichever
happens later; while data is latched on the rising edge
of WE or CE, whichever happens first. Standard
microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing parameters.
8
Am29F040
Table 4. Am29F040 Command Definitions
Fourth Bus
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Command
Sequence
Read/Reset
Addr
Data Addr Data Addr Data Addr
Data
Addr Data Addr Data
Read/Reset
Read/Reset
1
4
XXXXH F0H
5555H AAH 2AAAH 55H 5555H F0H
RA
00H
01H
PA
RD
01H
A4H
PD
Autoselect
4
5555H AAH 2AAAH 55H 5555H 90H
5555H AAH 2AAAH 55H 5555H A0H
Byte Program
Chip Erase
4
6
6
5555H AAH 2AAAH 55H 5555H 80H 5555H
5555H AAH 2AAAH 55H 5555H 80H 5555H
AAH 2AAAH 55H 5555H 10H
AAH 2AAAH 55H SA 30H
Sector Erase
Sector Erase Suspend
Sector Erase Resume
Erase can be suspended during sector erase with Addr (don’t care), Data (B0H)
Erase can be resumed after suspend with Addr (don’t care), Data (30H)
Notes:
1. Address bits A15, A16, A17, and A18 = X = Don’t Care for all address commands except for Program Address (PA), Sector
Address (SA), Read Address (RA), and autoselect sector protect verify.
2. Bus operations are defined in Table 1.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WEpulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16 will uniquely select any sector (see Table 3).
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
5. Read from non-erasing sectors is allowed in the Erase Suspend mode.
The device contains a command autoselect operation
Read/Reset Command
to supplement traditional PROM programming method-
The read or reset operation is initiated by writing the
ology. The operation is initiated by writing the auto-
read/reset command sequence into the command reg-
select command sequence into the command register.
ister. Microprocessor read cycles retrieve array data
Following the command write, a read cycle from ad-
from the memory. The device remains enabled for
dress XX00H retrieves the manufacture code of 01H. A
reads until the command register contents are altered.
read cycle from address XX01H returns the device
The device will automatically power-up in the read/
reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value en-
sures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific
timing parameters.
code A4H (see Table 2). All manufacturer and device
codes will exhibit odd parity with the MSB (DQ7)
defined as the parity bit.
Scanning the sector addresses (A16, A17, A18) while
(A6, A1, A0) = (0, 1, 0) will produce a logical “1” at
device output DQ0 for a protected sector.
To terminate the operation, it is necessary to write the
read/reset command sequence into the register.
Autoselect Command
Byte Programming
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access the signature codes by
raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired
system design practice.
The device is programmed on a byte-by-byte basis.
Programming is a four bus cycle operation. There are
two “unlock” write cycles. These are followed by the
program setup command and data write cycles. Ad-
dresses are latched on the falling edge of CE or WE,
whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The
Am29F040
9
rising edge of CE or WE (whichever happens first)
begins programming. Upon executing the Embedded
Program Algorithm command sequence the system is
not required to provide further controls or timings. The
device will automatically provide adequate internally
generated program pulses and verify the programmed
cell margin.
Sector Erase
Sector erase is a six bus cycle operation.There are two
“unlock” write cycles. These are followed by writing the
“setup” command. Two more “unlock” write cycles are
then followed by the sector erase command.The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(data) is latched on the rising edge of WE. A time-out
of 80 µs from the rising edge of the last sector erase
command will initiate the sector erase command(s).
The automatic programming operation is completed
when the data on DQ7 is equivalent to data written to
this bit (see Write Operation Status section) at which
time the device returns to the read mode and ad-
dresses are no longer latched. Therefore, the device
requires that a valid address to the device be supplied
by the system at this particular instance of time. Hence,
Data Polling must be performed at the memory location
which is being programmed.
Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be
concurrently erased. The time between writes must be
less than 80 µs, otherwise that command will not be ac-
cepted. It is recommended that processor interrupts be
disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector
Erase command is written. A time-out of 80 µs from the
rising edge of the last WE will initiate the execution of
the Sector Erase command(s). If another falling edge of
the WE occurs within the 80 µs time-out window the
timer is reset. (Monitor DQ3 to determine if the sector
erase window is still open, see section DQ3, Sector
Erase Timer.) Any command other than Sector Erase
or Erase Suspend during this period resets the device
to read mode, ignoring the previous command string. In
that case, restart the erase on those sectors and allow
them to complete. (Refer to the Write Operation Status
section for Sector Erase Timer operation.) Loading the
sector erase buffer may be done in any sequence and
with any number of sectors (1 to 8).
Any commands written to the chip during this period
will be ignored.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success, according
to the data polling algorithm, but a read from reset/read
mode will show that the data is still “0”. Only erase
operations can convert “0”s to “1”s.
Figure 1 illustrates the Embedded Programming Algorithm
using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“setup” command. Two more “unlock” write cycles are
then followed by the chip erase command.
Sector erase does not require the user to program the
device prior to erase. The device automatically
programs all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not
affected. The system is not required to provide any
controls or timings during these operations.
Chip erase does not require the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device auto-
matically will program and verify the entire memory for
an all zero data pattern prior to electrical erase. The
chip erase is performed sequentially one sector at a
time.The system is not required to provide any controls
or timings during these operations.
The automatic sector erase begins after the 80 µs time
out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the
data on DQ7 is “1" (see Write Operation Status section)
at which time the device returns to read mode. During
the execution of the Sector Erase command, only the
Erase Suspend and Erase Resume commands are
allowed. All other commands will be ignored. Data poll-
ing must be performed at an address within any of the
sectors being erased.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and termi-
nates when the data on DQ7 is “1” (see Write Operation
Status section) at which time the device returns to read
the mode.
Figure 2 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Figure 2 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
10
Am29F040
When the Erase Suspend command is written during
the Sector Erase operation, the device will take a max-
imum of 15 µs to suspend the erase operation. When
the device has entered the erase-suspended mode,
DQ7 bit will be at logic “1”, and DQ6 will stop toggling.
The user must use the address of the erasing sector for
reading DQ6 and DQ7 to determine if the erase opera-
tion has been suspended. Further writes of the Erase
Suspend command are ignored.
Erase Suspend
The Erase Suspend command allows the user to inter-
rupt a Sector Erase operation and then perform data
reads from a sector not being erased.This command is
applicable ONLY during the Sector Erase operation
which includes the time-out period for sector erase.The
Erase Suspend command will be ignored if written dur-
ing the Chip Erase operation or Embedded Program Al-
gorithm. Writing the Erase Suspend command during
the Sector Erase time-out results in immediate termina-
tion of the time-out period and suspension of the erase
operation.
When the erase operation has been suspended, the
device defaults to the erase-suspend-read mode.
Reading data in this mode is the same as reading from
the standard read mode except that the data must be
read from sectors that have not been erase-suspended.
Any other command written during the Erase Sus-
pend mode will be ignored except the Erase Resume
command. Writing the Erase Resume command
resumes the erase operation. The addresses are
“don’t-cares” when writing the Erase Suspend or
Erase Resume command.
To resume the operation of Sector Erase, the Resume
command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. An-
other Erase Suspend command can be written after the
chip has resumed erasing.
Write Operation Status
Table 5. Write Operation Status
Status
DQ7
DQ7
0
DQ6
Toggle
DQ5
DQ3
Byte Programming in Embedded Algorithm
Embedded Erase Algorithm
0
0
0
0
1
1
Toggle
In Progress
Erase
Erase Suspended Sector
1
No Toggle
Suspended
Mode
Non-Erase Suspended Sector
Data
Data
Data
Data
Byte-Programming in Embedded Algorithm
Embedded Erase Algorithm
DQ7
0
Toggle
Toggle
1
1
0
1
Exceeded
Time Limits
Polling must be performed at sector address within any
of the sectors being erased and not a protected sector.
Otherwise, the status may not be valid. Once the Em-
bedded Algorithm operation is close to being com-
pleted, the Am29F040 data pins (DQ7) may change
asynchronously while the output enable (OE) is as-
serted low. This means that the device is driving status
information on DQ7 at one instant of time and then that
byte’s valid data at the next instant of time. Depending
on when the system samples the DQ7 output, it may
read the status or valid data. Even if the device has
completed the Embedded Algorithm operation and
DQ7 has a valid data, the data outputs on DQ0–DQ6
may be still invalid. The valid data on DQ0–DQ7 will be
read on the successive read attempts.
DQ7
Data Polling
The Am29F040 device features Data Polling as a
method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the
Embedded Program Algorithm an attempt to read the
device produces the compliment of the data last written
to DQ7. Upon completion of the Embedded Program
Algorithm, reading the device produces the true data
last written to DQ7. During the Embedded Erase Algo-
rithm, reading the device produces a “0” at the DQ7
output. Upon completion of the Embedded Erase Algo-
rithm, reading the device produces a “1” at the DQ7
output. The flowchart for Data Polling (DQ7) is shown
in Figure 3.
The Data Polling feature is active during the Embedded
Programming Algorithm, Embedded Erase Algorithm,
Erase Suspend, or sector erase time-out (see Table 5).
For chip erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse se-
quence. For sector erase, the Data Polling is valid after
the last rising edge of the sector erase WE pulse. Data
Am29F040
11
See Figure 12 for the Data Polling timing specifications
and diagrams.
If this failure condition occurs during the chip erase op-
eration, it specifies that the entire chip is bad or combi-
nation of sectors are bad.
DQ6
If this failure condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector may not be
reused, (other sectors are still functional and can be
reused).
Toggle Bit
The Am29F040 also features the “Toggle Bit” as a
method to indicate to the host system that the Embed-
ded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm
cycle, successive attempts to read (OE toggling) data
from the device will result in DQ6 toggling between
one and zero. Once the Embedded Program or Erase
Algorithm cycle is completed, DQ6 will stop toggling
and valid data will be read on the next successive
attempts. During programming, the Toggle Bit is valid
after the rising edge of the fourth WE pulse in the four
write pulse sequence. For chip erase, the Toggle Bit
is valid after the rising edge of the sixth WE pulse in
the six write pulse sequence. For Sector erase, the
Toggle Bit is valid after the last rising edge of the
sector erase WE pulse.The Toggle Bit is active during
the sector time out.
The DQ5 failure condition may also appear if a user
tries to program a “1” to a location previously pro-
grammed to “0”. In this case the device locks out and
never completes the Embedded Algorithm operation.
Hence, the system never reads a valid data on DQ7 bit
and DQ6 never stops toggling. Once the device has ex-
ceeded timing limits, the DQ5 bit will indicate a “1”.
Please note that this is not a device failure condition
since the device was incorrectly used.
DQ3
Sector Erase Timer
After the completion of the initial sector erase com-
mand sequence the sector erase time-out will begin.
DQ3 will remain low until the time-out is complete. Data
Polling and Toggle Bit are valid after the initial sector
erase command sequence.
In programming, if the sector being written to is pro-
tected, the toggle bit will toggle for about 2 µs and then
stop toggling without the data having changed. In
erase, the device will erase all the selected sectors ex-
cept for the ones that are protected. If all selected sec-
tors are protected, the chip will toggle the toggle bit for
about 100 µs and then drop back into read mode, hav-
ing changed none of the data.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, DQ3 may be
used to determine if the sector erase timer window is
still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If DQ3 is low (“0”), the device will accept ad-
ditional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 is high on
the second status check, the command may not have
been accepted.
Either CE or OE toggling will cause the DQ6 to toggle.
See Figure 13 for the Toggle Bit timing specifications
and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count).
Under these conditions DQ5 will produce a “1”. This is
a failure condition which indicates that the program or
erase cycle was not successfully completed. Data Poll-
ing is the only operating function of the device under
this condition. The CE circuit will partially power down
the device under these conditions (to approximately
2 mA). The OE and WE pins will control the output
disable functions as described in Table 1.
Refer to Table 5, Write Operation Status.
Data Protection
The Am29F040 is designed to offer protection
against accidental erasure or programming caused
by spurious system level signals that may exist dur-
ing power transitions. During power up the device
automatically resets the internal state machine in the
Read mode. Also, with its control register architec-
ture, alteration of the memory contents only occurs
after successful completion of specific multi-bus
cycle command sequences.
If this failure condition occurs during sector erase oper-
ation, it specifies that a particular sector is bad and it
may not be reused, however, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other sec-
tors.Write the Reset command sequence to the device,
and then execute program or erase command se-
quence. This allows the system to continue to use the
other active sectors in the device.
The device also incorporates several features to
prevent inadvertent write cycles resulting from V
CC
power-up and power-down transitions or system noise.
12
Am29F040
Low V Write Inhibit
Logical Inhibit
CC
To avoid initiation of a write cycle during V power-up
Writing is inhibited by holding any one of OE = V ,
IL
CC
and power-down, the Am29F040 locks out write cycles
CE = V or WE = V . To initiate a write cycle CE and
IH IH
for V
< V
(see DC Characteristics section for
WE must be a logical zero while OE is a logical one.
CC
LKO
voltages). When V < V
disabled, all internal program/erase circuits are
disabled, and the device resets to the read mode. The
, the command register is
CC
LKO
Power-Up Write Inhibit
Power-up of the device with WE = CE = V and
IL
Am29F040 ignores all writes until V > V
.The user
OE = V will not accept commands on the rising edge
CC
LKO
IH
must ensure that the control pins are in the correct logic
state when V > V to prevent unintentional writes.
of WE. The internal state machine is automatically
reset to the read mode on power-up.
CC
LKO
Write Pulse “Glitch” Protection
Sector Protect
Noise pulses of less than 5 ns (typical) on OE, CE or
WE will not initiate a write cycle.
Sectors of the Am29F040 may be hardware protected
using programming equipment at the users factory.The
protection circuitry will disable both program and erase
functions for the protected sector(s). Requests to pro-
gram or erase a protected sector will be ignored by the
device.
Am29F040
13
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence
(see below)
Data Poll Device
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
17113E-7
Figure 1. Embedded Programming Algorithm
14
Am29F040
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence
(see below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Individual Sector/Multiple Sector
Chip Erase Command Sequence
Erase Command Sequence
(Address/Command):
(Address/Command):
5555H/AAH
2AAAH/55H
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional
Sector Address/30H
17113E-8
Figure 2. Embedded Erase Algorithm
Am29F040
15
Start
VA =Byte address for programming
=Any of the sector addresses within the
sector being erased during sector erase
operation
Read Byte
(DQ0–DQ7)
Addr = VA
=XXXXH during chip erase
Yes
DQ7 = Data
?
No
No
DQ5 = 1
?
Yes
Read Byte
(DQ0–DQ7)
Addr = VA
Yes
DQ7 = Data
?
Pass
No
Fail
17113E-9
Note:
DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 3. Data Polling Algorithm
16
Am29F040
Start
VA =Byte address for programming
=Any of the sector addresses within the
sector being erased during sector erase
operation
Read Byte
(DQ0–DQ7)
Addr = VA
=XXXXH during chip erase
No
DQ6 = Data
?
Yes
No
DQ5 = 1
?
Yes
Read Byte
(DQ0–DQ7)
Addr = VA
No
DQ6 = Data
?
Pass
Yes
Fail
17113E-10
Note:
DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.
Figure 5. Toggle Bit Algorithm
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
17113E-11
Figure 6. Maximum Negative Overshoot Waveform
20 ns
V
+ 2.0 V
CC
V
+ 0.5 V
2.0 V
CC
17113E-12
20 ns
20 ns
Figure 7. Maximum Positive Overshoot Waveform
Am29F040
17
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
Ceramic Packages . . . . . . . . . . . . . . –65°C to +150°C
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature (T ). . . . . . . . . . . .0°C to +70°C
A
Industrial (I) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (T ). . . . . . . . . .–40°C to +85°C
A
Extended (E) Devices
Voltage with Respect to Ground
All pins except A9 (Note 1). . . . . . . . . –2.0 V to +7.0 V
Ambient Temperature (T ). . . . . . . . .–55°C to +125°C
A
V
(Note 1). . . . . . . . . . . . . . . . . . . . –2.0 V to +7.0 V
V
V
V
Supply Voltages
CC
CC
CC
CC
A9 (Note 2). . . . . . . . . . . . . . . . . . . . –2.0 V to +13.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
for Am29F040-55. . . . . . . . . . +4.75 V to +5.25 V
for Am29F040
-70, -90, -120, -150 . . . . . . . . . . . . +4.50 V to +5.50 V
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
Operating ranges define those limits between which the
functionality of the device is guaranteed.
voltage transitions, inputs may undershoot V to –2.0 V
SS
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is V
+ 0.5 V. During voltage transitions,
CC
input and I/O pins may overshoot to V
periods up to 20ns.
+ 2.0 V for
CC
2. Minimum DC input voltage on A9 pin is –0.5 V. During
voltage transitions, A9 may undershoot V to –2.0 V for
SS
periods of up to 20 ns. Maximum DC input voltage on A9
is +12.5 V which may overshoot to 14.0 V for periods up
to 20 ns.
3. No more than one output shorted to ground at a time.
Duration of the short circuit should not be greater than
one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is
a stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
18
Am29F040
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
= V to V , V = V Max
Min
Max
±1.0
50
Unit
µA
I
Input Load Current
V
IN
LI
SS
CC CC
CC
I
A9 Input Load Current
Output Leakage Current
V
= V Max, A9 = 12.5 V
µA
LIT
CC
CC
I
V
= V to V , V = V Max
±1.0
30
µA
LO
OUT
SS
CC CC
CC
I
I
I
V
V
Active Read Current (Note 1)
Active Program/Erase Current
CE = V OE = V
mA
CC1
CC
IL,
IH
CC
CE = V OE = V
40
mA
CC2
CC3
IL,
IH
(Notes 2, 3)
V
Standby Current
V
= V Max, CE = V
IH
1.0
0.8
mA
V
CC
CC
CC
V
Input Low Level
–0.5
2.0
IL
IH
ID
V
V
Input High Level
V
+ 0.5
V
CC
Voltage for Autoselect and Sector Protect
Output Low Voltage
V
= 5.25 V
10.5
12.5
0.45
V
CC
V
I
= 12 mA, V = V Min
V
OL
OL
CC
CC
V
Output High Level
I
= –2.5 mA, V = V Min
2.4
3.2
V
OH
OH
CC
CC
V
Low V Lock-Out Voltage
4.2
V
LKO
CC
Notes:
1. The I current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
CC
The frequency component typically is less than 2 mA/MHz, with OEat V .
IH
2. I active while Embedded Algorithm (program or erase) is in progress.
CC
3. Not 100% tested.
Am29F040
19
DC CHARACTERISTICS (continued)
CMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current
Test Description
= V to V , V = V Max
Min
Typ
Max
±1.0
50
Unit
µA
I
V
IN
LI
SS
CC CC
CC
I
A9 Input Load Current
Output Leakage Current
V
= V Max, A9 = 12.5 V
µA
LIT
CC
CC
I
V
= V to V , V = V Max
±1.0
µA
LO
OUT
SS
CC CC
CC
V
Active Read Current
CC
I
CE = V OE = V
IH
20
30
40
mA
mA
CC1
IL,
(Note 1)
V
Active Program/Erase
CC
I
I
CE
OE
= VIH
30
1
CC2
= VIL,
Current (Notes 2, 3)
V
Standby Current (Note 4)
V
= V Max, CE = V ± 0.5 V
5
µA
V
CC3
CC
CC
CC
CC
V
Input Low Level
Input High Level
–0.5
0.8
IL
V
0.7 x V
V + 0.3
CC
V
IH
CC
Voltage for Autoselect and
Sector Protect
V
V
= 5.25 V
10.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
Output High Voltage
I
= 12.0 mA, V = V Min
V
V
V
V
OL
OL
CC
CC
V
I
= –2.5 mA, V = V Min
0.85V
CC
OH1
OH
CC
CC
V
I
= –100 µA, V = V Min
V
–0.4
OH2
OH
CC
CC
CC
V
Low V Lock-out Voltage
3.2
4.2
LKO
CC
Notes:
1. The I current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
CC
The frequency component typically is less than 2 mA/MHz, with OEat V .
IH
2. I active while Embedded Algorithm (program or erase) is in progress.
CC
3. Not 100% tested.
4. I
= 20 µA max at extended temperatures (> +85°C).
CC3
20
Am29F040
AC CHARACTERISTICS
Read Only Operations Characteristics
Parameter Symbols
Speed Options (Note 1)
JEDEC Standard
Description
Test Setup
Min
-55
-70
-90
-120
-150
Unit
t
t
Read Cycle Time (Note 3)
55
70
90
120
150
ns
AVAV
RC
CE = V
OE = V
IL
t
t
Address to Output Delay
Max
55
70
90
120
150
ns
AVQV
ACC
IL
t
t
Chip Enable to Output Delay
Output Enable to Output Delay
OE = V
Max
Max
55
30
70
30
90
35
120
50
150
55
ns
ns
ELQV
CE
IL
t
t
t
GLQV
OE
Chip Enable to Output High Z
(Notes 2, 3)
t
Max
18
18
20
20
20
20
30
30
35
35
ns
ns
EHQZ
DF
DF
Output Enable to Output
High Z (Notes 2, 3)
t
t
GHQZ
Output Hold Time from
Addresses, CE or OE,
Whichever Occurs First
t
t
Min
0
0
0
0
0
ns
AXQX
OH
Notes:
1. Test Conditions (for -55): Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level, input and output: 1.5 V and 1.5 V
(for all others):
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 20 ns
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level, input and output: 0.8 V and 2.0 V
2. Output driver disable time.
3. Not 100% tested.
5.0 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
C
6.2 kΩ
L
Diodes = IN3064
or Equivalent
17113E-13
Notes:
For –55: C = 30 pF including jig capacitance
L
For all others: C = 100 pF including jig capacitance
L
Figure 8. Test Conditions
Am29F040
21
AC CHARACTERISTICS
Write/Erase/Program Operations
Parameter Symbols
Speed Options
JEDEC
Standard
Description
Write Cycle Time (Note 2)
Address Setup Time
Address Hold Time
-55
55
0
-70
-90
90
0
-120
-150
150
0
Unit
ns
t
t
Min
Min
Min
Min
Min
Min
Min
70
0
120
0
AVAV
WC
t
t
ns
AVWL
WLAX
DVWH
WHDX
AS
AH
DS
DH
t
t
40
25
0
45
30
0
45
45
0
50
50
0
50
50
0
ns
t
t
Data Setup Time
ns
t
t
Data Hold Time
ns
t
Output Enable Setup Time
0
0
0
0
0
ns
OES
Output Read (Note 2)
Enable
0
0
0
0
0
ns
t
OEH
Toggle and Data Polling
(Note 2)
Hold
Time
Min
10
10
10
10
10
ns
t
t
Read Recover Time Before Write
CE Setup Time
Min
Min
Min
Min
Min
Typ
Typ
Max
Typ
Max
Min
0
0
0
0
0
0
0
0
0
0
ns
ns
GHWL
GHWL
t
t
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
t
CE Hold Time
0
0
0
0
0
ns
t
t
Write Pulse Width
30
20
7
35
20
7
45
20
7
50
20
7
50
20
7
ns
t
t
Write Pulse Width High
Byte Programming Operation
ns
WPH
t
t
t
t
µs
WHWH1
WHWH1
1
1
1
1
1
sec
sec
sec
sec
µs
Sector Erase Operation (Note 1)
Chip Erase Operation (Note 1)
WHWH2
WHWH2
8
8
8
8
8
8
8
8
8
8
t
t
WHWH3
WHWH3
64
50
64
50
64
50
64
50
64
50
t
V
Setup Time (Note 2)
VCS
CC
Notes:
1. This does not include the preprogramming time.
2. Not 100% tested.
22
Am29F040
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING WAVEFORMS
t
RC
Addresses
Addresses Stable
t
ACC
CE
OE
(t
)
DF
t
OE
WE
(t
)
CE
(t
)
OH
High Z
High Z
Output Valid
Outputs
17113E-14
Figure 9. AC Waveforms for Read Operations
Am29F040
23
SWITCHING WAVEFORMS
Data Polling
PA
PA
5555H
t
Addresses
CE
t
t
RC
AH
WC
t
AS
t
GHWL
OE
t
t
WHWH1
WP
WE
t
WPH
t
CS
t
DF
t
t
DH
OE
D
Data
5.0 V
PD
DQ7
A0H
OUT
t
DS
t
OH
t
CE
17113E-15
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. D is the output of the data written to the device.
OUT
5. Figure indicates last two bus cycles of four bus cycle sequence.
Figure 10. Program Operation Timings
t
AH
Addresses
5555H
2AAAH
5555H
5555H
2AAAH
SA
t
AS
CE
OE
t
GHWL
t
WP
WE
t
WPH
t
CS
t
DH
Data
t
55H
80H
55H
10H/30H
AAH
AAH
DS
V
t
CC
VCS
17113E-16
Note:
SA is the sector address for Sector Erase. Addresses = don’t care for Chip Erase.
Figure 11. AC Waveforms Chip/Sector Erase Operations
24
Am29F040
SWITCHING WAVEFORMS
t
CH
CE
t
DF
t
OE
OE
t
OEH
WE
t
CE
t
OH
*
High Z
DQ7 =
DQ7
DQ7
Valid Data
t
WHWH 1 or 2
DQ0 – DQ6
Valid Data
DQ0 – DQ6 = Invalid
DQ0 – DQ6
17113E-17
*DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 12. AC Waveforms for Data Polling During Embedded Algorithm Operations
CE
t
OEH
WE
t
OES
OE
*
Data
(DQ0–DQ7)
DQ6 =
Stop Toggling
DQ0–DQ7
Valid
DQ6 = Toggle
DQ6 = Toggle
t
t
OE
OH
17113E-18
*DQ6 stops toggling (The device has completed the Embedded operation.)
Figure 13. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
Am29F040
25
AC CHARACTERISTICS
Write/Erase/Program Operations
Alternate CE Controlled Writes
Parameter Symbols
Speed Options
JEDEC
Standard
Description
Write Cycle Time (Note 2)
Address Setup Time
Address Hold Time
-55
55
0
-70
-90
90
0
-120
-150
150
0
Unit
ns
t
t
Min
Min
Min
Min
Min
Min
Min
70
0
120
0
AVAV
AVEL
ELAX
DVEH
EHDX
WC
t
t
ns
AS
AH
DS
DH
t
t
40
25
0
45
30
0
45
45
0
50
50
0
50
50
0
ns
t
t
Data Setup Time
ns
t
t
Data Hold Time
ns
t
Output Enable Setup Time
0
0
0
0
0
ns
OES
Output Read (Note 2)
Enable
0
0
0
0
0
ns
t
OEH
Toggle and Data Polling
(Note 2)
Hold
Time
Min
10
10
10
10
10
ns
t
t
t
Read Recover Time Before Write
WE Setup Time
Min
Min
Min
Min
Min
Typ
Typ
Max
Typ
Max
Min
0
0
0
0
0
0
0
0
0
0
ns
ns
GHEL
GHEL
t
WLEL
WS
t
t
WE Hold Time
0
0
0
0
0
ns
EHWH
WH
t
t
CE Pulse Width
30
20
7
35
20
7
45
20
7
50
20
7
50
20
7
ns
ELEH
CP
t
t
CE Pulse Width High
Byte Programming Operation
ns
EHEL
CPH
t
t
t
t
µs
WHWH1
WHWH1
1
1
1
1
1
sec
sec
sec
sec
µs
Sector Erase Operation (Note 1)
Chip Erase Operation (Note 1)
WHWH2
WHWH2
8
8
8
8
8
8
8
8
8
8
t
t
WHWH3
WHWH3
64
30
64
50
64
50
64
50
64
50
t
V
Setup Time (Note 2)
VCS
CC
Notes:
1. This does not include the preprogramming time.
2. Not 100% tested.
26
Am29F040
SWITCHING WAVEFORMS
Data Polling
PA
PA
5555H
Addresses
WE
t
AH
t
WC
t
AS
t
GHEL
OE
t
t
WHWH1
CP
CE
t
CPH
t
WS
t
DH
D
Data
5.0 V
PD
DQ7
A0H
OUT
t
DS
17113E-19
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. D is the output of the data written to the device.
OUT
5. Figure indicates last two bus cycles of four bus cycle sequence.
Figure 14. Alternate CE Controlled Program Operation Timings
Am29F040
27
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time
Typ
Max
Unit
sec
sec
µs
Comments
1.0 (Note 1)
8 (Note 1)
7 (Note 1)
3.6 (Note 1)
8
Excludes 00H programming prior to erasure
Excludes 00H programming prior to erasure
Excludes system-level overhead (Note 3)
Excludes system-level overhead (Note 3)
Chip Erase Time
64
Byte Programming Time
Chip Programming Time
300 (Note 2)
10.8 (Notes 2, 4)
sec
Notes:
1. 25°C, 5 V V , 100,000 cycles.
CC
2. Under worst case condition of 90°C, 4.5 V V , 100,000 cycles.
CC
3. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each
byte. In the preprogramming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure.
4. The Embedded Algorithms allow for 1.8 ms byte program time. DQ5 = “1" only after a byte takes the theoretical maximum time
to program. A minimal number of bytes may require significantly more programming pulses than the typical byte.The majority
of the bytes will program within one or two pulses (7 to 14µs).This is demonstrated by theTypical and Maximum Programming
Times listed above.
LATCHUP CHARACTERISTICS
Min
Max
V + 1.0 V
CC
Input Voltage with respect to V on all I/O pins
–1.0 V
SS
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 5.0 V, one pin at a time.
CC
CC
LCC PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
= 0
IN
Typ
6
Max
7.5
12
Unit
C
Input Capacitance
V
pF
pF
pF
IN
C
Output Capacitance
V
= 0
8.5
7.5
OUT
OUT
C
Control Pin Capacitance
V
= 0
9
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
TSOP PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
6
Max
7.5
12
Unit
pF
C
Input Capacitance
V
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8.5
7.5
pF
OUT
OUT
C
V
= 0
9
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
28
Am29F040
PLCC PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
4
Max
6
Unit
pF
C
Input Capacitance
V
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8
12
12
pF
OUT
OUT
C
V
= 0
8
pF
IN2
PP
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
PDIP PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
4
Max
6
Unit
pF
C
Input Capacitance
V
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8
12
12
pF
OUT
OUT
C
V
= 0
8
pF
IN2
PP
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
Am29F040
29
PHYSICAL DIMENSIONS
PD 032
32-Pin Plastic DIP (measured in inches)
1.640
1.680
.600
.625
17
16
32
.008
.015
.530
.580
Pin 1 I.D.
.630
.700
.045
.065
0°
10°
.005 MIN
.140
.225
16-038-SB_AG
PD 032
DG75
SEATING PLANE
.090
.110
.015
.060
.014
.022
2-28-95 ae
.120
.160
PL 032
32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.495
.447
.453
.009
.015
.042
.056
.125
.140
.585
.595
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
16-038FPO-5
PL 032
DA79
.026
.032
TOP VIEW
SIDE VIEW
6-28-94 ae
30
Am29F040
PHYSICAL DIMENSIONS (continued)
TS 032
32-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
0.17
0.27
7.90
8.10
0.50 BSC
0.05
0.15
18.30
18.50
19.80
20.20
0.08
16-038-TSOP-2
TS 032
DA95
1.20
MAX
0.20
0.10
0.21
8-14-96 lv
0°
5°
0.50
0.70
Am29F040
31
PHYSICAL DIMENSIONS (continued)
TSR032
32-Pin Reversed Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
0.17
0.27
7.90
8.10
0.50 BSC
0.05
0.15
18.30
18.50
19.80
20.20
16-038-TSOP-2
TSR032
DA95
0.08
1.20
MAX
0.20
0.10
0.21
8-15-96 lv
0°
5°
0.50
0.70
32
Am29F040
Sector Erase
DATA SHEET REVISION SUMMARY FOR
AM29F040
Changed time-out to 80 µs. Deleted note. In second
paragraph, deleted third sentence from end. In fourth
paragraph, changed third sentence from end.
Distinctive Characteristics
Changed low power consumption specifications to typ-
ical values.
User Note for Chip Erase and Sector Erase
Commands
Added “enhanced power management” bullet.
Deleted section.
General Description
Erase Suspend
Fifth paragraph, changed sector erase time to 1.0 sec.
Deleted last sentence of fourth paragraph. Deleted fifth
paragraph.
Product Selector Guide
Removed the -75 (70 ns, ±5%) speed option.
Table 5—Write Operation Status
Ordering Information
Added overbars to DQ7.
Added -55 speed option to the example part number.
Removed the -75 speed option from the valid combina-
tions. Added industrial and extended temperature
ranges to -55 valid combinations. Added extended tem-
perature to -70 valid combinations.
DQ7—Data Polling
Fourth paragraph, added “Erase Suspend.”
DQ5—Exceeded Timing Limits
Clarified first sentence in fifth paragraph.
Table 1—User Bus Operations
Absolute Maximum Ratings
Changed I/O write entry to “PD” and I/O read entry to
“RD”; now matches Table 4. Corrected reference to ta-
bles in Note 2.
Corrected V in second sentence to V.
SS
Operating Ranges—V Supply Voltages
CC
Added -55 and -70 speed options. Deleted -75 speed
option.
Standby Mode
Changed maximum CMOS standby mode current to
5 µA.
DC Characteristics
TTL/NMOS Compatible: Changed I
specifications.
, I
, and V
Autoselect
CC1 CC2
ID
ID
Deleted fourth paragraph.
CMOS Compatible: Changed I
, I
, I
and V
CC1 CC2 CC3
Table 2—Autoselect Codes
specifications, added typical values. Added Note 4.
Changed table title.
AC Characteristics
Table 3—Sector Addresses
Read Only Operations Characteristics: Removed -75
speed option. Changed t in -55 column to 30 ns.
Changed table title.
GLQV
Combined Notes 1 and 2.
Sector Protection
Figure 7—Test Conditions
Reworded second paragraph, second sentence.
Changed first C in note to -55.
L
Sector Unprotection
AC Characteristics
Deleted after second sentence.
Write/Erase/Program Operations (also same table for
Alternate CE Controlled Writes): Removed -75 speed
Table 4—Command Definitions
Added “X” to first cycle of first Read/Reset command.
Changed fourth cycle in Byte Program row from “data”
to “PD”. Deleted Note 1. Rewrote Notes 2 and 6.
option. Changed specifications on t
, t
,
WHWH1 WHWH2
and t
.
WHWH3
Erase and Programming Performance
Changed maximum specifications. Clarified note 5. De-
leted Note 2.
Trademarks
Copyright © 1996 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29F040
33
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明