AM29F004B-T-70JF [AMD]
4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory; 4兆位（ 512K的×8位） CMOS 5.0伏只引导扇区闪存
| 型号： | AM29F004B-T-70JF |
| 厂家： | 
AMD |
| 描述： | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| 文件： | 总37页 (文件大小：1050K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am29F004B
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number Am29F004B Revision E Amendment 2 Issue Date July 29, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29F004B
4 Megabit (512 K x 8-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
5.0 Volt single power supply operation
Top or bottom boot block configurations available
— Minimizes system-level power requirements
Minimum 1,000,000 write cycle guarantee per
sector
High performance
Package option
— Access times as fast as 70 ns
— 32-pin PLCC
Manufactured on 0.32 µm process technology
Compatible with JEDEC standards
Ultra low power consumption (typical values at
— Pinout and software compatible with single-
power supply Flash
5 MHz)
— 20 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby mode current
— Superior inadvertent write protection
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
— Supports full chip erase
— Sector Protection features:
Erase Suspend/Erase Resume
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
Sectors can be locked in-system or via
programming equipment
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
20-year data retention at 125°C
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice. 8/5/05This document contains information on a product under development at Advanced
Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or
Publication# 22286 Rev: E Amendment/2
Issue Date: July 29, 2005
A D V A N C E I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29F004B is a 4 Mbit, 5.0 volt-only Flash memory
device organized as 524,288 bytes. The data appears on
DQ0–DQ7. The device is offered in a 32-pin PLCC package.
This device is designed to be programmed in-system with the
is not already programmed) before executing the erase opera-
tion. During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase
operation is complete by reading the DQ7 (Data# Polling), or
DQ6 (toggle) status bits. After a program or erase cycle is
completed, the device is ready to read array data or accept
another command.
standard system 5.0 volt V
supply. A 12.0 volt V is not
CC
PP
required for program or erase operations. The device can also
be programmed in standard EPROM programmers.
The device offers access times of 70, 90, and 120 ns, allowing
high speed microprocessors to operate without wait states.
To eliminate bus contention each device has separate chip
enable (CE#), write enable (WE#) and output enable (OE#)
controls.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Each device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and regu-
lated voltages are provided for the program and erase
operations.
Hardware data protection measures include a low V
CC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature dis-
ables both program and erase operations in any combination
of sectors of memory. This can be achieved in-system or via
programming equipment.
The Am29F004B is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands
are written to the command register using standard micropro-
cessor write timing. Register contents serve as inputs to an
internal state-machine that controls the erase and program-
ming circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from other
Flash or EPROM devices.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any sector that is not selected for erasure. True back-
ground erase can thus be achieved.
The device offers a standby mode as a power-saving fea-
ture. Once the system places the device into the standby
mode power consumption is greatly reduced.
Device programming occurs by executing the program
command sequence. This initiates the Embedded Program
algorithm-an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin.
AMD’s Flash technology combines years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via Fowler-
Nordheim tunnelling. The data is programmed using hot elec-
tron injection.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algorithm–an
internal algorithm that automatically preprograms the array (if it
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Am29F004B
8/5/05
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .8
Am29F004B Device Bus Operations ................................................8
Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 8
Program and Erase Operation Status ...................................... 8
Standby Mode .......................................................................... 8
Output Disable Mode ................................................................ 9
Am29F004B Top Boot Block Sector Addresses ...............................9
Am29F004B Bottom Boot Block Sector Addresses ..........................9
Autoselect Mode ..................................................................... 10
Am29F004B Autoselect Codes (High Voltage Method) ..................10
Sector Protection/Unprotection ............................................... 10
In-System Sector Protect/Sector Unprotect Algorithms ..................11
Temporary Sector Unprotect .................................................. 12
Temporary Sector Unprotect Operation ..........................................12
Hardware Data Protection ...................................................... 13
DQ6: Toggle Bit I .................................................................... 18
DQ2: Toggle Bit II ................................................................... 18
Reading Toggle Bits DQ6/DQ2 ............................................... 18
DQ5: Exceeded Timing Limits ................................................ 18
DQ3: Sector Erase Timer ....................................................... 18
Toggle Bit Algorithm ....................................................................... 19
Write Operation Status ................................................................... 19
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 20
Maximum Negative Overshoot Waveform ..................................... 20
Maximum Positive Overshoot Waveform ....................................... 20
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 20
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21
TTL/NMOS Compatible .......................................................... 21
CMOS Compatible .................................................................. 22
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Test Setup ...................................................................................... 23
Test Specifications ......................................................................... 23
Key to Switching Waveforms . . . . . . . . . . . . . . . 23
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Operations .................................................................... 24
Read Operations Timings .............................................................. 24
Erase/Program Operations ..................................................... 25
Program Operation Timings ........................................................... 26
Chip/Sector Erase Operation Timings ............................................ 26
Data# Polling Timings (During Embedded Algorithms) .................. 27
Toggle Bit Timings (During Embedded Algorithms) ....................... 27
DQ2 vs. DQ6.................................................................................. 27
Sector Unlock Sequence Timing Diagram ..................................... 28
Sector Relock Timing Diagram ...................................................... 28
Sector Protect/Unprotect Timing Diagram ..................................... 29
Alternate CE# Controlled Erase/Program Operations ............ 30
Alternate CE# Controlled Write Operation Timings ........................ 31
Erase and Programming Performance . . . . . . . 32
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 32
PLCC Pin Capacitance . . . . . . . . . . . . . . . . . . . . 32
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 33
PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 33
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 34
Low V Write Inhibit ......................................................................13
CC
Write Pulse Glitch Protection ..........................................................13
Logical Inhibit ..................................................................................13
Power-Up Write Inhibit ....................................................................13
Command Definitions . . . . . . . . . . . . . . . . . . . . . .13
Reading Array Data ................................................................ 13
Reset Command ..................................................................... 13
Autoselect Command Sequence ............................................ 13
Byte Program Command Sequence ....................................... 13
Program Operation ..........................................................................14
Chip Erase Command Sequence ........................................... 14
Sector Erase Command Sequence ........................................ 14
Erase Operation ..............................................................................15
Erase Suspend/Erase Resume Commands ........................... 15
Am29F004B Command Definitions .................................................16
Write Operation Status . . . . . . . . . . . . . . . . . . . . .17
DQ7: Data# Polling ................................................................. 17
Data# Polling Algorithm ...................................................................17
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Am29F004B
3
A D V A N C E I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F004B
Speed Option
VCC = 5.0 V 10ꢀ
-70
70
70
30
-90
90
90
35
-120
120
120
45
Max access time, ns (tACC
Max CE# access time, ns (tCE
Max OE# access time, ns (tOE
)
)
)
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
VCC
VSS
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A0–A18
4
Am29F004B
8/5/05
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
3
4
31 30
1 32
2
A7
A6
5
6
A14
A13
29
28
A5
A4
7
8
A8
A9
27
26
PLCC
A3
A2
9
A11
25
24
23
22
21
10
11
12
13
OE#
A1
A10
CE#
DQ7
A0
DQ0
16 17
19 20
18
15
14
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Am29F004B
5
A D V A N C E I N F O R M A T I O N
PIN CONFIGURATION
LOGIC SYMBOL
A0–A18
= 19 addresses
19
DQ0–DQ7 = 8 data inputs/outputs
A0–A18
8
CE#
OE#
WE#
=
=
=
=
Chip enable
Output enable
Write enable
DQ0–DQ7
CE#
OE#
V
+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
CC
WE#
V
=
=
Device ground
SS
NC
Pin not connected internally
6
Am29F004B
8/5/05
A D V A N C E I N F O R M A T I O N
ORDERING INFORMATION
Standard Product
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am29F004B
T
-70
J
I
TEMPERATURE RANGE
I
=
=
=
=
Industrial (–40°C to +85°C)
F
E
K
Industrial (–40°C to +85°C) for Pb-free package
Extended (–55°C to +125°C)
Extended (–55°C to +125°C) for Pb-free package
PACKAGE TYPE
32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
J
=
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top sector
Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F004B
4 Megabit (512 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
AM29F004BT-70
VCC Voltage
JI, JF
AM29F004BB-70
AM29F004BT-90
AM29F004BB-90
5.0 V 10ꢀ
JI, JE,
JF, JK
AM29F004BT-120
AM29F004BB-120
8/5/05
Am29F004B
7
A D V A N C E I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the internal
command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the com-
mand. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. Am29F004B Device Bus Operations
CE# OE# WE#
Operation
A0–A18
DQ0–DQ7
DOUT
DIN
Read
L
L
H
AIN
AIN
X
Write
L
H
X
X
H
X
L
X
X
H
X
CMOS Standby
TTL Standby
Output Disable
VCC 0.5 V
High-Z
High-Z
High-Z
X
H
L
X
X
Temporary Sector Unprotect (See Note)
X
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.ꢀ V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector
Unprotect for more information.
separate from the memory array) on DQ7–DQ0. Standard
read cycle timings apply in this mode. Refer to the Autoselect
Mode on page 10 and Autoselect Command Sequence sec-
tions for more information.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE# and OE# pins to V . CE# is the power control and
IL
selects the device. OE# is the output control and gates array
I
in the DC Characteristics table represents the active
data to the output pins. WE# should remain at V .
CC2
IH
current specification for the write mode. The AC
Characteristics on page 24 section contains timing specifica-
tion tables and timing diagrams for write operations.
The internal state machine is set for reading array data upon
device power-up. This ensures that no spurious alteration of
the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
Program and Erase Operation Status
During an erase or program operation, the system may check
the status of the operation by reading the status bits on DQ7–
DQ0. Standard read cycle timings and I read specifications
CC
apply. Refer to Write Operation Status on page 17 for more
information, and to each AC Characteristics section for timing
diagrams.
See Reading Array Data on page 13 for more information.
Refer to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for the
timing waveforms. I
sents the active current specification for reading array data.
in the DC Characteristics table repre-
CC1
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed
in the high impedance state, independent of the OE# input.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
The device enters the CMOS standby mode when CE# pin is
memory), the system must drive WE# and CE# to V , and
IL
held at V ± 0.5 V. (Note that this is a more restricted voltage
OE# to V .
CC
IH
range than V .) The device enters the TTL standby mode
IH
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables indicate the
address space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select a
sector. See the Command Definitions on page 13 section for
details on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
when CE# pin is held at V . The device requires standard
IH
access time (t ) for read access when the device is in either
CE
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
In the DC Characteristics tables, I
current specification.
represents the standby
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
CC3
8
Am29F004B
8/5/05
A D V A N C E I N F O R M A T I O N
Output Disable Mode
When the OE# input is at V , output from the device is dis-
IH
abled. The output pins are placed in the high impedance
state.
Table 2. Am29F004B Top Boot Block Sector Addresses
Sector Size
(Kbytes)
Address Range
(in hexadecimal)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
A18
0
A17
0
A16
0
A15
X
X
X
X
X
X
X
0
A14
X
A13
X
64
64
64
64
64
64
64
32
8
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–77FFFh
78000h–79FFFh
7A000h–7BFFFh
7C000h–7FFFFh
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
1
1
1
1
0
0
1
1
1
1
0
1
8
1
1
1
1
1
X
16
Table 3. Am29F004B Bottom Boot Block Sector Addresses
Sector Size
Address Range
(in hexadecimal)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
A18
0
A17
0
A16
A15
A14
A13
X
0
(Kbytes)
0
0
0
16
8
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
0
0
0
0
1
0
0
0
0
1
1
8
0
0
0
1
X
X
X
X
X
X
0
32
64
64
64
64
64
64
64
0
0
1
X
X
X
X
X
X
X
X
0
1
0
X
0
1
1
X
1
0
0
X
1
0
1
X
1
1
0
X
1
1
1
1
X
X
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Am29F004B
9
A D V A N C E I N F O R M A T I O N
the sector address must appear on the appropriate highest
Autoselect Mode
order address bits. Refer to the corresponding Sector
Address Tables. The Command Definitions table shows the
remaining address bits that are don’t care. When all neces-
sary bits are set as required, the programming equipment
may then read the corresponding identifier code on DQ7–
DQ0.
The autoselect mode provides manufacturer and device iden-
tification, and sector protection verification, through identifier
codes output on DQ7–DQ0. This mode is primarily intended
for programming equipment to automatically match a device
to be programmed with its corresponding programming algo-
rithm. However, the autoselect codes can also be accessed
in-system through the command register.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register,
as shown in the Command Definitions table. This method
When using programming equipment, the autoselect mode
requires V on address pin A9. Address pins A6, A1, and A0
must be as shown in Autoselect Codes (High Voltage
Method) table. In addition, when verifying sector protection,
ID
does not require V . See Command Definitions on page 13
ID
for details on using the autoselect mode.
Table 4. Am29F004B Autoselect Codes (High Voltage Method)
A18
to
A12
to
A8
to
A5
to
DQ7
to
Description
CE#
OE# WE# A13
A10
A9
A7
A6
A2
A1
A0
DQ0
Manufacturer ID: AMD
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
VID
X
L
X
L
L
01h
Device ID:
Am29F004B (Top Boot Block)
X
X
VID
X
L
L
X
L
L
H
H
77h
Device ID:
Am29F004B (Bottom Boot Block)
X
X
X
VID
X
X
X
X
7Bh
01h (protected)
Sector Protection Verification
L
L
H
SA
VID
L
H
L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
The alternate method intended only for programming equip-
Sector Protection/Unprotection
ment required V on address pin A9 and OE#. This method
ID
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
is compatible with programmer routines written for earlier 5.0
volt-only AMD Flash devices. Publication number 22289 con-
tains further details; contact an AMD representative to
request a copy.
The primary method requires V on the OE# pin only, and
ID
The device is shipped with all sectors unprotected. AMD
offers the option of programming and protecting sectors at its
factory prior to shipping the device through AMD’s Express-
Flash™ Service. Contact an AMD representative for details.
can be implemented either in-system or via programming
equipment. Figure 1, on page 11 and 2 show the algorithms
and Figure 16, on page 28, Figure 17, on page 28, and Figure
18, on page 29 show the timing diagrams. This method uses
standard microprocessor bus cycle timing in addition to the
sector unlock and sector relock sequences. For sector unpro-
tect, all unprotected sectors must first be protected prior to
the first sector unprotect write cycle.
It is possible to determine whether a sector is protected or
unprotected. See Autoselect Mode on page 10 for details.
10
Am29F004B
8/5/05
A D V A N C E I N F O R M A T I O N
START
START
PLSCNT = 1
Set OE# = V
Write Sector
Unlock sequence
PLSCNT = 1
Set OE# = V
Write Sector
Unlock sequence
.
ID
.
ID
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
with command 24h
with command 24h
Wait 1 ms
Wait 1 ms
Write 60h to
any address with
A6 = 1, A5 = 1,
A1 = 1, A0 = 0
Write 60h to any
address with
A6 = 0, A5 = 1,
A1 = 1, A0 = 0
unprotect address
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
Yes
A6 = 0, A5 = 1,
A1 = 1, A0 = 0
Set up first sector
address
Wait 150 ± 15 μs
Sector Unprotect:
Write 60h to sector
address with
Set OE# = V
IH
A6 = 1, A5 = 1,
A1 = 1, A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Set OE# = V
IH
Reset
PLSCNT = 1
A1 = 1, A0 = 0
Wait 15 ± 1.5 ms
Increment
PLSCNT
Set OE# = V
IL
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
(requires 1 μs
access time)
Increment
PLSCNT
No
Set OE# = V
IL
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
(requires 1 μs
access time)
No
PLSCNT
= 25?
Data = 01h?
Yes
Yes
Set up
next sector
address
No
Yes
No
Protect another
sector?
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Set OE# = V
.
ID
No
Write Sector
Relock sequence.
Set OE# = V
Last sector
verified?
Device failed
.
IH
Yes
Set OE# = V
.
Sector Protect
Algorithm
ID
Sector Protect
complete
Sector Unprotect
Algorithm
Write Sector
Relock sequence.
Set OE# = V
.
IH
Sector Unprotect
complete
Figure 1. In-System Sector Protect/Sector Unprotect Algorithms
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A D V A N C E I N F O R M A T I O N
Temporary Sector Unprotect
This feature allows temporary unprotection of previously pro-
tected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the OE# pin to 12.0
START
Volts (V ). Figure 2 shows the algorithm, and Figure 16, on
page 28 and Figure 17, on page 28 show the timing dia-
ID
OE# = VID
grams, for this feature. While OE# is at V , the sector unlock
ID
sequence is written to the device. After the sector unlock
sequence is written, the OE# pin is taken back to V . The
device is now in the temporary sector unprotect mode.
IH
Write the three-cycle
Unlock sequence with com-
mand 20h (Figure 16)
While in this mode, formerly protected sectors can be pro-
grammed or erased by selecting the appropriate sector
address during programming or erase operations. Either
sector erase or chip erase operations can be performed in
this mode. Byte program operations require only two cycles,
while sector and chip erase operations only require four
cycles. Refer to the Command Definitions table.
OE# = VIH (Note 1)
Perform Erase or
Program Operations
Exiting the temporary sector unprotect mode is accomplished
by either removing V
from the device or by taking OE#
CC
back to V and writing the sector relock sequence.
ID
OE# = VID
After writing the sector relock sequence, the OE# pin is taken
back to V and all previously protected sectors are protected
IH
again.
Write the two-cycle
Sector Relock sequence (Fig-
ure 17)
OE# = VIH
Temporary Sector
Unprotect
Completed (Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 2. Temporary Sector Unprotect Operation
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A D V A N C E I N F O R M A T I O N
The system must issue the reset command to re-enable the
Hardware Data Protection
device for reading array data if DQ5 goes high, or while in the
autoselect mode. See the Reset Command section, next.
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might oth-
erwise be caused by spurious system level signals during
See also “Requirements for Reading Array Data” in the
Device Bus Operations on page 8 section for more informa-
tion. The Read Operations table provides the read
parameters, and Read Operation Timings diagram shows the
timing diagram.
V
power-up and power-down transitions, or from system
CC
noise.
Reset Command
Low V
Write Inhibit
CC
Writing the reset command to the device resets the device to
reading array data. Address bits are don’t care for this
command.
When V is less than V
write cycles. This protects data during V
power-down. The command register and all internal pro-
gram/erase circuits are disabled, and the device resets.
Subsequent writes are ignored until V is greater than V
, the device does not accept any
CC
LKO
power-up and
CC
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the device to reading array data. Once
erasure begins, however, the device ignores reset commands
until the operation is complete.
.
CC
LKO
The system must provide the proper signals to the control
pins to prevent unintentional writes when V is greater than
CC
V
.
LKO
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data (also
applies to programming in Erase Suspend mode). Once pro-
gramming begins, however, the device ignores reset
commands until the operation is complete.
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE#
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V ,
IL
CE# = V or WE# = V . To initiate a write cycle, CE# and
WE# must be a logical zero while OE# is a logical one.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
IH
IH
Power-Up Write Inhibit
If WE# = CE# = V and OE# = V during power up, the
IL
IH
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset to
reading array data on power-up.
If DQ5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
Autoselect Command Sequence
COMMAND DEFINITIONS
The autoselect command sequence allows the host system
to access the manufacturer and devices codes, and deter-
mine whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
PROM programmers and requires V on address bit A9.
ID
All addresses are latched on the falling edge of WE# or CE#,
whichever happens later. All data is latched on the rising edge
of WE# or CE#, whichever happens first. Refer to the appro-
priate timing diagrams in AC Characteristics on page 24.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
Reading Array Data
A read cycle at address XX00h or retrieves the manufacturer
code. A read cycle at address XX01h returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in returns 01h if that sector is protected, or 00h
if it is unprotected. Refer to the Sector Address tables for valid
sector addresses.
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing
an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the
device enters the Erase Suspend mode. The system can
read array data using the standard read timings, except that
if it reads at an address within erase-suspended sectors, the
device outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See Reset
Command for more information on this mode.
The system must write the reset command to exit the autose-
lect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
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A D V A N C E I N F O R M A T I O N
cycles, followed by the program set-up command. The
Chip Erase Command Sequence
program address and data are written next, which in turn ini-
tiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated program pulses
and verify the programmed cell margin. (Note that if the
device is in the temporary sector unprotect mode, the byte
program command sequence only requires two cycles.) The
Command Definitions table shows the address and data
requirements for the byte program command sequence.
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. (Note that if the
device is in the temporary sector unprotect mode, the chip
erase command sequence only requires four cycles.) The
Command Definitions table shows the address and data
requirements for the chip erase command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using DQ7 or DQ6. See Write
Operation Status on page 17 for information on these status
bits.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The Sector Erase command
sequence should be reinitiated once the device returns to
reading array data, to ensure data integrity.
Any commands written to the device during the Embedded
Program Algorithm are ignored. The Sector Erase command
sequence should be reinitiated once the device returns to
reading array data, to ensure data integrity.
The system can determine the status of the erase operation
by using DQ7, DQ6, or DQ2. See Write Operation Status on
page 17 for information on these status bits. When the
Embedded Erase algorithm is complete, the device returns to
reading array data and addresses are no longer latched.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a 0 back to
a 1. Attempting to do so may halt the operation and set DQ5
to 1, or cause the Data# Polling algorithm to indicate the oper-
ation was successful. However, a succeeding read shows
that the data is still 0. Only erase operations can convert a 0
to a 1”.
Figure 4, on page 15 illustrates the algorithm for the erase
operation. See the Erase/Program Operations on page 2ꢀ
for parameters, and to Figure 12, on page 26 for timing
waveforms.
Sector Erase Command Sequence
START
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. (Note that if the
device is in the temporary sector unprotect mode, the sector
erase command sequence only requires four cycles.) The
Command Definitions table shows the address and data
requirements for the sector erase command sequence.
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the sector for an all zero data
pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
in progress
Verify Data?
No
Yes
After the command sequence is written, a sector erase time-
out of 50 µs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50 µs, otherwise the last address and command
might not be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during this time
to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written. If
the time between additional sector erase commands can be
assumed to be less than 50 µs, the system need not monitor
DQ3. Any command other than Sector Erase or Erase
Suspend during the time-out period resets the device to
reading array data. The system must rewrite the command
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See the appropriate Command Definitions table for program
command sequence.
Figure 3. Program Operation
14
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A D V A N C E I N F O R M A T I O N
sequence and any additional sector addresses and
commands.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or program
data to, any sector not selected for erasure. This command is
valid only during the sector erase operation, including the 50
µs time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if written
during the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are
don’t-cares when writing the Erase Suspend command.
The system can monitor DQ3 to determine if the sector erase
timer timed out. (See DQ3: Sector Erase Timer on page 18.)
The time-out begins from the rising edge of the final WE#
pulse in the command sequence.
Once the sector erase operation begins, only the Erase
Suspend command is valid. All other commands are ignored.
The Sector Erase command sequence should be reinitiated
once the device returns to reading array data, to ensure data
integrity.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using DQ7, DQ6, or DQ2. Refer to Write Oper-
ation Status on page 17 for information on these status bits.
When the Erase Suspend command is written during a sector
erase operation, the device requires a maximum of 20 µs to
suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-
out, the device immediately terminates the time-out period
and suspends the erase operation.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations on page 2ꢀ for
parameters, and to the Sector Erase Operations Timing
diagram for timing waveforms.
After the erase operation is suspended, the system can read
array data from or program data to any sector not selected for
erasure. (The device “erase suspends” all sectors selected
for erasure.) Normal read and write timings and command
definitions apply. Reading at any address within erase-sus-
pended sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to deter-
mine if a sector is actively erasing or is erase-suspended.
See Write Operation Status on page 17 for information on
these status bits.
START
Write Erase
Command Sequence
After an erase-suspended program operation is complete,
the system can once again read array data within non-sus-
pended sectors. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits, just as
in the standard program operation. See Write Operation
Status on page 17 for more information.
Data Poll
from System
Embedded
Erase
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence on page 13 for more
information.
algorithm
in progress
No
Data = FFh?
Yes
The system must write the Erase Resume command
(address bits are don’t care) to exit the erase suspend mode
and continue the sector erase operation. Further writes of the
Resume command are ignored. Another Erase Suspend
command can be written after the device resumes erasing.
Erasure Completed
Note:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See DQ3: Sector Erase Timer on page 18 for more information.
Figure 4. Erase Operation
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A D V A N C E I N F O R M A T I O N
Table 5. Am29F004B Command Definitions
Bus Cycles (Notes 2–4)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data Addr Data Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
RA
XXX
555
RD
F0
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
01
77
Device ID,
4
4
555
555
AA
AA
Top Boot Block
Autoselect
(Note 7)
Device ID,
Bottom Boot Block
2AA
2AA
55
55
555
555
90
90
X01
7B
00
01
Sector Protect Verify
(Note 8)
(SA)
X02
4
555
AA
Program
4
6
6
1
1
3
2
4
4
3
2
555
555
AA
AA
AA
B0
30
2AA
2AA
2AA
55
55
55
555
555
555
A0
80
80
PA
PD
AA
AA
Chip Erase
Sector Erase
555
555
2AA
2AA
55
55
555
SA
10
30
555
Erase Suspend (Note 11)
Erase Resume (Note 12)
Temporary Enter TSU Mode
Sector
Unprotect
XXX
XXX
555
AA
A0
80
2AA
PA
55
PD
AA
AA
55
555
20
Program
XXX
XXX
XXX
555
Sector Erase
XXX
XXX
2AA
XXX
XXX
XXX
555
55
55
24
SA
555
SA+
30
10
60
Mode (Note
9)
Chip Erase
80
Sector Unlock (Note 9)
AA
90
SA+
60
SA+
40
Sector Relock (Notes 9, 10)
XXX
00
Legend:
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
X = Don’t care
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A13 uniquely select any sector.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SA+ = The sector address must be asserted in combination with A0
= 0, A1 = 1, Aꢀ = 1, and A6 = 0 (for protect) or 1 (for unprotect).
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
Notes:
1. See Table 1 for description of bus operations.
8. The data is 00h for an unprotected sector and 01h for a protected
sector. See Autoselect Command Sequence on page 13 for
more information.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are
write operations.
9. To activate the sequence, OE# must be at VID.
10. The sector relock command in the second cycle may be written
as either 00h or F0h.
4. Address bits A18–A11 are don’t cares for unlock and command
cycles, except when PA or SA is required.
11. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
ꢀ. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data
when device is in the autoselect mode, or if DQꢀ goes high (while
the device is providing status data).
12. The Erase Resume command is valid only during the Erase Sus-
pend mode.
7. The fourth cycle of the autoselect command sequence is a read
cycle.
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A D V A N C E I N F O R M A T I O N
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
write operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 6 on
page 19 and the following subsections describe the functions
of these bits. DQ7 and DQ6 each offer a method for deter-
mining whether a program or erase operation is complete or
in progress. These three bits are discussed first.
START
Read DQ7–DQ0
Addr = VA
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data# Polling is
valid after the rising edge of the final WE# pulse in the
program or erase command sequence.
Yes
DQ7 = Data?
During the Embedded Program algorithm, the device outputs
on DQ7 the complement of the datum programmed to DQ7.
This DQ7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is com-
plete, the device outputs the datum programmed to DQ7. The
system must provide the program address to read valid status
information on DQ7. If a program address falls within a pro-
tected sector, Data# Polling on DQ7 is active for
approximately 2 µs, then the device returns to reading array
data.
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling pro-
duces a “0” on DQ7. When the Embedded Erase algorithm is
complete, or if the device enters the Erase Suspend mode,
Data# Polling produces a “1” on DQ7. This is analogous to
the complement/true datum output described for the
Embedded Program algorithm: the erase function changes
all the bits in a sector to “1”; prior to this, the device outputs
the “complement,” or “0.” The system must provide an
address within any of the sectors selected for erasure to read
valid status information on DQ7.
Yes
DQ7 = Data?
No
PASS
FAIL
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data# Polling on DQ7 is
active for approximately 100 µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a sector erase
operation, a valid address is an address within any sector
selected for erasure. During chip erase, a valid address is any
non-protected sector address.
When the system detects DQ7 changes from the comple-
ment to true data, it can read valid data at DQ7–DQ0 on the
following read cycles. This is because DQ7 may change
asynchronously with DQ0–DQ6 while Output Enable (OE#) is
asserted low. The Data# Polling Timings (During Embedded
Algorithms) figure in the AC Characteristics on page 24
section illustrates this.
2. DQ7 should be rechecked even if DQꢀ = “1” because DQ7 may
change simultaneously with DQꢀ.
Figure 5. Data# Polling Algorithm
Table 6 on page 19 shows the outputs for Data# Polling on
DQ7. Figure 5, on page 17 shows the Data# Polling
algorithm.
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17
A D V A N C E I N F O R M A T I O N
explains the algorithm. See also the DQ6: Toggle Bit I on
DQ6: Toggle Bit I
page 18 subsection. Refer to the Toggle Bit Timings figure for
the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows
the differences between DQ2 and DQ6 in graphical form.
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device entered the Erase Suspend mode. Toggle
Bit I may be read at any address, and is valid after the rising
edge of the final WE# pulse in the command sequence (prior
to the program or erase operation), and during the sector
erase time-out.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 19 for the following discussion.
Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to deter-
mine whether a toggle bit is toggling. Typically, a system
would note and store the value of the toggle bit after the first
read. After the second read, the system would compare the
new value of the toggle bit with the first. If the toggle bit is not
toggling, the device completed the program or erase opera-
tion. The system can read array data on DQ7–DQ0 on the
following read cycle.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause DQ6 to toggle.
(The system may use either OE# or CE# to control the read
cycles.) When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 μs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
However, if after the initial two read cycles, the system deter-
mines that the toggle bit is still toggling, the system also
should note whether the value of DQ5 is high (see the section
on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as DQ5 went high. If the toggle bit
is no longer toggling, the device successfully completed the
program or erase operation. If it is still toggling, the device did
not complete the operation successfully, and the system must
write the reset command to return to reading array data.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the
device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see the subsection on DQ7: Data#
Polling).
The remaining scenario is that the system initially determines
that the toggle bit is toggling and DQ5 has not gone high. The
system may continue to monitor the toggle bit and DQ5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6, on page 19).
If a program address falls within a protected sector, DQ6
toggles for approximately 2 µs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 6 for the toggle bit algo-
rithm, and to the Toggle Bit Timings figure in the “AC
Characteristics” section for the timing diagram. The DQ2 vs.
DQ6 figure shows the differences between DQ2 and DQ6 in
graphical form. See also the subsection on DQ2: Toggle Bit II.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time exceeded
a specified internal pulse count limit. Under these conditions
DQ5 produces a 1. This is a failure condition that indicates
the program or erase cycle was not successfully completed.
DQ2: Toggle Bit II
The DQ5 failure condition may appear if the system tries to
program a 1 to a location that is previously programmed to 0.
Only an erase operation can change a “0” back to a 1.
Under this condition, the device halts the operation, and
when the operation exceeds the timing limits, DQ5 produces
a 1.
The Toggle Bit II on DQ2, when used with DQ6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final WE# pulse in the command sequence.
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
DQ2 toggles when the system reads at addresses within
those sectors that were selected for erasure. (The system
may use either OE# or CE# to control the read cycles.) But
DQ2 cannot distinguish whether the sector is actively erasing
or is erase-suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase Sus-
pend, but cannot distinguish which sectors are selected for
erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 on page 19 to compare
outputs for DQ2 and DQ6.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read DQ3 to determine whether or not an erase opera-
tion started. (The sector erase timer does not apply to the
chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional
sector erase command. When the time-out is complete, DQ3
switches from 0 to 1. The system may ignore DQ3 if the
system can guarantee that the time between additional sector
Figure 6, on page 19 shows the toggle bit algorithm in flow-
chart form, and the section DQ2: Toggle Bit II on page 18
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Am29F004B
8/5/05
A D V A N C E I N F O R M A T I O N
erase commands is always less than 50 μs. See also the
Sector Erase Command Sequence on page 14 section.
START
After the sector erase command sequence is written, the
system should read the status on DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure the device accepts the command
sequence, and then read DQ3. If DQ3 is 1, the internally con-
trolled erase cycle started; all further commands (other than
Erase Suspend) are ignored until the erase operation is com-
plete. If DQ3 is 0, the device accepts additional sector erase
commands. To ensure the command was accepted, the
system software should check the status of DQ3 prior to and
following each subsequent sector erase command. If DQ3 is
high on the second status check, the last command might not
have been accepted. Table 6 on page 19 shows the outputs
for DQ3.
Read DQ7–DQ0
(Note
1)
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
(Notes
1, 2)
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
See text.
2. Recheck toggle bit because it may stop toggling as DQꢀ
changes to 1. See text.
Figure 6. Toggle Bit Algorithm
Table 6. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 1)
DQ6
(Note 2)
DQ3
N/A
1
(Note 1)
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Erase
Suspend
Mode
Reading within Non-Erase Suspended
Sector
Data
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQꢀ switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQꢀ:
Exceeded Timing Limits on page 18 for more information.
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19
A D V A N C E I N F O R M A T I O N
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
20 ns
20 ns
Plastic Packages . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
+0.8 V
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . . . . . . –55°C to +125°C
–0.5 V
–2.0 V
Voltage with Respect to Ground
V
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
CC
A9, OE# (Note 2) . . . . . . . . . . . . . . . . . . . .–2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . 200 mA
20 ns
Figure 7. Maximum Negative Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.ꢀ V. During voltage
transitions, input or I/O pins may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 7, on page 20. Maximum DC
voltage on input or I/O pins is VCC +0.ꢀ V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for
periods up to 20 ns. See Figure 8, on page 20.
20 ns
2. Minimum DC input voltage on pins A9 and OE# is –0.ꢀ V. During
voltage transitions, A9 and OE# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 7, on page 20. Maximum DC
input voltage on pin A9 is +12.ꢀ V which may overshoot to +13.ꢀ
V for periods up to 20 ns.
VCC
+2.0 V
VCC
+0.5 V
3. No more than one output may be shorted to ground at a time.
Duration of the short circuit should not be greater than one
second.
2.0 V
20 ns
20 ns
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating con-
ditions for extended periods may affect device reliability.
Figure 8. Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . . . . . . –40°C to +85°C
A
Extended (E) Devices
Ambient Temperature (T ) . . . . . . . . . . . . . –55°C to +125°C
A
V
Supply Voltages
CC
V
V
for 5ꢀ devices. . . . . . . . . . . . . . . .+4.75 V to +5.25 V
for 10ꢀ devices. . . . . . . . . . . . . . . . .+4.5 V to +5.5 V
CC
CC
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
20
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A D V A N C E I N F O R M A T I O N
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC max
±1.0
µA
A9, OE# Input Load Current
(Note 4)
VCC = VCC max;
A9, OE# = 12.5 V
ILIT
50
µA
ILO
ICC1
ICC2
ICC3
VIL
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC max
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
CE#, OE# = VIH
±1.0
30
µA
mA
mA
mA
V
VCC Active Read Current (Notes 1, 2)
VCC Active Write Current (Notes 1, 3, 4)
VCC Standby Current (Note 1)
Input Low Voltage
20
30
40
0.4
1
–0.5
2.0
0.8
VCC
+ 0.5
VIH
VID
Input High Voltage
V
V
Voltage for Autoselect and Temporary Sector
Unprotect
VCC = 5.0 V
11.5
12.5
0.45
VOL
VOH
VLKO
Output Low Voltage
IOL = 12 mA, VCC = VCC min
IOH = –2.5 mA, VCC = VCC min
V
V
V
Output High Voltage
Low VCC Lock-Out Voltage
2.4
3.2
4.2
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax
2. The ICC current listed is typically less than 2 mA/MHz, with OE#
at VIH
.
3. ICC active while Embedded Erase or Embedded Program is in
progress.
.
4. Not 100% tested.
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A D V A N C E I N F O R M A T I O N
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
VIN = VSS to VCC
Min
Typ
Max
Unit
,
ILI
Input Load Current
±1.0
µA
VCC = VCC max
A9, OE#, Input Load Current (Note VCC = VCC max
;
ILIT
50
±1.0
30
µA
µA
4)
A9, OE# = 12.5 V
VOUT = VSS to VCC
VCC = VCC max
,
ILO
Output Leakage Current
VCC Active Read Current
(Notes 1, 2)
ICC1
ICC2
ICC3
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
CE# = VCC ± 0.5 V
20
30
mA
mA
µA
VCC Active Write Current
(Notes 1, 3, 4)
40
VCC Standby Current
(Notes 1, 5)
0.3
5
VIL
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
VIH
0.7 x VCC
VCC + 0.3
Voltage for Autoselect and
Temporary Sector Unprotect
VID
VCC = 5.0 V
11.5
12.5
0.45
V
VOL
Output Low Voltage
IOL = 12 mA, VCC = VCC min
IOH = –2.5 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
V
V
VOH1
VOH2
VLKO
0.85 VCC
VCC–0.4
3.2
Output High Voltage
Low VCC Lock-Out Voltage
4.2
V
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax
2. The ICC current listed is typically less than 2 mA/MHz, with OE#
at VIH
.
3. ICC active while Embedded Erase or Embedded Program is in
progress.
.
4. Not 100% tested.
ꢀ. ICC3 = 20 µA max at extended temperature (>+8ꢀ° C).
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A D V A N C E I N F O R M A T I O N
TEST CONDITIONS
Table 7. Test Specifications
Test Condition 70, 90, 120
Output Load 1 TTL gate
5.0 V
Unit
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
100
pF
Input Rise and Fall Times
Input Pulse Levels
20
ns
V
C
L
6.2 kΩ
0.45–2.4
Input timing measurement
reference levels
0.8, 2.0
0.8, 2.0
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 9. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
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23
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
-70
-90
-120
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Address to Output Delay
Min
70
90
120
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Max
70
90
120
ns
tELQV
tGLQV
tEHQZ
tCE
tOE
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
70
30
20
90
35
20
120
45
ns
ns
ns
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
30
Output Enable to Output High Z
(Note 1)
tGHQZ
tDF
tOEH
tOH
Max
Min
Min
20
20
0
30
ns
ns
ns
Read
Output Enable
Hold Time
(Note 1)
Toggle and
Data# Polling
10
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
tAXQX
Min
0
ns
Notes:
1. Not 100% tested.
2. See Table 7 and Figure 9, on page 23 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
OE#
tDF
tOE
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
Figure 10. Read Operations Timings
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8/5/05
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
-70
-90
90
0
-120
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
70
120
tAVWL
tWLAX
tDVWH
tWHDX
ns
tAH
45
30
45
45
0
50
50
ns
tDS
ns
tDH
tOES
Data Hold Time
ns
Output Enable Setup Time
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHWL
tWHWH1
tWHWH2
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
0
0
ns
ns
CE# Hold Time
tWP
Write Pulse Width
Write Pulse Width High
35
45
20
7
50
ns
tWPH
ns
tWHWH1 Programming Operation (Note 2)
tWHWH2 Sector Erase Operation (Note 2)
µs
1
sec
µs
tVCS
VCC Setup Time (Note 1)
50
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance on page 32 for more
information.
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25
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data
at the program address.
Figure 11. Program Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
VCC
Complete
55h
30h
Progress
10 for Chip Erase
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for
reading status data (”see Write Operation Status on page 17).
Figure 12. Chip/Sector Erase Operation Timings
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
tRC
Addresses
VA
tACC
tCE
VA
VA
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Valid Data
Status Data
True
Status Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 13. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Figure 15. DQ2 vs. DQ6
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27
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Parameter
JEDEC
Std.
Description
VID Rise and Fall Time (Not 100ꢀ tested)
All Speed Options
Unit
tVIDR
Min
500
ns
V
V
ID
, V
SS IL
OE#
or V
IH
t
VIDR
A18 – A0
555h
AAh
2AAh
55h
555h
D7 – D0
20h/24h
CE#
WE#
Device is ready to read from array.
If 20h is written, Sector Unprotect mode
is enabled. If 24h is written, command mode
Sector Protect/Unprotect is enabled.
Figure 16. Sector Unlock Sequence Timing Diagram
V
V
ID
, V
IH
OE#
SS IL
or V
0 V or 5 V
t
t
VIDR
VIDR
A18 – A0
XXXh
90h
XXXh
D7 – D0
F0h or 00h
CE#
WE#
Device is in either Temporary Sector Unprotect
mode or command mode Sector Protect/Unprotect.
Device exits Temporary Sector Unprotect mode
or command mode Sector Protect/Unprotect.
Returns to reading array data.
Figure 17. Sector Relock Timing Diagram
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
V
ID
V
IH
OE#
V
SS
A18 – A0
XXXh
60h
Valid (Note 2)
Valid (Note 2)
D7 – D0
Array Data
60h
40h
CE#
WE#
Sector Unlock sequence (three cycles)
Sector Relock sequence (two cycles)
Notes:
1. To enable the command mode sector protection/unprotection
algorithm, the system must issue the command 24h in the sector
unlock sequence.
unprotection, a valid address consists of the sector address with
A6 = 1, Aꢀ = 1, A1 = 1, A0 = 0.
2. For sector protection, a valid address consists of the sector
address with A6 = 0, Aꢀ = 1, A1 = 1, A0 = 0. For sector
Figure 18. Sector Protect/Unprotect Timing Diagram
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program
Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
-70
-90
90
0
-120
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
70
120
tAVEL
ns
tELAX
tDVEH
tEHDX
tAH
45
30
45
45
0
50
50
ns
tDS
ns
tDH
Data Hold Time
ns
tOES
Output Enable Setup Time
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
CE# Pulse Width
CE# Pulse Width High
35
45
20
7
50
ns
tCPH
ns
tWHWH1 tWHWH1 Programming Operation (Note 2)
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
1. Not 100% tested.
µs
1
sec
2. See Erase and Programming Performance on page 32 for more
information.
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
555 for programPA for program
2AA for erase SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
t
t
WC
AS
t
AH
t
WH
WE#
OE#
t
GHEL
t
WHWH1 or
t
t
CP
CE#
t
WS
CPH
t
D
t
D
DOUT
DQ7
Data
A0 for programPD for program
55 for erase
30 for sector erase
10 for chip erase
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of data written to device, DOUT = data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 19. Alternate CE# Controlled Write Operation Timings
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31
A D V A N C E I N F O R M A T I O N
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
1
8
8
Excludes 00h programming prior to
erasure (Note 4)
Chip Erase Time
s
Byte Programming Time
Chip Programming Time (Note 3)
7
300
µs
s
Excludes system level overhead
(Note 5)
3.6
10.8
Notes:
1. Typical program and erase times assume the following conditions: 2ꢀ°C, ꢀ.0 V VCC, 1,000,000 cycles. Additionally, programming typicals
assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.ꢀ V (4.7ꢀ V for ꢀ% devices), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
ꢀ. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table for further
information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9 and OE#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = ꢀ.0 V, one pin at a time.
PLCC PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Conditions
Typ
4
Max
6
Unit
pF
CIN
VIN = 0
COUT
CIN2
Output Capacitance
VOUT = 0
VPP = 0
8
12
12
pF
Control Pin Capacitance
8
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 2ꢀ°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
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A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
PL 032—32-Pin Plastic Leaded Chip Carrier
Dwg rev AH; 10/99
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33
A D V A N C E I N F O R M A T I O N
In-System Sector Protect/Unprotect Algorithms
REVISION SUMMARY
figure
Revision A (January 1999)
Initial release.
Added tolerance specifications to the 150 µs and 15 ms waits.
Clarified that reading from the sector address during either
sector protect or unprotect algorithm requires an access time
of 1 µs.
Revision B (March 10, 1999)
Global
Revision C (November 12, 1999)
Revised document into full data sheet.
AC Characteristics—Figure 11, Program
Operations Timing and Figure 12, Chip/Sector
Erase Operations
Revision B+1 (March 18, 1999)
In-System Sector Protect/Sector Unprotect
Algorithms figure
Deleted t
and changed OE# waveform to start at high.
GHWL
Physical Dimensions
Added requirements for asserting address A5 and setting
Replaced figures with more detailed illustrations.
OE# to V during both algorithms.
IH
Command Definitions table
Revision D (February 22, 2000)
Global
Added A5 requirement to definition for SA+ in the legend. In
the fourth cycle of the Sector Relock sequence, changed
address from XXX to SA+.
The “preliminary” designation was removed from the docu-
ment. Parameters are now stable, and only speed, package,
and temperature range combinations are expected to change
in future data sheet revisions.
Sector Protect/Unprotect Timing Diagram
Modified drawing to indicate that OE# should be dropped to
V
during the third cycle.
IH
Revision E (November 29, 2000)
Added table of contents.
Revision B+2 (May 14, 1999)
Ordering Information
Ordering Information
Changed the temperature range in the example to I.
Device Bus Operation table
Deleted burn-in option.
Table , Command Definitions
Corrected the highest bit in the address range column header
to A18.
In Note 4, corrected lower address bit of don’t care range to
A11.
Command Definitions table
Revision E+1 (March 28, 2005)
Global
In Note 4, changed the address range for bits that are don’t
care to A18–A12.
Added Colophon
DC Characteristics table
In Note 5, deleted reference to I
.
Updated Trademark
CC4
Read Operations Timings and Alternate CE#
Controlled Write Operations figures
Ordering Information
Added Pb-free temperature ranges for Industrial and
Extended packaging
Deleted RESET# waveform.
Added Valid Combination Codes
Revision B+3 (July 12, 1999)
Revision E+2 (July 26, 2005)
Global
Global
Deleted all references to the PDIP package. Changed data
sheet status to Preliminary.
Removed all 55 ns information from the Datasheet.
34
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8/5/05
A D V A N C E I N F O R M A T I O N
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2000-2005 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
8/5/05
Am29F004B
35
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