AM29F002NBB-70EC [AMD]
2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory; 2兆位（ 256千×8位） CMOS 5.0伏只引导扇区闪存
| 型号： | AM29F002NBB-70EC |
| 厂家： | 
AMD |
| 描述： | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| 文件： | 总42页 (文件大小：800K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am29F002B/Am29F002NB
Data Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 21527 Revision D Amendment 5 Issue Date November 1, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29F002B/Am29F002NB
2 Megabit (256 K x 8-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Embedded Algorithms
— 5.0 Volt-only operation for read, erase, and
program operations
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Minimizes system level requirements
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F002 device
■ Minimum 1,000,000 write cycle guarantee per
■ High performance
sector
— Access times as fast as 55 ns
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
■ Low power consumption (typical values at
5 MHz)
— 1 µA standby mode current
— 20 mA read current
— 32-pin PDIP
— 32-pin TSOP
— 30 mA program/erase current
— 32-pin PLCC
■ Flexible sector architecture
■ Compatibility with JEDEC standards
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
— Pinout and software compatible with
single-power supply Flash
— Supports full chip erase
— Superior inadvertent write protection
— Sector Protection features:
■ Data# Polling and toggle bits
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
— Provides a software method of detecting
program or erase operation completion
Sectors can be locked via programming equipment
■ Erase Suspend/Erase Resume
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Top or bottom boot block configurations available
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data (not available on Am29F002NB)
Publication# 21527 Rev: D Amendment: 5
Issue Date: November 1, 2006
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
D A T A S H E E T
GENERAL DESCRIPTION
The Am29F002B Family consists of 2 Mbit, 5.0
volt-only Flash memory devices organized as 262,144
bytes. The Am29F002B offers the RESET# function,
the Am29F002NB does not. The data appears on
DQ7–DQ0. The device is offered in 32-pin PLCC,
32-pin TSOP, and 32-pin PDIP packages. This device
is designed to be programmed in-system with the stan-
Erase algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
dard system 5.0 volt V supply. No V is required for
CC
PP
write or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and ben-
efits of the Am29F002, which was manufactured using
0.5 µm process technology.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 55, 70, and
90 ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection
feature disables both program and erase operations in
any combination of the sectors of memory. This can be
achieved via programming equipment.
The device requires only a single 5.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
(This feature is not available on the Am29F002NB.)
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
2
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .8
Table 1. Am29F002B/Am29F002NB Device Bus Operations . . . . . .8
Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . 8
Writing Commands/Command Sequences . . . . . . . . . . . . . . . 8
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . 8
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Am29F002B/Am29F002NB Top Boot Block Sector
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . 18
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . 18
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 21
Figure 6. Maximum Negative Overshoot Waveform . . . . . . . . . . . 21
Figure 7. Maximum Positive Overshoot Waveform . . . . . . . . . . . . 21
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 21
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Key to Switching Waveforms . . . . . . . . . . . . . . . 24
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Read Operations Timings . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Program Operation Timings . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. Chip/Sector Erase Operation Timings . . . . . . . . . . . . . 29
Figure 13. Data# Polling Timings (During Embedded Algorithms) . 30
Figure 14. Toggle Bit Timings (During Embedded Algorithms) . . . 30
Figure 15. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16. Temporary Sector Unprotect Timing Diagram
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3. Am29F002B/Am29F002NB Bottom Boot Block Sector
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Am29F002B/Am29F002NB Autoselect Codes (High
Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 10
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 1. Temporary Sector Unprotect Operation . . . . . . . . . . . . . .11
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Low VCC Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Pulse “Glitch” Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Command Definitions . . . . . . . . . . . . . . . . . . . . . .12
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . 12
Byte Program Command Sequence . . . . . . . . . . . . . . . . . . . 12
Figure 2. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . 13
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . 13
Figure 3. Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . 15
Command Definitions ............................................................. 16
Table 5. Am29F002B/Am29F002NB Command Definitions . . . . . .16
Write Operation Status . . . . . . . . . . . . . . . . . . . . .17
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . .17
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
(Am29F002B only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Alternate CE# Controlled Write Operation Timings . . . 33
Erase and Programming Performance . . . . . . . 34
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 34
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 34
PLCC and PDIP Pin Capacitance . . . . . . . . . . . . 35
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 36
PD 032—32-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . 36
PL 032—32-Pin Plastic Leaded Chip Carrier . . . . . . . . . . . . 37
TS 032—32-Pin Standard Thin Small Package . . . . . . . . . . 38
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision A (July 1998) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision B (January 1999) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision C (November 12, 1999) . . . . . . . . . . . . . . . . . . . . . 39
Revision D (November 28, 2000) . . . . . . . . . . . . . . . . . . . . . 39
Revision D +1 (November 5, 2004) . . . . . . . . . . . . . . . . . . . . 39
Revision D +2 (August 3, 2005) . . . . . . . . . . . . . . . . . . . . . . . 39
Revision D3 (December 13, 2005) . . . . . . . . . . . . . . . . . . . . 39
Revision D4 (May 17, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision D5 (November 1, 2006) . . . . . . . . . . . . . . . . . . . . . 39
November 1, 2006 21527D5
Am29F002B/Am29F002NB
3
D A T A S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F002B/Am29F002NB
VCC = 5.0 V 5%
Speed Option
-55
VCC = 5.0 V 10%
-70
70
70
30
-90
90
90
35
Max access time, ns (tACC
Max CE# access time, ns (tCE
Max OE# access time, ns (tOE
)
55
55
30
)
)
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
VCC
VSS
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
RESET#
n/a Am29F002NB
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A0–A17
4
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
CONNECTION DIAGRAMS
NC on Am29F002NB
NC on Am29F002NB
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
RESET#
A16
A15
A12
A7
2
WE#
A17
A14
A13
A8
3
3
4
31 30
1 32
2
4
A7
A6
5
6
A14
A13
29
28
5
A6
6
A5
A4
7
A8
27
26
25
24
23
22
21
A5
7
A9
8
A9
A4
8
A11
OE#
A10
CE#
DQ7
DQ6
PDIP
PLCC
A3
9
A11
OE#
A10
CE#
DQ7
A3
9
A2
10
11
12
13
A2
10
11
12
13
14
15
16
A1
A1
A0
A0
DQ0
DQ0
16 17
19 20
18
15
14
DQ1
DQ2
DQ5
DQ4
DQ3
V
SS
A11
A9
A8
A13
A14
A17
WE#
VCC
OE#
A10
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard TSOP
NC on Am29F002NB
RESET#
A16
A15
A12
A7
A6
A5
A4
A1
A2
A3
November 1, 2006 21527D5
Am29F002B/Am29F002NB
5
D A T A S H E E T
PIN CONFIGURATION
LOGIC SYMBOL
A0–A17
= 18 addresses
18
DQ0–DQ7 = 8 data inputs/outputs
A0–A17
8
CE#
=
=
=
=
Chip enable
Output enable
Write enable
DQ0–DQ7
OE#
WE#
CE#
OE#
RESET#
Hardware reset pin, active low
(not available on Am29F002NB)
WE#
V
=
+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
CC
RESET#
N/C on Am29F002NB
V
=
=
Device ground
SS
NC
Pin not connected internally
6
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
ORDERING INFORMATION
Standard Product
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29F002B/
Am29F002NB
T
-55
P
C
TEMPERATURE RANGE
C
I
=
=
=
=
=
=
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
E
D
F
K
Extended (–55°C to +125°C)
Commercial (0°C to +70°C) for Pb-free Package
Industrial (–40°C to +85°C) for Pb-free Package
Extended (–55°C to +125°C) for Pb-free Package
PACKAGE TYPE
P
J
=
=
=
32-Pin Plastic DIP (PD 032)
32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032)
E
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top sector
Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F002B/Am29F002NB
2 Megabit (256 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Valid Combinations
Valid Combinations
VCC Voltage
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM29F002BT-55
PC,
JC, JI,
EC, EI, ED, EF,
PD, JD, JF
AM29F002BB-55
AM29F002NBT-55
AM29F002NBB-55
5.0 V 5%
AM29F002BT-70
AM29F002BB-70
AM29F002NBT-70
AM29F002NBB-70
PC, PI,
JC, JI,
EC, EI, ED, EF
PD, PF, JD, JF
PC, PI, PE,
JC, JI, JE,
EC, EI, EE
ED, EF, EK
PD, PF, PK
JD, JF, JK
5.0 V 10%
AM29F002BT-90
AM29F002BB-90
AM29F002NBT-90
AM29F002NBB-90
November 1, 2006 21527D5
Am29F002B/Am29F002NB
7
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. The appropriate device bus
operations table lists the inputs and control levels
required, and the resulting output. The following sub-
sections describe each of these operations in further
detail.
Table 1. Am29F002B/Am29F002NB Device Bus Operations
RESET#
Operation
CE#
OE# WE#
(n/a Am29F002NB)
A0–A17
DQ0–DQ7
DOUT
Read
Write
L
L
H
X
X
H
X
H
L
H
H
H
H
H
L
AIN
AIN
X
L
DIN
CMOS Standby
VCC 0.5 V
X
X
H
X
High-Z
High-Z
High-Z
High-Z
TTL Standby
H
L
X
Output Disable
X
Reset (n/a on Am29F002NB)
X
X
Temporary Sector Unprotect
(See Note)
X
X
X
VID
X
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.ꢀ V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information. This function requires
the RESET# pin and is therefore not available on the Am29F002NB device.
sectors of memory), the system must drive WE# and
Requirements for Reading Array Data
To read array data from the outputs, the system must
CE# to V , and OE# to V .
IL
IH
drive the CE# and OE# pins to V . CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the Command Defini-
tions section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
IL
should remain at V .
IH
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the “Autoselect Mode” and
Autoselect Command Sequence sections for more
information.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
I
in the DC Characteristics table represents the
CC2
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
the timing waveforms. I
in the DC Characteristics
CC1
table represents the active current specification for
reading array data.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
8
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
Status” for more information, and to each AC Charac-
teristics section for timing diagrams.
RESET#: Hardware Reset Pin
Note: The RESET# pin is not available on the
Am29F002NB.
Standby Mode
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
drives the RESET# pin low for at least a period of t
,
RP
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
The device enters the CMOS standby mode when CE#
and RESET# pins (CE# only on the Am29F002NB) are
both held at V
± 0.5 V. (Note that this is a more
CC
restricted voltage range than V .) The device enters
IH
the TTL standby mode when CE# and RESET# pins
(CE# only on the Am29F002NB) are both held at V .
IH
Current is reduced for the duration of the RESET#
The device requires standard access time (t ) for read
CE
pulse. When RESET# is held at V , the device enters
IL
access when the device is in either of these standby
modes, before it is ready to read data.
the TTL standby mode; if RESET# is held at V
SS
0.5 V, the device enters the CMOS standby mode.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the AC Characteristics tables for RESET#
parameters and timing diagram.
In the DC Characteristics tables, I
standby current specification.
represents the
CC3
Output Disable Mode
When the OE# input is at V , output from the device is
IH
disabled. The output pins are placed in the high imped-
ance state.
Table 2. Am29F002B/Am29F002NB Top Boot Block Sector Address Table
Sector Size
(Kbytes)
Address Range
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
A17
0
A16
0
A15
X
A14
X
A13
X
(in hexadecimal)
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–37FFFh
38000h–39FFFh
3A000h–3BFFFh
3C000h–3FFFFh
64
64
64
32
8
0
1
X
X
X
1
0
X
X
X
1
1
0
X
X
1
1
1
0
0
1
1
1
0
1
8
1
1
1
1
X
16
November 1, 2006 21527D5
Am29F002B/Am29F002NB
9
D A T A S H E E T
Table 3. Am29F002B/Am29F002NB Bottom Boot Block Sector Address Table
Sector Size
(Kbytes)
Address Range
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
A17
0
A16
0
A15
0
A14
0
A13
X
(in hexadecimal)
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
16
8
0
0
0
1
0
0
0
0
1
1
8
0
0
1
X
X
32
64
64
64
0
1
X
X
X
1
0
X
X
X
1
1
X
X
X
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
the appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that
are don’t care. When all necessary bits have been set
as required, the programming equipment may then
read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
When using programming equipment, the autoselect
mode requires V on address pin A9. Address pins A6,
tions table. This method does not require V . See
ID
ID
A1, and A0 must be as shown in Autoselect Codes
(High Voltage Method) table. In addition, when verifying
sector protection, the sector address must appear on
“Command Definitions” for details on using the autose-
lect mode.
Table 4. Am29F002B/Am29F002NB Autoselect Codes (High Voltage Method)
A17 A12
to to
CE# OE# WE# A13 A10 A9
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
A6
A1
A0
Manufacturer ID: AMD
L
L
L
L
H
H
X
X
VID
X
X
L
X
X
L
L
01h
B0h
Device ID:
Am29F002B/Am29F002NB
(Top Boot Block)
X
X
VID
L
L
L
L
H
H
L
L
L
L
L
L
H
H
H
Device ID:
Am29F002B/Am29F002NB
(Bottom Boot Block)
X
X
X
VID
X
X
X
X
34h
01h
(protected)
Sector Protection Verification
L
L
H
SA
VID
L
H
L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
10
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
Sector protection/unprotection must be implemented
using programming equipment. The procedure
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
requires a high voltage (V ) on address pin A9 and the
ID
control pins. Details on this method are provided in the
supplements, publication numbers 20819
(Am29F002B) and 21183 (Am29F002NB). Contact an
AMD representative to obtain a copy of the appropriate
document.
spurious system level signals during V power-up and
CC
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
power-down transitions, or from system noise.
Low V
Write Inhibit
CC
When V
is less than V
, the device does not
LKO
CC
accept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
CC
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
device resets. Subsequent writes are ignored until V
CC
is greater than V
proper signals to the control pins to prevent uninten-
. The system must provide the
LKO
Temporary Sector Unprotect
Note: This feature requires the RESET# pin and is
tional writes when V is greater than V
.
CC
LKO
therefore not available on the Am29F002NB.
Write Pulse “Glitch” Protection
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
RESET# pin to V . During this mode, formerly pro-
ID
tected sectors can be programmed or erased by
Write cycles are inhibited by holding any one of OE# =
V , CE# = V or WE# = V . To initiate a write cycle,
selecting the sector addresses. Once V is removed
ID
IL
IH
IH
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algo-
rithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V and OE# = V during power up, the
IL
IH
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect
Completed (Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
November 1, 2006 21527D5
Am29F002B/Am29F002NB
11
D A T A S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the
improper sequence resets the device to reading array
data.
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase
Suspend).
Reading Array Data
Autoselect Command Sequence
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
mers and requires V on address bit A9.
ID
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the manu-
facturer code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector
address (SA) and the address 02h in returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to
the Sector Address tables for valid sector addresses.
The system must issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
12
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
DQ7 or DQ6. See “Write Operation Status” for informa-
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
tion on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. On the
Am29F002B only, note that a hardware reset during
the sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. On the
Am29F002B only, note that a hardware reset during
the sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
START
Write Program
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the
sector erase command sequence.
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
Programming
Completed
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
November 1, 2006 21527D5
Am29F002B/Am29F002NB
13
D A T A S H E E T
interrupts can be re-enabled after the last Sector Erase the Sector Erase Operations Timing diagram for timing
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
waveforms.
START
Write Erase
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Command Sequence
Data Poll
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. On the Am29F002B only, note that a hard-
ware reset during the sector erase operation
immediately terminates the operation. The Sector
Erase command sequence should be reinitiated once
the device has returned to reading array data, to
ensure data integrity.
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, or
DQ2. Refer to “Write Operation Status” for information
on these status bits.
Erasure Completed
Notes:
1. See the appropriate Command Definitions table for erase
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
14
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
system can use DQ7, or DQ6 and DQ2 together, to
Erase Suspend/Erase Resume Commands
determine if a sector is actively erasing or is erase-sus-
pended. See “Write Operation Status” for information
on these status bits.
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more
information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
November 1, 2006 21527D5
Am29F002B/Am29F002NB
15
D A T A S H E E T
Command Definitions
Table 5. Am29F002B/Am29F002NB Command Definitions
Bus Cycles (Notes 2–4)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data Addr Data Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
RA
XXX
555
RD
F0
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
01
B0
Device ID,
4
4
555
555
AA
AA
Top Boot Block
Auto-
select
Device ID,
2AA
2AA
55
55
555
555
90
90
X01
34
(Note 7) Bottom Boot Block
00
01
Sector Protect Verify
(Note 8)
(SA)
X02
4
555
AA
Program
4
6
6
1
1
555
555
AA
AA
AA
B0
30
2AA
2AA
2AA
55
55
55
555
555
555
A0
80
80
PA
PD
AA
AA
Chip Erase
555
555
2AA
2AA
55
55
555
SA
10
30
Sector Erase
555
Erase Suspend (Note 9)
Erase Resume (Note 10)
XXX
XXX
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17–A13 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
7. The fourth cycle of the autoselect command sequence is a
read cycle.
2. All values are in hexadecimal.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Address bits A17–A11 are don’t cares for unlock and
command cycles, except when PA or SA is required.
9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
ꢀ. No unlock or command cycles required when reading array
data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQꢀ goes
high (while the device is providing status data).
10. The Erase Resume command is valid only during the Erase
Suspend mode.
16
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 6 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 2 µs, then the device returns to reading
array data.
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.
Yes
DQ7 = Data?
No
PASS
FAIL
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQꢀ = “1” because
DQ7 may change simultaneously with DQꢀ.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data#
Polling Timings (During Embedded Algorithms) figure
in the “AC Characteristics” section illustrates this.
Figure 4. Data# Polling Algorithm
November 1, 2006 21527D5
Am29F002B/Am29F002NB
17
D A T A S H E E T
control the read cycles.) But DQ2 cannot distinguish
DQ6: Toggle Bit I
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. (The system may use either OE#
or CE# to control the read cycles.) When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 μs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences
between DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 5).
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
18
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
START
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
Read DQ7–DQ0
Read DQ7–DQ0
(Note 1)
No
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the
system can guarantee that the time between additional
sector erase commands will always be less than 50 μs.
See also the “Sector Erase Command Sequence”
section.
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 6 shows the outputs for DQ3.
(Notes
1, 2)
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQꢀ
changes to “1”. See text.
Figure 5. Toggle Bit Algorithm
November 1, 2006 21527D5
Am29F002B/Am29F002NB
19
D A T A S H E E T
Table 6. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 1)
DQ7#
0
DQ6
(Note 2)
DQ3
N/A
1
(Note 1)
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
0
No toggle
Toggle
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQꢀ switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQꢀ: Exceeded Timing Limits” for more information.
20
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
+0.8 V
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
–0.5 V
–2.0 V
Voltage with Respect to Ground
V
(Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
CC
A9, OE#, and
20 ns
RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Figure 6. Maximum Negative
Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.ꢀ V. During
voltage transitions, input or I/O pins may overshoot VSS to
–2.0 V for periods of up to 20 ns. See Figure 6. Maximum
DC voltage on input or I/O pins is VCC +0.ꢀ V. During
voltage transitions, input or I/O pins may overshoot to VCC
+2.0 V for periods up to 20 ns. See Figure 7.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.ꢀ V. During voltage transitions, A9, OE#, and
2.0 V
RESET# may overshoot VSS to –2.0 V for periods of up to
20 ns. See Figure 6. Maximum DC input voltage on pin A9
is +12.ꢀ V which may overshoot to +13.ꢀ V for periods up
to 20 ns. (RESET# is not available on Am29F002NB)
20 ns
20 ns
Figure 7. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C
A
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C
A
Extended (E) Devices
Ambient Temperature (T ) . . . . . . . . –55°C to +125°C
A
V
V
V
Supply Voltages
CC
CC
CC
for 5% devices. . . . . . . . . . .+4.75 V to +5.25 V
for 10% devices. . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
November 1, 2006 21527D5
Am29F002B/Am29F002NB
21
D A T A S H E E T
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Description
Input Load Current
A9, OE#, RESET# Input Load Current VCC = VCC max
Test Conditions
Min
Typ
Max
Unit
ILI
VIN = VSS to VCC, VCC = VCC max
±1.0
µA
;
ILIT
50
µA
(Notes 1, 5)
A9, OE#, RESET# = 12.5 V
VOUT = VSS to VCC, VCC = VCC max
CE# = VIL, OE# = VIH
ILO
ICC1
ICC2
ICC3
ICC4
VIL
Output Leakage Current
VCC Active Read Current (Notes 2, 3)
±1.0
30
40
1
µA
mA
mA
mA
mA
V
20
30
VCC Active Write Current (Notes 2, 4, 5) CE# = VIL, OE# = VIH
VCC Standby Current (Note 2)
VCC Reset Current (Notes 1, 2)
Input Low Voltage
CE#, OE# = VIH
RESET# = VIL
0.4
0.4
1
–0.5
2.0
0.8
VCC
+ 0.5
VIH
VID
Input High Voltage
V
V
Voltage for Autoselect and Temporary
Sector Unprotect
VCC = 5.0 V
11.5
12.5
0.45
VOL
VOH
VLKO
Output Low Voltage
IOL = 12 mA, VCC = VCC min
IOH = –2.5 mA, VCC = VCC min
V
V
V
Output High Voltage
Low VCC Lock-Out Voltage
2.4
3.2
4.2
Notes:
1. RESET# is not available on Am29F002NB.
2. Maximum ICC specifications are tested with VCC = VCCmax
.
3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
4. ICC active while Embedded Erase or Embedded Program is in progress.
ꢀ. Not 100% tested.
22
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
VIN = VSS to VCC
Min
Typ
Max
Unit
,
ILI
Input Load Current
±1.0
µA
VCC = VCC max
A9, OE#, RESET#
Input Load Current (Notes 1, 5) A9, OE#, RESET# = 12.5 V
VCC = VCC max
;
ILIT
50
±1.0
30
40
5
µA
µA
mA
mA
µA
µA
VOUT = VSS to VCC
VCC = VCC max
,
ILO
Output Leakage Current
VCC Active Read Current
(Notes 2, 3)
ICC1
ICC2
ICC3
ICC4
CE# = VIL, OE# = VIH
20
30
1
VCC Active Write Current
(Notes 2, 4, 5)
CE# = VIL, OE# = VIH
CE# = VCC ± 0.5 V
RESET# = VIL
VCC Standby Current
(Notes 2, 6)
VCC Reset Current
(Notes 1, 2, 6)
1
5
VIL
VIH
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
0.7 x VCC
VCC + 0.3
Voltage for Autoselect and
Temporary Sector Unprotect
VID
V
CC = 5.0 V
11.5
12.5
0.45
V
VOL
Output Low Voltage
IOL = 12 mA, VCC = VCC min
IOH = –2.5 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
V
V
VOH1
VOH2
VLKO
0.85 VCC
VCC–0.4
3.2
Output High Voltage
Low VCC Lock-Out Voltage
4.2
V
Notes:
1. RESET# is not available on Am29F002NB.
2. Maximum ICC specifications are tested with VCC = VCCmax
.
3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
4. ICC active while Embedded Erase or Embedded Program is in progress.
ꢀ. Not 100% tested.
6. ICC3 and ICC4 = 20 µA max at extended temperature (>+8ꢀ° C).
November 1, 2006 21527D5
Am29F002B/Am29F002NB
23
D A T A S H E E T
TEST CONDITIONS
Table 7. Test Specifications
All
5.0 V
Test Condition
-55
others
Unit
2.7 kΩ
Output Load
1 TTL gate
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
5
100
20
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
ns
V
0.0–3.0 0.45–2.4
Input timing measurement
reference levels
1.5
1.5
0.8, 2.0
0.8, 2.0
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
Figure 8. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
24
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
-55
-70
-90
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
55
55
70
90
90
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Address to Output Delay
Max
70
ns
tELQV
tGLQV
tEHQZ
tCE
tOE
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
55
30
15
70
30
20
90
35
20
ns
ns
ns
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z
(Note 1)
tGHQZ
tDF
tOEH
tOH
Max
Min
Min
15
20
0
20
ns
ns
ns
Read
Output Enable
Hold Time
(Note 1)
Toggle and
Data# Polling
10
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
tAXQX
Min
0
ns
Notes:
1. Not 100% tested.
2. See Table 7 and Figure 8 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
n/a Am29F002NB
Figure 9. Read Operations Timings
November 1, 2006 21527D5
Am29F002B/Am29F002NB
25
D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
tREADY
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
tREADY
500
ns
tRP
tRH
RESET# Pulse Width
Min
Min
500
50
ns
ns
RESET# High Time Before Read (See Note)
Note: Not 100% tested. RESET# is not available on Am29F002NB.
CE#, OE#
tRH
RESET#
n/a Am29F002NB
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
RESET#
n/a Am29F002NB
tRP
Figure 10. RESET# Timings
26
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
-55
-70
70
0
-90
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
55
90
tAVWL
tWLAX
tDVWH
tWHDX
ns
tAH
45
25
45
30
0
45
45
ns
tDS
ns
tDH
tOES
Data Hold Time
ns
Output Enable Setup Time
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHWL
tWHWH1
tWHWH2
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
0
0
ns
ns
CE# Hold Time
tWP
Write Pulse Width
Write Pulse Width High
30
35
20
7
45
ns
tWPH
ns
tWHWH1 Programming Operation (Note 2)
tWHWH2 Sector Erase Operation (Note 2)
µs
1
sec
µs
tVCS
VCC Setup Time (Note 1)
50
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
November 1, 2006 21527D5
Am29F002B/Am29F002NB
27
D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 11. Program Operation Timings
28
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
VCC
Complete
55h
30h
Progress
10 for Chip Erase
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (”see “Write Operation Status”).
Figure 12. Chip/Sector Erase Operation Timings
November 1, 2006 21527D5
Am29F002B/Am29F002NB
29
D A T A S H E E T
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
Complement
High Z
High Z
DQ7
Valid Data
Complement
Status Data
True
DQ0–DQ6
Valid Data
Status Data
True
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 13. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
30
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 15. DQ2 vs. DQ6
Temporary Sector Unprotect (Am29F002B only)
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
Figure 16. Temporary Sector Unprotect Timing Diagram (Am29F002B only)
November 1, 2006 21527D5
Am29F002B/Am29F002NB
31
D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
-55
-70
70
0
-90
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
55
90
tAVEL
ns
tELAX
tDVEH
tEHDX
tAH
45
25
45
30
0
45
45
ns
tDS
ns
tDH
Data Hold Time
ns
tOES
Output Enable Setup Time
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tWS
tWH
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
WE# Hold Time
tCP
CE# Pulse Width
30
35
20
7
45
ns
tEHEL
tCPH
CE# Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
ns
tWHWH1
tWHWH2
tWHWH1
tWHWH2
µs
1
sec
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
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Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of data written to device, DOUT = data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 17. Alternate CE# Controlled Write Operation Timings
November 1, 2006 21527D5
Am29F002B/Am29F002NB
33
D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
1
7
8
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
s
Byte Programming Time
Chip Programming Time (Note 3)
7
300
5.4
µs
s
Excludes system level
overhead (Note 5)
1.8
Notes:
1. Typical program and erase times assume the following conditions: 2ꢀ×C, ꢀ.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.ꢀ V (4.7ꢀ V for ꢀ% devices), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
ꢀ. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table ꢀ
for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = ꢀ.0 V, one pin at a time. RESET# not available on Am29F002NB.
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 2ꢀ°C, f = 1.0 MHz.
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Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
PLCC AND PDIP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Conditions
Typ
4
Max
6
Unit
pF
CIN
COUT
CIN2
VIN = 0
Output Capacitance
VOUT = 0
VPP = 0
8
12
12
pF
Control Pin Capacitance
8
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 2ꢀ°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
November 1, 2006 21527D5
Am29F002B/Am29F002NB
35
D A T A S H E E T
PHYSICAL DIMENSIONS
PD 032—32-Pin Plastic DIP
Dwg rev AD; 10/99
36
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
PHYSICAL DIMENSIONS (continued)
PL 032—32-Pin Plastic Leaded Chip Carrier
Dwg rev AH; 10/99
November 1, 2006 21527D5
Am29F002B/Am29F002NB
37
D A T A S H E E T
PHYSICAL DIMENSIONS (continued)
TS 032—32-Pin Standard Thin Small Package
Dwg rev AA; 10/99
38
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A S H E E T
REVISION SUMMARY
Physical Dimensions
Revision A (July 1998)
Replaced figures with more detailed illustrations.
Initial release.
Revision D (November 28, 2000)
Global
Revision B (January 1999)
Distinctive Characteristics
Added:
Added table of contents.
Ordering Information
■ 20-year data retention at 125°C
Deleted burn-in option.
— Reliable operation for the life of the system
AC Characterisitics—Read Operations Table
Table 5, Command Definitions
t
, t
: Changed the 55 speed option to 15 ns
In Note 4, changed the lower address bit of don’t care
range to A11.
EHQZ GHQZ
from 20 ns
AC Characteristics—Erase/Program Operations
Revision D +1 (November 5, 2004)
Ordering Information and Valid Combinations
Added Pb-Free options
t
t
t
: Changed the 90 speed option to 45 ns from 50 ns.
WLAX
DVWH
WLWH
: Changed the 55 speed option to 25 ns from 30 ns.
: changed the 55 speed option to 30 ns from 35 ns.
Revision D +2 (August 3, 2005)
Ordering Information and Valid Combinations
Added Pb-Free options
AC Characteristics—Alternate CE# Controlled
Erase/Program Operations
t
t
t
: Changed the 55 speed option to 25 ns from 30 ns.
DVEH
: Changed the 55 speed option to 30 ns from 35 ns.
ELEH
Revision D3 (December 13, 2005)
Global
: Changed the 90 speed option to 45 ns from 50 ns.
ELAX
DC Characteristics—TTL/NMOS Compatible
, I , I , I : Added Note 2 “Maximum I
Deleted 120 ns speed option.
I
CC1 CC2 CC3 CC4
CC
CC
Revision D4 (May 17, 2006)
Added “Not recommended for new designs” note.
specifications are tested with V = V
”.
CC
CCmax
DC Characteristics—CMOS Compatible
, I , I , I : Added Note 2 “Maximum I
I
Revision D5 (November 1, 2006)
Deleted “Not recommended for new designs” note.
CC1 CC2 CC3 CC4
specifications are tested with V = V
”.
CC
CCmax
Revision C (November 12, 1999)
AC Characteristics—Figure 11. Program
Operations Timing and Figure 12. Chip/Sector
Erase Operations
Deleted t
high.
and changed OE# waveform to start at
GHWL
November 1, 2006 21527D5
Am29F002B/Am29F002NB
39
D A T A S H E E T
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de-
vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea-
sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2006 Spansion Inc. All rights reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof, are
trademarks of Spansion Inc. Other company and product names used in this publication are for identification purposes only and may be trade-
marks of their respective companies.
Copyright © 1998–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade-
marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are
for identification purposes only and may be trademarks of their respective companies
40
Am29F002B/Am29F002NB
21527D5 November 1, 2006
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