A160CT15VC_技术文档

Am29SL160C

Data Sheet

The following document contains information on Spansion memory products. Although the document

is marked with the name of the company that originally developed the specification, Spansion will

continue to offer these products to existing customers.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 21635 Revision

C

Amendment

5

Issue Date January 23, 2007

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29SL160C

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 1.8 Volt-only Super Low Voltage Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

SOFTWARE FEATURES

■

Secured Silicon (SecSi) Sector: 256-byte sector

■

Supports Common Flash Memory Interface (CFI)

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

■

Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

■

Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

— Customer lockable: Customer may program own

custom data. Once locked, data cannot be changed

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

■

Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

HARDWARE FEATURES

Package options

— 48-ball FBGA

— 48-pin TSOP

■

Any combination of sectors can be erased

■

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■

Top or bottom boot block

Manufactured on 0.32 µm process technology

Compatible with JEDEC standards

■

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to reading array data

— Pinout and software compatible with single-power-

supply flash standard

WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect status

PERFORMANCE CHARACTERISTICS

■

High performance

— Access time as fast 100 ns

— Acceleration (ACC) function accelerates program

timing

— Program time: 8 µs/word typical using Accelerate

■

Sector protection

— Hardware method of locking a sector, either in-

system or using programming equipment, to prevent

any program or erase operation within that sector

■

Ultra low power consumption (typical values)

— 1 mA active read current at 1 MHz

— 5 mA active read current at 5 MHz

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

— 1 µA in standby or automatic sleep mode

■

Minimum 1 million erase cycles guaranteed per

sector

20 Year data retention at 125°C

— Reliable operation for the life of the system

Publication# 21635 Rev: C Amendment/5

Issue Date: January 23, 2007

This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may

be revised by subsequent versions or modifications due to changes in technical specifications.

D A T A S H E E T

GENERAL DESCRIPTION

The Am29SL160C is a 16 Mbit, 1.8 V volt-only Flash

memory organized as 2,097,152 bytes or 1,048,576

words. The data appears on DQ0–DQ15. The device is

offered in 48-pin TSOP and 48-ball FBGA packages.

The word-wide data (x16) appears on DQ15–DQ0; the

byte-wide (x8) data appears on DQ7–DQ0. This device is

designed to be programmed and erased in-system with a

single 1.8 volt V_CCsupply. No V_PPis required for program

or erase operations. The device can also be programmed

in standard EPROM programmers.

During erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

completes, the device is ready to read array data or

accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

The standard device offers access times of 90, 100,

120, or 150 ns, allowing microprocessors to operate

without wait states. To eliminate bus contention the

device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

Hardware data protection measures include a low

V

_CCdetector that automatically inhibits write operations

during power transitions. The hardware sector pro-

tection feature disables both program and erase

operations in any combination of the sectors of

memory. This is achieved in-system or via program-

ming equipment.

The device requires only a single 1.8 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor to

read the boot-up firmware from the Flash memory.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

The device offers two power-saving features. When

addresses are stable for a specified amount of time, the

device enters the automatic sleep mode. The system

can also place the device into the standby mode.

Power consumption is greatly reduced in both modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automati-

cally preprograms the array (if it is not already

programmed) before executing the erase operation.

2

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for FBGA Packages .................. 6

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Am29SL160C Device Bus Operations ...............................9

Word/Byte Configuration .......................................................... 9

Requirements for Reading Array Data ..................................... 9

Writing Commands/Command Sequences ............................ 10

Accelerated Program Operation ............................................. 10

Program and Erase Operation Status .................................... 10

Standby Mode ........................................................................ 10

Automatic Sleep Mode ........................................................... 10

RESET#: Hardware Reset Pin ............................................... 10

Output Disable Mode .............................................................. 11

Table 2. Am29SL160CT Top Boot Sector Architecture ..................12

Table 3. Am29SL160CB Bottom Boot Sector Architecture .............13

Autoselect Mode ..................................................................... 14

Table 4. Am29SL160C Autoselect Codes (High Voltage Method) ..14

Sector/Sector Block Protection and Unprotection .................. 15

Table 5. Top Boot Sector/Sector Block Addresses

Write Operation Status . . . . . . . . . . . . . . . . . . . . 27

DQ7: Data# Polling ................................................................. 27

Figure 5. Data# Polling Algorithm .................................................. 27

RY/BY#: Ready/Busy# ............................................................ 28

DQ6: Toggle Bit I .................................................................... 28

DQ2: Toggle Bit II ................................................................... 28

Reading Toggle Bits DQ6/DQ2 ............................................... 28

DQ5: Exceeded Timing Limits ................................................ 29

DQ3: Sector Erase Timer ....................................................... 29

Figure 6. Toggle Bit Algorithm........................................................ 29

Table 13. Write Operation Status ................................................... 30

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 31

Figure 7. Maximum Negative Overshoot Waveform ...................... 31

Figure 8. Maximum Positive Overshoot Waveform........................ 31

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 31

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic

Sleep Currents).............................................................................. 33

Figure 10. Typical I_CC1vs. Frequency............................................ 33

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 11. Test Setup..................................................................... 34

Table 14. Test Specifications ......................................................... 34

Figure 12. Input Waveforms and Measurement Levels ................. 34

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35

Read Operations .................................................................... 35

Figure 13. Read Operations Timings ............................................. 35

Hardware Reset (RESET#) .................................................... 36

Figure 14. RESET# Timings .......................................................... 36

Word/Byte Configuration (BYTE#) ........................................ 37

Figure 15. BYTE# Timings for Read Operations............................ 37

Figure 16. BYTE# Timings for Write Operations............................ 37

Erase/Program Operations ..................................................... 38

Figure 17. Program Operation Timings.......................................... 39

Figure 18. Chip/Sector Erase Operation Timings .......................... 40

Figure 19. Data# Polling Timings (During Embedded Algorithms). 41

Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 41

Figure 21. DQ2 vs. DQ6................................................................. 42

Figure 22. Temporary Sector Unprotect Timing Diagram .............. 42

Figure 23. Accelerated Program Timing Diagram.......................... 43

Figure 24. Sector Protect/Unprotect Timing Diagram .................... 43

Figure 25. Alternate CE# Controlled Write Operation Timings ...... 45

Erase And Programming Performance . . . . . . . 46

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 46

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 46

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 47

TS 048—48-Pin Standard TSOP ............................................ 47

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

for Protection/Unprotection .............................................................15

Table 6. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection ...........................................15

Write Protect (WP#) ................................................................ 16

Temporary Sector Unprotect .................................................. 16

Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 17

Figure 2. Temporary Sector Unprotect Operation........................... 18

Secured Silicon (SecSi) Sector Flash Memory Region .......... 18

Table 7. SecSi Sector Addresses ...................................................18

Hardware Data Protection ...................................................... 18

Common Flash Memory Interface (CFI). . . . . . . 19

Table 8. CFI Query Identification String ..........................................19

Table 9. System Interface String .....................................................20

Table 10. Device Geometry Definition ............................................20

Table 11. Primary Vendor-Specific Extended Query ......................21

Command Definitions . . . . . . . . . . . . . . . . . . . . . 21

Reading Array Data ................................................................ 21

Reset Command ..................................................................... 21

Autoselect Command Sequence ............................................ 22

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 22

Word/Byte Program Command Sequence ............................. 22

Figure 3. Program Operation .......................................................... 23

Chip Erase Command Sequence ........................................... 24

Sector Erase Command Sequence ........................................ 24

Erase Suspend/Erase Resume Commands ........................... 24

Figure 4. Erase Operation............................................................... 25

Command Definitions ............................................................. 26

Table 12. Am29SL160C Command Definitions ..............................26

8 x 9 mm package .................................................................. 48

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49

January 23, 2007 21635C5

Am29SL160C

3

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Family Part Number

Am29SL160C

Speed Options

-100

-120

120

50

-150

150

65

Max access time, ns (t_ACC

Max CE# access time, ns (t_CE

Max OE# access time, ns (t_OE

)

100

35

)

Note:See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

WP#/ACC

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A0–A19

4

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

A8

A19

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

WP#/ACC

RY/BY#

A18

A17

A7

Standard TSOP

A6

A5

A4

A3

A2

A1

January 23, 2007 21635C5

Am29SL160C

5

D A T A S H E E T

CONNECTION DIAGRAMS (Continued)

48-Ball FBGA

(Top View, Balls Facing Down)

A6

B6

C6

D6

E6

F6

G6

H6

V_SS

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

A19

DQ5

DQ12

V_CC

DQ4

A3 B3

C3

D3

E3

F3

G3

H3

RY/BY# WP#/ACC A18

NC

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

V_SS

CE#

OE#

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

Special Handling Instructions for FBGA

Packages

Special handling is required for Flash Memory products

in FBGA packages.

6

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

PIN CONFIGURATION

LOGIC SYMBOL

A0–A19

= 20 addresses

20

DQ0–DQ14 = 15 data inputs/outputs

A0–A19

16 or 8

DQ15/A-1

=

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

DQ0–DQ15

(A-1)

CE#

=

Chip enable

Output enable

Write enable

CE#

OE#

WE#

WP#/ACC

Hardware write protect/acceleration

WP#/ACC

RESET#

BYTE#

RY/BY#

RESET#

BYTE#

RY/BY#

V_CC

=

Hardware reset pin, active low

Selects 8-bit or 16-bit mode

Ready/Busy# output

1.8–2.2 V single power supply

Device ground

V_SS

NC

Pin not connected internally

January 23, 2007 21635C5

Am29SL160C

7

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29SL160C

T

-100

E

C

N

STANDARD PROCESSING

N = SecSi Sector factory-locked with random ESN

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

D = Commercial (0^oC to +70^oC) with Pb-free Package

F = Industrial (-40^oC to +85^oC) with Pb-free Package

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

WC = 48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 9 mm package (FBC048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29SL160C

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages

AM29SL160CT-100,

Valid Combinations for FBGA Packages

Order Number

Package Marking

AM29SL160CB-100

AM29SL160CT-100,

AM29SL160CB-100

A160CT10V,

A160CB10V

AM29SL160CT-120,

AM29SL160CB-120

EC, EI

ED, EF

WCC,

AM29SL160CT-120,

AM29SL160CB-120

WCI, A160CT12V,

WCD, A160CB12V

C, I,

D, F

AM29SL160CT-150,

AM29SL160CB-150

WCF

AM29SL160CT-150,

AM29SL160CB-150

A160CT15V,

A160CB15V

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

8

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus

operations, the inputs and control levels they require,

and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Am29SL160C Device Bus Operations

DQ8–DQ15

DQ0– BYTE# BYTE#

Addresses

(Note 1)

Operation

CE# OE# WE# RESET# WP#/ACC

DQ7

= V_IH

= V_IL

Read

Write

(Program/Erase)

L

H

X

A_IN

D_OUT

DQ8–DQ14 = High-Z,

DQ15 = A-1

L

H

L

H

(Note 3)

A_IN

D_IN

V_CC

0.2 V

V_CC

0.2 V

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect

(Note 2)

L

H

L

V_ID

X

D_IN

X

Sector Address,

(Note 3) A6 = H, A1 = H,

A0 = L

Sector Unprotect

(Note 2)

L

H

X

L

V_ID

D_IN

X

Temporary Sector

Unprotect

X

(Note 3)

A_IN

D_IN

High-Z

Legend:

L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 10 1.0 V, V_HH= 10 0.ꢀ V, X = Don’t Care, A_IN= Address In, D_IN= Data In,

D_OUT= Data Out

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = V_IH), A19:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector

Block Protection and Unprotection” on page 1ꢀ.

3. If WP#/ACC = V_IL, the two outermost boot sectors are protected. If WP#/ACC = V_IH, the two outermost boot sectors are

protected or unprotected as previously set by the system. If WP#/ACC = V_HH, all sectors, including the two outermost boot

sectors, are unprotected.

Word/Byte Configuration

Requirements for Reading Array Data

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

should remain at V_IH. The BYTE# pin determines

whether the device outputs array data in words or

bytes.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No

command is necessary in this mode to obtain array

January 23, 2007 21635C5

Am29SL160C

9

D A T A S H E E T

data. Standard microprocessor read cycles that assert

If the system asserts V_HHon the pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode and uses the higher voltage on the pin to reduce

the time required for program operations. The system

would use a two-cycle program command sequence as

required by the Unlock Bypass mode. Removing V_HH

from the WP#/ACC pin returns the device to normal

operation.

valid addresses on the device address inputs produce

valid data on the device data outputs. The device

remains enabled for read access until the command

register contents are altered.

See “Reading Array Data” on page 21 for more infor-

mation. Refer to the AC table for timing specifications

and to Figure 13, on page 35 for the timing diagram.

I_CC1in the DC Characteristics table represents the

active current specification for reading array data.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I_CC

read specifications apply. Refer to “Write Operation

Status” on page 27 for more information, and to “AC

Characteristics” on page 35 for timing diagrams.

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

Standby Mode

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” on page 9

for more information.

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are

required to program a word or byte, instead of four. The

“Word/Byte Program Command Sequence” on

page 22 contains details on programming data to the

device using both standard and Unlock Bypass

command sequences.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.2 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_CC± 0.2 V, the device is in the standby mode, but the

standby current is greater. The device requires stan-

dard access time (t_CE) for read access when the device

is in either of these standby modes, before it is ready to

read data.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2, on page 12 and

Table 3, on page 13 indicate the address space that

each sector occupies. A “sector address” consists of

the address bits required to uniquely select a sector.

The “Command Definitions” on page 21 contains

details on erasing a sector or the entire chip, or sus-

pending/resuming the erase operation.

The device also enters the standby mode when the

RESET# pin is driven low. Refer to “RESET#: Hard-

ware Reset Pin” on page 10.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

After the system writes the autoselect command

sequence, the device enters the autoselect mode. The

system can then read autoselect codes from the

internal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings apply

in this mode. Refer to “Autoselect Mode” on page 14

and “Autoselect Command Sequence” on page 22 for

more information.

I_CC3in the DC Characteristics table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC+ 50

ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address

access timings provide new data when addresses are

changed. While in sleep mode, output data is latched

and always available to the system. I_CC4in the DC

Characteristics table represents the automatic sleep

mode current specification.

I_CC2in the DC Characteristics table represents the

active current specification for the write mode. The “AC

Characteristics” on page 35 contains timing specifica-

tion tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operation

through the ACC function, which is one of two functions

provided by the WP#/ACC pin. This function is primarily

intended to allow faster in-system programming of the

device during the system production process.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the

10

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

RESET# pin is driven low for at least a period of t_RP, the

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the

RESET# pin returns to V_IH.

device immediately terminates any operation in

progress, tristates all output pins, and ignores all read/

write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to

reading array data. The operation that was interrupted

should be reinitiated once the device is ready to accept

another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.2 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS0.2 V, the standby current is

greater.

Refer to “AC Characteristics” on page 35 for RESET#

parameters and to “RESET# Timings” on page 36 for

the timing diagram.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

January 23, 2007 21635C5

Am29SL160C

11

D A T A S H E E T

Table 2. Am29SL160CT Top Boot Sector Architecture

Sector Address

Sector A19 A18 A17 A16 A15 A14 A13 A12 (Kbytes/Kwords)

Address Range (in Hexadecimal

Sector Size

Byte Mode (x8)

000000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–10FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

Word Mode (x16)

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

80000h–87FFFh

88000h–8FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

64/32

8/4

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

1A0000h–1AFFFFh D0000h–D7FFFh

1B0000h–1BFFFFh D8000h–DFFFFh

1C0000h–1CFFFFh E0000h–E7FFFh

1D0000h–1DFFFFh E8000h–EFFFFh

1E0000h–1EFFFFh

1F0000h–1F1FFFh

1F2000h–1F3FFFh

1F4000h–1F5FFFh

1F6000h–1F7FFFh

F0000h–F7FFFh

F8000h–F8FFFh

F9000h–F9FFFh

FA000h–FAFFFh

FB000h–FBFFFh

0

1

8/4

0

1

0

8/4

0

1

8/4

1

0

8/4

1F8000h–1F9FFFh FC0004–FCFFFh

1FA000h–1FBFFFh FD000h–FDFFFh

1FC000h–1DFFFFh FE000h–FEFFFh

1

0

1

8/4

1

0

8/4

1

8/4

1FE000h–1FFFFFh

FF000h–FFFFFh

Note: Address range is A19:A-1 in byte mode and A19:A0 in

word mode. See “Word/Byte Configuration” section for more

information.

12

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

Table 3. Am29SL160CB Bottom Boot Sector Architecture

Sector Address

Sector A19 A18 A17 A16 A15 A14 A13 A12 (Kbytes/Kwords)

Address Range (in hexadecimal)

Sector Size

Byte Mode (x8)

000000h–001FFFh

002000h–003FFFh

004000h–005FFFh

006000h–07FFFFh

008000h–009FFFh

00A000h–00BFFFh

00C000h–00DFFFh

00E000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–10FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

Word Mode (x16)

00000h–00FFFh

01000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–04FFFh

05000h–05FFFh

06000h–06FFFh

07000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

80000h–87FFFh

88000h–8FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8/4

SA2

0

1

0

8/4

SA3

0

1

8/4

SA4

1

0

8/4

SA5

1

0

1

8/4

SA6

1

0

8/4

SA7

1

8/4

SA8

X

64/32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

1A0000h–1AFFFFh D0000h–D7FFFh

1B0000h–1BFFFFh D8000h–DFFFFh

1C0000h–1CFFFFh E0000h–E7FFFh

1D0000h–1DFFFFh E8000h–EFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

F0000h–F7FFFh

F8000h–FFFFFh

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section for more information.

January 23, 2007 21635C5

Am29SL160C

13

D A T A S H E E T

must appear on the appropriate highest order address

Autoselect Mode

bits (see Tables 2 and 3). Table 4 shows the remaining

address bits that are don’t care. When all necessary

bits are set as required, the programming equipment

may then read the corresponding identifier code on

DQ7–DQ0.

The autoselect mode provides manufacturer and

device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 12, on page 26.

This method does not require V_ID. See “Command Def-

initions” on page 21 for details on using the autoselect

mode.

When using programming equipment, the autoselect

mode requires V_IDon address pin A9. Address pins A6,

A1, and A0 must be as shown in Table 4. In addition,

when verifying sector protection, the sector address

Table 4. Am29SL160C Autoselect Codes (High Voltage Method)

A19 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Description

A6

A1

Manufacturer ID: AMD

L

H

X

V_ID

X

L

X

L

X

01h

E4

Device ID:

Am29SL160CT

(Top Boot Block)

Word

Byte

Word

Byte

22h

X

V_ID

L

H

L

H

X

22h

X

E4

E7

Device ID:

Am29SL160CB

(Bottom Boot Block)

X

V_ID

X

H

L

01h

(protected)

X

Sector Protection Verification

L

H

SA

L

H

00h

(unprotected)

81h

(factory

locked)

SecSi Sector Indicator bit

(DQ7)

H

X

L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

Note: Outputs for data bits DQ8–DQ1ꢀ are for BYTE#=V_IH. DQ8–DQ1ꢀ are don’t care when BYTE#=V_IL.

14

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

Table 6. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector/Sector Block Protection and

Unprotection

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Table 5

and Table 6).

Sector / Sector

Block

A19–A12

Sector / Sector Block Size

SA38

11111XXX

64 Kbytes

11110XXX,

11101XXX,

11100XXX

SA37-SA35

192 (3x64) Kbytes

SA34-SA31

SA30-SA27

SA26-SA23

SA22-SA19

SA18-SA15

SA14-SA11

110XXXXX

101XXXXX

100XXXXX

011XXXXX

010XXXXX

001XXXXX

256 (4x64) Kbytes

Table 5. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection

Sector / Sector

Block

A19–A12

Sector / Sector Block Size

SA0

00000XXX

64 Kbytes

00001XXX,

00010XXX,

00011XXX

SA1-SA3

192 (3x64) Kbytes

00001XXX,

00010XXX,

00011XXX

SA10-SA8

192 (3x64) Kbytes

SA4-SA7

SA8-SA11

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

001XXXXX

010XXXXX

011XXXXX

100XXXXX

101XXXXX

110XXXXX

256 (4x64) Kbytes

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

00000111

00000110

00000101

00000100

00000011

00000010

00000001

00000000

8 Kbytes

11100XXX,

11101XXX,

11110XXX

SA28-SA30

192 (3x64) Kbytes

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

8 Kbytes

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection/unprotection is implemented

via two methods.

January 23, 2007 21635C5

Am29SL160C

15

D A T A S H E E T

The primary method requires V_IDon the RESET# pin

using the method described in “Sector/Sector Block

Protection and Unprotection” on page 15. The two out-

ermost 8 Kbyte boot sectors are the two sectors

containing the lowest addresses in a bottom-boot-con-

figured device, or the two sectors containing the

highest addresses in a top-boot-configured device.

only, and is implemented either in-system or via pro-

gramming equipment. Figure 1, on page 17 shows the

algorithms and Figure 24, on page 43 shows the timing

diagram. This method uses standard microprocessor

bus cycle timing. For sector unprotect, all unprotected

sectors must first be protected prior to the first sector

unprotect write cycle.

If the system asserts V_IHon the WP#/ACC pin, the

device reverts to whether the two outermost 8 Kbyte

boot sectors were last set to be protected or unpro-

tected. That is, sector protection or unprotection for

these two sectors depends on whether they were last

protected or unprotected using the method described

in “Sector/Sector Block Protection and Unprotection”

on page 15.

The alternate method intended only for programming

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices. Pub-

lication number 21622 contains further details. Contact

an AMD representative to request the document con-

taining further details.

Note that if the system asserts V_HHon the WP#/ACC

pin, all sectors, including the two outermost sectors,

are unprotected. V_HHis intended for accelerated in-

system programming of the device during system pro-

duction. It is advisable, therefore, not to assert V_HHon

this pin after the system has been placed in the field for

use. If faster programming is desired, the system may

use the unlock bypass program command sequence.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” on page 14 for

details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the

RESET# pin to V_ID. During this mode, formerly pro-

tected sectors can be programmed or erased by

selecting the sector addresses. Once V_IDis removed

from the RESET# pin, all the previously protected

sectors are protected again. Figure 2, on page 18

shows the algorithm, and Figure 22, on page 42 shows

the timing diagrams, for this feature.

Write Protect (WP#)

The write protect function provides a hardware method

of protecting certain boot sectors without using V_ID.

This function is one of two provided by the WP#/ACC

pin.

If the system asserts V_ILon the WP#/ACC pin, the

device disables program and erase functions in the two

“outermost” 8 Kbyte boot sectors independently of

whether those sectors were protected or unprotected

16

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 μs

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 1. In-System Sector Protect/Unprotect Algorithms

Am29SL160C

January 23, 2007 21635C5

17

D A T A S H E E T

on page 22). Table 7, on page 18 shows the layout for

the SecSi Sector.

START

Table 7. SecSi Sector Addresses

RESET# = V_ID

(Note 1)

Address Range

Description

Word Mode (x16) Byte Mode (x8)

16-byte random ESN

00–07h

08–7Fh

000–00Fh

010–0FFh

Perform Erase or

Program Operations

User-defined code or

factory erased (all 1s)

RESET# = V_IH

The device continues to read from the SecSi Sector

until the system issues the Exit SecSi Sector command

sequence, or until power is removed from the device.

On power-up, or following a hardware reset, the device

reverts to sending commands to the boot sectors.

Temporary Sector

Unprotect Completed

(Note 2)

Hardware Data Protection

Notes:

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 12, on

page 26 for command definitions). In addition, the fol-

lowing hardware data protection measures prevent

accidental erasure or programming, which might other-

wise be caused by spurious system level signals during

V_CCpower-up and power-down transitions, or from

system noise.

1. All protected sectors unprotected. (If WP#/ACC = V_IL,

the outermost sectors remain protected)

2. All previously protected sectors are protected once

again.

Figure 2. Temporary Sector Unprotect Operation

Secured Silicon (SecSi) Sector Flash

Memory Region

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not accept

any write cycles. This protects data during V_CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until V_CC

is greater than V_LKO. The system must provide the

proper signals to the control pins to prevent uninten-

The Secured Silicon (SecSi) Sector is a flash memory

region that enables permanent part identification

through an Electronic Serial Number (ESN). The SecSi

Sector in this device is 256 bytes in length. The device

contains a SecSi Sector indicator bit that allows the

system to determine whether or not the SecSi Sector

was factory locked. This indicator bit is permanently set

at the factory and cannot be changed, which prevents

a factory-locked part from being cloned.

tional writes when V_CCis greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

AMD offers this device only with the SecSi Sector

factory serialized and locked. The first sixteen bytes of

the SecSi Sector contain a random ESN. To utilize the

remainder SecSi Sector space, customers must

provide their code to AMD through AMD’s Express

Flash service. The factory will program and perma-

nently protect the SecSi Sector (in addition to

programming and protecting the remainder of the

device as required).

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

The system can read the SecSi Sector by writing the

Enter SecSi Sector command sequence (see “Enter

SecSi Sector/Exit SecSi Sector Command Sequence”

If WE# = CE# = V_ILand OE# = V_IHduring power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

18

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

given in Table 8, on page 19 to Table 11, on page 21.

To terminate reading CFI data, the system must write

the reset command.

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-indepen-

dent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Table 8, on page 19

to Table 11, on page 21. The system must write the

reset command to return the device to the autoselect

mode.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/products/nvd/over-

view/cfi.html. Alternatively, contact an AMD

representative for copies of these documents.

This device enters the CFI Query mode when the

system writes the CFI Query command, 98h, to

address 55h in word mode (or address AAh in byte

mode), any time the device is ready to read array data.

The system can read CFI information at the addresses

Table 8. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

January 23, 2007 21635C5

Am29SL160C

19

D A T A S H E E T

Table 9. System Interface String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

V_CCMin. (write/erase)

0018h

1Bh

1Ch

36h

38h

D7–D4: volt, D3–D0: 100 millivolt

V_CCMax. (write/erase)

0022h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 10. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

27h

4Eh

0015h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of bytes in multi-byte write = 2^N

(00h = not supported)

2Ch

58h

0002h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

001Eh

0000h

0001h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

20

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

Table 11. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0030h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock

0 = Required, 1 = Not Required

45h

46h

47h

48h

8Ah

8Ch

8Eh

90h

0000h

0002h

0001h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

49h

92h

0004h

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

Simultaneous Operation

00 = Not Supported, 01 = Supported

4Ah

4Bh

4Ch

94h

96h

98h

0000h

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” on page 24 for

more information on this mode.

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 12, on page 26 defines the valid reg-

ister command sequences. Writing incorrect address

and data values or writing them in the improper

sequence resets the device to reading array data.

The system must issue the reset command to re-

enable the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See “Reset Com-

mand”, next.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in “AC

Characteristics” on page 35.

See also “Requirements for Reading Array Data” on

page 9 for more information. The table provides the

read parameters, and Figure 13, on page 35 shows the

timing diagram.

Reading Array Data

Reset Command

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or

Embedded Erase algorithm.

Writing the reset command to the device resets the

device to reading array data. Address bits are don’t

care for this command.

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the device to reading

array data. Once erasure begins, however, the device

ignores reset commands until the operation is

complete.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The

system can read array data using the standard read

timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data. After completing a programming operation in the

The reset command may be written between the

sequence cycles in a program command sequence

January 23, 2007 21635C5

Am29SL160C

21

D A T A S H E E T

before programming begins. This resets the device to Flash Memory Region” on page 18 for further

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

information.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock

write cycles, followed by the program set-up command.

The program address and data are written next, which

in turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically generates the program

pulses and verifies the programmed cell margin.

Table 12, on page 26 shows the address and data

requirements for the byte program command

sequence.

The reset command may be written between the

sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to

reading array data (also applies during Erase

Suspend).

See “AC Characteristics” on page 35 for parameters, and

to Figure 14, on page 36 for the timing diagram.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

addresses are no longer latched. The system can

determine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

on page 27 for information on these status bits.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 12, on page 26 shows the address and data

requirements. This method is an alternative to that

shown in Table 4, on page 14, which is intended for

PROM programmers and requires V_IDon address bit

A9.

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The Byte Program command

sequence should be reinitiated once the device resets

to reading array data, to ensure data integrity.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence. A read cycle at address XX00h retrieves the

manufacturer code. A read cycle at address 01h in

word mode (or 02h in byte mode) returns the device

code. A read cycle containing a sector address (SA)

and the address 02h in word mode (or 04h in byte

mode) returns 01h if that sector is protected, or 00h if it

is unprotected. Refer to Table 2, on page 12 and

Table 3, on page 13 for valid sector addresses.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read shows that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to

program bytes or words to the device faster than using

the standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. The

device then enters the unlock bypass mode. A two-

cycle unlock bypass program command sequence is all

that is required to program in this mode. The first cycle

in this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 12, on page 26 shows the

requirements for the command sequence.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Enter SecSi Sector/Exit SecSi Sector Com-

mand Sequence

The SecSi Sector region provides a secured data area

containing a random, sixteen-byte electronic serial

number (ESN). The system can access the SecSi

Sector region by issuing the three-cycle Enter SecSi

Sector command sequence. The device continues to

access the SecSi Sector region until the system issues

the four-cycle Exit SecSi command sequence. The Exit

SecSi command sequence returns the device to

normal operation. Table 12, on page 26 shows the

address and data requirements for both command

sequences. See also “Secured Silicon (SecSi) Sector

22

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

data 90h; the second cycle the data 00h. Addresses

are don’t cares. The device then returns to reading

array data.

START

Write Program

Command Sequence

The device offers accelerated program operations

through the WP#/ACC pin. This function is intended

only to speed in-system programming of the device

during system production. When the system asserts

V_HHon the WP#/ACC pin, the device automatically

enters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that the

WP#/ACC pin must not be at V_HHfor any operation

other than accelerated programming, or device

damage may result. In addition, the WP#/ACC pin must

not be left floating or unconnected; inconsistent

behavior of the device may result.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Figure 3 illustrates the algorithm for the program oper-

ation. See “Erase/Program Operations” on page 38 for

parameters, and Figure 17, on page 39 for timing

diagrams.

Programming

Completed

Note: See Table 12, on page 26 for program command

sequence.

Figure 3. Program Operation

January 23, 2007 21635C5

Am29SL160C

23

D A T A S H E E T

be accepted, and erasure may begin. It is recom-

Chip Erase Command Sequence

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts are re-enabled after the last Sector Erase

command is written. If the time between additional

sector erase commands can be assumed to be less

than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Erase

Suspend during the time-out period resets the

device to reading array data. The system must

rewrite the command sequence and any additional

sector addresses and commands.

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 12, on

page 26 shows the address and data requirements for

the chip erase command sequence.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See “DQ3: Sector Erase

Timer” on page 29.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Any commands written to the chip during the

Embedded Erase algorithm are ignored. Note that a

hardware reset during the chip erase operation imme-

diately terminates the operation. The Chip Erase

command sequence should be reinitiated once the

device returns to reading array data, to ensure data

integrity.

Once the sector erase operation begins, only the Erase

Suspend command is valid. All other commands are

ignored. Note that a hardware reset during the sector

erase operation immediately terminates the operation.

The Sector Erase command sequence should be rein-

itiated once the device returns to reading array data, to

ensure data integrity.

The system can determine the status of the erase oper-

ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write

Operation Status” on page 27 for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data and

addresses are no longer latched.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. (Refer to “Write Operation Status” on

page 27 for information on these status bits.)

Figure 4, on page 25 illustrates the algorithm for the

erase operation. See “Erase/Program Operations” on

page 38 for parameters, and Figure 18, on page 40 for

timing diagrams.

Figure 4, on page 25 illustrates the algorithm for the

erase operation. Refer to the “Erase/Program Opera-

tions” on page 38 for parameters, and to Figure 18, on

page 40 for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 12, on page 26 shows the

address and data requirements for the sector erase

command sequence.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to

interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation.

Addresses are “don’t-cares” when writing the Erase

Suspend command.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of

sectors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might not

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

24

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

After the erase operation is suspended, the system can

Erase Suspend command can be written after the

device resumes erasing.

read array data from or program data to any sector not

selected for erasure. (The device “erase suspends” all

sectors selected for erasure.) Normal read and write

timings and command definitions apply. Reading at any

address within erase-suspended sectors produces

status data on DQ7–DQ0. The system can use DQ7, or

DQ6 and DQ2 together, to determine if a sector is

actively erasing or is erase-suspended. See “Write

Operation Status” on page 27 for information on these

status bits.

START

Write Erase

Command Sequence

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard program oper-

ation. See “Write Operation Status” on page 27 for

more information.

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

on page 22 for more information.

Data = FFH?

Yes

Erasure Completed

Notes:

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

1. See Table 12, on page 26 for erase command sequence.

2. See “DQ3: Sector Erase Timer” on page 29 for more in-

formation.

Figure 4. Erase Operation

January 23, 2007 21635C5

Am29SL160C

25

D A T A S H E E T

Command Definitions

Table 12. Am29SL160C Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Data Addr Data

Fifth

Sixth

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

AAA

RD

F0

Word

Manufacturer ID

Byte

2AA

555

4

AA

55

90

X00

X01

01

AAA

22E4/

22E7

Device ID

Word

555

2AA

555

(Top Boot/Bottom

4

AA

Boot)

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

AAA

555

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

PA

AAA

555

X02

X03

E4/E7

SecSi Sector Factory

Protect

4

3

4

3

AA

55

90

88

90

A0

20

AAA

555

AAA

555

X06

(SA)X02

(SA)X04

Sector Protect Verify

(Note 9)

AAA

555

AAA

555

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

AAA

555

AAA

555

XXX

PA

00

AAA

555

AAA

555

PD

AAA

555

AAA

555

Unlock Bypass

AAA

XXX

AAA

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

A0

90

PD

00

2

BA

555

AAA

555

AAA

BA

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

AAA

Word

Sector Erase

Byte

6

SA

AAA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

BA

Word

CFI Query (Note 14)

Byte

55

1

98

AA

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A19–A12 uniquely select any sector.

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

Notes:

1. See Table 1, on page 9 for description of bus operations.

9. The data is 00h for an unprotected sector and 01h for a protected

sector. Data bits DQ1ꢀ–DQ8 are don’t care. See the Autoselect

Command Sequence section for more information.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

10. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

4. Data bits DQ1ꢀ–DQ8 are don’t cares in byte mode.

11. The Unlock Bypass Reset command is required to return to the

read mode when in the unlock bypass mode.

ꢀ. Unless otherwise noted, address bits A19–A11 are don’t cares.

6. No unlock or command cycles required when in read mode.

12. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when in the autoselect mode, or if DQꢀ goes high (while providing

status information).

13. The Erase Resume command is valid only during the Erase

Suspend mode.

8. The fourth cycle of the autoselect command sequence is a read

cycle.

14. Command is valid when device is ready to read array data or

when device is in autoselect mode.

26

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a program or erase operation: DQ2, DQ3,

DQ5, DQ6, DQ7, and RY/BY#. Table 13, on page 30

and the following subsections describe the functions of

these bits. DQ7 and DQ6 each offer a method for deter-

mining whether a program or erase operation is

complete or in progress. The device also provides a

hardware-based output signal, RY/BY#, to determine

whether an embedded program or erase operation is in

progress or is completed.

page 41, Data# Polling Timings (During Embedded

Algorithms), in the “AC Characteristics” section illus-

trates this.

Table 13, on page 30 shows the outputs for Data#

Polling on DQ7. Figure 5, on page 27 shows the Data#

Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in progress

or completed, or whether the device is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command

sequence.

Read DQ7–DQ0

Addr = VA

Yes

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

information on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protected.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQꢀ = “1” because

DQ7 may change simultaneously with DQꢀ.

When the system detects DQ7 changes from the com-

plement to true data, it can read valid data at DQ7–

DQ0 on the following read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 19, on

Figure 5. Data# Polling Algorithm

January 23, 2007 21635C5

Am29SL160C

27

D A T A S H E E T

DQ6 also toggles during the erase-suspend-program

RY/BY#: Ready/Busy#

mode, and stops toggling once the Embedded

Program algorithm is complete.

RY/BY# is a dedicated, open-drain output pin that indi-

cates whether an Embedded Algorithm is in progress

or complete. The RY/BY# status is valid after the rising

edge of the final WE# pulse in the command sequence.

Since RY/BY# is an open-drain output, several RY/BY#

pins can be tied together in parallel with a pull-up

Table 13, on page 30 shows the outputs for Toggle Bit I

on DQ6. Figure 6, on page 29 shows the toggle bit

algorithm. Figure 20, on page 41 shows the toggle bit

timing diagrams. Figure 21, on page 42 shows the dif-

ferences between DQ2 and DQ6 in graphical form. See

also the subsection on “DQ2: Toggle Bit II”.

resistor to V_CC

.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence. The device toggles DQ2 with

each OE# or CE# read cycle.

Table 13, on page 30 shows the outputs for RY/BY#.

Figure 14, on page 36, Figure 17, on page 39 and

Figure 18, on page 40 shows RY/BY# for reset, pro-

gram, and erase operations, respectively.

DQ2 toggles when the system reads at addresses

within those sectors that were selected for erasure. But

DQ2 cannot distinguish whether the sector is actively

erasing or is erase-suspended. DQ6, by comparison,

indicates whether the device is actively erasing, or is in

Erase Suspend, but cannot distinguish which sectors

are selected for erasure. Thus, both status bits are

required for sector and mode information. Refer to

Table 13, on page 30 to compare outputs for DQ2 and

DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm

operation, successive read cycles to any address

cause DQ6 to toggle (The system may use either OE#

or CE# to control the read cycles). When the operation

is complete, DQ6 stops toggling.

Figure 6, on page 29 shows the toggle bit algorithm in

flowchart form, and the section “DQ2: Toggle Bit II”

explains the algorithm. See also the “DQ6: Toggle Bit I”

subsection. Figure 20, on page 41 shows the toggle bit

timing diagram. Figure 21, on page 42 shows the differ-

ences between DQ2 and DQ6 in graphical form.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 toggles

for approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are

protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6, on page 29 for the following discus-

sion. Whenever the system initially begins reading

toggle bit status, it must read DQ7–DQ0 at least twice

in a row to determine whether a toggle bit is toggling.

Typically, the system would note and store the value of

the toggle bit after the first read. After the second read,

the system would compare the new value of the toggle

bit with the first. If the toggle bit is not toggling, the

device completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling” on

page 27).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device successfully completed the

program or erase operation. If it is still toggling, the

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

28

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

device did not completed the operation successfully,

to and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted. Table 13,

on page 30 shows the outputs for DQ3.

and the system must write the reset command to return

to reading array data.

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 is not

high. The system may continue to monitor the toggle bit

and DQ5 through successive read cycles, determining

the status as described in the previous paragraph.

Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the begin-

ning of the algorithm when it returns to determine the

status of the operation (top of Figure 6).

START

Read DQ7–DQ0

(Note 1)

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

Read DQ7–DQ0

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation exceeds

the timing limits, DQ5 produces a “1.”

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

(Notes

1, 2)

Read DQ7–DQ0

Twice

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation began. (The sector erase timer does

not apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” If the time between additional sector

erase commands from the system are assumed to be

less than 50 μs, the system need not monitor DQ3. See

also the “Sector Erase Command Sequence” on

page 24.

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle

started; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device accepts additional sector erase

commands. To ensure the command is accepted, the

system software should check the status of DQ3 prior

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQꢀ

changes to “1”. See text.

Figure 6. Toggle Bit Algorithm

January 23, 2007 21635C5

Am29SL160C

29

D A T A S H E E T

Table 13. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend Reading within Non-Erase

Data

0

Data

N/A

Data

N/A

1

0

Mode

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQꢀ switches to ‘1’ when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See

“DQꢀ: Exceeded Timing Limits” on page 29 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

30

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

0.0 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V

_CC(Note 1). . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

A9, OE#,

and RESET# (Note 2) . . . . . . . .–0.5 V to +11.0 V

20 ns

All other pins (Note 1) . . . . . –0.5 V to V_CC+ 0.5 V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Figure 7. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.ꢀ V. During

voltage transitions, input or I/O pins may overshoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

DC voltage on input or I/O pins is V_CC+0.ꢀ V. During

voltage transitions, input or I/O pins may overshoot to V_CC

+2.0 V for periods up to 20 ns. See Figure 8.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.ꢀ V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot V_SSto –2.0

V for periods of up to 20 ns. See Figure 7. Maximum DC

input voltage on pin A9 is +11.0 V which may overshoot to

+12.ꢀ V for periods up to 20 ns. Maximum DC input

voltage on pin WP#/ACC is +10.0 V which may overshoot

to +11.ꢀ V for periods up to 20 ns.

2.0 V

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

V_CCSupply Voltages

V

_CC, all speed options . . . . . . . . . . . .+1.8 V to +2.2 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

January 23, 2007 21635C5

Am29SL160C

31

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Conditions

V_IN= V_SSto V_CC

Min

Typ

Max

±1.0

35

Unit

µA

,

I_LI

Input Load Current

V_CC= V_{CC max}

I_LIT

I_LO

A9 Input Load Current

Output Leakage Current

V_CC= V_{CC max}; A9 = 11.0 V

µA

V_OUT= V_SSto V_CC

,

±1.0

µA

V_CC= V_{CC max}

5 MHz

1 MHz

5 MHz

1 MHz

5

1

5

1

10

3

CE# = V_IL,OE# ₌V_IH,

Byte Mode

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

10

3

CE# = V_IL,OE# ₌V_IH,

Word Mode

V_CCActive Write Current

(Notes 2, 3, 5)

I_CC2

CE# = V_IL,OE# ₌V_IH

20

30

mA

I_CC3

I_CC4

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE#, RESET# = V_CC±0.2 V

RESET# = V_SS± 0.2 V

1

5

µA

Automatic Sleep Mode

(Notes 2, 3)

V_IH= V_CC± 0.2 V;

V_IL= V_SS± 0.2 V

I_CC5

1

5

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.5

0.2 x V_CC

V_CC+ 0.3

V

0.8 x V_CC

Voltage for WP#/ACC Sector

Protect/Unprotect and Program

Acceleration

V_HH

8.5

9.0

9.5

V

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V_CC= 2.0 V

11.0

0.1

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 100 μA, V_CC= V_{CC min}

I_OH= –100 μA, V_CC= V_{CC min}

V_CC–0.1

1.2

Low V_CCLock-Out Voltage

(Note 4)

V_LKO

1.5

V

Notes:

1. The I_CCcurrent listed is typically less than 1 mA/MHz, with OE# at V_IL. Typical V_CCis 2.0 V.

2. The maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ ꢀ0 ns.

ꢀ. Not 100% tested.

32

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

DC CHARACTERISTICS (Continued)

Zero Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

10

8

2.2 V

6

4

1.8 V

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 2ꢀ °C

Figure 10. Typical I_CC1vs. Frequency

January 23, 2007 21635C5

Am29SL160C

33

D A T A S H E E T

TEST CONDITIONS

Table 14. Test Specifications

-120,

Test Condition

-100

-150

Unit

Output Load

1 TTL gate

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

100

pF

C

L

Input Rise and Fall Times

Input Pulse Levels

5

0.0–2.0

ns

V

Input timing measurement

reference levels

1.0

V

Output timing measurement

reference levels

Figure 11. Test Setup

Key To Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

2.0 V

0.0 V

1.0 V

Input

Measurement Level

Output

Figure 12. Input Waveforms and Measurement Levels

34

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

Read Operations

Parameter

Speed Option

JEDEC

Std

Description

Test Setup

-100

-120

-150

Unit

t_AVAV

t_RC

Read Cycle Time (Note 1)

Address to Output Delay

Min

100

120

150

ns

CE# = V_IL

OE# = V_IL

t_AVQV

t_ACC

Max

120

ns

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_CE

t_OE

t_DF

Chip Enable to Output Delay

OE# = V_IL

Max

Min

100

35

120

50

16

0

150

65

ns

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

Read

Output Enable

Hold Time (Note 1)

t_OEH

Toggle and

Data# Polling

Min

30

0

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1)

t_AXQX

t_OH

Notes:

1. Not 100% tested.

2. See Figure 11, on page 34 and Table 14, on page 34 for

test specifications.

.

t_RC

Addresses Stable

Addresses

t_ACC

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operations Timings

January 23, 2007 21635C5

Am29SL160C

35

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

Max

All Speed Options

Unit

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (see Note)

t_READY

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (see Note)

t_READY

Max

500

ns

t_RP

t_RH

t_RB

RESET# Pulse Width

Min

500

200

0

ns

RESET# High Time Before Read (see Note)

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. RESET# Timings

36

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

t_{ELFL/ ELFH}

t_FLQZ

Description

CE# to BYTE# Switching Low or High

-100

-120

10

-150

Unit

ns

t

Max

Min

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

50

60

ns

t_FHQV

100

120

150

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

Switching

DQ0–DQ14

from word

to byte

Address

Input

DQ15

Output

mode

DQ15/A-1

BYTE#

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t_FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 16. BYTE# Timings for Write Operations

Am29SL160C

January 23, 2007 21635C5

37

D A T A S H E E T

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

Write Cycle Time (Note 1)

-100

-120

120

0

-150

Unit

ns

Min

100

150

t_AVWL

t_WLAX

t_DVWH

t_WHDX

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

ns

t_AH

50

60

0

70

ns

t_DS

ns

t_DH

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHWL

t_CS

t_CH

CE# Setup Time

Min

Typ

0

ns

CE# Hold Time

0

t_WP

Write Pulse Width

Write Pulse Width High

50

60

30

10

12

70

t_WPH

Byte

Programming Operation (Notes 1, 2)

µs

Word

t_WHWH1

Accelerated Program Operation, Byte or Word

(Note 2)

Typ

8

t_WHWH2

t_WHWH2Sector Erase Operation (Notes 1, 2)

Typ

Min

Max

2

50

0

sec

µs

t_VCS

t_RB

V_CCSetup Time

Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

200

ns

Notes:

1. Not 100% tested.

2. See “Erase And Programming Performance” on page 46 for more information.

38

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

January 23, 2007 21635C5

Am29SL160C

39

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

40

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

Complement

High Z

DQ7

Valid Data

Complement

Status Data

True

DQ0–DQ6

Valid Data

Status Data

True

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

January 23, 2007 21635C5

Am29SL160C

41

D A T A S H E E T

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 21. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

V_IDRise and Fall Time

All Speed Options

Unit

ns

Min

500

V_HHRise and Fall Time

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

V_ID

RESET#

0 or 1.8 V

t_VIDR

0 or 1.8 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 22. Temporary Sector Unprotect Timing Diagram

42

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

V_HH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 23. Accelerated Program Timing Diagram

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

60h 60h

Valid*

Verify

40h

Data

Status

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 24. Sector Protect/Unprotect Timing Diagram

January 23, 2007 21635C5

Am29SL160C

43

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

Write Cycle Time (Note 1)

-100

-120

120

0

-150

Unit

ns

Min

100

150

t_AVEL

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

ns

t_ELAX

t_AH

50

60

0

70

ns

t_DVEH

t_EHDX

t_DS

ns

t_DH

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

0

CE# Pulse Width

CE# Pulse Width High

50

60

30

10

12

70

t_CPH

Byte

Programming Operation

(Notes 1, 2)

µs

Word

t_WHWH1

Accelerated Program Operation, Byte or Word

(Note 2)

Typ

8

2

µs

t_WHWH2

Notes:

t_WHWH2

Sector Erase Operation (Notes 1, 2)

sec

1. Not 100% tested.

2. See “Erase And Programming Performance” on page 46 for more information.

44

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written, D_OUT= data written

2. Figure indicates the last two bus cycles of command sequence.

3. Word mode address used as an example.

Figure 25. Alternate CE# Controlled Write Operation Timings

January 23, 2007 21635C5

Am29SL160C

45

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

s

Comments

Sector Erase Time

2

15

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

70

10

12

8

s

Byte Programming Time

Word Programming Time

Accelerated Program Time, Word/Byte

300

360

240

160

120

µs

s

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

20

14

Chip Programming Time

(Note 3)

s

Notes:

1. Typical program and erase times assume the following conditions: 2ꢀ°C, 2.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 1.8 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

ꢀ. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 12, on page 26 for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

11.0 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–0.5 V

V_CC+ 0.5 V

+100 mA

–100 mA

Includes all pins except V_CC. Test conditions: V_CC= 1.8 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 2ꢀ°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

46

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic Space Centering.

January 23, 2007 21635C5

Am29SL160C

47

D A T A S H E E T

PHYSICAL DIMENSIONS

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

8 x 9 mm package

Dwg rev AF; 10/99

48

Am29SL160C

21635C5 January 23, 2007

D A T A S H E E T

REVISION SUMMARY

Revision A (December 1998)

Revision A+5 (July 23, 1999)

Initial release.

Global

Added 90 ns speed option.

Revision A+1 (January 1999)

Revision A+6 (September 1, 1999)

Distinctive Characteristics

WP#/ACC pin: In the third subbullet, deleted reference

AC Characteristics

to increased erase performance.

Hardware Reset (RESET#) table: Deleted t_RPDspecifi-

cation. Erase/Program Operations table: Deleted t_OES

specification.

Device Bus Operations

Accelerated Program and Erase Operations: Deleted

all references to accelerated erase.

Revision A+7 (September 7, 1999)

Sector/Sector Block Protection and Unprotection:

Changed section name and text to include tables and

references to sector block protection and unprotection.

Distinctive Characteristics

Ultra low power consumption bullet: Corrected values

to match those in the DC Characteristics table.

AC Characteristics

Accelerated Program Timing Diagram: Deleted refer-

ence in title to accelerated erase.

Alternate CE# Controlled Erase/Program Operations:

Deleted t_OESspecification.

Revision A+2 (March 23, 1999)

Connection Diagrams

Revision B (December 14, 1999)

AC Characteristics—Figure 17. Program

Operations Timing and Figure 18. Chip/Sector

Erase Operations

Corrected the TSOP pinout on pins 13 and 14.

Revision A+3 (April 12, 1999)

Global

Deleted t_GHWLand changed OE# waveform to start at

high.

Modified the description of accelerated programming to

emphasize that it is intended only to speed in-system

programming of the device during the system produc-

tion process.

Physical Dimensions

Replaced figures with more detailed illustrations.

Revision C (February 21, 2000)

Distinctive Characteristics

Removed “Advance Information” designation from data

sheet. Data sheet parameters are now stable; only

speed, package, and temperature range combinations

are expected to change in future revisions.

Secured Silicon (SecSi) Sector bullet: Added the 8-byte

unique serial number to description.

Device Bus Operations table

Modified Note 3 to indicate sector protection behavior

when V_IHis asserted on WP#/ACC. Applied Note 3 to

the WP#/ACC column for write operations.

Device Bus Operations table

Changed standby voltage specification to V_CC0.2 V.

Standby Mode

Ordering Information

Changed standby voltage specification to V_CC0.2 V.

Added the “N” designator to the optional processing

section.

DC Characteristics table

Changed test conditions for I_CC3, I_CC4, I_CC5to V_CC0.2

V.

Secured Silicon (SecSi) Sector Flash Memory

Region

Modified explanatory text to indicate that devices now

have an 8-byte unique ESN in addition to the 16-byte

random ESN. Added table for address range

clarification.

Revision C+1 (November 14, 2000)

Global

Added dash to speed options and OPNs. Added table

of contents.

Revision A+4 (May 14, 1999)

Global

AC Characteristics—Read Operations

Changed t_DFto 16 ns for all speeds.

Deleted all references to the unique ESN.

January 23, 2007 21635C5

Am29SL160C

49

D A T A S H E E T

Valid Combinations for FBGA Packages

Revision C+2 (June 11, 2002)

Added WCD, and WCF to Order Number column, and

added D, and F to Package Marking column.

Secured Silicon (SecSi) Sector Flash Memory

Region

Deleted reference to A-1 not being used in addressing,

and to address bits that are don’t cares. In Table 7,

changed lower address bit for user-defined code to 08h

(word mode) and 010h (byte mode).

Revision C4 (July 13, 2005)

Global

Deleted 90 ns speed option.

Ordering Information

Revision C+3 (November 1, 2004)

Global

Deleted options for extended temperature range in Pb-

free packages.

Added colophon and reference links.

Revision C5 (January 23, 2007)

Erase and Program Operations table

Changed t_BUSYto a maximum specification.

Ordering Information

Added temperature ranges for Pb-free Package

Valid Combinations for TSOP Packages

Added ED, and EF combinations.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are

for identification purposes only and may be trademarks of their respective companies.

thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

50

Am29SL160C

21635C5 January 23, 2007


型号：	A160CT15VC
厂家：	AMD
描述：	16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory 16兆位（2M ×8位/ 1的M× 16位） CMOS 1.8伏只超低电压闪存闪存
文件：	总52页 (文件大小：1031K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A160CT15VC [AMD]

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