28F256_技术文档

FINAL

Am28F256

256 Kilobit (32 K x 8-Bit)

CMOS 12.0 Volt, Bulk Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

■ High performance

■ Latch-up protected to 100 mA

from –1 V to V +1 V

CC

— 70 ns maximum access time

■ Flasherase Electrical Bulk Chip-Erase

■ CMOS Low power consumption

— 30 mA maximum active current

— 100 µA maximum standby current

— No data retention power consumption

— One second typical chip-erase

■ Flashrite Programming

— 10 µs typical byte-program

— 0.5 second typical chip program

■ Compatible with JEDEC-standard byte-wide

■ Command register architecture for

microprocessor/microcontroller compatible

write interface

32-Pin EPROM pinouts

— 32-pin PDIP

— 32-pin PLCC

■ On-chip address and data latches

— 32-pin TSOP

■ Advanced CMOS flash memory technology

— Low cost single transistor memory cell

■ Automatic write/erase pulse stop timer

■ 10,000 write/erase cycles minimum

■ Write and erase voltage 12.0 V ±5%

GENERAL DESCRIPTION

The Am28F256 is a 256 K Flash memory organized as

32 Kbytes of 8 bits each. AMD’s Flash memories offer

the most cost-effective and reliable read/write non-

volatile random access memory. The Am28F256 is

packaged in 32-pin PDIP, PLCC, and TSOP versions. It

is designed to be reprogrammed and erased in-system

or in standard EPROM programmers. The Am28F256

is erased when shipped from the factory.

The AMD cell is designed to optimize the erase and

programming mechanisms. In addition, the combina-

tion of advanced tunnel oxide processing and low

internal electric fields for erase and programming

operations produces reliable cycling. The Am28F256

uses a 12.0V±5% V

high voltage input to perform

PP

the Flasherase and Flashrite algorithms.

The highest degree of latch-up protection is achieved

with AMD’s proprietary non-epi process. Latch-up

protection is provided for stresses up to 100 milliamps

The standard Am28F256 offers access times as fast as

70 ns, allowing operation of high-speed microproces-

sors without wait states. To eliminate bus contention,

on address and data pins from –1 V to V

+1 V.

CC

#

the Am28F256 has separate chip enable (CE ) and

The Am28F256 is byte programmable using 10 µs

programming pulses in accordance with AMD’s

Flashrite programming algorithm. The typical room

temperature programming time of the Am28F256 is a

half a second. The entire chip is bulk erased using

10 ms erase pulses according to AMD’s Flasherase

alrogithm. Typical erasure at room temperature is

accomplished in less than one second. The windowed

package and the 15-20 minutes required for EPROM

erasure using ultra-violet light are eliminated.

#

output enable (OE ) controls.

AMD’s Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

Am28F256 uses a command register to manage this

functionality, while maintaining a standard JEDEC

Flash Standard 32-pin pinout. The command register

allows for 100% TTL level control inputs and fixed

power supply levels during erase and programming.

AMD’s Flash technology reliably stores memory

contents even after 10,000 erase and program cycles.

Publication# 11560 Rev: G Amendment/+2

Issue Date: January 1998

#

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as inputs to an internal state-machine which

controls the erase and programming circuitry. During

write cycles, the command register internally latches ad-

dress and data needed for the programming and erase

operations. For system design simplification, the

lowing discussion, the WE pin is used as the write cycle

control pin throughout the rest of this text. All setup and

hold times are with respect to the WE signal.

#

AMD’s Flash technology combines years of EPROM

and EEPROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The

Am28F256 electrically erases all bits simultaneously

using Fowler-Nordheim tunneling. The bytes are

programmed one byte at a time using the EPROM

programming mechanism of hot electron injection.

#

Am28F256 is designed to support either WE or CE

controlled writes. During a system write cycle, ad-

#

dresses are latched on the falling edge of WE or CE

whichever occurs last. Data is latched on the rising edge

#

of WE or CE whichever occurs first. To simplify the fol-

BLOCK DIAGRAM

DQ0–DQ7

V

CC

V

SS

Erase

Voltage

Switch

Input/Output

Buffers

V

PP

To Array

State

WE#

Control

Program

Voltage

Switch

Command

Register

Chip Enable

Output Enable

Logic

CE#

OE#

Data

Latch

Low V

Detector

CC

Y-Gating

Y-Decoder

Program/Erase

Pulse Timer

Address

Latch

262,144

Bit

X-Decoder

A0–A14

Cell Matrix

11560F-1

PRODUCT SELECTOR GUIDE

Family Part Number

Am28F256

-120

Speed Options (V

= 5.0 V 10%)

±

-70

70

35

-90

90

35

-150

150

55

-200

200

55

CC

Max Access Time (ns)

CE# (E#) Access (ns)

OE# (G#) Access (ns)

120

50

2

Am28F256

CONNECTION DIAGRAMS

PDIP

PLCC

V

1

2

3

32

31

V

CC

PP

NC

WE# (W#)

NC

30

29

28

27

A12

A7

A14

4

5

3

4

31 30

1 32

2

A13

A7

A6

5

6

A14

A13

29

28

A6

A5

A8

6

7

8

9

A5

A4

7

A8

A9

27

26

25

24

23

22

21

26

25

8

A9

A11

A4

A3

A2

A3

9

A11

OE# (G#)

A10

24

23

22

21

A2

10

11

12

13

OE# (G#)

A10

10

11

12

A1

CE# (E#)

DQ7

A1

A0

CE# (E#)

DQ7

DQ0

DQ6

DQ5

13

14

15

16

20

16 17

19 20

18

15

14

DQ1

DQ2

19

18

17

DQ4

DQ3

V

SS

11560F-3

11560F-2

Note: Pin 1 is marked for orientation.

Am28F256

3

CONNECTION DIAGRAMS (continued)

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

A11

A9

A8

A13

A14

NC

OE#

A10

CE#

D7

D6

D5

WE#

D4

D3

V

CC

9

V

PP

SS

10

11

12

13

14

15

16

NC

A12

A7

A6

A5

D2

D1

D0

A0

A1

A2

A3

A4

32-Pin TSOP—Standard Pinout

OE#

A10

CE#

D7

D6

D5

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

A11

A9

A8

A13

A14

NC

D4

D3

WE#

V

CC

PP

V

9

SS

D2

D1

D0

A0

A1

A2

A3

10

11

12

13

14

15

16

NC

A12

A7

A6

A5

A4

32-Pin TSOP—Reverse Pinout

11560G-4

LOGIC SYMBOL

15

A0–A14

8

DQ0–DQ7

CE# (E#)

OE# (G#)

WE# (W#)

11560F-5

4

Am28F256

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of:

AM28F256

-70

J

C

B

OPTIONAL PROCESSING

Blank = Standard Processing

B

= Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am28F256

256 Kilobit (32 K x 8-Bit) CMOS Flash Memory

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

AM28F256-70

PC, PI, PE,

AM28F256-90

AM28F256-120

AM28F256-150

AM28F256-200

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

Am28F256

5

PIN DESCRIPTION

A0–A14

V_CC

Address Inputs for memory locations. Internal latches

hold addresses during write cycles.

Power supply for device operation. (5.0 V ± 5% or 10%)

V_PP

#

CE (E )

Program voltage input. V

must be at high voltage in

PP

Chip Enable active low input activates the chip’s control

logic and input buffers. Chip Enable high will deselect

the device and operates the chip in stand-by mode.

order to write to the command register. The command

register controls all functions required to alter the

memory array contents. Memory contents cannot be

altered when V_PP≤ V_CC+2 V.

DQ0–DQ7

V_SS

Data Inputs during memory write cycles. Internal

latches hold data during write cycles. Data Outputs

during memory read cycles.

Ground

#

WE (W )

NC

Write Enable active low input controls the write function

of the command register to the memory array. The

target address is latched on the falling edge of the

Write Enable pulse and the appropriate data is latched

on the rising edge of the pulse. Write Enable high

inhibits writing to the device.

No Connect-corresponding pin is not connected

internally to the die.

#

OE (G )

Output Enable active low input gates the outputs of the

device through the data buffers during memory

read cycles. Output Enable is high during command

sequencing and program/erase operations.

6

Am28F256

BASIC PRINCIPLES

The device uses 100% TTL-level control inputs to

manage the command register. Erase and repro-

gramming operations use a fixed 12.0 V ± 5% high

voltage input.

formation must be supplied with the Erase-verify

command. This command verifies the margin and

outputs the addressed byte in order to compare the

array data with FFh data (Byte erased).

After successful data verification the Erase-verify

command is written again with new address infor-

mation. Each byte of the array is sequentially veri-

fied in this manner.

Read Only Memory

Without high V_PPvoltage, the device functions as a

read only memory and operates like a standard

EPROM. The control inputs still manage traditional

read, standby, output disable, and Auto select modes.

If data of the addressed location is not verified, the

Erase sequence is repeated until the entire array is

successfully verified or the sequence is repeated

1000 times.

Command Register

The command register is enabled only when high volt-

age is applied to the V

pin. The erase and repro-

Flashrite Programming Sequence

PP

gramming operations are only accessed via the

register. In addition, two-cycle commands are required

for erase and reprogramming operations. The tradi-

tional read, standby, output disable, and Auto select

modes are available via the register.

A three step command sequence (a two-cycle Program

command and one cycle Verify command) is required

to program a byte of the Flash array. Refer to the Flash-

rite Algorithm.

1. Program Setup: Write the Setup Program com-

The device’s command register is written using stan-

dard microprocessor write timings. The register con-

trols an internal state machine that manages all device

operations. For system design simplification, the de-

vice is designed to support either WE# or CE# con-

trolled writes. During a system write cycle, addresses

are latched on the falling edge of WE# or CE# which-

ever occurs last. Data is latched on the rising edge of

WE# or CE# whichever occur first. To simplify the fol-

lowing discussion, the WE# pin is used as the write

cycle control pin throughout the rest of this text. All

setup and hold times are with respect to the WE# sig-

nal.

mand to the command register.

2. Program: Write the Program command to the com-

mand register with the appropriate Address and

Data. The system software routines must now time-

out the program pulse width (10 µs) prior to issuing

the Program-verify command. An integrated stop

timer prevents any possibility of overprogramming.

3. Program-Verify: Write the Program-verify com-

mand to the command register. This command ter-

minates the programming operation. In addition,

this command verifies the margin and outputs the

byte just programmed in order to compare the array

data with the original data programmed. After suc-

cessful data verification, the programming se-

quence is initiated again for the next byte address to

be programmed.

Overview of Erase/Program Operations

Flasherase™ Sequence

A multiple step command sequence is required to

erase the Flash device (a two-cycle Erase command

and repeated one cycle verify commands).

If data is not verified successfully, the Program se-

quence is repeated until a successful comparison is

verified or the sequence is repeated 25 times.

Note: The Flash memory array must be completely

programmed to 0’s prior to erasure. Refer to the

Flashrite™ Programming Algorithm.

Data Protection

The device is designed to offer protection against acci-

dental erasure or programming caused by spurious

system level signals that may exist during power transi-

tions. The device powers up in its read only state. Also,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences.

1. Erase Setup: Write the Setup Erase command to

the command register.

2. Erase: Write the Erase command (same as Setup

Erase command) to the command register again.

The second command initiates the erase operation.

The system software routines must now time-out

the erase pulse width (10 ms) prior to issuing the

Erase-verify command. An integrated stop timer

prevents any possibility of overerasure.

The device also incorporates several features to pre-

vent inadvertent write cycles resulting fromV_CCpower-

up and power-down transitions or system noise.

3. Erase-Verify: Write the Erase-verify command to

the command register. This command terminates

the erase operation. After the erase operation,

each byte of the array must be verified. Address in-

Low V_CCWrite Inhibit

To avoid initiation of a write cycle during V_CCpower-up

and power-down, the device locks out write cycles for

Am28F256

7

V_CC< V_LKO(see DC Characteristics section for

voltages). When V_CC< V_LKO, the command register is

disabled, all internal program/erase circuits are

disabled, and the device resets to the read mode. The

device ignores all writes until V_CC> V_LKO. The user

must ensure that the control pins are in the correct logic

state when V_CC> V_LKOto prevent uninitentional writes.

Logical Inhibit

Writing is inhibited by holding any one of OE# = V_IL, CE#

= V_IHor WE# = V_IH. To initiate a write cycle CE# and

WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE# = CE# = V_ILand

OE# = V_IHwill not accept commands on the rising

edge of WE#. The internal state machine is automat-

ically reset to the read mode on power-up.

Write Pulse “Glitch” Protection

Noise pulses of less than 10 ns (typical) on OE#, CE#

or WE# will not initiate a write cycle.

FUNCTIONAL DESCRIPTION

Description Of User Modes

Table 1. Am28F256 Device Bus Operations (Notes 7 and 8)

#

WE

CE

OE

V

PP

#

Operation

(E )

(G )

(W ) (Note 1)

A0

X

A9

X

I/O

Read

V

X

V

D

OUT

IL

PPL

Standby

V

X

HIGH Z

IH

Output Disable

V

X

HIGH Z

IL

IH

Read-Only

Auto-select Manufacturer

Code (Note 2)

V

CODE

(01h)

ID

V

IL

PPL

IL

(Note 3)

Auto-select Device

Code (Note 2)

V

CODE

(A1h)

ID

V

IL

IH

(Note 3)

Read

A0

A9

D

PPH

OUT

(Note 4)

Standby (Note 5)

Output Disable

Write

V

X

V

X

HIGH Z

IH

PPH

Read/Write

Legend:

V

IL

IH

V

A0

A9

D

IL

IN

(Note 6)

X = Don’t care, where Don’t Care is either V or V levels. V

= V < V + 2 V. See DC Characteristics for voltage levels

PP CC

IL

IH

PPL

of V

. 0 V < An < V + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

PPH

CC

Notes:

1.

V

may be grounded, connected with a resistor to ground, or < V + 2.0 V. V

is the programming voltage specified for

PPL

CC

PPH

the device. Refer to the DC characteristics. When V = V

, memory contents can be read but not written or erased.

PP

PPL

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < V < 13.0 V. Minimum V rise time and fall time (between 0 and V voltages) is 500 ns.

ID

4. Read operation with V = V

may access array data or the Auto select codes.

PP

PPH

5. With V at high voltage, the standby current is I + I (standby).

PP

CC

PP

6. Refer to Table 3 for valid D during a write operation.

IN

7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V or V levels. In the Auto select mode all

IL

IH

addresses except A and A must be held at V .

9

0

IL

8. If V ≤ 1.0 Volt, the voltage difference between V and V should not exceed 10.0 volts. Also, the Am28F256 has a V

PP

CC

PP

CC

rise time and fall time specification of 500 ns minimum.

8

Am28F256

READ ONLY MODE

When V_PPis less than V_CC+ 2 V, the command register

is inactive. The device can either read array or autose-

lect data, or be standby mode.

Output Disable

Output from the device is disabled when OE# is at a

logic high level. When disabled, output pins are in a

high impedance state.

Read

The device functions as a read only memory when V_PP

< V_CC+ 2 V. The device has two control functions. Both

must be satisfied in order to output data. CE# controls

power to the device. This pin should be used for spe-

cific device selection. OE# controls the device outputs

and should be used to gate data to the output pins if a

device is selected.

Auto Select

Flash memories can be programmed in-system or in a

standard PROM programmer. The device may be sol-

dered to the circuit board upon receipt of shipment and

programmed in-system. Alternatively, the device may

initially be programmed in a PROM programmer prior

to soldering the device to the board.

Address access time t_ACCis equal to the delay from

stable addresses to valid output data. The chip enable

access time t_CEis the delay from stable addresses and

stable CE# to valid data at the output pins. The output

enable access time is the delay from the falling edge of

OE# to valid data at the output pins (assuming the ad-

dresses have been stable at least t_ACC–t_OE).

The Auto select mode allows the reading out of a binary

code from the device that will identify its manufacturer

and type. This mode is intended for the purpose

of automatically matching the device to be pro-

grammed with its corresponding programming algo-

rithm. This mode is functional over the entire

temperature range of the device.

Standby Mode

Programming In A PROM Programmer

The device has two standby modes. The CMOS

standby mode (CE# input held at V_CC± 0.5 V), con-

sumes less than 100 µA of current. TTL standby mode

To activate this mode, the programming equipment

must force V_ID(11.5 V to 13.0 V) on address A9. Two

identifier bytes may then be sequenced from the device

outputs by toggling address A₀from V_ILto V_IH. All other

address lines must be held at V_IL, and V_PPmust be

less than or equal to V_CC+ 2.0 V while using this Auto

select mode. Byte 0 (A0 = V_IL) represents the manufac-

turer code and byte 1 (A0 = V_IH) the device identifier

code. For the device these two bytes are given in Table

2 below. All identifiers for manufacturer and device

codes will exhibit odd parity with the MSB (DQ7) de-

fined as the parity bit.

(CE# is held at V ) reduces the current requirements

IH

to less than 1mA. When in the standby mode the out-

puts are in a high impedance state, independent of the

OE# input.

If the device is deselected during erasure, program-

ming, or program/erase verification, the device will

draw active current until the operation is terminated.

Table 2. Am28F256 Auto Select Code

Code

(HEX)

Type

A0

Manufacturer Code

Device Code

V

01

IL

V

A1

IH

Am28F256

9

ERASE, PROGRAM, AND READ MODE

When V_PPis equal to 12.0 V ± 5%, the command reg-

ister is active. All functions are available. That is, the

device can program, erase, read array or autoselect

data, or be standby mode.

Refer to AC Write Characteristics and the Erase/Pro-

gramming Waveforms for specific timing parameters.

Command Definitions

The contents of the command register default to 00h

(Read Mode) in the absence of high voltage applied to

the V_PPpin. The device operates as a read only mem-

ory. High voltage on the V_PPpin enables the command

register. Device operations are selected by writing spe-

cific data codes into the command register. Table 3 de-

fines these register commands.

Write Operations

High voltage must be applied to the V_PPpin in order to

activate the command register. Data written to the reg-

ister serves as input to the internal state machine. The

output of the state machine determines the operational

function of the device.

The command register does not occupy an addressable

memory location. The register is a latch that stores the

command, along with the address and data information

needed to execute the command. The register is written

by bringing WE# and CE# to V_IL, while OE# is at V_IH.

Addresses are latched on the falling edge of WE#, while

data is latched on the rising edge of the WE# pulse.

Standard microprocessor write timings are used.

Read Command

Memory contents can be accessed via the read com-

mand when V_PPis high. To read from the device, write

00h into the command register. Standard microproces-

sor read cycles access data from the memory. The de-

vice will remain in the read mode until the command

register contents are altered.

The command register defaults to 00h (read mode)

upon V_PPpower-up. The 00h (Read Mode) register de-

fault helps ensure that inadvertent alteration of the

memory contents does not occur during the V_PPpower

transition. Refer to the AC Read Characteristics and

Waveforms for the specific timing parameters.

The device requires the OE# pin to be V_IHfor write op-

erations. This condition eliminates the possibility for

bus contention during programming operations. In

order to write, OE# must be V_IH, and CE# and WE#

must be V_IL. If any pin is not in the correct state a write

command will not be executed.

Table 3. Am28F256 Command Definitions

First Bus Cycle

Operation Address

Second Bus Cycle

Data

Operation Address

Data

Command (Note 4)

Read Memory

(Note 1) (Note 2)

(Note 3)

(Note 1)

(Note 2)

(Note 3)

Write

X

00h/FFh

Read

RA

RD

Read Auto select

Erase Set-up/Erase Write

Erase-Verify

Write

80h or 90h Read

00h/01h

01h/A1h

20h

A0h

40h

C0h

FFh

Write

Read

Write

Read

Write

X

EA

X

EVD

PD

Program Setup/Program

Program-Verify

PA

X

PVD

FFh

Reset

X

Notes:

1. Bus operations are defined in Table 1.

2. RA = Address of the memory location to be read.

EA = Address of the memory location to be read during erase-verify.

PA = Address of the memory location to be programmed.

X = Don’t care.

Addresses are latched on the falling edge of the WE# pulse.

3. RD = Data read from location RA during read operation.

EVD = Data read from location EA during erase-verify.

PD = Data to be programmed at location PA. Data latched on the rising edge of WE#.

PVD = Data read from location PA during program-verify. PA is latched on the Program command.

4. Refer to the appropriate section for algorithms and timing diagrams.

10

Am28F256

FLASHERASE ERASE SEQUENCE

Erase Setup

ated by writing A0h to the register. The byte address to

be verified must be supplied with the command. Ad-

dresses are latched on the falling edge of the WE#

pulse or CE# pulse, whichever occurs later. The rising

edge of the WE# pulse terminates the erase operation.

Erase Setup is the first of a two-cycle erase command.

It is a command-only operation that stages the device

for bulk chip erase. The array contents are not altered

with this command. 20h is written to the command reg-

ister in order to perform the Erase Setup operation.

Margin Verify

During the Erase-verify operation, the device applies

an internally generated margin voltage to the

addressed byte. Reading FFh from the addressed byte

indicates that all bits in the byte are properly erased.

Erase

The second two-cycle erase command initiates the

bulk erase operation. You must write the Erase com-

mand (20h) again to the register. The erase operation

begins with the rising edge of the WE# pulse. The

erase operation must be terminated by writing a new

command (Erase-verify) to the register.

Verify Next Address

You must write the Erase-verify command with the ap-

propriate address to the register prior to verification of

each address. Each new address is latched on the fall-

ing edge of WE# or CE# pulse, whichever occurs later.

The process continues for each byte in the memory

array until a byte does not return FFh data or all the

bytes in the array are accessed and verified.

This two step sequence of the Setup and Erase com-

mands helps to ensure that memory contents are not

accidentally erased. Also, chip erasure can only occur

when high voltage is applied to the V_PPpin and all con-

trol pins are in their proper state. In absence of this high

voltage, memory contents cannot be altered. Refer to

AC Erase Characteristics and Waveforms for specific

timing parameters.

If an address is not verified to FFh data, the entire chip

is erased again (refer to Erase Setup/Erase). Erase

verification then resumes at the address that failed to

verify. Erase is complete when all bytes in the array

have been verified. The device is now ready to be pro-

grammed. At this point, the verification operation is ter-

minated by writing a valid command (e.g. Program

Setup) to the command register. Figure 1 and Table 4,

the Flasherase electrical erase algorithm, illustrate how

commands and bus operations are combined to per-

form electrical erasure. Refer to AC Erase Characteris-

tics and Waveforms for specific timing parameters.

Note: The Flash memory device must be fully

programmed to 00h data prior to erasure. This

equalizes the charge on all memory cells ensuring

reliable erasure.

Erase-Verify Command

The erase operation erases all bytes of the array

in parallel. After the erase operation, all bytes must be

sequentially verified. The Erase-verify operation is initi-

Am28F256

11

Start

Ye s

Data = 00h

No

Program All Bytes to 00h

Apply V

PPH

Address = 00h

PLSCNT = 0

Write Erase Setup Command

Write Erase Command

Time out 10 ms

Write Erase Verify

Time out 6 µs

Read Data from Device

No

Increment

PLSCNT

PLSCNT =

1000

Data = FFh

Yes

Ye s

Apply V

PPL

No

Increment Address

Last Address

Erase Error

Ye s

Write Reset Command

Apply V

PPL

Erasure Completed

Figure 1. Flasherase Electrical Erase Algorithm

11559G-6

12

Am28F256

FLASHERASE ELECTRICAL ERASE ALGORITHM

This Flash memory device erases the entire array in

parallel. The erase time depends on V_PP, temperature,

and number of erase/program cycles on the device. In

general, reprogramming time increases as the number

of erase/program cycles increases.

algorithm. Erasure then continues with an initial erase

operation. Erase verification (Data = FFh) begins at

address 0000h and continues through the array to the

last address, or until data other than FFh is

encountered. If a byte fails to verify, the device is

erased again. With each erase operation, an

increasing number of bytes verify to the erased state.

Typically, devices are erased in less than 100 pulses

(one second). Erase efficiency may be improved by

storing the address of the last byte that fails to verify in

a register. Following the next erase operation,

verification may start at the stored address location. A

total of 1000 erase pulses are allowed per reprogram

cycle, which corresponds to approximately 10 seconds

of cumulative erase time. The entire sequence of erase

and byte verification is performed with high voltage

applied to the V_PPpin. Figure 1 illustrates the electrical

erase algorithm.

The Flasherase electrical erase algorithm employs an

interactive closed loop flow to simultaneously erase all

bits in the array. Erasure begins with a read of the mem-

ory contents. The device is erased when shipped from

the factory. Reading FFh data from the device would

immediately be followed by executing the Flashrite pro-

gramming algorithm with the appropriate data pattern.

Should the device be currently programmed, data other

than FFh will be returned from address locations.

Follow the Flasherase algorithm. Uniform and reliable

erasure is ensured by first programming all bits in the

device to their charged state (Data = 00h). This is

accomplished using the Flashrite Programming

Table 4. Flasherase Electrical Erase Algorithm

Bus Operations

Command

Comments

Entire memory must = 00h before erasure (Note 3)

Note: Use Flashrite programming algorithm (Figure 3) for

programming.

Wait for V Ramp to V

(Note 1)

PP

PPH

Initialize:

Addresses

Standby

PLSCNT (Pulse count)

Erase Setup

Erase

Data = 20h

Write

Standby

Duration of Erase Operation (t

)

WHWH2

Address = Byte to Verify

Data = A0h

Write

Erase-Verify (Note 2)

Stops Erase Operation

Standby

Read

Write Recovery Time before Read = 6 µs

Read byte to verify erasure

Compare output to FFh

Increment pulse count

Standby

Write

Reset

Data = FFh, reset the register for read operations

Standby

Wait for V Ramp to V

(Note 1)

PP

PPL

Notes:

1. See AC and DC Characteristics for values of V parameters. The V power supply can be hard-wired to the device or

PP

switchable. When V is switched, V

may be ground, no connect with a resistor tied to ground, or less than V + 2.0 V.

PP

PPL

CC

2. Erase Verify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written

with the read command.

3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.

Am28F256

13

A

B

C

D

E

F

G

Section

Addresses

CE

#

OE

#

WE

Data

Out

A0h

20h

Data

20h

V

CC

V

PP

11559G-7

G

A

B

C

D

E

F

Bus Cycle

Write

Time-out

N/A

Write

A0h

Time-out

N/A

Read

Standby

Compare

Data

Command

Function

20h

N/A

Proceed per

Erase

Algorithm

Erase

Setup

Erase

(10 ms)

Erase-

Verify

Transition

(6 µs)

Erase

Verification

Erase

Figure 2. AC Waveforms For Erase Operations

ANALYSIS OF ERASE TIMING WAVEFORM

Note: This analysis does not include the requirement

to program the entire array to 00h data prior to erasure.

Refer to the Flashrite Programming algorithm.

Time-Out

A software timing routine (10 ms duration) must be ini-

tiated on the rising edge of the WE# pulse of section B.

Erase Setup/Erase

Note: An integrated stop timer prevents any possibil-

ity of overerasure by limiting each time-out period of

10 ms.

This analysis illustrates the use of two-cycle erase

commands (section A and B). The first erase com-

mand (20h) is a Setup command and does not affect

the array data (section A). The second erase com-

mand (20h) initiates the erase operation (section B)

on the rising edge of this WE# pulse. All bytes of the

memory array are erased in parallel. No address infor-

mation is required.

Erase-Verify

Upon completion of the erase software timing routine,

the microprocessor must write the Erase-verify com-

mand (A0h). This command terminates the erase oper-

ation on the rising edge of the WE# pulse (section D).

The Erase-verify command also stages the device for

data verification (section F).

The erase pulse occurs in section C.

After each erase operation each byte must be verified.

The byte address to be verified must be supplied with

14

Am28F256

the Erase-verify command (section D). Addresses are

latched on the falling edge of the WE# pulse.

location fail to verify to FFh data, erase the device

again. Repeat sections A thru F. Resume verification

(section D) with the failed address.

Another software timing routine (6 µs duration) must be

executed to allow for generation of internal voltages for

margin checking and read operation (section E).

Each data change sequence allows the device to use

up to 1,000 erase pulses to completely erase. Typically

100 erase pulses are required.

During Erase-verification (section F) each address that

returns FFh data is successfully erased. Each address

of the array is sequentially verified in this manner by re-

peating sections D thru F until the entire array is veri-

fied or an address fails to verify. Should an address

Note: All address locations must be programmed to

00h prior to erase. This equalizes the charge on all

memory cells and ensures reliable erasure.

FLASHRITE PROGRAMMING SEQUENCE

Program Setup

Program-verify operation stages the device for verifica-

tion of the last byte programmed. Addresses were pre-

viously latched. No new information is required.

The device is programmed byte by byte. Bytes may be

programmed sequentially or at random. Program Setup

is the first of a two-cycle program command. It stages

the device for byte programming. The Program Setup

operation is performed by writing 40h to the command

register.

Margin Verify

During the Program-verify operation, the device applies

an internally generated margin voltage to the ad-

dressed byte. A normal microprocessor read cycle out-

puts the data. A successful comparison between the

programmed byte and the true data indicates that the

byte was successfully programmed. The original pro-

grammed data should be stored for comparison. Pro-

gramming then proceeds to the next desired byte

location. Should the byte fail to verify, reprogram (refer

to Program Setup/Program). Figure 3 and Table 5 indi-

cate how instructions are combined with the bus oper-

ations to perform byte programming. Refer to AC

Programming Characteristics and Waveforms for spe-

cific timing parameters.

Program

Only after the program Setup operation is completed

will the next WE# pulse initiate the active programming

operation. The appropriate address and data for pro-

gramming must be available on the second WE# pulse.

Addresses and data are internally latched on the falling

and rising edge of the WE# pulse respectively. The ris-

ing edge of WE# also begins the programming opera-

tion. You must write the Program-verify command to

terminate the programming operation. This two step

sequence of the Setup and Program commands helps

to ensure that memory contents are not accidentally

written. Also, programming can only occur when high

voltage is applied to the V_PPpin and all control pins are

in their proper state. In absence of this high voltage,

memory contents cannot be programmed.

Flashrite Programming Algorithm

The device Flashrite Programming algorithm employs

an interactive closed loop flow to program data byte by

byte. Bytes may be programmed sequentially or at ran-

dom. The Flashrite Programming algorithm uses 10 µs

programming pulses. Each operation is followed by a

byte verification to determine when the addressed byte

has been successfully programmed. The program al-

gorithm allows for up to 25 programming operations per

byte per reprogramming cycle. Most bytes verify after

the first or second pulse. The entire sequence of pro-

gramming and byte verification is performed with high

Refer to AC Characteristics and Waveforms for specific

timing parameters.

Program Verify Command

Following each programming operation, the byte just

programmed must be verified.

Write C0h into the command register in order to initiate

the Program-verify operation. The rising edge of this

WE pulse terminates the programming operation. The

voltage applied to the V

pin. Figure 3 and Table 5 il-

PP

lustrate the programming algorithm.

Am28F256

15

Start

Apply V

PPH

PLSCNT = 0

Write Program Setup Command

Write Program Command (A/D)

Time out 10 µs

Write Program Verify Command

Time out 6 µs

Read Data from Device

No

PLSCNT =

No

Verify Byte

Increment PLSCNT

25?

Ye s

No

Increment Address

Last Address

Ye s

Write Reset Command

Apply V

PPL

Programming Completed

Device Failed

11559G-8

Figure 3. Flashrite Programming Algorithm

16

Am28F256

Table 5. Flashrite Programming Algorithm

Command

Bus Operations

Standby

Comments

(Note 1)

PPH

Wait for V Ramp to V

PP

Initialize Pulse counter

Program Setup

Program

Data = 40h

Write

Valid Address/Data

Standby

Write

Duration of Programming Operation (t

)

WHWH1

Program-Verify (Note 2)

Data = C0h Stops Program Operation

Standby

Read

Write Recovery Time before Read = 6 µs

Read Byte to Verify Programming

Standby

Write

Compare Data Output to Data Expected

Reset

Data = FFh, resets the register for read operations.

Wait for V Ramp to V (Note 1)

Standby

PP

PPL

Notes:

1. See AC and DC Characteristics for values of V parameters. The V power supply can be hard-wired to the device or

PP

switchable. When V is switched, V

may be ground, no connect with a resistor tied to ground, or less than V + 2.0 V.

PP

PPL

CC

2. Program Verify is performed only after byte programming. A final read/compare may be performed (optional) after the register

is written with the read command.

Am28F256

17

B

A

C

D

E

F

G

Section

Addresses

CE

#

OE

#

WE

Data

Out

Data

In

20h

Data

A0h

V

CC

V

PP

11559G-9

G

A

B

C

D

E

F

Bus Cycle

Write

Time-out

Write

Time-out

Read

Standby

Program

Address,

Program Data

C0h

(Stops

Program)

Compare

Data

Command

40h

N/A

Program

Command

Latch

Address and

Data

Proceed per

Programming

Algorithm

Program

Setup

Program

(10 µs)

Program

Verify

Transition

(6 µs)

Program

Verification

Function

Figure 4. AC Waveforms for Programming Operations

ANALYSIS OF PROGRAM TIMING WAVEFORMS

Program Setup/Program

Time-Out

Two-cycle write commands are required for program

operations (section A and B). The first program com-

mand (40h) is a Setup command and does not affect

the array data (section A).The second program com-

mand latches address and data required for program-

ming on the falling and rising edge of WE# respectively

(section B). The rising edge of this WE# pulse (section

B) also initiates the programming pulse. The device is

programmed on a byte by byte basis either sequentially

or randomly.

A software timing routine (10 µs duration) must be initi-

ated on the rising edge of the WE# pulse of section B.

Note: An integrated stop timer prevents any possibility

of overprogramming by limiting each time-out period of

10 µs.

Program-Verify

Upon completion of the program timing routine, the mi-

croprocessor must write the program-verify command

(C0h). This command terminates the programming op-

eration on the rising edge of the WE# pulse (section D).

The program-verify command also stages the device

for data verification (section F). Another software timing

routine (6 µs duration) must be executed to allow for

The program pulse occurs in section C.

18

Am28F256

generation of internal voltages for margin checking and

read operations (section E).

Parallel Device Erasure

Many applications will use more than one Flash

memory device. Total erase time may be minimized by

implementing a parallel erase algorithm. Flash

memories may erase at different rates. Therefore each

device must be verified separately. When a device is

completely erased and verified use a masking code to

prevent further erasure. The other devices will continue

to erase until verified. The masking code applied could

be the read command (00h).

During program-verification (section F) each byte just

programmed is read to compare array data with original

program data. When successfully verified, the next de-

sired address is programmed. Should a byte fail to ver-

ify, reprogram the byte (repeat section A thru F). Each

data change sequence allows the device to use up to

25 program pulses per byte. Typically, bytes are verified

within one or two pulses.

Algorithm Timing Delays

Power-Up/Power-Down Sequence

There are four different timing delays associated with

the Flasherase and Flashrite algorithms:

The device powers-up in the Read only mode. Power

supply sequencing is not required. Note that if V_CC

≤

1.0 Volt, the voltage difference between V_PPand V_CC

should not exceed 10.0 Volts. Also, the device has V_PP

rise time and fall time specification of 500 ns minimum.

1. The first delay is associated with the V_PPrise-time

when V_PPfirst turns on. The capacitors on the V_PP

bus cause an RC ramp. After switching on the V_PP

,

the delay required is proportional to the number of

devices being erased and the 0.1 mF/device. V_PP

must reach its final value 100 ns before commands

are executed.

Reset Command

The Reset command initializes the Flash memory de-

vice to the Read mode. In addition, it also provides the

user with a safe method to abort any device operation

(including program or erase).

2. The second delay time is the erase time pulse width

(10 ms). A software timing routine should be run by

the local microprocessor to time out the delay. The

erase operation must be terminated at the conclu-

sion of the timing routine or prior to executing any

system interrupts that may occur during the erase

operation. To ensure proper device operation, write

the Erase-verify operation after each pulse.

The Reset command must be written two consecutive

times after the setup Program command (40h). This will

reset the device to the Read mode.

Following any other Flash command write the Reset

command once to the device. This will safely abort any

previous operation and initialize the device to the

Read mode.

3. A third delay time is required for each programming

pulse width (10 ms). The programming algorithm is

interactive and verifies each byte after a program

pulse. The program operation must be terminated at

the conclusion of the timing routine or prior to exe-

cuting any system interrupts that may occur during

the programming operation.

The Setup Program command (40h) is the only com-

mand that requires a two sequence reset cycle. The

first Reset command is interpreted as program data.

However, FFh data is considered null data during pro-

gramming operations (memory cells are only pro-

grammed from a logical “1” to “0”). The second Reset

command safely aborts the programming operation

and resets the device to the Read mode.

4. A fourth timing delay associated with both the

Flasherase and Flashrite algorithms is the write re-

covery time (6 ms). During this time internal circuitry

is changing voltage levels from the erase/ program

level to those used for margin verify and read oper-

ations. An attempt to read the device during this pe-

riod will result in possible false data (it may appear

the device is not properly erased or programmed).

Memory contents are not altered in any case.

This detailed information is for your reference. It may

prove easier to always issue the Reset command two

consecutive times. This eliminates the need to deter-

mine if you are in the setup Program state or not.

Note: Software timing routines should be written in

machine language for each of the delays. Code written

in machine language requires knowledge of the appro-

priate microprocessor clock speed in order to accu-

rately time each delay.

Programming In-System

Flash memories can be programmed in-system or in a

standard PROM programmer. The device may be sol-

dered to the circuit board upon receipt of shipment and

programmed in-system. Alternatively, the device may

initially be programmed in a PROM programmer prior

to soldering the device to the board.

Am28F256

19

The device contains an Auto Select operation to sup-

plement traditional PROM programming methodology.

The operation is initiated by writing 80h or 90h into the

command register. Following this command, a read

cycle address 0000h retrieves the manufacturer code

of 01h. A read cycle from address 0001h returns the

device code. To terminate the operation, it is necessary

to write another valid command, such as Reset (FFh),

into the register.

Auto Select Command

AMD’s Flash memories are designed for use in applica-

tions where the local CPU alters memory contents. Ac-

cordingly, manufacturer and device codes must be

accessible while the device resides in the target sys-

tem. PROM programmers typically access the signa-

ture codes by raising A9 to a high voltage. However,

multiplexing high voltage onto address lines is not a

generally desired system design practice.

20

Am28F256

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature . . . . . . . . . . . . –65°C to +150°C

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Commercial (C) Devices

Ambient Temperature (T_A). . . . . . . . . . . .0°C to +70°C

Ambient Temperature

Industrial (I) Devices

with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C

Ambient Temperature (T_A). . . . . . . . . .–40°C to +85°C

Voltage with Respect To Ground

Extended (E) Devices

All pins except A9 and V (Note 1) .–2.0 V to +7.0 V

Ambient Temperature (T_A). . . . . . . . .–55°C to +125°C

PP

V

_CC(Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

_PP(Note 2). . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

V

_CCSupply Voltages

_CC. . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

V_PPVoltages

Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V

V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Program, Erase, and Verify. . . . . . +11.4 V to +12.6 V

Notes:

Operating ranges define those limits between which the

functionality of the device is guaranteed.

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, inputs may overshoot V to –2.0 V for

SS

periods of up to 20 ns. Maximum DC voltage on input and

I/O pins is V

+ 0.5 V. During voltage transitions, input

CC

and I/O pins may overshoot to V

to 20ns.

+ 2.0V for periods up

CC

2. Minimum DC input voltage on A9 and V pins is –0.5 V.

PP

During voltage transitions, A9 and V

may overshoot

PP

V

to –2.0 V for periods of up to 20 ns. Maximum DC

SS

input voltage on A9 and V

is +13.0 V which may

PP

overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time. Du-

ration of the short circuit should not be greater than one

second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at these

or any other conditions above those indicated in the opera-

tional sections of this specification is not implied. Exposure of

the device to absolute maximum rating conditions for extended

periods may affect device reliability.

Am28F256

21

MAXIMUM OVERSHOOT

Maximum Negative Input Overshoot

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

11560F-10

Maximum Positive Input Overshoot

20 ns

V

+ 2.0 V

CC

V

+ 0.5 V

2.0 V

CC

20 ns

11560F-11

Maximum V Overshoot

PP

20 ns

14.0 V

13.5 V

+ 0.5 V

V

CC

20 ns

11560F-12

22

Am28F256

DC CHARACTERISTICS over operating range unless otherwise specified

TTL/NMOS Compatible

Parameter

Symbol

Parameter Description

Input Leakage Current

Test Conditions

= V Max, V = V or V

SS

Min

Typ

Max

±1.0

1.0

Unit

µA

I

V

LI

CC

IN

CC

I

Output Leakage Current

= V Max, V

= V or V

SS

µA

LO

CC

OUT

CC

I

V

Standby Current

= V Max, CE# = V

IH

0.2

20

mA

CCS

CC

V

Max, CE# = V OE# = V

IL, IH

CC = CC

I

Active Read Current

30

mA

CC1

CC2

I

= 0 mA, at 6 MHz

OUT

CE# = V

IL

V

Programming Current

20

CC

Programming in Progress (Note 4)

CE# = V

IL

I

V

Erase Current

mA

µA

CC3

PPS

CC

PP

Erasure in Progress (Note 4)

Standby Current

V

= V

±1.0

200

PP

PPL

PPH

PPL

PPH

70

I

V

Read Current

µA

PP1

PP

±1.0

I

V

Programming Current

Erase Current

10

30

mA

PP2

PP

Programming in Progress (Note 4)

V

= V

PP

PPH

I

30

PP3

Erasure in Progress (Note 4)

V

Input Low Voltage

–0.5

2.0

0.8

V

IL

V

Input High Voltage

V

+ 0.5

CC

IH

V

Output Low Voltage

Output High Voltage

A9 Auto Select Voltage

A9 Auto Select Current

I

= 5.8 mA, V = V Min

0.45

V

OL

CC

V

= –2.5 mA, V = V Min

2.4

V

OH1

OH

CC

V

A9 = V

11.5

13.0

50

V

ID

I

A9 = V Max, V = V Max

CC

5

µA

ID

CC

V

during Read-Only

Note: Erase/Program are inhibited

when V = V

PP

V

0.0

V

+2.0

V

PPL

CC

Operations

PP

PPL

V

during Read/Write

PP

V

11.4

3.2

12.6

V

PPH

Operations

V

Low V Lock-out Voltage

3.7

LKO

CC

Notes:

1. Caution: The Am28F256 must not be removed from (or inserted into) a socket when V or V is applied. If V ≤ 1.0 Volt,

CC

PP

CC

the voltage difference between V and V should not exceed 10.0 Volts. Also, the Am28F256 has a V rise time and fall

PP

CC

PP

time specification of 500 ns minimum.

2.

I

is tested with OE# = V to simulate open outputs.

CC1 IH

3. Maximum active power usage is the sum of I and I ..

CC

PP

4. Not 100% tested.

Am28F256

23

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

= V Max, V = V or V

SS

Min

Typ

Max

±1.0

100

Unit

µA

I

Input Leakage Current

Output Leakage Current

V

LI

CC

IN

CC

I

= V Max, V

= V or V

SS

µA

LO

CC

OUT

CC

I

V

Standby Current

= V Max, CE# = V + 0.5 V

15

20

µA

CCS

CC

= V Max, CE# = V OE# = V

IH

CC

IL,

I

Active Read Current

30

mA

CC1

CC2

I

= 0 mA, at 6 MHz

OUT

CE# = V

IL

V

Programming Current

Erase Current

20

CC

Programming in Progress (Note 4)

CE# = V

IL

I

CC3

PPS

Erasure in Progress (Note 4)

V

Standby Current

Read Current

V

= V

±1.0

µA

PP

PPL

PPH

I

70

10

200

PP1

I

V

Programming Current

Erase Current

30

mA

PP2

PP

Programming in Progress (Note 4)

V

= V

PP

PPH

I

10

30

PP3

Erasure in Progress (Note 4)

V

Input Low Voltage

Input High Voltage

Output Low Voltage

–0.5

0.8

V

IL

V

0.7 V

V

+ 0.5

IH

CC

V

I

= 5.8 mA, V = V Min

0.45

OL

OH

CC

V

= –2.5 mA, V = V Min

0.85 V

CC

OH1

CC

Output High Voltage

V

= –100 µA, V = V Min

V

–0.4

CC

OH2

CC

V

A9 Auto Select Voltage

A9 Auto Select Current

A9 = V

11.5

0.0

13.0

50

V

ID

I

A9 = V Max, V = V Max

5

µA

ID

CC

V

during Read-Only

Note: Erase/Program are inhibited

when V = V

PPL

V

+ 2.0

CC

V

PPL

Operations

PP

PPL

V

during Read/Write

PP

V

11.4

3.2

12.6

V

PPH

Operations

V

Low V Lock-out Voltage

3.7

LKO

CC

Notes:

1. Caution: The Am28F256 must not be removed from (or inserted into) a socket when V or V is applied. If V ≤ 1.0 volt,

CC

PP

CC

the voltage difference between V and V should not exceed 10.0 volts. Also, the Am28F256 has a V rise time and fall

PP

CC

PP

time specification of 500 ns minimum.

2.

I

is tested with OE# = V to simulate open outputs.

CC1 IH

3. Maximum active power usage is the sum of I and I

.

PP

CC

4. Not 100% tested.

24

Am28F256

25

20

15

10

5

I

Active

in mA

CC

55 C

°

0 C

°

25 C

°

70 C

°

125 C

°

0

1

2

3

4

5

6

7

8

9

10

11

12

Frequency in MHz

11560F-13

Figure 5. Am28F256—Average I_CCActive vs. Frequency

V

_CC= 5.5 V, Addressing Pattern = Minmax

Data Pattern = Checkerboard

TEST CONDITIONS

Table 6. Test Specifications

5.0 V

Test Condition

Output Load

-70

All others Unit

1 TTL gate

2.7 k

Ω

Device

Under

Test

Output Load Capacitance, C

(including jig capacitance)

L

30

100

pF

Input Rise and Fall Times

Input Pulse Levels

10

ns

V

≤

C

L

6.2 k

Ω

0.0–3.0 0.45–2.4

Input timing measurement

reference levels

1.5

0.8, 2.0

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

11560G-14

Figure 6. Test Setup

Am28F256

25

SWITCHING TEST WAVEFORMS

3 V

0 V

2.4 V

2.0 V

0.8 V

2.0 V

0.8 V

Test Points

1.5 V

Test Points

1.5 V

0.45 V

Input

Output

Input

Output

AC Testing (all speed options except -70): Inputs are driven at

2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise

and fall times are ≤10 ns.

AC Testing for -70 devices: Inputs are driven at 3.0 V for a

logic “1” and 0 V for a logic “0”. Input pulse rise and fall times

are ≤10 ns.

11560G-15

SWITCHING CHARACTERISTICS over operating range unless otherwise specified

AC Characteristics—Read Only Operation

Parameter Symbols

JEDEC Standard

Am28F256 Speed Options

Parameter Description

Read Cycle Time (Note 2)

-70

70

35

-90

90

35

-120

120

50

-150

150

55

-200

200

55

Unit

ns

t

Min

Max

AVAV

RC

t

Chip Enable AccessTime

Address Access Time

ns

ELQV

CE

t

ns

AVQV

GLQV

ACC

t

Output Enable Access Time

ns

OE

Chip Enable to Output in Low Z

(Note 2)

t

Min

Max

Min

0

20

0

20

0

30

0

35

0

35

0

ns

ELQX

EHQZ

GLQX

GHQZ

LZ

Chip Disable to Output in High Z

(Note 1)

t

DF

Output Enable to Output in Low Z

(Note 2)

t

OLZ

Output Disable to Output in High Z

(Note 2)

t

Max

20

30

35

DF

Output Hold from first of Address,

CE#, or OE# Change (Note 2)

t

Min

0

6

0

6

0

6

0

6

0

6

ns

µs

AXQX

OH

t

Write Recovery Time before Read

WHGL

V

Setup Time to Valid Read

CC

t

50

VCS

(Note 2)

Notes:

1. Guaranteed by design not tested.

2. Not 100% tested.

26

Am28F256

AC Characteristics—Write/Erase/Program Operations

Parameter Symbols

Am28F256 Speed Options

JEDEC

Standard

Parameter Description

Write Cycle Time (Note 4)

Address Set-up Time

Address Hold Time

-70

70

0

-90

90

0

-120

120

0

-150

150

0

-200

200

0

Unit

ns

t

Min

AVAV

WC

t

ns

AVWL

WLAX

DVWH

WHDX

AS

AH

DS

DH

t

45

10

45

10

50

60

75

ns

t

Data Setup Time

50

ns

t

Data Hold Time

10

ns

Write Recovery Time

before Read

t

Min

6

0

6

0

6

0

6

0

6

0

µs

WHGL

GHWL

WR

Read Recovery Time

before Write

t

Chip Enable Set-up Time

Chip Enable Hold Time

Write Pulse Width

Min

0

ns

ELWL

WHEH

WLWH

CS

CH

WP

t

45

50

60

Write Pulse

Width HIGH

t

Min

20

10

20

10

20

10

20

10

20

10

ns

µs

ms

ns

µs

ns

WHWL

WPH

Duration of Programming

Operation (Note 2)

t

WHWH1

WHWH2

Duration of

Erase Operation (Note 2)

9.5

100

50

9.5

100

50

9.5

100

50

9.5

100

50

9.5

100

50

V

Setup Time to

PP

t

VPEL

Chip Enable LOW (Note 4)

V

Set-up Time to

CC

t

VCS

Chip Enable LOW (Note 4)

V

Rise Time

PP

t

500

100

500

100

500

100

500

100

500

100

VPPR

90% V

(Note 4)

PPH

V

Fall Time

PP

t

VPPF

10% V

(Note 4)

PPL

V

< V

LKO

CC

t

LKO

to Reset (Note 4)

Notes:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC

Characteristics for Read Only operations.

2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally

on the device.

3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In

systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all setup, hold and

inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

4. Not 100% tested.

Am28F256

27

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

SWITCHING WAVEFORMS

Device and

Address Selection

Data

Valid

Outputs

Enabled

Power-up, Standby

Addresses

Standby, Power-Down

Addresses Stable

t

(t

)

AVAV RC

CE# (E#)

OE# (G#)

t

(t

EHQZ

)

DF

t

WHGL

GHQZ

(t

)

DF

WE# (W#)

t

(t

)

GLQV OE

t

(t

)

ELQV CE

t

(t

)

AXQX OH

t

(t

)

GLQX OLZ

t

VCS

t

(t

)

ELQX LZ

High Z

Output Valid

Data (DQ)

t

(t

AVQV ACC

5.0 V

V

CC

0 V

11560G-16

Figure 7. AC Waveforms for Read Operations

28

Am28F256

SWITCHING WAVEFORMS

Power-up,

Standby

Setup Erase

Command

Erase

Command

Erase-Verify

Command

Erase

Standby,

Erasure

Verification Power-down

Addresses

CE# (E#)

t

)

(t

)

t

(t

)

AVAV RC

AVAV WC

t

(t

t

(t

)

WLAX AH

AVWL AS

t

(t

)

t

(t

)

ELWL CS

EHQZ DF

t

(t

)

WHEH CH

OE# (G#)

WE# (W#)

t

WHWH2

t

WHGL

t

(t

)

GHWL OES

t

(t

)

GHQZ DF

t

(t

)

GLQV OE

t

(t

)

t

(t

)

t

(t

)

WLWH WP

WHWL WPH

GLQX OLZ

t

(t

)

t

(t

)

DVWH DS

AXQX OH

t

(t

)

WHDX DH

VALID

DATA

OUT

HIGH Z

DATA IN

= 20h

DATA IN

= 20h

DATA IN =

A0h

Data (DQ)

5.0 V

t

(t

)

ELQX LZ

t

(t

ELQV CE

VCS

V

CC

0 V

t

VPEL

V

PPH

V

PP

V

PPL

11560F-17

Figure 8. AC Waveforms for Erase Operations

Am28F256

29

SWITCHING WAVEFORMS

Program

Command

Latch Address

Programming

and Data Command

Power-up, SetupProgram

Programming Standby,

Verification Power-down

Verify

Standby

Command

Addresses

CE# (E#)

t

(t

)

t

(t

)

AVAV RC

AVAV WC

t

(t

)

WLAX AH

t

(t

)

AVWL AS

t

(t

)

t

(t

)

ELWL CS

GHQZ DF

t

(t

)

WHEH CH

OE# (G#)

WE# (W#)

t

WHWH1

t

WHGL

t

(t

)

GHWL OES

t

(t

)

GHQZ DF

t

(t

)

GLQV OE

t

(t

)

t

(t

)

WLWH WP

GLQX OLZ

t

(t

)

WHWL WPH

t

(t

)

t

(t

)

DVWH DS

AXQX OH

t

(t

)

WHDX DH

VALID

DATA

OUT

HIGH Z

DATA IN

= 40h

DATA IN

= C0h

DATA IN

Data (DQ)

5.0 V

t

(t

)

ELQX LZ

t

(t

ELQV CE

VCS

V

CC

0 V

t

VPEL

V

PPH

V

PP

V

PPL

11560F-18

Figure 9. AC Waveforms for Programming Operations

30

Am28F256

ERASE AND PROGRAMMING PERFORMANCE

Limits

Typ

Max

Parameter

Chip Erase Time

Min

(Note 1) (Note 2)

Unit

sec

Comments

1

10

3

Excludes 00h programming prior to erasure

Excludes system-level overhead

Chip Programming Time

Write/Erase Cycles

0.5

sec

10,000

Cycles

Notes:

1. 25°C, 12 V V

.

PP

2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count

(Flasherase = 1000 max and Flashrite = 25 max). Typical worst case for program and erase is significantly less than the actual

device limit.

LATCHUP CHARACTERISTICS

Min

Max

Input Voltage with respect to V on all pins except I/O pins (Including A9 and V

)

PP

–1.0 V

–100 mA

13.5 V

SS

Input Voltage with respect to V on all pins I/O pins

V

+ 1.0 V

CC

SS

Current

+100 mA

Includes all pins except V . Test conditions: V = 5.0 V, one pin at a time.

CC

PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Output Capacitance

Input Capacitance

Test Conditions

Typ

8

Max

10

Unit

pF

C

V

= 0

IN

C

V

= 0

8

12

pF

OUT

C

V

V = 0

PP

8

12

pF

IN2

PP

Note: Sampled, not 100% tested. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

Am28F256

31

PHYSICAL DIMENSIONS

PD032—32-Pin Plastic DIP (measured in inches)

1.640

1.670

.600

.625

17

16

32

.009

.015

.530

.580

Pin 1 I.D.

.630

.700

.045

.065

0°

10°

.005 MIN

.140

.225

16-038-S_AG

PD 032

EC75

SEATING PLANE

.090

.110

.015

.060

.016

.022

5-28-97 lv

.120

.160

PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

.485

.495

.447

.453

.009

.015

.042

.056

.125

.140

.585

.595

Pin 1 I.D.

.080

.095

.547

.553

SEATING

PLANE

.400

REF.

.490

.530

.013

.021

.050 REF.

16-038FPO-5

PL 032

DA79

.026

.032

TOP VIEW

SIDE VIEW

6-28-94 ae

32

Am28F256

PHYSICAL DIMENSIONS

TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

7.90

8.10

0.50 B

0.05

0.15

18.30

18.50

19.80

20.20

0.08

0.20

0.10

0.21

16-038-TSOP-2

TS 032

DA95

1.20

MAX

3-25-97 lv

0°

5°

0.50

0.70

Am28F256

33

PHYSICAL DIMENSIONS

TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

7.90

8.10

0.50 BSC

0.05

0.15

18.30

18.50

19.80

20.20

16-038-TSOP-2

TSR032

DA95

0.08

0.20

1.20

MAX

0.10

0.21

3-25-97 lv

0°

5°

0.50

0.70

34

Am28F256

DATA SHEET REVISION SUMMARY FOR

AM28F256

Revision G+2

Programming In A PROM Programmer:

Revision G

Deleted the paragraph “(Refer to the AUTO SELECT

paragraph in the ERASE, PROGRAM, and READ

MODE section for programming the Flash memory de-

vice in-system).”

Deleted -75, -95, and -250 speed options. Matched for-

matting to other current data sheets.

Revision G+1

Figure 3, Flashrite Programming Algorithm: Moved end

of arrow originating from Increment Address box so

that it points to the PLSCNT = 0 box, not the Write Pro-

gram Verify Command box. This is a correction to the

diagram on page 6-189 of the 1998 Flash Memory

Data Book.

Trademarks

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am28F256

35


型号：	28F256
厂家：	AMD
描述：	256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory 256千位（是32K ×8位）的CMOS 12.0伏，整体擦除闪存闪存
文件：	总35页 (文件大小：467K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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