S3086TT11 [AMCC]
Clock Recovery Circuit, 1-Func, BICMOS, PQFP48, TQFP-48;
| 型号： | S3086TT11 |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | Clock Recovery Circuit, 1-Func, BICMOS, PQFP48, TQFP-48 ATM 异步传输模式 电信 信息通信管理 电信集成电路 |
| 文件： | 总2页 (文件大小：41K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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S3086
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30Mbps-3.0Gbps Continuous Rate CDR
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For all new designs, please consult the S3086 Design
Recommendations Application Note (AN 1239) for important
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General Description
PHY/PMD
S3078
S3076
The Continuous Rate Clock Recovery Unit (CRU) is a variable rate clock
recovery interface device. The device is suitable for use in applications such
as SONET/SDH, Fibre Channel, Fast Ethernet, HDTV, ESCON, Gigabit
Ethernet, and DS-3. The chip performs all necessary clock recovery functions
in conformance with the Bellcore 253, IEEE 802.3, and SMPTE 292/184
transmission standards.
The function of the S3086 continuous rate clock recovery unit is to derive
high speed timing signals for all rates between 30 Mbps and 2.7 Gbps. The
S3086 is implemented using AMCC's proven Phase Lock Loop (PLL)
technology. The figure below shows a typical network application.
The S3086 receives a scrambled NRZ signal from 30 Mbps to 2.7 Gbps and
recovers the clock from the data. The chip outputs a differential bit clock and
retimed data. An external oscillator may be used for continuous down stream
clocking in SONET applications.
The S3086 utilizes on-chip PLLs which consist of a phase detector, a loop
filter, and a Voltage Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO output and the serial data
input. A loop filter converts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO whose frequency is varied by
this voltage.
Features
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SiGe BiCMOS technology
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Complies with Bellcore and ITU-T specifications for jitter tolerance, jitter
transfer and jitter generation
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On-chip high frequency PLL with loop filter for clock recovery
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Programmable signal detect input active High or active Low (LVTTL and
LVPECL Input)
Supports clock recovery for entire band between 30 Mbps to 2.7 Gbps with
no gaps
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Capable of working at OC-48/12/3/1 with and without Forward Error
Correction (FEC), FireWire, HDTV, GE, FC, DTV, ESCON, FDDI, FE, and DS-3
rates
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Selectable optional reference clock (19.44/155.52 MHz for SONET rates or
user defined for non-SONET rates)
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All SONET rates utilize same loop filter
Loss of Lock Indication
Serial data input: 30 Mbps up to 2.7 Gbps (Differential CML)
Low jitter serial interface
+3.3 V supply
Compact 48-pin TQFP/TEP package
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MyAMCC - Product Summary
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Typical power 700 mW (Serial Clock Enabled)
Typical power 550 mW (Serial Clock Disabled)
Applications
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SONET/SDH/ATM/OC-3/OC-12/OC-48
Fibre Channel
Gigabit Ethernet/Fast Ethernet
High Definition Television/Digital Television (HDTV/DTV)
FireWire
Fibre Distributed Data Interface (FDDI)
Enterprise Systems Connection (ESCON)
DS-3
S3086 Typical Network Application
S3086 - Typical Network Application
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