S-2057A [AMCC]
Telecom Circuit, 1-Func, Bipolar, PDSO20, 4.40 X 6.50 MM, 0.90 MM HEIGHT, TSSOP-20;
| 型号： | S-2057A |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | Telecom Circuit, 1-Func, Bipolar, PDSO20, 4.40 X 6.50 MM, 0.90 MM HEIGHT, TSSOP-20 电信 光电二极管 电信集成电路 |
| 文件： | 总9页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DEVICE
SPECIFICATION
S2057
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
devices in the loop. Normal mode is enabled by setting
theSELpinACTIVE, whichincludesthediskintheloop
via the DDI/DDO ports. When the disk drive is either
absent or non-functional, Bypass mode is selected by
setting the SEL pin INACTIVE. This routes data directly
from IN to OUT, bypassing the disk ports. Direct attach
Fibre Channel Disk Drives have an “LRC Interlock”
signal designed to directly control the select function.
Table 1 is a truth table describing the data flow through
the S2057.
FEATURES
• Supports ANSI X3T11 1.0625 Gbps FCALdisk
attach
• ANSI x3T11 Fibre Channel Compatible
• IEEE 802.3z Gigabit Ethernet Compatible
• 1250 Mbps (Gigabit Ethernet) operation
• Fully differential for minimum deterministic
jitter accumulation (10 ps nominal)
• TTL Bypass Select
Jitter Performance
• High speed LVPECL I/O
• 0.2 W Typical power dissipation
• 3.3 V power supply
The primary AC parameter of importance is determinis-
tic jitter accumulation (data eye degradation) inserted
by the port bypass circuit. The S2057 utilizes high
bandwidth, low skew differential circuitry to provide
symmetric rise and fall times and excellent noise immu-
nity. This results in a nominal deterministic jitter accu-
mulation of ±10 ps.
• 20-pin TSSOP
GENERAL DESCRIPTION
The S2057 is a single channel Port Bypass Circuit
(PBC), designed to minimize jitter accumulation by
providing a high bandwidth fully differential data path.
Primary application is in Fibre Channel Arbitrated Loop
(FC-AL) disk arrays to allow hot swapping of FC-AL
drives. The S2057 is designed to support 1.0625 Gbps
and 1.25 Gbps data rates.
For arrays of disk drives greater than 4, it is recom-
mended that the S2057 be cascaded with the S2058
(Port Bypass with repeater) in a ratio of 4:1 to perform
clock and data retiming. This insures optimal jitter
performance for the disk array system.
TheS2057isahighspeed2:1multiplexerwith2modes
of operation: Normal and Bypass. A block diagram is
shown in Figure 1, and a system diagram showing the
S2057 in a single loop of a disk array is shown in Figure 2.
A disk drive connects on the Disk Drive input and output
ports (DDIP/N, DDOP/N), while the INP/N and OUTP/
N ports connect to the upstream and downstream
Table 1. Truth Table
SEL1
OUT
IN
DDO
IN
0
1
DDI
IN
Figure 1. S2057 Block Diagram
DDO P/N
DDI P/N
SEL
1
0
IN P/N
OUT P/N
PBC
1
August 8, 2000 / Revision C
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
S2057
Figure 2. Functional Block Diagram
S2058
Dual SC
or
DB-9
Optics
or
Copper
S2058
normal
FC-AL Disk Drive
0
1
LRC Interlock
E_STORE
TX
RX
Disk
Storage
S2057
bypass
Pulldown for Bypass in
Absence of Disk Drive
0
1
TX
S2057
FC-AL Disk Drive
normal
LRC Interlock
E_STORE
0
1
TX
RX
Disk
Storage
S2057
2
August 8, 2000 / Revision C
S2057
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
Figure 3. Timing Waveforms
IN P/N
DDI P/N
OUT P/N
DDO P/N
T1, 2, 3
Figure 4. Differential Voltage
500mV
VP - P = 1000mV
Single-ended swing
Figure 5. Input Termination
Biased at Vcc -0.65V
S2057
0.1µF
100 Ω
0.1µF
Figure 6. Output Connection
0.1 µf
150Ω
150Ω
Backplane
0.1 µf
S2057
3
August 8, 2000 / Revision C
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
S2057
Table 2. Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin#
7, 6
4, 3
Description
INP
INN
Diff.
LVPECL
I
I
Differential inputs from the downstream PBC port.
DDIP
DDIN
Diff.
LVPECL
Disk Drive Input. Serial input from the local transmitter on PBC
port 1.
A Low selects the "BYPASS" mode causing the output of the
previous port to propagate to the next port or OUT. When High,
this signal selects "NORMAL" mode which routes the previous
port to the local output, DDO and routes the local input, DDI to
the next port or OUT.
SEL
TTL
I
11
DDOP
DDON
Diff.
LVPECL
Disk Drive Output. Serial output driving the local receiver
corresponding to PBC port 1.
O
O
19, 18
15, 14
OUTP
OUTN
Diff.
LVPECL
Serial output driving the upstream PBC port.
Power Supply. 3.3V nominal.
1, 2, 10,
12, 17, 20
VCC
GND
+3.3V
GND
Ground. Ground pins are phyisically attached to the die
mounting surface, and are an important part of the thermal path.
For best thermal performance, all ground pins should be
connected to a ground plane, using multiple vias if possible.
5, 8, 9,
13, 16
4
August 8, 2000 / Revision C
S2057
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
Figure 7. S2057 Pinout Package
VCC
VCC
DDIN
DDIP
GND
INN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
DDOP
DDON
VCC
GND
OUTP
OUTN
GND
VCC
INP
GND
GND
VCC
SEL
5
August 8, 2000 / Revision C
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
S2057
Figure 8. S2057 20 TSSOP (4.4 mm) Package
6
August 8, 2000 / Revision C
S2057
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
Table 3. AC Characteristics (Over recommended operating conditions.)
Parameter
Description
Typ
Max Units
Conditions
TRDDO
TFDDO
Serial Data rise and fall time (Disk
drive outputs, DDO).
20% to 80% tested on a sample
basis.
185
350
ps
Flow through propagation delay IN to
OUT.
Delay with all circuits bypassed. 50
Ohm load.
T1
T2
T3
530
580
560
1000
1000
1000
ps
ps
ps
Flow through propagation delay IN to
DDO.
Delay with PBC in Normal or Bypass
mode. 50 Ohm load.
Flow through propagation delay DDI
to OUT.
Delay with PBC in Normal mode. 50
Ohm load.
TROUT
TFOUT
Serial data rise and fall time (Bypass
output, OUT).
20% to 80% tested on a sample
basis.
122
3
200
5
ps
ps
RMS output jitter accumulated with
K28.7 code from IN to OUT - PBC in
bypass mode. Tested on a sample
basis.
Random jitter accumulation
TjitterRMS
Deterministic output jitter accumulated
K28.5 code from IN to OUT, both PBC
stages bypassed. 941 ps input pulse
width. Tested on a sample basis.
Deterministic jitter accumulation
±10
±30
ps
TjitterDJ
Table 4. DC Characteristics (Over recommended operating conditions.)
Parameter
VIH(ITL)
VIL(ITL)
IIH(ITL)
IIL(ITL)
VCC
Description
Input HIGH voltage (SEL-TTL)
Input LOW voltage (SEL-TTL)
Input HIGH current (SEL-TTL)
Input LOW current (SEL-TTL)
Supply Voltage
Min
2.0
0
Typ
Max
3.47
0.8
Units
V
Conditions
V
50
µA
µA
V
VIN = 2.4V
-500
3.13
V
V
IN = 0.5V
CC = 3.30V ± 5%
3.47
70
Supply Current
50
mA
W
ICC
Outputs open, VCC = VCC max
Outputs open, VCC = VCC max
Power Dissipation
0.18
0.25
PD
AC Coupled. Internally DC
biased VCC - 0.65V
Receiver differential peak-to-peak
input sensitivity, INP/N & DDIP/N
1
300
2600
∆VIN(DF)
mVp-p
mVp-p
mVp-p
DDOP/N output differential peak-to-
peak voltage swing
1
1
1000 1400 2200
1200 1300 2200
50Ω to VCC -2.0V
50Ω to VCC -2.0V
∆VOUTN(L_SO)
OUTP/N output differential peak-to-
peak voltage swing
∆VOUTN(OUT)
7
August 8, 2000 / Revision C
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
S2057
Table 5. Absolute Maximum Ratings1
Parameter
Min
-0.5
-0.5
-0.5
Typ
Max
Units
+4
V
V
V
TTL Power Supply Voltage (VCC
)
PECL DC Input Voltage (VINP
)
VCC+0.5
3.47
TTL DC Input Voltage (VINP
DC Voltage applied to outputs for High output
state (VIN TTL
)
-0.5
V
VCC+0.5
)
50
50
mA
mA
C˚
C˚
V
TTL Output Current (IOUT) (DC, output High)
PECL Output Current (IOUT), (DC output High)
Case Temperature Under Bias (TC)
-55
-65
125
150
1000
Storage Temperature (TSTG
Maximum Input
)
1. CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time
without causing permanent damage. Functionality at or above the values listed is not implied. Exposure
to these values for extended periods may affect device reliability.
Table 6. Recommended Operating Conditions 2
Parameter
Min
+3.13
0
Typ
Max
+3.47
70
Units
V
Power Supply Voltage (VCC
)
Ambient Operating Temperature Range (T)
C˚
2. AMCC guarantees the functional and parametric operation of the part under “Recommended Operating
Conditions” (except where specifically noted in the AC and DC Parametric tables).
8
August 8, 2000 / Revision C
S2057
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
Ordering Information
Grade
Device
Package
Speed Grade
S – Commercial
2057
A – 20 TSSOP
Note: For Fibre Channel rates
(1.062 Gbps), this part does
not have a speed grade
designation.
Grade
Device
Package
Speed Grade
S – Commercial
2057
A – 20 TSSOP
12 – 1.25 Gbps (Gigabit Ethernet)
X – X X X X
X
–
X X
Grade
Part Number
Package Speed Grade
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (619) 450-9333 • (800) 755-2622 • Fax: (619) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 2000 Applied Micro Circuits Corporation
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