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EPF8282ALC84-3 [ALTERA]

Loadable PLD, CMOS, PQCC84, PLASTIC, LCC-84;
EPF8282ALC84-3
型号： EPF8282ALC84-3
厂家： ALTERA CORPORATION    ALTERA CORPORATION
描述：

Loadable PLD, CMOS, PQCC84, PLASTIC, LCC-84

时钟 LTE 栅 输入元件 可编程逻辑
文件： 总62页 (文件大小：346K)
中文：  中文翻译
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FLEX 8000  
Programmable Logic  
Device Family  
®
January 2003, ver. 11.1  
Data Sheet  
1
■
■
Low-cost, high-density, register-rich CMOS programmable logic  
device (PLD) family (see Table 1)  
Features...  
–
–
2,500 to 16,000 usable gates  
282 to 1,500 registers  
System-level features  
–
In-circuit reconfigurability (ICR) via external configuration  
devices or intelligent controller  
–
Fully compliant with the peripheral component interconnect  
Special Interest Group (PCI SIG) PCI Local Bus Specification,  
Revision 2.2 for 5.0-V operation  
–
–
–
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)  
circuitry compliant with IEEE Std. 1149.1-1990 on selected devices  
MultiVoltTM I/O interface enabling device core to run at 5.0 V,  
while I/O pins are compatible with 5.0-V and 3.3-V logic levels  
Low power consumption (typical specification is 0.5 mA or less in  
standby mode)  
3
■
Flexible interconnect  
–
FastTrack® Interconnect continuous routing structure for fast,  
predictable interconnect delays  
–
Dedicated carry chain that implements arithmetic functions such  
as fast adders, counters, and comparators (automatically used by  
software tools and megafunctions)  
–
–
Dedicated cascade chain that implements high-speed, high-fan-in  
logic functions (automatically used by software tools and  
megafunctions)  
Tri-state emulation that implements internal tri-state nets  
■
■
Powerful I/O pins  
Programmable output slew-rate control reduces switching noise  
Table 1. FLEX 8000 Device Features  
Feature  
EPF8282A  
EPF8282AV  
EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A  
Usable gates  
2,500  
282  
26  
4,000  
452  
42  
6,000  
636  
63  
8,000  
820  
84  
12,000  
1,188  
126  
16,000  
1,500  
162  
Flipflops  
Logic array blocks (LABs)  
Logic elements (LEs)  
Maximum user I/O pins  
208  
78  
336  
120  
504  
136  
672  
152  
1,008  
184  
1,296  
208  
Altera Corporation  
1
DS-F8000-11.1  
FLEX 8000 Programmable Logic Device Family Data Sheet  
JTAG BST circuitry  
Yes  
No  
Yes  
Yes  
No  
Yes  
■
■
■
■
Peripheral register for fast setup and clock-to-output delay  
Fabricated on an advanced SRAM process  
Available in a variety of packages with 84 to 304 pins (see Table 2)  
Software design support and automatic place-and-route provided by  
the Altera® MAX+PLUS® II development system for Windows-based  
PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM  
RISC System/6000 workstations  
...and More  
Features  
■
Additional design entry and simulation support provided by EDIF  
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),  
Verilog HDL, VHDL, and other interfaces to popular EDA tools from  
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,  
OrCAD, Synopsys, Synplicity, and Veribest  
Table 2. FLEX 8000 Package Options & I/O Pin Count  
Note (1)  
Device  
84-  
Pin  
100- 144-  
Pin Pin  
160- 160- 192- 208- 225- 232- 240- 280- 304-  
Pin Pin Pin Pin Pin Pin Pin Pin Pin  
PLCC TQFP TQFP PQFP PGA PGA PQFP BGA PGA PQFP PGA RQFP  
EPF8282A  
EPF8282AV  
EPF8452A  
EPF8636A  
EPF8820A  
EPF81188A  
EPF81500A  
68  
78  
78  
68  
68  
68  
120  
118  
120  
120  
136  
152  
136  
152  
148  
112  
152  
184  
184  
181  
208  
208  
Note:  
(1) FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad  
flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages.  
Altera’s Flexible Logic Element MatriX (FLEX®) family combines the  
benefits of both erasable programmable logic devices (EPLDs) and field-  
programmable gate arrays (FPGAs). The FLEX 8000 device family is ideal  
for a variety of applications because it combines the fine-grained  
architecture and high register count characteristics of FPGAs with the  
high speed and predictable interconnect delays of EPLDs. Logic is  
implemented in LEs that include compact 4-input look-up tables (LUTs)  
and programmable registers. High performance is provided by a fast,  
continuous network of routing resources.  
General  
Description  
2
Altera Corporation  
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
FLEX 8000 devices provide a large number of storage elements for  
applications such as digital signal processing (DSP), wide-data-path  
manipulation, and data transformation. These devices are an excellent  
choice for bus interfaces, TTL integration, coprocessor functions, and  
high-speed controllers. The high-pin-count packages can integrate  
multiple 32-bit buses into a single device. Table 3 shows FLEX 8000  
performance and LE requirements for typical applications.  
Table 3. FLEX 8000 Performance  
Application  
LEs Used  
Speed Grade  
A-3  
Units  
A-2  
A-4  
16  
16  
24  
4
16-bit loadable counter  
16-bit up/down counter  
24-bit accumulator  
125  
125  
87  
95  
95  
83  
83  
MHz  
MHz  
MHz  
ns  
67  
58  
16-bit address decode  
16-to-1 multiplexer  
4.2  
6.6  
4.9  
7.9  
6.3  
9.5  
10  
ns  
3
All FLEX 8000 device packages provide four dedicated inputs for  
synchronous control signals with large fan-outs. Each I/O pin has an  
associated register on the periphery of the device. As outputs, these  
registers provide fast clock-to-output times; as inputs, they offer quick  
setup times.  
The logic and interconnections in the FLEX 8000 architecture are  
configured with CMOS SRAM elements. FLEX 8000 devices are  
configured at system power-up with data stored in an industry-standard  
parallel EPROM or an Altera serial configuration devices, or with data  
provided by a system controller. Altera offers the EPC1, EPC1213,  
EPC1064, and EPC1441 configuration devices, which configure  
FLEX 8000 devices via a serial data stream. Configuration data can also be  
stored in an industry-standard 32 K × 8 bit or larger configuration device,  
or downloaded from system RAM. After a FLEX 8000 device has been  
configured, it can be reconfigured in-circuit by resetting the device and  
loading new data. Because reconfiguration requires less than 100 ms, real-  
time changes can be made during system operation. For information on  
how to configure FLEX 8000 devices, go to the following documents:  
■
■
■
■
■
Configuration Devices for APEX & FLEX Devices Data Sheet  
BitBlaster Serial Download Cable Data Sheet  
ByteBlasterMV Parallel Port Download Cable Data Sheet  
Application Note 33 (Configuring FLEX 8000 Devices)  
Application Note 38 (Configuring Multiple FLEX 8000 Devices)  
Altera Corporation  
3
FLEX 8000 Programmable Logic Device Family Data Sheet  
FLEX 8000 devices contain an optimized microprocessor interface that  
permits the microprocessor to configure FLEX 8000 devices serially, in  
parallel, synchronously, or asynchronously. The interface also enables the  
microprocessor to treat a FLEX 8000 device as memory and configure the  
device by writing to a virtual memory location, making it very easy for the  
designer to create configuration software.  
The FLEX 8000 family is supported by Altera’s MAX+PLUS II  
development system, a single, integrated package that offers schematic,  
text—including the Altera Hardware Description Language (AHDL),  
VHDL, and Verilog HDL—and waveform design entry, compilation and  
logic synthesis, simulation and timing analysis, and device programming.  
The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, library of  
parameterized modules (LPM), VHDL, Verilog HDL, and other interfaces  
for additional design entry and simulation support from other industry-  
standard PC- and UNIX workstation-based EDA tools. The  
MAX+PLUS II software runs on Windows-based PCs and Sun  
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000  
workstations.  
The MAX+PLUS II software interfaces easily with common gate array  
EDA tools for synthesis and simulation. For example, the MAX+PLUS II  
software can generate Verilog HDL files for simulation with tools such as  
Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains  
EDA libraries that use device-specific features such as carry chains, which  
are used for fast counter and arithmetic functions. For instance, the  
Synopsys Design Compiler library supplied with the MAX+PLUS II  
development system includes DesignWare functions that are optimized  
for the FLEX 8000 architecture.  
For more information on the MAX+PLUS II software, go to the  
MAX+PLUS II Programmable Logic Development System & Software Data  
Sheet.  
f
The FLEX 8000 architecture incorporates a large matrix of compact  
building blocks called logic elements (LEs). Each LE contains a 4-input  
LUT that provides combinatorial logic capability and a programmable  
register that offers sequential logic capability. The fine-grained structure  
of the LE provides highly efficient logic implementation.  
Functional  
Description  
Eight LEs are grouped together to form a logic array block (LAB). Each  
FLEX 8000 LAB is an independent structure with common inputs,  
interconnections, and control signals. The LAB architecture provides a  
coarse-grained structure for high device performance and easy routing.  
4
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 1 shows a block diagram of the FLEX 8000 architecture. Each group  
of eight LEs is combined into an LAB; LABs are arranged into rows and  
columns. The I/O pins are supported by I/O elements (IOEs) located at  
the ends of rows and columns. Each IOE contains a bidirectional I/O  
buffer and a flipflop that can be used as either an input or output register.  
Figure 1. FLEX 8000 Device Block Diagram  
IOE  
IOE  
IOE  
IOE  
I/O Element  
(IOE)  
IOE  
IOE  
IOE  
IOE  
FastTrack  
Interconnect  
Logic Array  
Block (LAB)  
3
IOE  
IOE  
IOE  
IOE  
Logic  
Element (LE)  
IOE  
IOE  
IOE  
IOE  
Signal interconnections within FLEX 8000 devices and between device  
pins are provided by the FastTrack Interconnect, a series of fast,  
continuous channels that run the entire length and width of the device.  
IOEs are located at the end of each row (horizontal) and column (vertical)  
FastTrack Interconnect path.  
Altera Corporation  
5
FLEX 8000 Programmable Logic Device Family Data Sheet  
Logic Array Block  
A logic array block (LAB) consists of eight LEs, their associated carry and  
cascade chains, LAB control signals, and the LAB local interconnect. The  
LAB provides the coarse-grained structure of the FLEX 8000 architecture.  
This structure enables FLEX 8000 devices to provide efficient routing,  
high device utilization, and high performance. Figure 2 shows a block  
diagram of the FLEX 8000 LAB.  
Figure 2. FLEX 8000 Logic Array Block  
Dedicated  
Inputs  
Row Interconnect  
24  
4
8
LAB Local  
Interconnect  
(32 channels)  
4
See Figure 8  
for details.  
Carry-In and  
Cascade-In  
from LAB  
on Left  
8
16  
LAB Control  
Signals  
4
2
Column-to-Row  
Interconnect  
LE1  
4
4
4
4
4
4
4
4
Column  
Interconnect  
LE2  
LE3  
LE4  
LE5  
LE6  
LE7  
LE8  
8
2
Carry-Out and  
Cascade-Out  
to LAB on Right  
6
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Each LAB provides four control signals that can be used in all eight LEs.  
Two of these signals can be used as clocks, and the other two for  
clear/preset control. The LAB control signals can be driven directly from  
a dedicated input pin, an I/O pin, or any internal signal via the LAB local  
interconnect. The dedicated inputs are typically used for global clock,  
clear, or preset signals because they provide synchronous control with  
very low skew across the device. FLEX 8000 devices support up to four  
individual global clock, clear, or preset control signals. If logic is required  
on a control signal, it can be generated in one or more LEs in any LAB and  
driven into the local interconnect of the target LAB.  
Logic Element  
The logic element (LE) is the smallest unit of logic in the FLEX 8000  
architecture, with a compact size that provides efficient logic utilization.  
Each LE contains a 4-input LUT, a programmable flipflop, a carry chain,  
and cascade chain. Figure 3 shows a block diagram of an LE.  
Figure 3. FLEX 8000 LE  
3
Carry-In  
Cascade-In  
DFF  
PRN  
DATA1  
DATA2  
DATA3  
DATA4  
Look-Up  
Table  
(LUT)  
LE-Out  
Carry  
Chain  
Cascade  
Chain  
D
Q
CLRN  
Clear/  
Preset  
Logic  
LABCTRL1  
LABCTRL2  
Clock  
Select  
LABCTRL3  
LABCTRL4  
Carry-Out  
Cascade-Out  
The LUT is a function generator that can quickly compute any function of  
four variables. The programmable flipflop in the LE can be configured for  
D, T, JK, or SR operation. The clock, clear, and preset control signals on the  
flipflop can be driven by dedicated input pins, general-purpose I/O pins,  
or any internal logic. For purely combinatorial functions, the flipflop is  
bypassed and the output of the LUT goes directly to the output of the LE.  
Altera Corporation  
7
FLEX 8000 Programmable Logic Device Family Data Sheet  
The FLEX 8000 architecture provides two dedicated high-speed data  
paths—carry chains and cascade chains—that connect adjacent LEs  
without using local interconnect paths. The carry chain supports high-  
speed counters and adders; the cascade chain implements wide-input  
functions with minimum delay. Carry and cascade chains connect all LEs  
in an LAB and all LABs in the same row. Heavy use of carry and cascade  
chains can reduce routing flexibility. Therefore, the use of carry and  
cascade chains should be limited to speed-critical portions of a design.  
Carry Chain  
The carry chain provides a very fast (less than 1 ns) carry-forward  
function between LEs. The carry-in signal from a lower-order bit moves  
forward into the higher-order bit via the carry chain, and feeds into both  
the LUT and the next portion of the carry chain. This feature allows the  
FLEX 8000 architecture to implement high-speed counters and adders of  
arbitrary width. The MAX+PLUS II Compiler can create carry chains  
automatically during design processing; designers can also insert carry  
chain logic manually during design entry.  
Figure 4 shows how an n-bit full adder can be implemented in n + 1 LEs  
with the carry chain. One portion of the LUT generates the sum of two bits  
using the input signals and the carry-in signal; the sum is routed to the  
output of the LE. The register is typically bypassed for simple adders, but  
can be used for an accumulator function. Another portion of the LUT and  
the carry chain logic generate the carry-out signal, which is routed directly  
to the carry-in signal of the next-higher-order bit. The final carry-out  
signal is routed to another LE, where it can be used as a general-purpose  
signal. In addition to mathematical functions, carry chain logic supports  
very fast counters and comparators.  
8
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 4. FLEX 8000 Carry Chain Operation  
Carry-In  
LU  
s1  
Register  
a1  
b1  
Carry  
LE1  
a2  
b2  
s2  
LUT  
Register  
Carry Chain  
LE2  
3
LUT  
sn  
an  
bn  
Register  
Carry Chain  
LEn  
LUT  
Carry-Out  
Register  
Carry Chain  
LEn + 1  
Cascade Chain  
With the cascade chain, the FLEX 8000 architecture can implement  
functions that have a very wide fan-in. Adjacent LUTs can be used to  
compute portions of the function in parallel; the cascade chain serially  
connects the intermediate values. The cascade chain can use a logical AND  
or logical OR(via De Morgan’s inversion) to connect the outputs of  
adjacent LEs. Each additional LE provides four more inputs to the  
effective width of a function, with a delay as low as 0.6 ns per LE.  
Altera Corporation  
9
FLEX 8000 Programmable Logic Device Family Data Sheet  
The MAX+PLUS II Compiler can create cascade chains automatically  
during design processing; designers can also insert cascade chain logic  
manually during design entry. Cascade chains longer than eight LEs are  
automatically implemented by linking LABs together. The last LE of an  
LAB cascades to the first LE of the next LAB.  
Figure 5 shows how the cascade function can connect adjacent LEs to  
form functions with a wide fan-in. These examples show functions of 4n  
variables implemented with n LEs. For a device with an A-2 speed grade,  
the LE delay is 2.4 ns; the cascade chain delay is 0.6 ns. With the cascade  
chain, 4.2 ns is needed to decode a 16-bit address.  
Figure 5. FLEX 8000 Cascade Chain Operation  
AND Cascade Chain  
OR Cascade Chain  
LE1  
LE2  
LE1  
LE2  
d[3..0]  
d[3..0]  
LUT  
LUT  
LUT  
LUT  
d[7..4]  
d[7..4]  
LEn  
LEn  
d[(4n-1)..4(n-1)]  
d[(4n-1)..4(n-1)]  
LUT  
LUT  
LE Operating Modes  
The FLEX 8000 LE can operate in one of four modes, each of which uses  
LE resources differently. See Figure 6. In each mode, seven of the ten  
available inputs to the LE—the four data inputs from the LAB local  
interconnect, the feedback from the programmable register, and the  
carry-in and cascade-in from the previous LE—are directed to different  
destinations to implement the desired logic function. The three remaining  
inputs to the LE provide clock, clear, and preset control for the register.  
The MAX+PLUS II software automatically chooses the appropriate mode  
for each application. Design performance can also be enhanced by  
designing for the operating mode that supports the desired application.  
10  
Altera Corporation  
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 6. FLEX 8000 LE Operating Modes  
Normal Mode  
Cascade-In  
LE-Out  
Carry-In  
PRN  
data1  
data2  
4-Input  
D
Q
LUT  
data3  
CLRN  
Cascade-Out  
data4  
Arithmetic Mode  
Carry-In  
Cascade-In  
LE-Out  
PRN  
D
Q
data1  
3-Input  
LUT  
data2  
CLRN  
Cascade-Out  
3-Input  
LUT  
3
Carry-Out  
Up/Down Counter Mode  
Cascade-In  
Carry-In  
(ena)  
(nclr)  
data1  
data2  
PRN  
3-Input  
LUT  
1
0
LE-Out  
D
Q
(data)  
data3  
CLRN  
3-Input  
LUT  
data4 (nload)  
Carry-Out  
Cascade-Out  
Clearable Counter Mode  
Carry-In  
(ena)  
(nclr)  
data1  
data2  
PRN  
3-Input  
LUT  
1
LE-Out  
D
Q
0
data3 (data)  
CLRN  
3-Input  
LUT  
(nload)  
data4  
Carry-Out  
Cascade-Out  
Altera Corporation  
11  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Normal Mode  
The normal mode is suitable for general logic applications and wide  
decoding functions that can take advantage of a cascade chain. In normal  
mode, four data inputs from the LAB local interconnect and the carry-in  
signal are the inputs to a 4-input LUT. Using a configurable SRAM bit, the  
MAX+PLUS II Compiler automatically selects the carry-in or the DATA3  
signal as an input. The LUT output can be combined with the cascade-in  
signal to form a cascade chain through the cascade-out signal. TheLE-Out  
signal—the data output of the LE—is either the combinatorial output of  
the LUT and cascade chain, or the data output (Q)of the programmable  
register.  
Arithmetic Mode  
The arithmetic mode offers two 3-input LUTs that are ideal for  
implementing adders, accumulators, and comparators. One LUT  
provides a 3-bit function; the other generates a carry bit. As shown in  
Figure 6, the first LUT uses the carry-in signal and two data inputs from  
the LAB local interconnect to generate a combinatorial or registered  
output. For example, in an adder, this output is the sum of three bits: a, b,  
and the carry-in. The second LUT uses the same three signals to generate  
a carry-out signal, thereby creating a carry chain. The arithmetic mode  
also supports a cascade chain.  
Up/Down Counter Mode  
The up/down counter mode offers counter enable, synchronous  
up/down control, and data loading options. These control signals are  
generated by the data inputs from the LAB local interconnect, the carry-in  
signal, and output feedback from the programmable register. Two 3-input  
LUTs are used: one generates the counter data, and the other generates the  
fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data  
can also be loaded asynchronously with the clear and preset register  
control signals, without using the LUT resources.  
Clearable Counter Mode  
The clearable counter mode is similar to the up/down counter mode, but  
supports a synchronous clear instead of the up/down control; the clear  
function is substituted for the cascade-in signal in the up/down counter  
mode. Two 3-input LUTs are used: one generates the counter data, and  
the other generates the fast carry bit. Synchronous loading is provided by  
a 2-to-1 multiplexer, and the output of this multiplexer is ANDed with a  
synchronous clear.  
12  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Internal Tri-State Emulation  
Internal tri-state emulation provides internal tri-stating without the  
limitations of a physical tri-state bus. In a physical tri-state bus, the  
tri-state buffers’ output enable signals select the signal that drives the bus.  
However, if multiple output enable signals are active, contending signals  
can be driven onto the bus. Conversely, if no output enable signals are  
active, the bus will float. Internal tri-state emulation resolves contending  
tri-state buffers to a low value and floating buses to a high value, thereby  
eliminating these problems. The MAX+PLUS II software automatically  
implements tri-state bus functionality with a multiplexer.  
Clear & Preset Logic Control  
Logic for the programmable register’s clear and preset functions is  
controlled by the DATA3, LABCTRL1, and LABCTRL2inputs to the LE. The  
clear and preset control structure of the LE is used to asynchronously load  
signals into a register. The register can be set up so that LABCTRL1  
implements an asynchronous load. The data to be loaded is driven to  
DATA3; when LABCTRL1is asserted, DATA3is loaded into the register.  
3
During compilation, the MAX+PLUS II Compiler automatically selects  
the best control signal implementation. Because the clear and preset  
functions are active-low, the Compiler automatically assigns a logic high  
to an unused clear or preset.  
The clear and preset logic is implemented in one of the following six  
asynchronous modes, which are chosen during design entry. LPM  
functions that use registers will automatically use the correct  
asynchronous mode. See Figure 7.  
■
■
■
■
■
■
Clear only  
Preset only  
Clear and preset  
Load with clear  
Load with preset  
Load without clear or preset  
Altera Corporation  
13  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 7. FLEX 8000 LE Asynchronous Clear & Preset Modes  
Asynchronous Clear  
Asynchronous Clear & Preset  
Asynchronous Preset  
VCC  
PRN  
LABCTRL1 or  
LABCTRL2  
LABCTRL1  
PRN  
PRN  
Q
D
Q
D
Q
D
CLRN  
CLRN  
CLRN  
LABCTRL1 or  
LABCTRL2  
LABCTRL2  
Asynchronous Load with Clear  
NOT  
NOT  
LABCTRL1  
(Asynchronous  
Load)  
PRN  
DATA3  
(Data)  
Q
D
CLRN  
LABCTRL2  
(Clear)  
Asynchronous Load with Preset  
NOT  
LABCTRL1  
(Asynchronous  
Load)  
LABCTRL2  
(Preset)  
PRN  
Q
D
DATA3  
(Data)  
CLRN  
NOT  
Asynchronous Load without Clear or Preset  
NOT  
LABCTRL1  
(Asynchronous  
Load)  
PRN  
DATA3  
(Data)  
Q
D
CLRN  
NOT  
14  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Asynchronous Clear  
A register is cleared by one of the two LABCTRLsignals. When the CLRn  
port receives a low signal, the register is set to zero.  
Asynchronous Preset  
An asynchronous preset is implemented as either an asynchronous load  
or an asynchronous clear. If DATA3is tied to VCC, asserting LABCTRLl  
asynchronously loads a 1into the register. Alternatively, the  
MAX+PLUS II software can provide preset control by using the clear and  
inverting the input and output of the register. Inversion control is  
available for the inputs to both LEs and IOEs. Therefore, if a register is  
preset by only one of the two LABCTRLsignals, the DATA3input is not  
needed and can be used for one of the LE operating modes.  
Asynchronous Clear & Preset  
When implementing asynchronous clear and preset, LABCTRL1controls  
the preset and LABCTRL2controls the clear. The DATA3input istied to VCC;  
therefore, asserting LABCTRL1asynchronously loads a 1into the register,  
effectively presetting the register. Asserting LABCTRL2clears the register.  
3
Asynchronous Load with Clear  
When implementing an asynchronous load with the clear, LABCTRL1  
implements the asynchronous load of DATA3by controlling the register  
preset and clear. LABCTRL2implements the clear by controlling the  
register clear.  
Asynchronous Load with Preset  
When implementing an asynchronous load in conjunction with a preset,  
the MAX+PLUS II software provides preset control by using the clear and  
inverting the input and output of the register. Asserting LABCTRL2clears  
the register, while asserting LABCTRL1loads the register. The  
MAX+PLUS II software inverts the signal that drives the DATA3signal to  
account for the inversion of the register’s output.  
Asynchronous Load without Clear or Preset  
When implementing an asynchronous load without the clear or preset,  
LABCTRL1implements the asynchronous load of DATA3by controlling the  
register preset and clear.  
Altera Corporation  
15  
FLEX 8000 Programmable Logic Device Family Data Sheet  
FastTrack Interconnect  
In the FLEX 8000 architecture, connections between LEs and device I/O  
pins are provided by the FastTrack Interconnect, a series of continuous  
horizontal (row) and vertical (column) routing channels that traverse the  
entire FLEX 8000 device. This device-wide routing structure provides  
predictable performance even in complex designs. In contrast, the  
segmented routing structure in FPGAs requires switch matrices to  
connect a variable number of routing paths, which increases the delays  
between logic resources and reduces performance.  
The LABs within FLEX 8000 devices are arranged into a matrix of  
columns and rows. Each row of LABs has a dedicated row interconnect  
that routes signals both into and out of the LABs in the row. The row  
interconnect can then drive I/O pins or feed other LABs in the device.  
Figure 8 shows how an LE drives the row and column interconnect.  
Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect  
16 Column  
Channels  
Row Channels  
(1)  
Each LE drives one  
row channel.  
LE1  
LE2  
to Local  
Feedback Feedback  
to Local  
Each LE drives up to  
two column channels.  
Note:  
(1) See Table 4 for the number of row channels.  
16  
Altera Corporation  
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
Each LE in an LAB can drive up to two separate column interconnect  
channels. Therefore, all 16 available column channels can be driven by the  
LAB. The column channels run vertically across the entire device, and  
share access to LABs in the same column but in different rows. The  
MAX+PLUS II Compiler chooses which LEs must be connected to a  
column channel. A row interconnect channel can be fed by the output of  
the LE or by two column channels. These three signals feed a multiplexer  
that connects to a specific row channel. Each LE is connected to one 3-to-1  
multiplexer. In an LAB, the multiplexers provide all 16 column channels  
with access to 8 row channels.  
Each column of LABs has a dedicated column interconnect that routes  
signals out of the LABs into the column. The column interconnect can then  
drive I/O pins or feed into the row interconnect to route the signals to  
other LABs in the device. A signal from the column interconnect, which  
can be either the output of an LE or an input from an I/O pin, must  
transfer to the row interconnect before it can enter an LAB. Table 4  
summarizes the FastTrack Interconnect resources available in each  
FLEX 8000 device.  
3
Table 4. FLEX 8000 FastTrack Interconnect Resources  
Device  
Rows Channels per Row Columns Channels per Column  
EPF8282A  
2
168  
13  
16  
EPF8282AV  
EPF8452A  
EPF8636A  
EPF8820A  
EPF81188A  
EPF81500A  
2
3
4
6
6
168  
168  
168  
168  
216  
21  
21  
21  
21  
27  
16  
16  
16  
16  
16  
Figure 9 shows the interconnection of four adjacent LABs, with row,  
column, and local interconnects, as well as the associated cascade and  
carry chains.  
Altera Corporation  
17  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 9. FLEX 8000 Device Interconnect Resources  
Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device.  
See Figure 12  
for details.  
IOE  
IOE  
IOE  
IOE  
Column  
Interconnect  
See Figure 11  
for details.  
Row  
Interconnect  
1
IOE  
IOE  
IOE  
1
8
8 IOE  
LAB  
A1  
LAB  
A2  
1
IOE  
IOE  
IOE  
1
8
8 IOE  
LAB  
B1  
LAB  
B2  
LAB Local  
Interconnect  
Cascade &  
Carry Chain  
IOE  
IOE  
IOE  
IOE  
I/O Element  
An IOE contains a bidirectional I/O buffer and a register that can be used  
either as an input register for external data that requires a fast setup time,  
or as an output register for data that requires fast clock-to-output  
performance. IOEs can be used as input, output, or bidirectional pins. The  
MAX+PLUS II Compiler uses the programmable inversion option to  
automatically invert signals from the row and column interconnect where  
appropriate. Figure 10 shows the IOE block diagram.  
18  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 10. FLEX 8000 IOE  
Numbers in parentheses are for EPF81500A devices only.  
I/O Controls  
6
To Row or Column  
Interconnect  
Programmable  
Inversion  
(6)  
VCC  
From Row or Column  
Interconnect  
D
Q
Slew-Rate  
Control  
CLRN  
VCC  
3
Row-to-IOE Connections  
Figure 11 illustrates the connection between row interconnect channels  
and IOEs. An input signal from an IOE can drive two separate row  
channels. When an IOE is used as an output, the signal is driven by an  
n-to-1 multiplexer that selects the row channels. The size of the  
multiplexer varies with the number of columns in a device. EPF81500A  
devices use a 27-to-1 multiplexer; EPF81188A, EPF8820A, EPF8636A, and  
EPF8452A devices use a 21-to-1 multiplexer; and EPF8282A and  
EPF8282AV devices use a 13-to-1 multiplexer. Eight IOEs are connected to  
each side of the row channels.  
Altera Corporation  
19  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 11. FLEX 8000 Row-to-IOE Connections  
Numbers in parentheses are for EPF81500A devices. See Note (1).  
2
2
2
2
IOE 1  
IOE 2  
IOE 3  
IOE 4  
IOE 5  
IOE 6  
IOE 7  
IOE 8  
n
Each IOE can drive  
up to two row  
channels.  
n
n
n
n
n
n
n
2
2
2
2
Row Interconnect  
168  
(216)  
168  
(216)  
2
2
2
2
Each IOE is  
driven by an  
n-to-1  
multiplexer.  
2
2
2
2
Note:  
(1) n = 13 for EPF8282A and EPF8282AV devices.  
n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices.  
n = 27 for EPF81500A devices.  
Column-to-IOE Connections  
Two IOEs are located at the top and bottom of the column channels (see  
Figure 12). When an IOE is used as an input, it can drive up to two  
separate column channels. The output signal to an IOE can choose from 8  
of the 16 column channels through an 8-to-1 multiplexer.  
20  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 12. FLEX 8000 Column-to-IOE Connections  
Each IOE is  
driven by an  
8-to-1  
Each IOE can drive  
up to two column  
signals.  
IOE  
IOE  
multiplexer.  
8
8
16  
Column Interconnect  
In addition to general-purpose I/O pins, FLEX 8000 devices have four  
dedicated input pins. These dedicated inputs provide low-skew, device-  
wide signal distribution, and are typically used for global clock, clear, and  
preset control signals. The signals from the dedicated inputs are available  
as control signals for all LABs and I/O elements in the device. The  
dedicated inputs can also be used as general-purpose data inputs because  
they can feed the local interconnect of each LAB in the device.  
3
Signals enter the FLEX 8000 device either from the I/O pins that provide  
general-purpose input capability or from the four dedicated inputs. The  
IOEs are located at the ends of the row and column interconnect channels.  
I/O pins can be used as input, output, or bidirectional pins. Each I/O pin  
has a register that can be used either as an input register for external data  
that requires fast setup times, or as an output register for data that  
requires fast clock-to-output performance. The MAX+PLUS II Compiler  
uses the programmable inversion option to invert signals automatically  
from the row and column interconnect when appropriate.  
The clock, clear, and output enable controls for the IOEs are provided by  
a network of I/O control signals. These signals can be supplied by either  
the dedicated input pins or by internal logic. The IOE control-signal paths  
are designed to minimize the skew across the device. All control-signal  
sources are buffered onto high-speed drivers that drive the signals around  
the periphery of the device. This “peripheral bus” can be configured to  
provide up to four output enable signals (10 in EPF81500A devices), and  
up to two clock or clear signals. Figure 13 on page 22 shows how two  
output enable signals are shared with one clock and one clear signal.  
Altera Corporation  
21  
FLEX 8000 Programmable Logic Device Family Data Sheet  
The signals for the peripheral bus can be generated by any of the four  
dedicated inputs or signals on the row interconnect channels, as shown in  
Figure 13. The number of row channels in a row that can drive the  
peripheral bus correlates to the number of columns in the FLEX 8000  
device. EPF8282A and EPF8282AV devices use 13 channels; EPF8452A,  
EPF8636A, EPF8820A, and EPF81188A devices use 21 channels; and  
EPF81500A devices use 27 channels. The first LE in each LAB is the source  
of the row channel signal. The six peripheral control signals (12 in  
EPF81500A devices) can be accessed by each IOE.  
Figure 13. FLEX 8000 Peripheral Bus  
Numbers in parentheses are for EPF81500A devices.  
Peripheral Control  
Signals  
Programmable  
Inversion  
4
Dedicated  
Inputs  
1
2
Row Channels  
(1)  
n
Note:  
(1) n = 13 for EPF8282A and EPF8282AV devices.  
n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices.  
n = 27 for EPF81500A devices.  
22  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 5 lists the source of the peripheral control signal for each FLEX 8000  
device by row.  
Table 5. Row Sources of FLEX 8000 Peripheral Control Signals  
Peripheral  
Control Signal EPF8282AV  
EPF8282A  
EPF8452A  
EPF8636A  
EPF8820A  
EPF81188A  
EPF81500A  
CLK0  
CLK1/OE1  
CLR0  
CLR1/OE0  
OE2  
Row A  
Row A  
Row A  
Row A  
Row E  
Row E  
Row B  
Row F  
Row C  
Row A  
Row A  
Row B  
Row C  
Row D  
Row D  
Row E  
Row F  
Row B  
Row B  
Row C  
Row C  
Row B  
Row A  
Row A  
Row B  
Row B  
Row F  
Row B  
Row B  
Row C  
Row D  
Row C  
Row A  
Row A  
Row A  
Row A  
Row D  
OE3  
Row B  
Row B  
Row B  
Row B  
Row A  
OE4  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
OE5  
OE6  
3
OE7  
OE8  
OE9  
This section discusses slew-rate control and MultiVolt I/O interface  
operation for FLEX 8000 devices.  
Output  
Configuration  
Slew-Rate Control  
The output buffer in each IOE has an adjustable output slew rate that can  
be configured for low-noise or high-speed performance. A slow slew rate  
reduces system noise by slowing signal transitions, adding a maximum  
delay of 3.5 ns. The slow slew-rate setting affects only the falling edge of  
a signal. The fast slew rate should be used for speed-critical outputs in  
systems that are adequately protected against noise. Designers can specify  
the slew rate on a pin-by-pin basis during design entry or assign a default  
slew rate to all pins on a global basis.  
For more information on high-speed system design, go to Application  
Note 75 (High-Speed Board Designs).  
f
Altera Corporation  
23  
FLEX 8000 Programmable Logic Device Family Data Sheet  
MultiVolt I/O Interface  
The FLEX 8000 device architecture supports the MultiVolt I/O interface  
feature, which allows EPF81500A, EPF81188A, EPF8820A, and EPF8636A  
devices to interface with systems with differing supply voltages. These  
devices in all packages—except for EPF8636A devices in 84-pin PLCC  
packages—can be set for 3.3-V or 5.0-V I/O pin operation. These devices  
have one set of VCC pins for internal operation and input buffers  
(VCCINT), and another set for I/O output drivers (VCCIO).  
The VCCINTpins must always be connected to a 5.0-V power supply. With  
a 5.0-V VCCINT level, input voltages are at TTL levels and are therefore  
compatible with 3.3-V and 5.0-V inputs.  
The VCCIOpins can be connected to either a 3.3-V or 5.0-V power supply,  
depending on the output requirements. When the VCCIOpins are  
connected to a 5.0-V power supply, the output levels are compatible with  
5.0-V systems. When the VCCIOpins are connected to a 3.3-V power  
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V  
or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V  
incur a nominally greater timing delay of tOD2 instead of tOD1. See Table 8  
on page 26.  
The EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A  
devices provide JTAG BST circuitry. FLEX 8000 devices with JTAG  
circuitry support the JTAG instructions shown in Table 6.  
IEEE Std.  
1149.1 (JTAG)  
Boundary-Scan  
Support  
Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions  
JTAG Instruction Description  
SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during  
normal device operation, and permits an initial data pattern to be output at the device pins.  
EXTEST  
Allows the external circuitry and board-level interconnections to be tested by forcing a test  
pattern at the output pins and capturing test results at the input pins.  
BYPASS  
Places the 1-bit bypass register between the TDIand TDOpins, which allows the BST  
data to pass synchronously through the selected device to adjacent devices during  
normal device operation.  
24  
Altera Corporation  
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
The instruction register length for FLEX 8000 devices is three bits. Table 7  
shows the boundary-scan register length for FLEX 8000 devices.  
Table 7. FLEX 8000 Boundary-Scan Register Length  
Device  
Boundary-Scan Register Length  
EPF8282A, EPF8282AV  
EPF8636A  
273  
417  
465  
645  
EPF8820A  
EPF81500A  
FLEX 8000 devices that support JTAG include weak pull-ups on the JTAG  
pins. Figure 14 shows the timing requirements for the JTAG signals.  
Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A  
JTAG Waveforms  
TMS  
3
TDI  
tJCP  
tJCH  
tJCL  
tJPH  
tJPSU  
TCK  
TDO  
t
tJPXZ  
tJPCO  
JPZX  
tJSSU  
tJSH  
Signal  
to Be  
Captured  
tJSCO  
tJSXZ  
tJSZX  
Signal  
to Be  
Driven  
Table 8 shows the timing parameters and values for EPF8282A,  
EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices.  
Altera Corporation  
25  
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 8. JTAG Timing Parameters & Values  
Symbol  
Parameter  
EPF8282A  
EPF8282AV  
EPF8636A  
EPF8820A  
EPF81500A  
Unit  
Min Max  
tJCP  
TCKclock period  
TCKclock high time  
TCKclock low time  
100  
50  
50  
20  
45  
25  
25  
25  
20  
45  
35  
35  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tJCH  
tJCL  
tJPSU  
tJPH  
JTAG port setup time  
JTAG port hold time  
tJPCO  
tJPZX  
tJPXZ  
tJSSU  
tJSH  
JTAG port clock to output  
JTAG port high-impedance to valid output  
JTAG port valid output to high-impedance  
Capture register setup time  
Capture register hold time  
tJSCO  
tJSZX  
tJSXZ  
Update register clock to output  
Update register high-impedance to valid output  
Update register valid output to high-impedance  
For detailed information on JTAG operation in FLEX 8000 devices, refer to  
Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera  
Devices).  
f
Each FLEX 8000 device is functionally tested and specified by Altera.  
Complete testing of each configurable SRAM bit and all logic  
functionality ensures 100% configuration yield. AC test measurements for  
FLEX 8000 devices are made under conditions equivalent to those shown  
in Figure 15. Designers can use multiple test patterns to configure devices  
during all stages of the production flow.  
Generic Testing  
26  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 15. FLEX 8000 AC Test Conditions  
Power supply transients can affect AC  
measurements. Simultaneous transitions  
of multiple outputs should be avoided for  
accurate measurement. Threshold tests  
must not be performed under AC  
VCC  
464 Ω  
(703 Ω)  
conditions. Large-amplitude, fast-ground-  
current transients normally occur as the  
device outputs discharge the load  
capacitances. When these transients flow  
through the parasitic inductance between  
the device ground pin and the test system  
ground, significant reductions in  
Device  
Output  
To Test  
System  
250 Ω  
(8.06 KΩ)  
C1 (includes  
JIG capacitance)  
observable noise immunity can result.  
Numbers in parentheses are for 3.3-V  
devices or outputs. Numbers without  
parentheses are for 5.0-V devices or  
outputs.  
Device input  
rise and fall  
times < 3 ns  
Tables 9 through 12 provide information on absolute maximum ratings,  
recommended operating conditions, operating conditions, and  
capacitance for 5.0-V FLEX 8000 devices.  
Operating  
Conditions  
3
Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings  
Note (1)  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
VCC  
VI  
Supply voltage  
With respect to ground (2)  
–2.0  
–2.0  
–25  
–65  
–65  
7.0  
7.0  
V
DC input voltage  
V
IOUT  
TSTG  
TAMB  
TJ  
DC output current, per pin  
Storage temperature  
Ambient temperature  
Junction temperature  
25  
mA  
° C  
° C  
° C  
° C  
No bias  
150  
135  
150  
135  
Under bias  
Ceramic packages, under bias  
PQFP and RQFP, under bias  
Altera Corporation  
27  
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
VCCINT Supply voltage for internal logic (3), (4)  
4.75 (4.50)  
5.25 (5.50)  
V
and input buffers  
VCCIO Supply voltage for output  
buffers, 5.0-V operation  
(3), (4)  
(3), (4)  
4.75 (4.50)  
3.00 (3.00)  
5.25 (5.50)  
3.60 (3.60)  
V
V
Supply voltage for output  
buffers, 3.3-V operation  
VI  
Input voltage  
–0.5  
0
VCCINT + 0.5  
V
V
VO  
TA  
Output voltage  
VCCIO  
70  
Operating temperature  
For commercial use  
For industrial use  
0
° C  
° C  
ns  
ns  
–40  
85  
tR  
tF  
Input rise time  
Input fall time  
40  
40  
Table 11. FLEX 8000 5.0-V Device DC Operating Conditions  
Notes (5), (6)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
VIH  
VIL  
High-level input voltage  
Low-level input voltage  
2.0  
–0.5  
2.4  
VCCINT + 0.5  
0.8  
V
V
V
VOH  
5.0-V high-level TTL output  
voltage  
IOH = –4 mA DC (7)  
VCCIO = 4.75 V  
3.3-V high-level TTL output  
voltage  
I
OH = –4 mA DC (7)  
2.4  
V
V
V
V
V
VCCIO = 3.00 V  
3.3-V high-level CMOS output IOH = –0.1 mA DC (7)  
voltage  
VCCIO – 0.2  
VCCIO = 3.00 V  
VOL  
5.0-V low-level TTL output  
voltage  
IOL = 12 mA DC (7)  
VCCIO = 4.75 V  
0.45  
0.45  
0.2  
3.3-V low-level TTL output  
voltage  
IOL = 12 mA DC (7)  
VCCIO = 3.00 V  
3.3-V low-level CMOS output IOL = 0.1 mA DC (7)  
voltage  
VCCIO = 3.00 V  
II  
Input leakage current  
VI = VCC or ground  
VO = VCC or ground  
–10  
–40  
10  
40  
µA  
µA  
IOZ  
Tri-state output off-state  
current  
ICC0  
VCC supply current (standby) VI = ground, no load  
0.5  
10  
mA  
28  
Altera Corporation  
 
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 12. FLEX 8000 5.0-V Device Capacitance  
Note (8)  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
CIN  
Input capacitance  
VIN = 0 V, f = 1.0 MHz  
VOUT = 0 V, f = 1.0 MHz  
10  
10  
pF  
pF  
COUT  
Output capacitance  
Notes to tables:  
(1) See the Operating Requirements for Altera Devices Data Sheet.  
(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for input  
currents less than 100 mA and periods shorter than 20 ns.  
(3) The maximum V  
rise time is 100 ms.  
CC  
(4) Numbers in parentheses are for industrial-temperature-range devices.  
(5) Typical values are for T = 25° C and V = 5.0 V.  
A
CC  
(6) These values are specified in Table 10 on page 28.  
(7) The I parameter refers to high-level TTL or CMOS output current; the I parameter refers to low-level TTL or  
OH  
OL  
CMOS output current.  
(8) Capacitance is sample-tested only.  
Tables 13 through 16 provide information on absolute maximum ratings,  
recommended operating conditions, operating conditions, and  
capacitance for 3.3-V FLEX 8000 devices.  
3
Table 13. FLEX 8000 3.3-V Device Absolute Maximum Ratings  
Note (1)  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
VCC  
VI  
Supply voltage  
With respect to ground (2)  
–2.0  
–2.0  
–25  
–65  
–65  
5.3  
5.3  
25  
V
DC input voltage  
V
IOUT  
TSTG  
TAMB  
TJ  
DC output current, per pin  
Storage temperature  
Ambient temperature  
Junction temperature  
mA  
° C  
° C  
° C  
No bias  
150  
135  
135  
Under bias  
Plastic packages, under bias  
Table 14. FLEX 8000 3.3-V Device Recommended Operating Conditions  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
VCC  
VI  
Supply voltage  
(3)  
3.0  
–0.3  
0
3.6  
VCC + 0.3  
VCC  
70  
V
V
Input voltage  
VO  
TA  
tR  
Output voltage  
Operating temperature  
Input rise time  
Input fall time  
V
For commercial use  
0
° C  
ns  
ns  
40  
tF  
40  
Altera Corporation  
29  
 
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 15. FLEX 8000 3.3-V Device DC Operating Conditions  
Note (4)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
VIH  
VIL  
VOH  
VOL  
II  
High-level input voltage  
Low-level input voltage  
High-level output voltage  
Low-level output voltage  
Input leakage current  
2.0  
–0.3  
VCC + 0.3  
0.8  
V
V
IOH = –0.1 mA DC (5)  
IOL = 4 mA DC (5)  
VI = VCC or ground  
VCC – 0.2  
V
0.45  
10  
V
–10  
–40  
µA  
µA  
mA  
IOZ  
ICC0  
Tri-state output off-state current VO = VCC or ground  
VCC supply current (standby) VI = ground, no load (6)  
40  
0.3  
10  
Table 16. FLEX 8000 3.3-V Device Capacitance  
Note (7)  
Conditions  
Symbol  
Parameter  
Min  
Max  
Unit  
CIN  
Input capacitance  
Output capacitance  
VIN = 0 V, f = 1.0 MHz  
VOUT = 0 V, f = 1.0 MHz  
10  
10  
pF  
pF  
COUT  
Notes to tables:  
(1) See the Operating Requirements for Altera Devices Data Sheet.  
(2) Minimum DC input voltage is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.3 V  
for input currents less than 100 mA and periods shorter than 20 ns.  
(3) The maximum V rise time is 100 ms. V must rise monotonically.  
CC  
CC  
(4) These values are specified in Table 14 on page 29.  
(5) The I parameter refers to high-level TTL output current; the I parameter refers to low-level TTL output current.  
OH  
OL  
(6) Typical values are for T = 25° C and V = 3.3 V.  
A
CC  
(7) Capacitance is sample-tested only.  
Figure 16 shows the typical output drive characteristics of 5.0-V  
FLEX 8000 devices. The output driver is compliant with PCI Local Bus  
Specification, Revision 2.2.  
30  
Altera Corporation  
 
 
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 16. Output Drive Characteristics of 5.0-V FLEX 8000 Devices (Except EPF8282A)  
200  
150  
100  
50  
200  
IOL  
IOL  
150  
Typical I  
Output  
Current (mA)  
O
Typical I  
Output  
O
Current (mA)  
V
CCINT = 5.0 V  
V
V
CCINT = 5.0 V  
CCIO = 5.0 V  
100  
VCCIO = 3.3 V  
Room Temperature  
Room Temperature  
IOH  
IOH  
50  
1
2
3
4
1
2
3
4
5
Output Voltage (V)  
Output Voltage (V)  
Figure 17 shows the typical output drive characteristics of 5.0-V  
EPF8282A devices. The output driver is compliant with PCI Local Bus  
Specification, Revision 2.2.  
3
Figure 17. Output Drive Characteristics of EPF8282A Devices with 5.0-V VCCIO  
150  
IOL  
120  
VCC = 5.0 V  
Room Temperature  
Typical I  
Output  
Current (mA)  
O
90  
60  
30  
IOH  
1
2
3
4
5
Output Voltage (V)  
Figure 18 shows the typical output drive characteristics of EPF8282AV  
devices.  
Altera Corporation  
31  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 18. Output Drive Characteristics of EPF8282AV Devices  
100  
75  
IOL  
Typical I  
Output  
O
VCC = 3.3 V  
50  
Current (mA)  
Room Temperature  
IOH  
25  
1
2
3
4
Output Voltage (V)  
The continuous, high-performance FastTrack Interconnect routing  
structure ensures predictable performance and accurate simulation and  
timing analysis. This predictable performance contrasts with that of  
FPGAs, which use a segmented connection scheme and hence have  
unpredictable performance. Timing simulation and delay prediction are  
available with the MAX+PLUS II Simulator and Timing Analyzer, or with  
industry-standard EDA tools. The Simulator offers both pre-synthesis  
functional simulation to evaluate logic design accuracy and post-  
synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer  
provides point-to-point timing delay information, setup and hold time  
prediction, and device-wide performance analysis.  
Timing Model  
Tables 17 through 20 describe the FLEX 8000 timing parameters and their  
symbols.  
32  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 17. FLEX 8000 Internal Timing Parameters  
Symbol  
Note (1)  
Parameter  
tIOD  
IOE register data delay  
tIOC  
IOE register control signal delay  
Output enable delay  
tIOE  
tIOCO  
tIOCOMB  
tIOSU  
tIOH  
IOE register clock-to-output delay  
IOE combinatorial delay  
IOE register setup time before clock; IOE register recovery time after asynchronous clear  
IOE register hold time after clock  
tIOCLR  
tIN  
IOE register clear delay  
Input pad and buffer delay  
tOD1  
tOD2  
tOD3  
tXZ  
Output buffer and pad delay, slow slew rate = off, VCCIO = 5.0 V C1 = 35 pF (2)  
Output buffer and pad delay, slow slew rate = off, VCCIO = 3.3 V C1 = 35 pF (2)  
Output buffer and pad delay, slow slew rate = on, C1 = 35 pF (3)  
Output buffer disable delay, C1 = 5 pF  
tZX1  
Output buffer enable delay, slow slew rate = off, VCCIO = 5.0 V, C1 = 35 pF (2)  
Output buffer enable delay, slow slew rate = off, VCCIO = 3.3 V, C1 = 35 pF (2)  
Output buffer enable delay, slow slew rate = on, C1 = 35 pF (3)  
3
tZX2  
tZX3  
Table 18. FLEX 8000 LE Timing Parameters  
Note (1)  
Parameter  
Symbol  
tLUT  
LUT delay for data-in  
tCLUT  
tRLUT  
tGATE  
tCASC  
tCICO  
tCGEN  
tCGENR  
tC  
LUT delay for carry-in  
LUT delay for LE register feedback  
Cascade gate delay  
Cascade chain routing delay  
Carry-in to carry-out delay  
Data-in to carry-out delay  
LE register feedback to carry-out delay  
LE register control signal delay  
LE register clock high time  
LE register clock low time  
tCH  
tCL  
tCO  
LE register clock-to-output delay  
Combinatorial delay  
tCOMB  
tSU  
LE register setup time before clock; LE register recovery time after asynchronous preset, clear, or  
load  
tH  
LE register hold time after clock  
LE register preset delay  
LE register clear delay  
tPRE  
tCLR  
Altera Corporation  
33  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 19. FLEX 8000 Interconnect Timing Parameters  
Note (1)  
Parameter  
Symbol  
tLABCASC  
tLABCARRY  
tLOCAL  
tROW  
Cascade delay between LEs in different LABs  
Carry delay between LEs in different LABs  
LAB local interconnect delay  
Row interconnect routing delay (4)  
Column interconnect routing delay  
Dedicated input to LE control delay  
Dedicated input to LE data delay (4)  
Dedicated input to IOE control delay  
tCOL  
tDIN_C  
tDIN_D  
tDIN_IO  
Table 20. FLEX 8000 External Reference Timing Characteristics  
Symbol Parameter  
Note (5)  
tDRR  
tODH  
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local interconnects (6)  
Output data hold time after clock (7)  
Notes to tables:  
(1) Internal timing parameters cannot be measured explicitly. They are worst-case delays based on testable and  
external parameters specified by Altera. Internal timing parameters should be used for estimating device  
performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case  
performance.  
(2) These values are specified in Table 10 on page 28 or Table 14 on page 29.  
(3) For the t  
and t  
parameters, V  
= 3.3 V or 5.0 V.  
OD3  
ZX3  
CCIO  
(4) The t  
and t  
delays are worst-case values for typical applications. Post-compilation timing simulation or  
ROW  
DIN_D  
timing analysis is required to determine actual worst-case performance.  
(5) External reference timing characteristics are factory-tested, worst-case values specified by Altera. A representative  
subset of signal paths is tested to approximate typical device applications.  
(6) For more information on test conditions, see Application Note 76 (Understanding FLEX 8000 Timing).  
(7) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This  
parameter applies to global and non-global clocking, and for LE and I/O element registers.  
The FLEX 8000 timing model shows the delays for various paths and  
functions in the circuit. See Figure 19. This model contains three distinct  
parts: the LE; the IOE; and the interconnect, including the row and column  
FastTrack Interconnect, LAB local interconnect, and carry and cascade  
interconnect paths. Each parameter shown in Figure 19 is expressed as a  
worst-case value in Tables 22 through 49. Hand-calculations that use the  
FLEX 8000 timing model and these timing parameters can be used to  
estimate FLEX 8000 device performance. Timing simulation or timing  
analysis after compilation is required to determine the final worst-case  
performance. Table 21 summarizes the interconnect paths shown in  
Figure 19.  
For more information on timing parameters, go to Application Note 76  
(Understanding FLEX 8000 Timing).  
f
34  
Altera Corporation  
tROW  
Carry-In from  
Previous LE  
Cascade-In from  
Previous LE  
LE  
IOE  
Register  
Delays  
Cascade  
Gate Delay  
I/O Register  
Delays  
Output  
Delays  
Output Data  
Delay  
LUT Delay  
tLUT  
I/O Pin  
tOD1  
tOD2  
tOD3  
tXZ  
tGATE  
tRLUT  
tIOCO  
tIOCOMB  
tIOSU  
tCO  
tIOD  
LE-Out  
tCOMB  
tSU  
tCLUT  
tIOH  
tH  
tZX1  
tZX2  
tZX3  
I/O Register  
Control  
Carry Chain  
Delay  
tIOCLR  
tPRE  
tCLR  
tLOCAL  
tIOC  
tCGEN  
tCOL  
tCGENR  
tIOE  
tCICO  
Input  
Delay  
Register  
Control  
tIN  
tC  
Cascade  
Routing Delay  
tCASC  
Data-In  
Dedicated  
Input Delays  
tDIN_D  
tDIN_C  
tDIN_IO  
tLABCASC  
tLABCARRY  
Cascade-Out Cascade-Out  
to Next LE in to Next LE in  
Carry-Out Carry-Out  
to Next LE to Next LE  
Next LAB  
Same LAB  
in Same  
LAB  
in Next  
LAB  
0
E X F 8 L 0 0  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 21. FLEX 8000 Timing Model Interconnect Paths  
Source  
Destination  
Total Delay  
tLOCAL  
LE-Out  
LE in same LAB  
t
t
ROW + tLOCAL  
LE-Out  
LE in same row, different LAB  
LE in different row  
IOE on column  
IOE on row  
COL + tROW + tLOCAL  
LE-Out  
tCOL  
LE-Out  
tROW  
LE-Out  
tROW + tLOCAL  
IOE on row  
IOE on column  
LE in same row  
Any LE  
t
COL + tROW + tLOCAL  
Tables 22 through 49 show the FLEX 8000 internal and external timing  
parameters.  
Table 22. EPF8282A Internal I/O Element Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
0.7  
1.7  
1.7  
1.0  
0.3  
Min  
Max  
Min  
Max  
0.9  
1.9  
1.9  
1.0  
0.1  
tIOD  
tIOC  
tIOE  
0.8  
1.8  
1.8  
1.0  
0.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tIOCO  
tIOCOMB  
tIOSU  
tIOH  
1.4  
0.0  
1.6  
0.0  
1.8  
0.0  
tIOCLR  
tIN  
1.2  
1.5  
1.1  
–
1.2  
1.6  
1.4  
–
1.2  
1.7  
1.7  
–
tOD1  
tOD2  
tOD3  
tXZ  
4.6  
1.4  
1.4  
–
4.9  
1.6  
1.6  
–
5.2  
1.8  
1.8  
–
tZX1  
tZX2  
tZX3  
4.9  
5.1  
5.3  
36  
Altera Corporation  
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 23. EPF8282A Interconnect Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
0.3  
0.3  
0.5  
4.2  
2.5  
5.0  
7.2  
5.0  
Min  
Max  
Min  
Max  
0.4  
0.4  
0.8  
4.2  
2.5  
5.5  
7.2  
5.5  
tLABCASC  
0.3  
0.3  
0.6  
4.2  
2.5  
5.0  
7.2  
5.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tLABCARRY  
tLOCAL  
tROW  
tCOL  
tDIN_C  
tDIN_D  
tDIN_IO  
3
Altera Corporation  
37  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 24. EPF8282A LE Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLUT  
2.0  
0.0  
0.9  
0.0  
0.6  
0.4  
0.4  
0.9  
1.6  
2.5  
0.0  
1.1  
0.0  
0.7  
0.5  
0.5  
1.1  
2.0  
3.2  
0.0  
1.5  
0.0  
0.9  
0.6  
0.7  
1.5  
2.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLUT  
tRLUT  
tGATE  
tCASC  
tCICO  
tCGEN  
tCGENR  
tC  
tCH  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
tCL  
tCO  
0.4  
0.4  
0.5  
0.5  
0.6  
0.6  
tCOMB  
tSU  
0.8  
0.9  
1.1  
1.1  
1.2  
1.5  
tH  
tPRE  
tCLR  
0.6  
0.6  
0.7  
0.7  
0.8  
0.8  
Table 25. EPF8282A External Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tDRR  
tODH  
15.8  
19.8  
24.8  
ns  
ns  
1.0  
1.0  
1.0  
38  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 26. EPF8282AV I/O Element Timing Parameters  
Symbol Speed Grade  
Unit  
A-3  
A-4  
Min  
Max  
Min  
Max  
tIOD  
0.9  
1.9  
1.9  
1.0  
0.1  
2.2  
2.0  
2.0  
2.0  
0.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tIOC  
tIOE  
tIOCO  
tIOCOMB  
tIOSU  
tIOH  
1.8  
0.0  
2.8  
0.2  
tIOCLR  
tIN  
1.2  
1.7  
1.7  
–
2.3  
3.4  
4.1  
–
tOD1  
tOD2  
tOD3  
tXZ  
3
5.2  
1.8  
1.8  
–
7.1  
4.3  
4.3  
–
tZX1  
tZX2  
tZX3  
5.3  
8.3  
Table 27. EPF8282AV Interconnect Timing Parameters  
Symbol  
Speed Grade  
Unit  
A-3  
A-4  
Min  
Max  
Min  
Max  
tLABCASC  
tLABCARRY  
tLOCAL  
tROW  
0.4  
0.4  
0.8  
4.2  
2.5  
5.5  
7.2  
5.5  
1.3  
0.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1.5  
6.3  
tCOL  
3.8  
tDIN_C  
8.0  
tDIN_D  
10.8  
9.0  
tDIN_IO  
Altera Corporation  
39  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 28. EPF8282AV Logic Element Timing Parameters  
Symbol  
Unit  
Speed Grade  
A-3  
A-4  
Min  
Max  
Min  
Max  
tLUT  
3.2  
0.0  
1.5  
0.0  
0.9  
0.6  
0.7  
1.5  
2.5  
7.3  
1.4  
5.1  
0.0  
2.8  
1.5  
2.2  
3.7  
4.7  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLUT  
tRLUT  
tGATE  
tCASC  
tCICO  
tCGEN  
tCGENR  
tC  
tCH  
4.0  
4.0  
6.0  
6.0  
tCL  
tCO  
0.6  
0.6  
0.9  
0.9  
tCOMB  
tSU  
1.2  
1.5  
2.4  
4.6  
tH  
tPRE  
tCLR  
0.8  
0.8  
1.3  
1.3  
Table 29. EPF8282AV External Timing Parameters  
Symbol Speed Grade  
Unit  
A-3  
A-4  
Min  
Max  
Min  
Max  
tDRR  
tODH  
24.8  
50.1  
ns  
ns  
1.0  
1.0  
40  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 30. EPF8452A I/O Element Timing Parameters  
Symbol  
Unit  
Speed Grade  
A-3  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tIOD  
tIOC  
tIOE  
0.7  
1.7  
1.7  
1.0  
0.3  
0.8  
1.8  
1.8  
1.0  
0.2  
0.9  
1.9  
1.9  
1.0  
0.1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tIOCO  
tIOCOMB  
tIOSU  
tIOH  
1.4  
0.0  
1.6  
0.0  
1.8  
0.0  
tIOCLR  
tIN  
1.2  
1.5  
1.1  
–
1.2  
1.6  
1.4  
–
1.2  
1.7  
1.7  
–
tOD1  
tOD2  
tOD3  
tXZ  
3
4.6  
1.4  
1.4  
–
4.9  
1.6  
1.6  
–
5.2  
1.8  
1.8  
–
tZX1  
tZX2  
tZX3  
4.9  
5.1  
5.3  
Table 31. EPF8452A Interconnect Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLABCASC  
tLABCARRY  
tLOCAL  
tROW  
0.3  
0.3  
0.5  
5.0  
3.0  
5.0  
7.0  
5.0  
0.4  
0.4  
0.5  
5.0  
3.0  
5.0  
7.0  
5.0  
0.4  
0.4  
0.7  
5.0  
3.0  
5.5  
7.5  
5.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCOL  
tDIN_C  
tDIN_D  
tDIN_IO  
Altera Corporation  
41  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 32. EPF8452A LE Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLUT  
2.0  
0.0  
0.9  
0.0  
0.6  
0.4  
0.4  
0.9  
1.6  
2.3  
0.2  
1.6  
0.0  
0.7  
0.5  
0.9  
1.4  
1.8  
3.0  
0.1  
1.6  
0.0  
0.9  
0.6  
0.8  
1.5  
2.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLUT  
tRLUT  
tGATE  
tCASC  
tCICO  
tCGEN  
tCGENR  
tC  
tCH  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
tCL  
tCO  
0.4  
0.4  
0.5  
0.5  
0.6  
0.6  
tCOMB  
tSU  
0.8  
0.9  
1.0  
1.1  
1.1  
1.4  
tH  
tPRE  
tCLR  
0.6  
0.6  
0.7  
0.7  
0.8  
0.8  
Table 33. EPF8452A External Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tDRR  
tODH  
16.0  
20.0  
25.0  
ns  
ns  
1.0  
1.0  
1.0  
42  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 34. EPF8636A I/O Element Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tIOD  
tIOC  
tIOE  
0.7  
1.7  
1.7  
1.0  
0.3  
0.8  
1.8  
1.8  
1.0  
0.2  
0.9  
1.9  
1.9  
1.0  
0.1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tIOCO  
tIOCOMB  
tIOSU  
tIOH  
1.4  
0.0  
1.6  
0.0  
1.8  
0.0  
tIOCLR  
tIN  
1.2  
1.5  
1.1  
1.6  
4.6  
1.4  
1.4  
1.9  
4.9  
1.2  
1.6  
1.4  
1.9  
4.9  
1.6  
1.6  
2.1  
5.1  
1.2  
1.7  
1.7  
2.2  
5.2  
1.8  
1.8  
2.3  
5.3  
tOD1  
tOD2  
tOD3  
tXZ  
3
tZX1  
tZX2  
tZX3  
Table 35. EPF8636A Interconnect Timing Parameters  
Symbol  
Unit  
Speed Grade  
A-3  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLABCASC  
tLABCARRY  
tLOCAL  
tROW  
0.3  
0.3  
0.5  
5.0  
3.0  
5.0  
7.0  
5.0  
0.4  
0.4  
0.5  
5.0  
3.0  
5.0  
7.0  
5.0  
0.4  
0.4  
0.7  
5.0  
3.0  
5.5  
7.5  
5.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCOL  
tDIN_C  
tDIN_D  
tDIN_IO  
Altera Corporation  
43  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 36. EPF8636A LE Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLUT  
tCLUT  
tRLUT  
tGATE  
tCASC  
tCICO  
tCGEN  
tCGENR  
tC  
2.0  
0.0  
0.9  
0.0  
0.6  
0.4  
0.4  
0.9  
1.6  
2.3  
0.2  
1.6  
0.0  
0.7  
0.5  
0.9  
1.4  
1.8  
3.0  
0.1  
1.6  
0.0  
0.9  
0.6  
0.8  
1.5  
2.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCH  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
tCL  
tCO  
0.4  
0.4  
0.5  
0.5  
0.6  
0.6  
tCOMB  
tSU  
0.8  
0.9  
1.0  
1.1  
1.1  
1.4  
tH  
tPRE  
tCLR  
0.6  
0.6  
0.7  
0.7  
0.8  
0.8  
Table 37. EPF8636A External Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tDRR  
tODH  
16.0  
20.0  
25.0  
ns  
ns  
1.0  
1.0  
1.0  
44  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 38. EPF8820A I/O Element Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tIOD  
tIOC  
tIOE  
0.7  
1.7  
1.7  
1.0  
0.3  
0.8  
1.8  
1.8  
1.0  
0.2  
0.9  
1.9  
1.9  
1.0  
0.1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tIOCO  
tIOCOMB  
tIOSU  
tIOH  
1.4  
0.0  
1.6  
0.0  
1.8  
0.0  
tIOCLR  
tIN  
1.2  
1.5  
1.1  
1.6  
4.6  
1.4  
1.4  
1.9  
4.9  
1.2  
1.6  
1.4  
1.9  
4.9  
1.6  
1.6  
2.1  
5.1  
1.2  
1.7  
1.7  
2.2  
5.2  
1.8  
1.8  
2.3  
5.3  
tOD1  
tOD2  
tOD3  
tXZ  
3
tZX1  
tZX2  
tZX3  
Table 39. EPF8820A Interconnect Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLABCASC  
0.3  
0.3  
0.5  
5.0  
3.0  
5.0  
7.0  
5.0  
0.3  
0.3  
0.6  
5.0  
3.0  
5.0  
7.0  
5.0  
0.4  
0.4  
0.8  
5.0  
3.0  
5.5  
7.5  
5.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tLABCARRY  
tLOCAL  
tROW  
tCOL  
tDIN_C  
tDIN_D  
tDIN_IO  
Altera Corporation  
45  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 40. EPF8820A LE Timing Parameters  
Symbol  
Unit  
Speed Grade  
A-3  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLUT  
2.0  
0.0  
0.9  
0.0  
0.6  
0.4  
0.4  
0.9  
1.6  
2.5  
0.0  
1.1  
0.0  
0.7  
0.5  
0.5  
1.1  
2.0  
3.2  
0.0  
1.5  
0.0  
0.9  
0.6  
0.7  
1.5  
2.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLUT  
tRLUT  
tGATE  
tCASC  
tCICO  
tCGEN  
tCGENR  
tC  
tCH  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
tCL  
tCO  
0.4  
0.4  
0.5  
0.5  
0.6  
0.6  
tCOMB  
tSU  
0.8  
0.9  
1.1  
1.1  
1.2  
1.5  
tH  
tPRE  
tCLR  
0.6  
0.6  
0.7  
0.7  
0.8  
0.8  
Table 41. EPF8820A External Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tDRR  
tODH  
16.0  
20.0  
25.0  
ns  
ns  
1.0  
1.0  
1.0  
46  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 42. EPF81188A I/O Element Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tIOD  
0.7  
1.7  
1.7  
1.0  
0.3  
0.8  
1.8  
1.8  
1.0  
0.2  
0.9  
1.9  
1.9  
1.0  
0.1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tIOC  
tIOE  
tIOCO  
tIOCOMB  
tIOSU  
tIOH  
1.4  
0.0  
1.6  
0.0  
1.8  
0.0  
tIOCLR  
tIN  
1.2  
1.5  
1.1  
1.6  
4.6  
1.4  
1.4  
1.9  
4.9  
1.2  
1.6  
1.4  
1.9  
4.9  
1.6  
1.6  
2.1  
5.1  
1.2  
1.7  
1.7  
2.2  
5.2  
1.8  
1.8  
2.3  
5.3  
tOD1  
tOD2  
tOD3  
tXZ  
3
tZX1  
tZX2  
tZX3  
Table 43. EPF81188A Interconnect Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLABCASC  
tLABCARRY  
tLOCAL  
tROW  
0.3  
0.3  
0.5  
5.0  
3.0  
5.0  
7.0  
5.0  
0.3  
0.3  
0.6  
5.0  
3.0  
5.0  
7.0  
5.0  
0.4  
0.4  
0.8  
5.0  
3.0  
5.5  
7.5  
5.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCOL  
tDIN_C  
tDIN_D  
tDIN_IO  
Altera Corporation  
47  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 44. EPF81188A LE Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLUT  
tCLUT  
tRLUT  
tGATE  
tCASC  
tCICO  
tCGEN  
tCGENR  
tC  
2.0  
0.0  
0.9  
0.0  
0.6  
0.4  
0.4  
0.9  
1.6  
2.5  
0.0  
1.1  
0.0  
0.7  
0.5  
0.5  
1.1  
2.0  
3.2  
0.0  
1.5  
0.0  
0.9  
0.6  
0.7  
1.5  
2.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCH  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
tCL  
tCO  
0.4  
0.4  
0.5  
0.5  
0.6  
0.6  
tCOMB  
tSU  
0.8  
0.9  
1.1  
1.1  
1.2  
1.5  
tH  
tPRE  
tCLR  
0.6  
0.6  
0.7  
0.7  
0.8  
0.8  
Table 45. EPF81188A External Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tDRR  
tODH  
16.0  
20.0  
25.0  
ns  
ns  
1.0  
1.0  
1.0  
48  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 46. EPF81500A I/O Element Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tIOD  
tIOC  
tIOE  
0.7  
1.7  
1.7  
1.0  
0.3  
0.8  
1.8  
1.8  
1.0  
0.2  
0.9  
1.9  
1.9  
1.0  
0.1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tIOCO  
tIOCOMB  
tIOSU  
tIOH  
1.4  
0.0  
1.6  
0.0  
1.8  
0.0  
tIOCLR  
tIN  
1.2  
1.5  
1.1  
1.6  
4.6  
1.4  
1.4  
1.9  
4.9  
1.2  
1.6  
1.4  
1.9  
4.9  
1.6  
1.6  
2.1  
5.1  
1.2  
1.7  
1.7  
2.2  
5.2  
1.8  
1.8  
2.3  
5.3  
tOD1  
tOD2  
tOD3  
tXZ  
3
tZX1  
tZX2  
tZX3  
Table 47. EPF81500A Interconnect Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLABCASC  
0.3  
0.3  
0.5  
6.2  
3.0  
5.0  
8.2  
5.0  
0.3  
0.3  
0.6  
6.2  
3.0  
5.0  
8.2  
5.0  
0.4  
0.4  
0.8  
6.2  
3.0  
5.5  
8.7  
5.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tLABCARRY  
tLOCAL  
tROW  
tCOL  
tDIN_C  
tDIN_D  
tDIN_IO  
Altera Corporation  
49  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 48. EPF81500A LE Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tLUT  
2.0  
0.0  
0.9  
0.0  
0.6  
0.4  
0.4  
0.9  
1.6  
2.5  
0.0  
1.1  
0.0  
0.7  
0.5  
0.5  
1.1  
2.0  
3.2  
0.0  
1.5  
0.0  
0.9  
0.6  
0.7  
1.5  
2.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLUT  
tRLUT  
tGATE  
tCASC  
tCICO  
tCGEN  
tCGENR  
tC  
tCH  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
tCL  
tCO  
0.4  
0.4  
0.5  
0.5  
0.6  
0.6  
tCOMB  
tSU  
0.8  
0.9  
1.1  
1.1  
1.2  
1.5  
tH  
tPRE  
tCLR  
0.6  
0.6  
0.7  
0.7  
0.8  
0.8  
Table 49. EPF81500A External Timing Parameters  
Symbol  
Speed Grade  
A-3  
Unit  
A-2  
A-4  
Min  
Max  
Min  
Max  
Min  
Max  
tDRR  
tODH  
16.1  
20.1  
25.1  
ns  
ns  
1.0  
1.0  
1.0  
50  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
The supply power (P) for FLEX 8000 devices can be calculated with the  
following equation:  
Power  
Consumption  
P = PINT + PIO = [(ICCSTANDBY + ICCACTIVE × VCC] + PIO  
)
Typical ICCSTANDBY values are shown as ICC0 in Table 11 on page 28 and  
Table 15 on page 30. The PIO value, which depends on the device output  
load characteristics and switching frequency, can be calculated using the  
guidelines given in Application Note 74 (Evaluating Power for Altera  
Devices). The ICCACTIVE value depends on the switching frequency and  
the application logic. This value can be calculated based on the amount of  
current that each LE typically consumes.  
The following equation shows the general formula for calculating  
ICCACTIVE  
:
µA  
MHz × LE  
I
= K × fM × N × togLC × ---------------------------  
AX  
CCACTIVE  
The parameters in this equation are shown below:  
3
fMAX = Maximum operating frequency in MHz  
N
= Total number of logic cells used in the device  
togLC = Average percentage of logic cells toggling at each clock  
= Constant, shown in Table 50  
K
Table 50. Values for Constant K  
Device  
K
5.0-V FLEX 8000 devices  
3.3-V FLEX 8000 devices  
75  
60  
This calculation provides an ICC estimate based on typical conditions  
with no output load. The actual ICC value should be verified during  
operation because this measurement is sensitive to the actual pattern in  
the device and the environmental operating conditions.  
Figure 20 shows the relationship between ICC and operating frequency  
for several LE utilization values.  
Altera Corporation  
51  
 
FLEX 8000 Programmable Logic Device Family Data Sheet  
Figure 20. FLEX 8000 ICCACTIVE vs. Operating Frequency  
5.0-V FLEX 8000 Devices  
1,000  
1,500 LEs  
800  
600  
400  
200  
1,000 LEs  
500 LEs  
I
Supply  
CC  
Current (mA)  
0
30  
60  
Frequency (MHz)  
3.3-V FLEX 8000 Devices  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
200 LEs  
150 LEs  
I
Supply  
CC  
Current (mA)  
100 LEs  
50 LEs  
30  
60  
0
Frequency (MHz)  
The FLEX 8000 architecture supports several configuration schemes to  
load a design into the device(s) on the circuit board. This section  
summarizes the device operating modes and available device  
configuration schemes.  
Configuration&  
Operation  
For more information, go to Application Note 33 (Configuring FLEX 8000  
Devices) and Application Note 38 (Configuring Multiple FLEX 8000 Devices).  
f
52  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Operating Modes  
The FLEX 8000 architecture uses SRAM elements that require  
configuration data to be loaded whenever the device powers up and  
begins operation. The process of physically loading the SRAM  
programming data into the device is called configuration. During  
initialization, which occurs immediately after configuration, the device  
resets registers, enables I/O pins, and begins to operate as a logic device.  
The I/O pins are tri-stated during power-up, and before and during  
configuration. The configuration and initialization processes together are  
called command mode; normal device operation is called user mode.  
SRAM elements allow FLEX 8000 devices to be reconfigured in-circuit  
with new programming data that is loaded into the device. Real-time  
reconfiguration is performed by forcing the device into command mode  
with a device pin, loading different programming data, reinitializing the  
device, and resuming user-mode operation. The entire reconfiguration  
process requires less than 100 ms and can be used to dynamically  
reconfigure an entire system. In-field upgrades can be performed by  
distributing new configuration files.  
3
Configuration Schemes  
The configuration data for a FLEX 8000 device can be loaded with one of  
six configuration schemes, chosen on the basis of the target application.  
Both active and passive schemes are available. In the active configuration  
schemes, the FLEX 8000 device functions as the controller, directing the  
loading operation, controlling external configuration devices, and  
completing the loading process. The clock source for all active  
configuration schemes is an oscillator on the FLEX 8000 device that  
operates between 2 MHz and 6 MHz. In the passive configuration  
schemes, an external controller guides the FLEX 8000 device. Table 51  
shows the data source for each of the six configuration schemes.  
Table 51. Data Source for Configuration  
Configuration Scheme  
Acronym  
Data Source  
Active serial  
AS  
Altera configuration device  
Parallel configuration device  
Parallel configuration device  
Serial data path  
Active parallel up  
APU  
APD  
PS  
Active parallel down  
Passive serial  
Passive parallel synchronous  
Passive parallel asynchronous  
PPS  
PPA  
Intelligent host  
Intelligent host  
Altera Corporation  
53  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Tables 52 through 54 show the pin names and numbers for the dedicated  
pins in each FLEX 8000 device package.  
Device  
Pin-Outs  
Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 1 of 3)  
Pin Name  
84-Pin  
PLCC  
84-Pin  
PLCC  
100-Pin  
TQFP  
100-Pin  
TQFP  
144-Pin  
TQFP  
160-Pin  
PGA  
160-Pin  
PQFP  
EPF8282A EPF8452A EPF8282A EPF8452A EPF8820A EPF8452A EPF8820A  
EPF8636A EPF8282AV (1)  
nSP(2)  
75  
74  
53  
32  
33  
10  
75  
75  
74  
51  
24  
25  
100  
1
76  
75  
51  
25  
26  
100  
1
110  
109  
72  
R1  
P2  
1
MSEL0(2)  
MSEL1(2)  
nSTATUS(2)  
nCONFIG(2)  
DCLK(2)  
74  
53  
32  
33  
10  
11  
30  
48  
49  
29  
28  
77  
50  
51  
55  
56  
57  
58  
60  
61  
62  
63  
64  
65  
66  
67  
69  
70  
71  
72  
2
A1  
44  
82  
81  
125  
124  
87  
89  
110  
118  
121  
100  
107  
40  
39  
38  
37  
36  
32  
30  
28  
26  
22  
20  
18  
16  
11  
10  
8
37  
C13  
A15  
P14  
N13  
F13  
C6  
B5  
38  
143  
144  
33  
CONF_DONE(2) 11  
nWS  
30  
48  
49  
29  
28  
77  
50  
51  
36  
56  
57  
58  
60  
61  
62  
63  
64  
65  
66  
67  
69  
70  
71  
76  
22  
42  
45  
21  
19  
77  
47  
49  
28  
55  
57  
58  
59  
60  
61  
62  
64  
65  
66  
67  
68  
69  
71  
76  
23  
45  
46  
22  
21  
78  
47  
48  
54  
55  
57  
58  
60  
61  
62  
64  
65  
66  
67  
68  
70  
71  
72  
73  
nRS  
31  
RDCLK  
nCS  
12  
4
D15  
E15  
P3  
CS  
3
RDYnBUSY  
CLKUSR  
ADD17  
ADD16  
ADD15  
ADD14  
ADD13  
ADD12  
ADD11  
ADD10  
ADD9  
20  
13  
C5  
B4  
75  
76  
E2  
77  
D1  
E1  
78  
79  
F3  
83  
F2  
85  
F1  
87  
G2  
G1  
H1  
H2  
J1  
89  
ADD8  
92  
ADD7  
94  
ADD6  
95  
ADD5  
97  
J2  
ADD4  
102  
103  
104  
105  
K2  
ADD3  
K1  
ADD2  
K3  
ADD1  
M1  
7
54  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 2 of 3)  
Pin Name  
84-Pin  
PLCC  
84-Pin  
PLCC  
100-Pin  
TQFP  
100-Pin  
TQFP  
144-Pin  
TQFP  
160-Pin  
PGA  
160-Pin  
PQFP  
EPF8282A EPF8452A EPF8282A EPF8452A EPF8820A EPF8452A EPF8820A  
EPF8636A EPF8282AV (1)  
ADD0  
78  
3
76  
78  
90  
91  
92  
95  
97  
99  
4
77  
89  
91  
95  
96  
97  
98  
4
106  
131  
132  
133  
134  
135  
137  
138  
140  
23  
N3  
P8  
P10  
R12  
R13  
P13  
R14  
N15  
K13  
P4  
–
6
DATA7  
2
140  
139  
138  
136  
135  
133  
132  
129  
97  
DATA6  
4
4
DATA5  
6
6
DATA4  
7
7
DATA3  
8
8
DATA2  
9
9
DATA1  
13  
14  
79  
55  
27  
72  
20  
52  
13  
DATA0  
14  
5
5
SDOUT(3)  
TDI(4)  
TDO(4)  
TCK(4), (6)  
TMS(4)  
TRST(7)  
78  
79  
54  
18  
72  
11  
50  
79  
–
45 (5)  
27 (5)  
44 (5)  
43 (5)  
52 (8)  
96  
17  
3
–
18  
–
102  
27  
–
88  
–
–
86  
–
29  
–
71  
–
45  
Dedicated  
12, 31, 54,  
73  
12, 31, 54, 3, 23, 53, 73 3, 24, 53,  
73 74  
17, 38, 59, 6, 20, 37, 56, 9, 32, 49,  
80 70, 87 59, 82  
9, 26, 82,  
99  
C3, D14,  
N2, R15  
14, 33, 94,  
113  
Inputs (10)  
VCCINT  
17, 38, 59,  
80  
8, 28, 70,  
90, 111  
B2, C4, D3, 3, 24, 46,  
D8, D12,  
G3, G12,  
H4, H13,  
J3, J12,  
M4, M7,  
M9, M13,  
N12  
92, 114,  
160  
VCCIO  
–
–
–
–
16, 40, 60,  
69, 91,  
–
23, 47, 57,  
69, 79,  
112, 122,  
141  
104, 127,  
137, 149,  
159  
Altera Corporation  
55  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 3 of 3)  
Pin Name  
84-Pin  
PLCC  
84-Pin  
PLCC  
100-Pin  
TQFP  
100-Pin  
TQFP  
144-Pin  
TQFP  
160-Pin  
PGA  
160-Pin  
PQFP  
EPF8282A EPF8452A EPF8282A EPF8452A EPF8820A EPF8452A EPF8820A  
EPF8636A EPF8282AV  
(1)  
GND  
5, 26, 47, 68 5, 26, 47,  
2, 13, 30, 44, 19, 44, 69, 7, 17, 27,  
C12, D4,  
D7, D9,  
D13, G4,  
G13, H3,  
H12, J4,  
J13, L1,  
M3, M8,  
M12, M15,  
N4  
12, 13, 34,  
35, 51, 63,  
75, 80, 83,  
93, 103,  
115, 126,  
131, 143,  
155  
68  
52, 63, 80,  
94  
94  
39, 54,  
80, 81,  
100,101,  
128, 142  
No Connect  
(N.C.)  
–
–
–
2, 6, 13, 30,  
37, 42, 43,  
50, 52, 56,  
63, 80, 87,  
92, 93, 99  
–
–
–
Total User I/O  
64  
64  
74  
64  
108  
116  
116  
Pins (9)  
56  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 53. FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2)  
Pin Name  
160-Pin  
PQFP  
160-Pin  
PQFP  
192-Pin PGA  
EPF8636A  
208-Pin  
PQFP  
208-Pin  
PQFP  
208-Pin  
PQFP  
EPF8452A  
EPF8636A  
EPF8820A EPF8636A (1) EPF8820A (1) EPF81188A (1)  
nSP(2)  
120  
1
3
R15  
T15  
T3  
207  
4
207  
4
5
MSEL0(2)  
MSEL1(2)  
117  
84  
21  
38  
49  
49  
33  
nSTATUS(2) 37  
nCONFIG(2) 40  
83  
B3  
108  
103  
158  
153  
108  
103  
158  
153  
124  
107  
154  
138  
81  
C3  
DCLK(2)  
1
4
120  
118  
C15  
B15  
CONF_DONE  
(2)  
nWS  
30  
89  
50  
48  
91  
93  
155  
44  
43  
33  
31  
29  
27  
24  
23  
22  
21  
20  
19  
18  
17  
13  
11  
9
C5  
114  
66  
114  
116  
137  
145  
148  
127  
134  
43  
118  
121  
137  
142  
144  
128  
134  
46  
nRS  
71  
B5  
RDCLK  
nCS  
73  
C11  
B13  
A16  
A8  
64  
29  
116  
118  
201  
59  
3
CS  
27  
RDYnBUSY  
CLKUSR  
ADD17  
ADD16  
ADD15  
ADD14  
ADD13  
ADD12  
ADD11  
ADD10  
ADD9  
125  
76  
A10  
R5  
78  
57  
91  
U3  
43  
42  
45  
92  
T5  
41  
41  
44  
94  
U4  
39  
40  
39  
95  
R6  
37  
39  
37  
96  
T6  
31  
35  
36  
97  
R7  
30  
33  
31  
98  
T7  
29  
31  
30  
99  
T8  
28  
29  
29  
ADD8  
101  
102  
103  
104  
105  
106  
109  
110  
123  
144  
150  
152  
U9  
24  
25  
26  
ADD7  
U10  
U11  
U12  
R12  
U14  
U15  
R13  
U16  
H17  
G17  
F17  
23  
23  
25  
ADD6  
22  
21  
24  
ADD5  
21  
19  
18  
ADD4  
14  
14  
17  
ADD3  
12  
13  
16  
ADD2  
10  
11  
10  
ADD1  
7
8
10  
9
ADD0  
157  
137  
132  
129  
203  
178  
172  
169  
9
8
DATA7  
DATA6  
DATA5  
178  
176  
174  
177  
175  
172  
Altera Corporation  
57  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 53. FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2)  
Pin Name  
160-Pin  
PQFP  
160-Pin  
PQFP  
192-Pin PGA  
EPF8636A  
208-Pin  
PQFP  
208-Pin  
PQFP  
208-Pin  
PQFP  
EPF8452A  
EPF8636A  
EPF8820A EPF8636A (1) EPF8820A (1) EPF81188A (1)  
DATA4  
154  
127  
E17  
G15  
F15  
E16  
C16  
C7 (11)  
R11  
B9  
165  
162  
160  
149  
147  
198  
72  
172  
171  
167  
165  
162  
124  
20  
170  
168  
166  
163  
161  
119  
–
DATA3  
157  
124  
122  
115  
113  
152  
55  
DATA2  
159  
DATA1  
11  
DATA0  
12  
SDOUT(3)  
TDI(4)  
TDO(4)  
TCK(4), (6)  
TMS(4)  
TRST(7)  
128  
–
–
95  
120  
74  
129  
30  
–
–
57  
U8  
–
–
59  
U7  
76  
32  
–
–
40  
R3  
54  
54  
–
Dedicated  
5, 36, 85, 116  
6, 35, 87, 116 A5, U5, U13, 7, 45, 112,  
A13 150  
17, 36, 121,  
140  
13, 41, 116,  
146  
Inputs (10)  
VCCINT  
21, 41, 53, 67,  
4, 5, 26, 85,  
C8, C9, C10, 5, 6, 33, 110, 5, 6, 27, 48,  
4, 20, 35, 48,  
50, 102, 114,  
131, 147  
(5.0 V)  
80, 81, 100, 121, 106  
133, 147, 160  
R8, R9, R10, 137  
R14  
119, 141  
VCCIO  
(5.0 V or  
3.3 V)  
–
25, 41, 60, 70, D3, D4, D9,  
32, 55, 78, 91, 26, 55, 69, 87, 3, 19, 34, 49,  
80, 107, 121, D14, D15, G4, 102,138,159, 102,131,159, 69, 87, 106,  
140, 149, 160 G14, L4, L14, 182, 193, 206 173, 191, 206 123, 140, 156,  
P4, P9, P14  
174, 192  
GND  
13, 14, 28, 46,  
15, 16, 36, 37, C4, D7, D8,  
19, 20, 46, 47, 15, 16, 37, 38, 11, 12, 27, 28,  
60, 75, 93, 107, 45, 51, 75, 84, D10, D11, H4, 60, 67, 96,  
60, 78, 96,  
H14, K4, K14, 109,111,124, 109,110,120, 96, 105, 115,  
117,126,131, P7, P8, P10, 125,151,164, 130,142,152, 122, 132, 139,  
42, 43, 60, 78,  
108, 126, 140,  
155  
86, 96, 97,  
154  
P11  
171, 200  
164, 182, 200 148, 155, 159,  
165, 183, 201  
No Connect 2, 3, 38, 39, 70, 2, 39, 82, 119 C6, C12, C13, 1, 2, 3, 16, 17, 1, 2, 3, 50, 51, 1, 2, 51, 52, 53,  
(N.C.)  
82, 83, 118, 119,  
148  
C14, E3, E15, 18, 25, 26, 27, 52, 53, 104,  
F3, J3, J4, 34, 35, 36, 50, 105,106,107, 157, 158, 207,  
J14, J15, N3, 51, 52, 53, 154,155,156, 208  
N15, P3, P15, 104,105,106, 157, 208  
54, 103, 104,  
R4 (12)  
107,121,122,  
123,130,131,  
132,139,140,  
141,154,155,  
156, 157, 208  
Total User  
116  
114  
132, 148 (13) 132  
148  
144  
I/O Pins (9)  
58  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3)  
Pin Name  
225-Pin  
BGA  
232-Pin  
PGA  
240-Pin  
PQFP  
240-Pin  
PQFP  
280-Pin  
PGA  
304-Pin  
RQFP  
EPF8820A  
EPF81188A  
EPF81188A  
EPF81500A  
EPF81500A  
EPF81500A  
nSP(2)  
A15  
C14  
237  
237  
W1  
304  
MSEL0(2)  
MSEL1(2)  
nSTATUS(2)  
nCONFIG(2)  
DCLK(2)  
B14  
R15  
P2  
G15  
L15  
L3  
21  
19  
N1  
26  
40  
38  
H3  
51  
141  
117  
184  
160  
133  
137  
158  
166  
169  
146  
155  
58  
142  
120  
183  
161  
134  
138  
159  
167  
170  
147  
156  
56  
G19  
B18  
U18  
M16  
F18  
G18  
M17  
N16  
N18  
J17  
K19  
E3  
178  
152  
230  
204  
167  
171  
202  
212  
215  
183  
199  
73  
R1  
R4  
B2  
C4  
CONF_DONE(2) A1  
G3  
nWS  
L4  
P1  
nRS  
K5  
N1  
RDCLK  
nCS  
F1  
G2  
D1  
E2  
CS  
C1  
E3  
3
RDYnBUSY  
CLKUSR  
ADD17  
ADD16  
ADD15  
ADD14  
ADD13  
ADD12  
ADD11  
ADD10  
ADD9  
J3  
K2  
G2  
H2  
M14  
L12  
M15  
L13  
L14  
K13  
K15  
J13  
J15  
G14  
G13  
G11  
F14  
E13  
D15  
D14  
E12  
C15  
A7  
R15  
T17  
P15  
M14  
M15  
M16  
K15  
K17  
J14  
J15  
H17  
H15  
F16  
F15  
F14  
D15  
B17  
C15  
A7  
56  
54  
E2  
71  
54  
52  
F4  
69  
47  
45  
G1  
60  
45  
43  
H2  
58  
43  
41  
H1  
56  
36  
34  
J3  
47  
34  
32  
K3  
45  
32  
30  
K4  
43  
ADD8  
29  
27  
L1  
34  
ADD7  
27  
25  
L2  
32  
ADD6  
25  
23  
M1  
N2  
30  
ADD5  
18  
16  
20  
ADD4  
16  
14  
N3  
18  
ADD3  
14  
12  
N4  
16  
ADD2  
7
5
U1  
8
ADD1  
5
3
U2  
6
ADD0  
3
1
V1  
4
DATA7  
DATA6  
DATA5  
205  
203  
200  
199  
197  
196  
W13  
W14  
W15  
254  
252  
250  
D7  
D8  
A6  
B7  
Altera Corporation  
59  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3)  
Pin Name  
225-Pin  
BGA  
232-Pin  
PGA  
240-Pin  
PQFP  
240-Pin  
PQFP  
280-Pin  
PGA  
304-Pin  
RQFP  
EPF8820A  
EPF81188A  
EPF81188A  
EPF81500A  
EPF81500A  
EPF81500A  
DATA4  
A5  
C7  
198  
194  
W16  
248  
DATA3  
DATA2  
DATA1  
DATA0  
SDOUT(3)  
TDI  
B5  
D7  
B5  
A3  
A2  
N2  
–
196  
194  
191  
189  
135  
–
193  
W17  
246  
E6  
190  
V16  
243  
D5  
189  
U16  
241  
C4  
187  
V17  
239  
K1  
136  
F19  
169  
F15 (4)  
J2 (4)  
J14 (4)  
J12 (4)  
P14  
63 (14)  
117  
B1 (14)  
C17  
80 (14)  
149  
TDO  
–
–
TCK (6)  
TMS  
–
–
116 (14)  
64 (14)  
115 (14)  
A19 (14)  
C2 (14)  
A18 (14)  
148 (14)  
81 (14)  
145 (14)  
–
–
TRST(7)  
–
–
Dedicated Inputs F4, L1, K12, C1, C17, R1, 10, 51, 130,  
8, 49, 131,  
172  
F1, F16, P3, 12, 64, 164,  
P19 217  
(10)  
E15  
R17  
171  
VCCINT  
F5, F10, E1, E4, H4, L4,  
L2, K4, M12, P12, L14,  
20, 42, 64, 66, 18, 40, 60, 62, B17, D3, D15, 24, 54, 77,  
114,128,150, 91, 114, 129, E8, E10, E12, 144, 79, 115,  
(5.0 V)  
P15, H13,  
H14, B15,  
C13  
H14, E14,  
R14, U1  
172, 236  
151,173,209, E14, R7, R9, 162,191,218,  
236  
R11, R13,  
R14, T14  
266, 301  
VCCIO  
H3, H2, P6,  
N10, M13,  
19, 41, 65, 81, 17, 39, 61, 78, D14, E7, E9, 22, 53, 78, 99,  
(5.0 V or 3.3 V) R6, P10, N10, M5, K13, K5, 99, 116, 140, 94, 108, 130, E11, E13, R6, 119,137,163,  
R14, N13,  
H15, H12,  
D12, A14,  
B10, A10, B6,  
C6, A2, C3,  
M4, R2  
H13, H5, F5, 162,186,202, 152,174,191, R8, R10, R12, 193,220,244,  
E10, E8, N8, 220, 235  
F13  
205, 221, 235 T13, T15  
262, 282, 300  
60  
Altera Corporation  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)  
Pin Name  
225-Pin  
BGA  
232-Pin  
PGA  
240-Pin  
PQFP  
240-Pin  
PQFP  
280-Pin  
PGA  
304-Pin  
RQFP  
EPF8820A  
EPF81188A  
EPF81188A  
EPF81500A  
EPF81500A  
EPF81500A  
GND  
B1, D4, E14, A1, D6, E11, 8, 9, 30, 31,  
F7, F8, F9, E7, E9, G4,  
F12, G6, G7, G5, G13,  
G8, G9, G10, G14, J5, J13, 139,151,161, 119,140,141, F15, G5, G15, 128, 150,  
6, 7, 28, 29,  
D4, D5, D16, 9, 11, 36, 38,  
65, 67, 90,  
108,115,129, 92, 101, 118, E15, E16, F5, 108, 116,  
52, 53, 72, 90, 50, 51, 71, 85, E4, E5, E6,  
H1, H4, H5,  
H6, H7, H8,  
K4, K14, L5, 173,185,187, 162,163,184, H5, H15, J5, 151,175,177,  
L13, N4, N7, 193, 211, 229 185,186,198, J15, K5, K15, 206,208,231,  
H9, H10, H11, N9, N11, N14  
J6, J7, J8, J9,  
208, 214, 228 L5, L15, M5, 232,237,253,  
M15, N5,  
265, 273, 291  
J10, K6, K7,  
N15, P4, P5,  
P15, P16, R4,  
R5, R15, R16,  
T4, T5, T16,  
U17  
K8, K9, K11,  
L15, N3, P1  
No Connect  
(N.C.)  
–
–
61, 62, 119,  
120,181,182,  
239, 240  
–
–
10, 21, 23, 25,  
35, 37, 39, 40,  
41, 42, 52, 55,  
66, 68, 146,  
147,161,173,  
174,176,187,  
188,189,190,  
192,194,195,  
205,207,219,  
221,233,234,  
235,236,302,  
303  
3
Total User I/O  
148  
180  
180  
177  
204  
204  
Pins (9)  
Altera Corporation  
61  
FLEX 8000 Programmable Logic Device Family Data Sheet  
Notes to tables:  
(1) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74  
(Evaluating Power for Altera Devices) for more information.  
(2) This pin is a dedicated pin and is not available as a user I/O pin.  
(3) SDOUTwill drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the  
MAX+PLUS II software will not use SDOUTas a user I/O pin; the user can override the MAX+PLUS II software and  
use SDOUTas a user I/O pin.  
(4) If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin.  
(5) JTAG pins are available for EPF8636A devices only. These pins are dedicated user I/O pins.  
(6) If this pin is used as an input in user mode, ensure that it does not toggle before or during configuration.  
(7) TRSTis a dedicated input pin for JTAG use. This pin must be grounded if JTAG BST is not used.  
(8) Pin 52 is a V pin on EPF8452A devices only.  
CC  
(9) The user I/O pin count includes dedicated input pins and all I/O pins.  
(10) Unused dedicated inputs should be tied to ground on the board.  
(11) SDOUTdoes not exist in the EPF8636GC192 device.  
(12) These pins are no connect (N.C.) pins for EPF8636A devices only. They are user I/O pins in EPF8820A devices.  
(13) EPF8636A devices have 132 user I/O pins; EPF8820A devices have 148 user I/O pins.  
(14) For EPF81500A devices, these pins are dedicated JTAG pins and are not available as user I/O pins. If JTAG BST is  
not used, TDI, TCK, TMS, and TRSTshould be tied to GND.  
The information contained in the FLEX 8000 Programmable Logic Device  
Family Data Sheet version 11.1 supersedes information published in  
previous versions. The FLEX 8000 Programmable Logic Device Family Data  
Sheet version 11.1 contains the following change: minor textual updates.  
Revision  
History  
62  
Altera Corporation  

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