EP1AGX60EF780C6N_技术文档

Section I. Arria GX Device Data Sheet

®

This section provides designers with the data sheet specifications for Arria GX

devices. They contain feature definitions of the transceivers, internal architecture,

configuration, and JTAG boundary-scan testing information, DC operating

conditions, AC timing parameters, a reference to power consumption, and ordering

information for Arria GX devices.

This section includes the following chapters:

■

Chapter 1, Arria GX Device Family Overview

Chapter 2, Arria GX Architecture

Chapter 3, Configuration and Testing

Chapter 4, DC and Switching Characteristics

Chapter 5, Reference and Ordering Information

Revision History

Refer to each chapter for its own specific revision history. For information about when

each chapter was updated, refer to the Chapter Revision Dates section, which appears

in the full handbook.

Arria GX Device Handbook, Volume 1

I–2

Section I: Arria GX Device Data Sheet

Arria GX Device Handbook, Volume 1

1. Arria GX Device Family Overview

AGX51001-2.0

Introduction

The Arria^®GX family of devices combines 3.125 Gbps serial transceivers with reliable

packaging technology and a proven logic array. Arria GX devices include 4 to 12

high-speed transceiver channels, each incorporating clock data recovery (CDR)

technology and embedded SERDES circuitry designed to support PCI-Express,

Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with

the ability to develop proprietary, serial-based IP using its Basic mode. The

transceivers build upon the success of the Stratix^®II GX family. The Arria GX FPGA

technology offers a 1.2-V logic array with the right level of performance and

dependability needed to support these mainstream protocols.

Features

The key features of Arria GX devices include:

■

Transceiver block features

■

High-speed serial transceiver channels with CDR support up to 3.125 Gbps.

■

Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver

channels

■

Support for the following CDR-based bus standards—PCI Express, Gigabit

Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to

develop proprietary, serial-based IP using its Basic mode

■

Individual transmitter and receiver channel power-down capability for

reduced power consumption during non-operation

1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter

output buffers

Receiver indicator for loss of signal (available only in PCI Express [PIPE]

mode)

Hot socketing feature for hot plug-in or hot swap and power sequencing

support without the use of external devices

Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial

Digital Interface (SDI), and Serial RapidIO

8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit

decoding

Phase compensation FIFO buffer performs clock domain translation between

the transceiver block and the logic array

Channel aligner compliant with XAUI

Arria GX Device Handbook, Volume 1

1–2

Chapter 1: Arria GX Device Family Overview

Features

■

Main device features:

■

TriMatrix memory consisting of three RAM block sizes to implement true

dual-port memory and first-in first-out (FIFO) buffers with performance up to

380 MHz

■

Up to 16 global clock networks with up to 32 regional clock networks per

device

High-speed DSP blocks provide dedicated implementation of multipliers,

multiply-accumulate functions, and finite impulse response (FIR) filters

Up to four enhanced phase-locked loops (PLLs) per device provide spread

spectrum, programmable bandwidth, clock switch-over, and advanced

multiplication and phase shifting

■

Support for numerous single-ended and differential I/O standards

High-speed source-synchronous differential I/O support on up to 47 channels

Support for source-synchronous bus standards, including SPI-4 Phase 2

(POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1

■

Support for high-speed external memory including DDR and DDR2 SDRAM,

and SDR SDRAM

Support for multiple intellectual property megafunctions from Altera^®

MegaCore^®functions and Altera Megafunction Partners Program (AMPP^SM

)

Support for remote configuration updates

Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with flip chip

packages.

Table 1–1. Arria GX Device Features (Part 1 of 2)

EP1AGX20C

C

EP1AGX35C/D

EP1AGX50C/D

EP1AGX60C/D/E

D

EP1AGX90E

Feature

Package

C

D

C

D

C

E

484-pin,

780-pin

(Flip chip)

484-pin

780-pin

484-pin

780-pin,

484-pin

780-pin

1152-pin 1152-pin

(Flip chip)

(Flip chip) (Flip chip) (Flip chip) 1152-pin

(Flip chip)

(Flip chip) (Flip chip)

(Flip chip)

ALMs

8,632

13,408

20,064

24,040

36,088

90,220

Equivalent

logic

elements

(LEs)

21,580

33,520

50,160

60,100

Transceiver

channels

4

8

4

8

4

8

12

Transceiver

data rate

600 Mbps

to 3.125

Gbps

600 Mbps to 3.125

Gbps

600 Mbps to 3.125

Gbps

600 Mbps to 3.125 Gbps

600 Mbps

to 3.125

Gbps

Source-

synchronous

receive

31

31, 42

31

42

47

channels

Arria GX Device Handbook, Volume 1

Chapter 1: Arria GX Device Family Overview

1–3

Features

Table 1–1. Arria GX Device Features (Part 2 of 2)

EP1AGX20C

C

EP1AGX35C/D

EP1AGX50C/D

EP1AGX60C/D/E

D

EP1AGX90E

E

Feature

Source-

C

D

C

D

C

E

synchronous

transmit

29

29, 42

29

42

45

channels

M512 RAM

blocks

(32 × 18 bits)

166

118

197

140

313

242

326

252

478

400

M4K RAM

blocks

(128 × 36

bits)

M-RAM

blocks

(4096 × 144

bits)

1

2

4

Total RAM

bits

1,229,184

40

1,348,416

56

2,475,072

2,528,640

128

4,477,824

176

Embedded

multipliers

(18 × 18)

104

26

DSP blocks

PLLs

10

4

14

4

32

4

44

8

4

4, 8

8

Maximum

user I/O pins

230, 341

230

341

229

350, 514

229

350

514

538

Arria GX devices are available in space-saving FBGA packages (refer to Table 1–2). All

Arria GX devices support vertical migration within the same package. With vertical

migration support, designers can migrate to devices whose dedicated pins,

configuration pins, and power pins are the same for a given package across device

densities. For I/O pin migration across densities, the designer must cross-reference

the available I/O pins with the device pin-outs for all planned densities of a given

package type to identify which I/O pins are migratable.

Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2)

Source-Synchronous Channels Maximum User I/O Pin Count

Transceiver

Channels

1152-Pin

FBGA

(35 mm)

Device

484-Pin FBGA

(23 mm)

780-Pin FBGA

(29 mm)

Receive

Transmit

EP1AGX20C

EP1AGX35C

EP1AGX50C

EP1AGX60C

EP1AGX35D

EP1AGX50D

4

8

31

29

230

229

—

341

—

31

29

—

31

29

—

31

29

341

350

—

31, 42

29, 42

—

514

Arria GX Device Handbook, Volume 1

1–4

Chapter 1: Arria GX Device Family Overview

Document Revision History

Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 2 of 2)

Source-Synchronous Channels Maximum User I/O Pin Count

Transceiver

Channels

1152-Pin

FBGA

(35 mm)

Device

484-Pin FBGA

(23 mm)

780-Pin FBGA

(29 mm)

Receive

Transmit

EP1AGX60D

EP1AGX60E

EP1AGX90E

8

31

42

47

29

42

45

—

350

—

12

514

538

—

Table 1–3 lists the Arria GX device package sizes.

Table 1–3. Arria GX FBGA Package Sizes

Dimension

Pitch (mm)

Area (mm²)

484 Pins

1.00

780 Pins

1.00

1152 Pins

1.00

1225

529

841

Length × width

(mm × mm)

23 × 23

29 × 29

35 × 35

Document Revision History

Table 1–4 lists the revision history for this chapter.

Table 1–4. Document Revision History

Date and Document Version

Changes Made

■ Document template update.

■ Minor text edits.

Summary of Changes

December 2009, v2.0

—

May 2008, v1.2

Included support for SDI,

SerialLite II, and XAUI.

June 2007, v1.1

May 2007, v1.0

Included GIGE information.

Initial Release

—

Arria GX Device Handbook, Volume 1

2. Arria GX Architecture

AGX51002-2.0

Transceivers

Arria^®GX devices incorporate up to 12 high-speed serial transceiver channels that

build on the success of the Stratix^®II GX device family. Arria GX transceivers are

structured into full-duplex (transmitter and receiver) four-channel groups called

transceiver blocks located on the right side of the device. You can configure the

transceiver blocks to support the following serial connectivity protocols

(functional modes):

■

PCI Express (PIPE)

Gigabit Ethernet (GIGE)

XAUI

Basic (600 Mbps to 3.125 Gbps)

SDI (HD, 3G)

Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)

Transceivers within each block are independent and have their own set of dividers.

Therefore, each transceiver can operate at different frequencies. Each block can select

from two reference clocks to provide two clock domains that each transceiver can

select from.

Table 2–1 lists the number of transceiver channels for each member of the Arria GX

family.

Table 2–1. Arria GX Transceiver Channels

Device

Number of Transceiver Channels

EP1AGX20C

EP1AGX35C

EP1AGX35D

EP1AGX50C

EP1AGX50D

EP1AGX60C

EP1AGX60D

EP1AGX60E

EP1AGX90E

4

8

4

8

4

8

12

Arria GX Device Handbook, Volume 1

2–2

Chapter 2: Arria GX Architecture

Transceivers

Figure 2–1 shows a high-level diagram of the transceiver block architecture divided

into four channels.

Figure 2–1. Transceiver Block

Transceiver Block

RX1

Channel 1

TX1

RX0

Channel 0

Arria GX

Logic Array

TX0

Supporting Blocks

(PLLs, State Machines,

Programming)

REFCLK_1

REFCLK_0

RX2

Channel 2

Channel 3

TX2

RX3

TX3

Each transceiver block has:

■

Four transceiver channels with dedicated physical coding sublayer (PCS) and

physical media attachment (PMA) circuitry

One transmitter PLL that takes in a reference clock and generates high-speed serial

clock depending on the functional mode

Four receiver PLLs and clock recovery unit (CRU) to recover clock and data from

the received serial data stream

State machines and other logic to implement special features required to support

each protocol

Figure 2–2 shows functional blocks that make up a transceiver channel.

Figure 2–2. Arria GX Transceiver Channel Block Diagram

PMA Analog Section

PCS Digital Section

FPGA Fabric

n

Word

Deserializer

Aligner

(1)

m

Phase

Compensation

FIFO Buffer

Rate

Matcher

8B/10B

Decoder

Byte

Deserializer

Clock

Recovery

Unit

(2)

XAUI

Lane

Deskew

Reference

Clock

Receiver

PLL

Transmitter

PLL

Reference

Clock

n

Serializer

m

Phase

Compensation

FIFO Buffer

Byte

Serializer

(1)

8B/10B

Encoder

(2)

Notes to Figure 2–2:

(1) “n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA.

n = 8 or 10.

(2) “m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the transceiver. m = 8, 10, 16, or 20.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–3

Transceivers

Each transceiver channel is full-duplex and consists of a transmitter channel and a

receiver channel.

The transmitter channel contains the following sub-blocks:

■

Transmitter phase compensation first-in first-out (FIFO) buffer

Byte serializer (optional)

8B/10B encoder (optional)

Serializer (parallel-to-serial converter)

Transmitter differential output buffer

The receiver channel contains the following:

■

Receiver differential input buffer

Receiver lock detector and run length checker

CRU

Deserializer

Pattern detector

Word aligner

Lane deskew

Rate matcher (optional)

8B/10B decoder (optional)

Byte deserializer (optional)

Receiver phase compensation FIFO buffer

You can configure the transceiver channels to the desired functional modes using the

ALT2GXB MegaCore instance in the Quartus^®II MegaWizard^™Plug-in Manager for

the Arria GX device family. Depending on the selected functional mode, the

Quartus II software automatically configures the transceiver channels to employ a

subset of the sub-blocks listed above.

Transmitter Path

This section describes the data path through the Arria GX transmitter. The sub-blocks

are described in order from the PLD-transmitter parallel interface to the serial

transmitter buffer.

Clock Multiplier Unit

Each transceiver block has a clock multiplier unit (CMU) that takes in a reference

clock and synthesizes two clocks: a high-speed serial clock to serialize the data and a

low-speed parallel clock to clock the transmitter digital logic (PCS).

The CMU is further divided into three sub-blocks:

■

One transmitter PLL

One central clock divider block

Four local clock divider blocks (one per channel)

Arria GX Device Handbook, Volume 1

2–4

Chapter 2: Arria GX Architecture

Transceivers

Figure 2–3 shows the block diagram of the clock multiplier unit.

Figure 2–3. Clock Multiplier Unit

CMU Block

Transmitter High-Speed Serial

and Low-Speed Parallel Clocks

Transmitter Channels [3:2]

Local Clock

TX Clock

Divider Block

Gen Block

Reference Clock

from REFCLKs,

Global Clock (1),

Inter-Transceiver

Lines

Central Clock

Divider

Transmitter

PLL

Block

Transmitter High-Speed Serial

and Low-Speed Parallel Clocks

Local Clock

_DT_iviX_derC_Bl_loo_cc_kk

Gen Block

Transmitter Channels [1:0]

The transmitter PLL multiplies the input reference clock to generate the high-speed

serial clock required to support the intended protocol. It implements a half-rate

voltage controlled oscillator (VCO) that generates a clock at half the frequency of the

serial data rate for which it is configured.

Figure 2–4 shows the block diagram of the transmitter PLL.

Figure 2–4. Transmitter PLL

Transmitter PLL

/M⁽¹⁾

To

Inter-Transceiver Lines

up

down

Dedicated

REFCLK0

/2

Phase

Frequency

Detector

Charge

Pump + Loop

Filter

Voltage

Controlled

Oscillator

High Speed

Serial Clock

/L⁽¹⁾

Dedicated

REFCLK1

INCLK

Inter-Transceiver Lines[2:0]

Global Clock ⁽²⁾

Notes to Figure 2–4:

(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your

selections, the MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers (clock multiplication factors).

(2) The global clock line must be driven from an input pin only.

The reference clock input to the transmitter PLL can be derived from:

■

One of two available dedicated reference clock input pins (REFCLK0or REFCLK1)

of the associated transceiver block

■

PLD global clock network (must be driven directly from an input clock pin and

cannot be driven by user logic or enhanced PLL)

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–5

Transceivers

■

Inter-transceiver block lines driven by reference clock input pins of other

transceiver blocks

1

Altera^®recommends using the dedicated reference clock input pins (REFCLK0or

REFCLK1) to provide reference clock for the transmitter PLL.

Table 2–2 lists the adjustable parameters in the transmitter PLL.

Table 2–2. Transmitter PLL Specifications

Parameter

Input reference frequency range

Data rate support

Specifications

50 MHz to 622.08 MHz

600 Mbps to 3.125 Gbps

Low, medium, or high

Bandwidth

The transmitter PLL output feeds the central clock divider block and the local clock

divider blocks. These clock divider blocks divide the high-speed serial clock to

generate the low-speed parallel clock for the transceiver PCS logic and

PLD-transceiver interface clock.

Transmitter Phase Compensation FIFO Buffer

A transmitter phase compensation FIFO is located at each transmitter channel’s logic

array interface. It compensates for the phase difference between the transmitter PCS

clock and the local PLD clock. The transmitter phase compensation FIFO is used in all

supported functional modes. The transmitter phase compensation FIFO buffer is eight

words deep in PCI Express (PIPE) mode and four words deep in all other modes.

f

For more information about architecture and clocking, refer to the Arria GX Transceiver

Architecture chapter.

Byte Serializer

The byte serializer takes in two-byte wide data from the transmitter phase

compensation FIFO buffer and serializes it into a one-byte wide data at twice the

speed. The transmit data path after the byte serializer is 8 or 10 bits. This allows

clocking the PLD-transceiver interface at half the speed when compared with the

transmitter PCS logic. The byte serializer is bypassed in GIGE mode. After

serialization, the byte serializer transmits the least significant byte (LSByte) first and

the most significant byte (MSByte) last.

Arria GX Device Handbook, Volume 1

2–6

Chapter 2: Arria GX Architecture

Transceivers

Figure 2–5 shows byte serializer input and output. datain[15:0]is the input to the

byte serializer from the transmitter phase compensation FIFO; dataout[7:0]is the

output of the byte serializer.

Figure 2–5. Byte Serializer Operation (Note 1)

D1

D2

D3

datain[15:0]

dataout[7:0]

{8'h00,8'h01}

{8'h02,8'h03}

xxxx

D1_LSByte

D1_MSByte

D2_LSByte

D2_MSByte

xxxxxxxxxx

8'h01

8'h00

8'h03

8'h02

Note to Figure 2–5:

(1) datainmay be 16 or 20 bits. dataoutmay be 8 or 10 bits.

8B/10B Encoder

The 8B/10B encoder block is used in all supported functional modes. The 8B/10B

encoder block takes in 8-bit data from the byte serializer or the transmitter phase

compensation FIFO buffer. It generates a 10-bit code group with proper running

disparity from the 8-bit character and a 1-bit control identifier (tx_ctrlenable).

When tx_ctrlenableis low, the 8-bit character is encoded as data code group

(Dx.y). When tx_ctrlenableis high, the 8-bit character is encoded as a control

code group (Kx.y). The 10-bit code group is fed to the serializer. The 8B/10B encoder

conforms to the IEEE 802.3 1998 edition standard.

f

For additional information regarding 8B/10B encoding rules, refer to the Specifications

and Additional Information chapter.

Figure 2–6 shows the 8B/10B conversion format.

Figure 2–6. 8B/10B Encoder

7

6

5

F

4

3

2

1

0

Ctrl

H

G

E

D

C

B

A

8B-10B Conversion

j

h

g

f

i

e

4

d

3

c

b

a

0

9

8

7

6

5

2

1

MSB

LSB

During reset (tx_digitalreset), the running disparity and data registers are

cleared and the 8B/10B encoder continously outputs a K28.5 pattern from the

RD-column. After out of reset, the 8B/10B encoder starts with a negative disparity

(RD-) and transmits three K28.5 code groups for synchronizing before it starts

encoding the input data or control character.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–7

Transceivers

Transmit State Machine

The transmit state machine operates in either PCI Express (PIPE) mode, XAUI mode,

or GIGE mode, depending on the protocol used.

GIGE Mode

In GIGE mode, the transmit state machine converts all idle ordered sets (/K28.5/,

/Dx.y/) to either /I1/ or /I2/ ordered sets. The /I1/ set consists of a negative-ending

disparity /K28.5/ (denoted by /K28.5/-), followed by a neutral /D5.6/. The /I2/ set

consists of a positive-ending disparity /K28.5/ (denoted by /K28.5/+) and a

negative-ending disparity /D16.2/ (denoted by /D16.2/-). The transmit state

machines do not convert any of the ordered sets to match /C1/ or /C2/, which are

the configuration ordered sets. (/C1/ and /C2/ are defined by [/K28.5/, /D21.5/]

and [/K28.5/, /D2.2/], respectively). Both the /I1/ and /I2/ ordered sets guarantee a

negative-ending disparity after each ordered set.

XAUI Mode

The transmit state machine translates the XAUI XGMII code group to the XAUI PCS

code group. Table 2–3 lists the code conversion.

Table 2–3. On-Chip Termination Support by I/O Banks

XGMII TXC

XGMII TXD

PCS Code-Group

Description

Normal data

0

1

00 through FF

Dxx.y

07

9C

FB

FD

FE

K28.0 or K28.3 or K28.5

Idle in ||I||

Idle in ||T||

Sequence

Start

K28.5

K28.4

K27.7

K29.7

K30.7

Terminate

Error

Refer to IEEE 802.3 reserved code

groups

Refer to IEEE 802.3 reserved code

groups

Reserved code groups

1

Other value

K30.7

Invalid XGMII character

The XAUI PCS idle code groups, /K28.0/ (/R/) and /K28.5/ (/K/), are automatically

randomized based on a PRBS7 pattern with an ×7 + ×6 + 1 polynomial. The /K28.3/

(/A/) code group is automatically generated between 16 and 31 idle code groups. The

idle randomization on the /A/, /K/, and /R/ code groups is automatically done by

the transmit state machine.

Serializer (Parallel-to-Serial Converter)

The serializer block clocks in 8- or 10-bit encoded data from the 8B/10B encoder using

the low-speed parallel clock and clocks out serial data using the high-speed serial

clock from the central or local clock divider blocks. The serializer feeds the data LSB to

MSB to the transmitter output buffer.

Arria GX Device Handbook, Volume 1

2–8

Chapter 2: Arria GX Architecture

Transceivers

Figure 2–7 shows the serializer block diagram.

Figure 2–7. Serializer

D9

D8

D7

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D6

10

D5

8B/10B

From

Encoder

D4

D3

D2

D1

D0

To Transmitter

Output Buffer

Low-speed parallel clock

High-speed serial clock

CMU

Central /

Local Clock

Divider

Transmitter Buffer

The Arria GX transceiver buffers support the 1.2- and 1.5-V PCML I/O standard at

rates up to 3.125 Gbps. The common mode voltage (V_CM) of the output driver may be

set to 600 or 700 mV.

f

For more information about the Arria GX transceiver buffers, refer to the Arria GX

Transceiver Architecture chapter.

The output buffer, as shown in Figure 2–8, is directly driven by the high-speed data

serializer and consists of a programmable output driver, a programmable

pre-emphasis circuit, and OCT circuitry.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–9

Transceivers

Figure 2–8. Output Buffer

Serializer

Output Buffer

Programmable

Pre-Emphasis

Output

Pins

Programmable

Output

Driver

Programmable Output Driver

The programmable output driver can be set to drive out differentially from 400 to

1200 mV. The differential output voltage (V_OD) can be statically set by using the

ALTGXB megafunction.

You can configure the output driver with 100- OCT or external OCT.

Differential signaling conventions are shown in Figure 2–9. The differential amplitude

represents the value of the voltage between the true and complement signals.

Peak-to-peak differential voltage is defined as 2 (V_HIGH– V_LOW) = 2 single-ended

voltage swing. The common mode voltage is the average of V_HIGHand V_LOW

.

Figure 2–9. Differential Signaling

Single-Ended Waveform

V

high

True

+V

OD

-

Complement

V

low

Differential Waveform

+400

+V

OD

0-V Differential

−400

2 * V

OD

-V

OD

(Differential)

V

OD

−

= V

V

low

high

Arria GX Device Handbook, Volume 1

2–10

Chapter 2: Arria GX Architecture

Transceivers

Programmable Pre-Emphasis

The programmable pre-emphasis module controls the output driver to boost high

frequency components and compensate for losses in the transmission medium, as

shown in Figure 2–10. Pre-emphasis is set statically using the ALTGXB megafunction.

Figure 2–10. Pre-Emphasis Signaling

V

MIN

MAX

V

MAX

Pre-Emphasis % = (

− 1) × 100

V

MIN

Pre-emphasis percentage is defined as (V_MAX/V_MIN– 1) × 100, where V_MAXis the

differential emphasized voltage (peak-to-peak) and V_MINis the differential

steady-state voltage (peak-to-peak).

PCI Express (PIPE) Receiver Detect

The Arria GX transmitter buffer has a built-in receiver detection circuit for use in PCI

Express (PIPE) mode. This circuit provides the ability to detect if there is a receiver

downstream by sending out a pulse on the channel and monitoring the reflection.

This mode requires a tri-stated transmitter buffer (in electrical idle mode).

PCI Express (PIPE) Electric Idles (or Individual Transmitter Tri-State)

The Arria GX transmitter buffer supports PCI Express (PIPE) electrical idles. This

feature is only active in PCI Express (PIPE) mode. The tx_forceelecidleport puts

the transmitter buffer in electrical idle mode. This port is available in all PCI Express

(PIPE) power-down modes and has specific usage in each mode.

Receiver Path

This section describes the data path through the Arria GX receiver. The sub-blocks are

described in order from the receiver buffer to the PLD-receiver parallel interface.

Receiver Buffer

The Arria GX receiver input buffer supports the 1.2-V and 1.5-V PCML I/O standards

at rates up to 3.125 Gbps. The common mode voltage of the receiver input buffer is

programmable between 0.85 V and 1.2 V. You must select the 0.85 V common mode

voltage for AC- and DC-coupled PCML links and 1.2 V common mode voltage for

DC-coupled LVDS links.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–11

Transceivers

The receiver has 100- on-chip differential termination (R_DOCT) for different

protocols, as shown in Figure 2–11. You can disable the receiver’s internal termination

if external terminations and biasing are provided. The receiver and transmitter

differential termination method can be set independently of each other.

Figure 2–11. Receiver Input Buffer

100-Ω

Termination

Input

Pins

Programmable

Equalizer

Differential

Input

Buffer

If a design uses external termination, the receiver must be externally terminated and

biased to 0.85 V or 1.2 V. Figure 2–12 shows an example of an external termination and

biasing circuit.

Figure 2–12. External Termination and Biasing Circuit

Receiver External Termination

and Biasing

Arria GX Device

V

DD

50-W

Termination

Resistance

R1

C1

Receiver

R1/R2 = 1K

´ {R2/(R1 + R 2)} = 0.85/1.2 V

RXIP

V

R2

DD

RXIN

Receiver External Termination

and Biasing

Transmission

Line

Programmable Equalizer

The Arria GX receivers provide a programmable receiver equalization feature to

compensate for the effects of channel attenuation for high-speed signaling. PCB traces

carrying these high-speed signals have low-pass filter characteristics. Impedance

mismatch boundaries can also cause signal degradation. Equalization in the receiver

diminishes the lossy attenuation effects of the PCB at high frequencies.

Arria GX Device Handbook, Volume 1

2–12

Chapter 2: Arria GX Architecture

Transceivers

The receiver equalization circuit is comprised of a programmable amplifier. Each

stage is a peaking equalizer with a different center frequency and programmable gain.

This allows varying amounts of gain to be applied, depending on the overall

frequency response of the channel loss. Channel loss is defined as the summation of

all losses through the PCB traces, vias, connectors, and cables present in the physical

link. The Quartus II software allows five equalization settings for Arria GX devices.

Receiver PLL and Clock Recovery Unit (CRU)

Each transceiver block has four receiver PLLs and CRU units, each of which is

dedicated to a receiver channel. The receiver PLL is fed by an input reference clock.

The receiver PLL, in conjunction with the CRU, generates two clocks: a high-speed

serial recovered clock that clocks the deserializer and a low-speed parallel recovered

clock that clocks the receiver's digital logic.

Figure 2–13 shows a block diagram of the receiver PLL and CRU circuits.

Figure 2–13. Receiver PLL and Clock Recovery Unit

/M

rx_pll_locked

CP+LF

Dedicated

/2

REFCLK0

up

dn

PFD

Dedicated

REFCLK1

/2

VCO

/L

rx_cruclk

up

dn

Inter-Transceiver Lines [2:0]

Global Clock (2)

rx_freqlocked

rx_locktorefclk

(

)

Clock Recovery Unit CRU Control

rx_locktodata

rx_datain

High-speed serial recovered clk

Low-speed parallel recovered clk

Notes to Figure 2–13:

(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your

selections, the ALTGXB MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers.

(2) The global clock line must be driven from an input pin only.

The reference clock input to the receiver PLL can be derived from:

■

One of the two available dedicated reference clock input pins (REFCLK0or

REFCLK1) of the associated transceiver block

PLD global clock network (must be driven directly from an input clock pin and

cannot be driven by user logic or enhanced PLL)

Inter-transceiver block lines driven by reference clock input pins of other

transceiver blocks

All the parameters listed are programmable in the Quartus II software. The receiver

PLL has the following features:

■

Operates from 600 Mbps to 3.125 Gbps.

Uses a reference clock between 50 MHz and 622.08 MHz.

Programmable bandwidth settings: low, medium, and high.

Programmable rx_locktorefclk(forces the receiver PLL to lock to reference

clock) and rx_locktodata(forces the receiver PLL to lock to data).

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–13

Transceivers

■

The voltage-controlled oscillator (V_CO) operates at half rate.

Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and 25. Not all

settings are supported for any particular frequency.

■

Two lock indication signals are provided. They are found in PFD mode

(lock-to-reference clock), and PD (lock-to-data).

The CRU controls whether the receiver PLL locks to the input reference clock

(lock-to-reference mode) or the incoming serial data (lock-to data mode). You can set

the CRU to switch between lock-to-data and lock-to-reference modes automatically or

manually. In automatic lock mode, the phase detector and dedicated parts per million

(PPM) detector within each receiver channel control the switch between lock-to-data

and lock-to-reference modes based on some pre-set conditions. In manual lock mode,

you can control the switch manually using the rx_locktorefclkand

rx_locktodata signals.

f

For more information, refer to the “Clock Recovery Unit” section in the Arria GX

Transceiver Protocol Support and Additional Features chapter.

Table 2–4 lists the behavior of the CRU block with respect to the rx_locktorefclk

and rx_locktodatasignals.

Table 2–4. CRU Manual Lock Signals

rx_locktorefclk

rx_locktodata

CRU Mode

Lock-to-reference clock

Lock-to-data

1

x

0

1

0

Automatic

If the rx_locktorefclkand rx_locktodataports are not used, the default

setting is automatic lock mode.

Deserializer

The deserializer block clocks in serial input data from the receiver buffer using the

high-speed serial recovered clock and deserializes into 8- or 10-bit parallel data using

the low-speed parallel recovered clock. The serial data is assumed to be received with

LSB first, followed by MSB. It feeds the deserialized 8- or 10-bit data to the word

aligner, as shown in Figure 2–14.

Arria GX Device Handbook, Volume 1

2–14

Chapter 2: Arria GX Architecture

Transceivers

Figure 2–14. Deserializer (Note 1)

Received Data

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

10

To Word

Aligner

Clock

High-speed serial recovered clock

Low-speed parallel recovered clock

Recovery

Unit

Note to Figure 2–14:

(1) This is a 10-bit deserializer. The deserializer can also convert 8 bits of data.

Word Aligner

The deserializer block creates 8- or 10-bit parallel data. The deserializer ignores

protocol symbol boundaries when converting this data. Therefore, the boundaries of

the transferred words are arbitrary. The word aligner aligns the incoming data based

on specific byte or word boundaries. The word alignment module is clocked by the

local receiver recovered clock during normal operation. All the data and programmed

patterns are defined as “big-endian” (most significant word followed by least

significant word). Most-significant-bit-first protocols should reverse the bit order of

word align patterns programmed.

This module detects word boundaries for 8B/10B-based protocols. This module is

also used to align to specific programmable patterns in PRBS7/23 test mode.

Pattern Detection

The programmable pattern detection logic can be programmed to align word

boundaries using a single 7- or 10-bit pattern. The pattern detector can either do an

exact match, or match the exact pattern and the complement of a given pattern. Once

the programmed pattern is found, the data stream is aligned to have the pattern on

the LSB portion of the data output bus.

XAUI, GIGE, PCI Express (PIPE), and Serial RapidIO standards have embedded state

machines for symbol boundary synchronization. These standards use K28.5 as their

10-bit programmed comma pattern. Each of these standards uses different algorithms

before signaling symbol boundary acquisition to the FPGA.

Pattern detection logic searches from the LSB to the MSB. If multiple patterns are

found within the search window, the pattern in the lower portion of the data stream

(corresponding to the pattern received earlier) is aligned and the rest of the matching

patterns are ignored.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–15

Transceivers

Once a pattern is detected and the data bus is aligned, the word boundary is locked.

The two detection status signals (rx_syncstatusand rx_patterndetect)

indicate that an alignment is complete.

Figure 2–15 is a block diagram of the word aligner.

Figure 2–15. Word Aligner

datain

bitslip

dataout

Word

Aligner

syncstatus

enapatternalign

clock

patterndetect

Control and Status Signals

The rx_enapatternalignsignal is the FPGA control signal that enables word

alignment in non-automatic modes. The rx_enapatternalignsignal is not used in

automatic modes (PCI Express [PIPE], XAUI, GIGE, and Serial RapidIO).

In manual alignment mode, after the rx_enapatternalignsignal is activated, the

rx_syncstatussignal goes high for one parallel clock cycle to indicate that the

alignment pattern has been detected and the word boundary has been locked. If

rx_enapatternalignis deactivated, the rx_syncstatussignal acts as a

re-synchronization signal to signify that the alignment pattern has been detected but

not locked on a different word boundary.

When using the synchronization state machine, the rx_syncstatussignal indicates

the link status. If the rx_syncstatussignal is high, link synchronization is

achieved. If the rx_syncstatussignal is low, link synchronization has not yet been

achieved, or there were enough code group errors to lose synchronization.

f

For more information about manual alignment modes, refer to the Arria GX Device

Handbook.

The rx_patterndetectsignal pulses high during a new alignment and whenever

the alignment pattern occurs on the current word boundary.

Programmable Run Length Violation

The word aligner supports a programmable run length violation counter. Whenever

the number of the continuous ‘0’ (or ‘1’) exceeds a user programmable value, the

rx_rlvsignal goes high for a minimum pulse width of two recovered clock cycles.

The maximum run values supported are 128 UI for 8-bit serialization or 160 UI for

10-bit serialization.

Running Disparity Check

The running disparity error rx_disperrand running disparity value

rx_runningdispare sent along with aligned data from the 8B/10B decoder to the

FPGA. You can ignore or act on the reported running disparity value and running

disparity error signals.

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2–16

Chapter 2: Arria GX Architecture

Transceivers

Bit-Slip Mode

The word aligner can operate in either pattern detection mode or in bit-slip mode.

The bit-slip mode provides the option to manually shift the word boundary through

the FPGA. This feature is useful for:

■

Longer synchronization patterns than the pattern detector can accommodate

Scrambled data stream

Input stream consisting of over-sampled data

The word aligner outputs a word boundary as it is received from the analog receiver

after reset. You can examine the word and search its boundary in the FPGA. To do so,

assert the rx_bitslipsignal. The rx_bitslipsignal should be toggled and held

constant for at least two FPGA clock cycles.

For every rising edge of the rx_bitslipsignal, the current word boundary is

slipped by one bit. Every time a bit is slipped, the bit received earliest is lost. If bit

slipping shifts a complete round of bus width, the word boundary is back to the

original boundary.

The rx_syncstatussignal is not available in bit-slipping mode.

Channel Aligner

The channel aligner is available only in XAUI mode and aligns the signals of all four

channels within a transceiver. The channel aligner follows the IEEE 802.3ae, clause 48

specification for channel bonding.

The channel aligner is a 16-word FIFO buffer with a state machine controlling the

channel bonding process. The state machine looks for an /A/ (/K28.3/) in each

channel and aligns all the /A/ code groups in the transceiver. When four columns of

/A/ (denoted by //A//) are detected, the rx_channelaligned signal goes high,

signifying that all the channels in the transceiver have been aligned. The reception of

four consecutive misaligned /A/ code groups restarts the channel alignment

sequence and sends the rx_channelalignedsignal low.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–17

Transceivers

Figure 2–16 shows misaligned channels before the channel aligner and the aligned

channels after the channel aligner.

Figure 2–16. Before and After the Channel Aligner

Lane 3

K

R

A

K

R

K

R

K

R

Lane 2

K

R

A

K

R

K

R

K

R

Lane 1

K

R

A

K

R

K

R

K

R

Lane 0

K

R

A

K

R

K

R

K

R

Lane 3

Lane 2

Lane 1

Lane 0

K

R

A

K

R

K

R

K

R

K

Rate Matcher

In asynchronous systems, the upstream transmitter and local receiver can be clocked

with independent reference clock sources. Frequency differences in the order of a few

hundred PPM can potentially corrupt the data at the receiver.

The rate matcher compensates for small clock frequency differences between the

upstream transmitter and the local receiver clocks by inserting or removing skip

characters from the inter packet gap (IPG) or idle streams. It inserts a skip character if

the local receiver is running a faster clock than the upstream transmitter. It deletes a

skip character if the local receiver is running a slower clock than the upstream

transmitter. The Quartus II software automatically configures the appropriate skip

character as specified in the IEEE 802.3 for GIGE mode and PCI-Express Base

Specification for PCI Express (PIPE) mode. The rate matcher is bypassed in Serial

RapidIO and must be implemented in the PLD logic array or external circuits

depending on your system design.

Table 2–5 lists the maximum frequency difference that the rate matcher can tolerate in

XAUI, PCI Express (PIPE), GIGE, and Basic functional modes.

Table 2–5. Rate Matcher PPM Tolerance

Function Mode

XAUI

PPM

100

300

100

300

PCI Express (PIPE)

GIGE

Basic

Arria GX Device Handbook, Volume 1

2–18

Chapter 2: Arria GX Architecture

Transceivers

XAUI Mode

In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae specification

for clock rate compensation. The rate matcher performs clock compensation on

columns of /R/ (/K28.0/), denoted by //R//. An //R// is added or deleted

automatically based on the number of words in the FIFO buffer.

PCI Express (PIPE) Mode Rate Matcher

In PCI Express (PIPE) mode, the rate matcher can compensate up to 300 PPM

(600 PPM total) frequency difference between the upstream transmitter and the

receiver. The rate matcher logic looks for skip ordered sets (SOS), which contains a

/K28.5/ comma followed by three /K28.0/ skip characters. The rate matcher logic

deletes or inserts /K28.0/ skip characters as necessary from/to the rate matcher FIFO.

The rate matcher in PCI Express (PIPE) mode has a FIFO buffer overflow and

underflow protection. In the event of a FIFO buffer overflow, the rate matcher deletes

any data after detecting the overflow condition to prevent FIFO pointer corruption

until the rate matcher is not full. In an underflow condition, the rate matcher inserts

9'h1FE (/K30.7/) until the FIFO buffer is not empty. These measures ensure that the

FIFO buffer can gracefully exit the overflow and underflow condition without

requiring a FIFO reset. The rate matcher FIFO overflow and underflow condition is

indicated on the pipestatusport.

You can bypass the rate matcher in PCI Express (PIPE) mode if you have a

synchronous system where the upstream transmitter and local receiver derive their

reference clocks from the same source.

GIGE Mode Rate Matcher

In GIGE mode, the rate matcher can compensate up to 100 PPM (200 PPM total)

frequency difference between the upstream transmitter and the receiver. The rate

matcher logic inserts or deletes /I2/ idle ordered sets to/from the rate matcher FIFO

during the inter-frame or inter-packet gap (IFG or IPG). /I2/ is selected as the rate

matching ordered set because it maintains the running disparity, unlike /I1/ that

alters the running disparity. Because the /I2/ ordered-set contains two 10-bit code

groups (/K28.5/, /D16.2/), 20 bits are inserted or deleted at a time for rate matching.

1

The rate matcher logic has the capability to insert or delete /C1/ or /C2/

configuration ordered sets when ‘GIGE Enhanced’ mode is chosen as the sub-protocol

in the MegaWizard Plug-In Manager.

If the frequency PPM difference between the upstream transmitter and the local

receiver is high, or if the packet size is too large, the rate matcher FIFO buffer can face

an overflow or underflow situation.

Basic Mode

In basic mode, you can program the skip and control pattern for rate matching. There

is no restriction on the deletion of a skip character in a cluster. The rate matcher

deletes the skip characters as long as they are available. For insertion, the rate matcher

inserts skip characters such that the number of skip characters at the output of rate

matcher does not exceed five.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–19

Transceivers

8B/10B Decoder

The 8B/10B decoder is used in all supported functional modes. The 8B/10B decoder

takes in 10-bit data from the rate matcher and decodes it into 8-bit data + 1-bit control

identifier, thereby restoring the original transmitted data at the receiver. The 8B/10B

decoder indicates whether the received 10-bit character is a data or control code

through the rx_ctrldetectport. If the received 10-bit code group is a control

character (Kx.y), the rx_ctrldetectsignal is driven high and if it is a data

character (Dx.y), the rx_ctrldetectsignal is driven low.

Figure 2–17 shows a 10-bit code group decoded to an 8-bit data and a 1-bit control

indicator.

Figure 2–17. 10-Bit to 8-Bit Conversion

j

h

8

g

7

f

i

e

4

d

3

c

b

a

0

9

6

5

2

1

MSB Received Last

LSB Received First

8B/10B Conversion

Parallel Data

ctrl

7

6

5

F

4

3

2

1

0

H

G

E

D

C

B

A

If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups, the 8B/10B

decoder block asserts an error flag on the rx_errdetectport. If the received 10-bit

code is detected with incorrect running disparity, the 8B/10B decoder block asserts an

error flag on the rx_disperrand rx_errdetectports. The error flag signals

(rx_errdetectand rx_disperr) have the same data path delay from the 8B/10B

decoder to the PLD-transceiver interface as the bad code group.

Receiver State Machine

The receiver state machine operates in Basic, GIGE, PCI Express (PIPE), and XAUI

modes. In GIGE mode, the receiver state machine replaces invalid code groups with

K30.7. In XAUI mode, the receiver state machine translates the XAUI PCS code group

to the XAUI XGMII code group.

Arria GX Device Handbook, Volume 1

2–20

Chapter 2: Arria GX Architecture

Transceivers

Byte Deserializer

Byte deserializer takes in one-byte wide data from the 8B/10B decoder and

deserializes it into a two-byte wide data at half the speed. This allows clocking the

PLD-receiver interface at half the speed as compared to the receiver PCS logic. The

byte deserializer is bypassed in GIGE mode.

The byte ordering at the receiver output might be different than what was

transmitted. This is a non-deterministic swap, because it depends on PLL lock times

and link delay. If required, you must implement byte ordering logic in the PLD to

correct this situation.

f

For more information about byte serializer, refer to the Arria GX Transceiver

Architecture chapter.

Receiver Phase Compensation FIFO Buffer

A receiver phase compensation FIFO buffer is located at each receiver channel’s logic

array interface. It compensates for the phase difference between the receiver PCS

clock and the local PLD receiver clock. The receiver phase compensation FIFO is used

in all supported functional modes. The receiver phase compensation FIFO buffer is

eight words deep in PCI Express (PIPE) mode and four words deep in all other

modes.

For more information about architecture and clocking, refer to the Arria GX Transceiver

Architecture chapter.

Loopback Modes

Arria GX transceivers support the following loopback configurations for diagnostic

purposes:

■

Serial loopback

Reverse serial loopback

Reverse serial loopback (pre-CDR)

PCI Express (PIPE) reverse parallel loopback (available only in [PIPE] mode)

Serial Loopback

Figure 2–18 shows the transceiver data path in serial loopback.

Figure 2–18. Transceiver Data Path in Serial Loopback

Transmitter PCS

Transmitter PMA

TX Phase

Compen-

sation

Byte

Serializer

8B/10B

Encoder

Serializer

FIFO

PLD

Logic

Array

Serial Loopback

Receiver PCS

Receiver PMA

RX Phase

Compen-

sation

Clock

Recovery

Unit

De-

Serializer

Rate

Match

FIFO

Byte

De-

Serializer

8B/10B

Decoder

Word

Aligner

FIFO

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–21

Transceivers

In GIGE and Serial RapidIO modes, you can dynamically put each transceiver

channel individually in serial loopback by controlling the rx_seriallpbkenport. A

high on the rx_seriallpbken port puts the transceiver into serial loopback and a

low takes the transceiver out of serial loopback.

As seen in Figure 2–18, the serial data output from the transmitter serializer is looped

back to the receiver CRU in serial loopback. The transmitter data path from the PLD

interface to the serializer in serial loopback is the same as in non-loopback mode. The

receiver data path from the clock recovery unit to the PLD interface in serial loopback

is the same as in non-loopback mode. Because the entire transceiver data path is

available in serial loopback, this option is often used to diagnose the data path as a

probable cause of link errors.

1

When serial loopback is enabled, the transmitter output buffer is still active and

drives the serial data out on the tx_dataoutport.

Reverse Serial Loopback

Reverse serial loopback mode uses the analog portion of the transceiver. An external

source (pattern generator or transceiver) generates the source data. The high-speed

serial source data arrives at the high-speed differential receiver input buffer, passes

through the CRU unit and the retimed serial data is looped back, and is transmitted

though the high-speed differential transmitter output buffer.

Figure 2–19 shows the data path in reverse serial loopback mode.

Figure 2–19. Arria GX Block in Reverse Serial Loopback Mode

Transmitter Digital Logic

Analog Receiver and

Transmitter Logic

BIST

PRBS

Generator

Incremental

Generator

TX Phase

Compensation

FIFO

Byte

Serializer

8B/10B

Encoder

Serializer

20

FPGA

Logic

Array

Reverse

Serial

Loopback

BIST

PRBS

Verify

Incremental

Verify

Byte

De-

serializer

Rate

Match

FIFO

Clock

De-

RX Phase

Compen-

sation

8B/10B

Decoder

Deskew

FIFO

Word

Aligner

Recovery

serializer

Unit

FIFO

Receiver Digital Logic

Arria GX Device Handbook, Volume 1

2–22

Chapter 2: Arria GX Architecture

Transceivers

Reverse Serial Pre-CDR Loopback

Reverse serial pre-CDR loopback mode uses the analog portion of the transceiver. An

external source (pattern generator or transceiver) generates the source data. The

high-speed serial source data arrives at the high-speed differential receiver input

buffer, loops back before the CRU unit, and is transmitted though the high-speed

differential transmitter output buffer. It is for test or verification use only to verify the

signal being received after the gain and equalization improvements of the input

buffer. The signal at the output is not exactly what is received because the signal goes

through the output buffer and the V_ODis changed to the V_ODsetting level.

Pre-emphasis settings have no effect.

Figure 2–20 shows the Arria GX block in reverse serial pre-CDR loopback mode.

Figure 2–20. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode

Transmitter Digital Logic

Analog Receiver and

Transmitter Logic

BIST

PRBS

Generator

BIST

Incremental

Generator

TX Phase

Compensation

Byte

Serializer

8B/10B

Encoder

Serializer

20

FIFO

FPGA

Logic

Array

Reverse

Serial

Pre-CDR

Loopback

BIST

Incremental

Verify

BIST

PRBS

Verify

Byte

De-

serializer

Rate

Match

FIFO

Clock

De-

RX Phase

Compen-

sation

8B/10B

Decoder

Deskew

FIFO

Word

Aligner

Recovery

serializer

Unit

FIFO

Receiver Digital Logic

PCI Express (PIPE) Reverse Parallel Loopback

Figure 2–21 shows the data path for PCI Express (PIPE) reverse parallel loopback. The

reverse parallel loopback configuration is compliant with the PCI Express (PIPE)

specification and is available only on PCI Express (PIPE) mode.

Figure 2–21. PCI Express (PIPE) Reverse Parallel Loopback

Transmitter PCS

Transmitter PMA

TX Phase

Compe-

nsation

FIFO

Byte

Serializer

8B/10B

Encoder

Serializer

PIPE

Interface

PIPE Reverse

Parallel Loopback

Receiver PCS

Receiver PMA

RX Phase

Clock

De-

Byte

De-

Serializer

Rate

Match

FIFO

Compe-

nsation

FIFO

8B/10B

Decoder

Word

Aligner

Recovery

Serializer

Unit

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–23

Transceivers

You can dynamically put the PCI Express (PIPE) mode transceiver in reverse parallel

loopback by controlling the tx_detectrxloopbackport instantiated in the

MegaWizard Plug-In Manager. A high on the tx_detectrxloopbackport in P0

power state puts the transceiver in reverse parallel loopback. A high on the

tx_detectrxloopbackport in any other power state does not put the transceiver

in reverse parallel loopback.

As seen in Figure 2–21, the serial data received on the rx_datainport in reverse

parallel loopback goes through the CRU, deserializer, word aligner, and the rate

matcher blocks. The parallel data at the output of the receiver rate matcher block is

looped back to the input of the transmitter serializer block. The serializer converts the

parallel data to serial data and feeds it to the transmitter output buffer that drives the

data out on the tx_dataoutport. The data at the output of the rate matcher also

goes through the 8B/10B decoder, byte deserializer, and receiver phase compensation

FIFO before being fed to the PLD on the rx_dataoutport.

Reset and Powerdown

Arria GX transceivers offer a power saving advantage with their ability to shut off

functions that are not needed.

The following three reset signals are available per transceiver channel and can be used

to individually reset the digital and analog portions within each channel:

■

tx_digitalreset

rx_analogreset

rx_digitalreset

The following two powerdown signals are available per transceiver block and can be

used to shut down an entire transceiver block that is not being used:

■

gxb_powerdown

gxb_enable

■

Arria GX Device Handbook, Volume 1

2–24

Chapter 2: Arria GX Architecture

Transceivers

Table 2–6 lists the reset signals available in Arria GX devices and the transceiver

circuitry affected by each signal.

Table 2–6. Reset Signal Map to Arria GX Blocks

Reset Signal

rx_digitalreset

rx_analogreset

tx_digitalreset

gxb_powerdown

gxb_enable

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

Calibration Block

Arria GX devices use the calibration block to calibrate OCT for the PLLs, and their

associated output buffers, and the terminating resistors on the transceivers. The

calibration block counters the effects of process, voltage, and temperature (PVT). The

calibration block references a derived voltage across an external reference resistor to

calibrate the OCT resistors on Arria GX devices. You can power down the calibration

block. However, powering down the calibration block during operations can yield

transmit and receive data errors.

Transceiver Clocking

This section describes the clock distribution in an Arria GX transceiver channel and

the PLD clock resource utilization by the transceiver blocks.

Transceiver Channel Clock Distribution

Each transceiver block has one transmitter PLL and four receiver PLLs.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–25

Transceivers

The transmitter PLL multiplies the input reference clock to generate a high-speed

serial clock at a frequency that is half the data rate of the configured functional mode.

This high-speed serial clock (or its divide-by-two version if the functional mode uses

byte serializer) is fed to the CMU clock divider block. Depending on the configured

functional mode, the CMU clock divider block divides the high-speed serial clock to

generate the low-speed parallel clock that clocks the transceiver PCS logic in the

associated channel. The low-speed parallel clock is also forwarded to the PLD logic

array on the tx_clkoutor coreclkoutports.

The receiver PLL in each channel is also fed by an input reference clock. The receiver

PLL along with the clock recovery unit generates a high-speed serial recovered clock

and a low-speed parallel recovered clock. The low-speed parallel recovered clock

feeds the receiver PCS logic until the rate matcher. The CMU low-speed parallel clock

clocks the rest of the logic from the rate matcher until the receiver phase

compensation FIFO. In modes that do not use a rate matcher, the receiver PCS logic is

clocked by the recovered clock until the receiver phase compensation FIFO.

The input reference clock to the transmitter and receiver PLLs can be derived from:

■

One of two available dedicated reference clock input pins (REFCLK0or REFCLK1)

of the associated transceiver block

PLD clock network (must be driven directly from an input clock pin and cannot be

driven by user logic or enhanced PLL)

Inter-transceiver block lines driven by reference clock input pins of other

transceiver blocks

Figure 2–22 shows the input reference clock sources for the transmitter and receiver

PLL.

Figure 2–22. Input Reference Clock Sources

Inter-Transceiver Lines [2]

Transceiver Block 2

Transceiver Block 1

Inter-Transceiver Lines [1]

Transceiver Block 0

Inter-Transceiver Lines [0]

Dedicated

REFCLK0

/2

Transmitter

PLL

Dedicated

REFCLK1

Inter-Transceiver Lines [2:0]

Global Clock (1)

Four

Receiver

PLLs

Global Clock (1)

Arria GX Device Handbook, Volume 1

2–26

Chapter 2: Arria GX Architecture

Transceivers

f

For more information about transceiver clocking in all supported functional modes,

refer to the Arria GX Transceiver Architecture chapter.

PLD Clock Utilization by Transceiver Blocks

Arria GX devices have up to 16 global clock (GCLK) lines and 16 regional clock

(RCLK) lines that are used to route the transceiver clocks. The following transceiver

clocks use the available global and regional clock resources:

■

pll_inclk(if driven from an FPGA input pin)

rx_cruclk(if driven from an FPGA input pin)

tx_clkout/coreclkout(CMU low-speed parallel clock forwarded to the PLD)

Recovered clock from each channel (rx_clkout) in non-rate matcher mode

Calibration clock (cal_blk_clk)

Fixed clock (fixedclkused for receiver detect circuitry in PCI Express [PIPE]

mode only)

Figure 2–23 and Figure 2–24 show the available GCLK and RCLK resources in Arria

GX devices.

Figure 2–23. Global Clock Resources in Arria GX Devices

CLK[15..12]

11 5

7

Arria GX

Transceiver

Block

GCLK[15..12]

GCLK[11..8]

1

2

GCLK[3..0]

CLK[3..0]

Arria GX

Transceiver

Block

GCLK[4..7]

8

12 6

CLK[7..4]

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–27

Transceivers

Figure 2–24. Regional Clock Resources in Arria GX Devices

CLK[15..12]

11 5

7

RCLK

[31..28]

[27..24]

Arria GX

Transceiver

Block

RCLK

[3..0]

RCLK

[23..20]

1

2

CLK[3..0]

RCLK

[7..4]

RCLK

[19..16]

Arria GX

Transceiver

Block

RCLK

[11..8]

RCLK

[15..12]

8

12 6

CLK[7..4]

For the RCLK or GCLK network to route into the transceiver, a local route input

output (LRIO) channel is required. Each LRIO clock region has up to eight clock paths

and each transceiver block has a maximum of eight clock paths for connecting with

LRIO clocks. These resources are limited and determine the number of clocks that can

be used between the PLD and transceiver blocks. Table 2–7 and Table 2–8 list the

number of LRIO resources available for Arria GX devices with different numbers of

transceiver blocks.

Table 2–7. Available Clocking Connections for Transceivers in EP1AGX35D, EP1AGX50D, and EP1AGX60D

Clock Resource

Transceiver

Source

Bank13

8 Clock I/O

Bank14

8 Clock I/O

Global Clock

Regional Clock

Region0 8 LRIO clock

Region1 8 LRIO clock

v

RCLK 20-27

RCLK 12-19

v

—

v

Table 2–8. Available Clocking Connections for Transceivers in EP1AGX60E and EP1AGX90E

Clock Resource Transceiver

Source

Bank13

8 Clock I/O

Bank14

8 Clock I/O

Bank15

8 Clock I/O

Global Clock

Regional Clock

Region0 8 LRIO clock

Region1 8 LRIO clock

Region2 8 LRIO clock

Region3 8 LRIO clock

v

RCLK 20-27

RCLK 12-19

v

—

v

—

v

Arria GX Device Handbook, Volume 1

2–28

Chapter 2: Arria GX Architecture

Logic Array Blocks

Each logic array block (LAB) consists of eight adaptive logic modules (ALMs), carry

chains, shared arithmetic chains, LAB control signals, local interconnects, and register

chain connection lines. The local interconnect transfers signals between ALMs in the

same LAB. Register chain connections transfer the output of an ALM register to the

adjacent ALM register in a LAB. The Quartus II Compiler places associated logic in a

LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register

chain connections for performance and area efficiency. Table 2–9 lists Arria GX device

resources. Figure 2–25 shows the Arria GX LAB structure.

Table 2–9. Arria GX Device Resources

M512 RAM

M4K RAM

DSP Block

Device

EP1AGX20

M-RAM Blocks

Columns/Blocks

166

197

313

326

478

118

140

242

252

400

1

2

4

10

14

26

32

44

EP1AGX35

EP1AGX50

EP1AGX60

EP1AGX90

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–29

Logic Array Blocks

Figure 2–25. Arria GX LAB Structure

Row Interconnects of

Variable Speed & Length

ALMs

Direct link

interconnect from

adjacent block

Direct link

interconnect from

adjacent block

Direct link

interconnect to

adjacent block

interconnect to

adjacent block

Local Interconnect

LAB

Local Interconnect is Driven

from Either Side by Columns & LABs,

& from Above by Rows

Column Interconnects of

Variable Speed & Length

LAB Interconnects

The LAB local interconnect can drive all eight ALMs in the same LAB. It is driven by

column and row interconnects and ALM outputs in the same LAB. Neighboring

LABs, M512 RAM blocks, M4K RAM blocks, M-RAM blocks, or digital signal

processing (DSP) blocks from the left and right can also drive the local interconnect of

a LAB through the direct link connection. The direct link connection feature

minimizes the use of row and column interconnects, providing higher performance

and flexibility. Each ALM can drive 24 ALMs through fast local and direct link

interconnects.

Arria GX Device Handbook, Volume 1

2–30

Chapter 2: Arria GX Architecture

Logic Array Blocks

Figure 2–26 shows the direct link connection.

Figure 2–26. Direct Link Connection

Direct link interconnect from

left LAB, TriMatrix^TMmemory

block, DSP block, or

Direct link interconnect from

right LAB, TriMatrix memory

block, DSP block, or IOE output

input/output element (IOE)

ALMs

Direct link

interconnect

to right

Direct link

interconnect

to left

Local

Interconnect

LAB

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its ALMs. The control

signals include three clocks, three clock enables, two asynchronous clears,

synchronous clear, asynchronous preset or load, and synchronous load control

signals, providing a maximum of 11 control signals at a time. Although synchronous

load and clear signals are generally used when implementing counters, they can also

be used with other functions.

Each LAB can use three clocks and three clock enable signals. However, there can only

be up to two unique clocks per LAB, as shown in the LAB control signal generation

circuit in Figure 2–27. Each LAB’s clock and clock enable signals are linked. For

example, any ALM in a particular LAB using the labclk1signal also uses

labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses

two LAB-wide clock signals. De-asserting the clock enable signal turns off the

corresponding LAB-wide clock. Each LAB can use two asynchronous clear signals

and an asynchronous load/preset signal. The asynchronous load acts as a preset

when the asynchronous load data input is tied high. When the asynchronous

load/preset signal is used, the labclkena0signal is no longer available.

The LAB row clocks [5..0]and LAB local interconnect generate the LAB-wide

control signals. The MultiTrack interconnects have inherently low skew. This low

skew allows the MultiTrack interconnects to distribute clock and control signals in

addition to data.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–31

Adaptive Logic Modules

Figure 2–27 shows the LAB control signal generation circuit.

Figure 2–27. LAB-Wide Control Signals

There are two unique

clock signals per LAB.

6

Dedicated Row LAB Clocks

6

Local Interconnect

labclr1

labclk0

syncload

labclk1

labclk2

labclkena2

labclkena0

or asyncload

or labpreset

labclkena1

labclr0

synclr

Adaptive Logic Modules

The basic building block of logic in the Arria GX architecture is the ALM. The ALM

provides advanced features with efficient logic utilization. Each ALM contains a

variety of look-up table (LUT)-based resources that can be divided between two

adaptive LUTs (ALUTs). With up to eight inputs to the two ALUTs, one ALM can

implement various combinations of two functions. This adaptability allows the ALM

to be completely backward-compatible with four-input LUT architectures. One ALM

can also implement any function of up to six inputs and certain seven-input functions.

In addition to the adaptive LUT-based resources, each ALM contains two

programmable registers, two dedicated full adders, a carry chain, a shared arithmetic

chain, and a register chain. Through these dedicated resources, the ALM can

efficiently implement various arithmetic functions and shift registers. Each ALM

drives all types of interconnects: local, row, column, carry chain, shared arithmetic

chain, register chain, and direct link interconnects. Figure 2–28 shows a high-level

block diagram of the Arria GX ALM while Figure 2–29 shows a detailed view of all

the connections in the ALM.

Arria GX Device Handbook, Volume 1

2–32

Chapter 2: Arria GX Architecture

Adaptive Logic Modules

Figure 2–28. High-Level Block Diagram of the Arria GX ALM

carry_in

shared_arith_in

reg_chain_in

To general or

local routing

dataf0

To general or

local routing

adder0

D

Q

datae0

dataa

reg0

datab

Combinational

Logic

datac

datad

To general or

local routing

adder1

D

Q

datae1

dataf1

reg1

To general or

local routing

carry_out

shared_arith_out

reg_chain_out

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–33

Adaptive Logic Modules

Figure 2–29. Arria GX ALM Details

I n t e r c o n n e c t

L o c a l

Arria GX Device Handbook, Volume 1

2–34

Chapter 2: Arria GX Architecture

Adaptive Logic Modules

One ALM contains two programmable registers. Each register has data, clock, clock

enable, synchronous and asynchronous clear, asynchronous load data, and

synchronous and asynchronous load/preset inputs.

Global signals, general-purpose I/O pins, or any internal logic can drive the register's

clock and clear control signals. Either general-purpose I/O pins or internal logic can

drive the clock enable, preset, asynchronous load, and asynchronous load data. The

asynchronous load data input comes from the dataeor datafinput of the ALM,

which are the same inputs that can be used for register packing. For combinational

functions, the register is bypassed and the output of the LUT drives directly to the

outputs of the ALM.

Each ALM has two sets of outputs that drive the local, row, and column routing

resources. The LUT, adder, or register output can drive these output drivers

independently (refer to Figure 2–29). For each set of output drivers, two ALM outputs

can drive column, row, or direct link routing connections. One of these ALM outputs

can also drive local interconnect resources. This allows the LUT or adder to drive one

output while the register drives another output. This feature, called register packing,

improves device utilization because the device can use the register and combinational

logic for unrelated functions. Another special packing mode allows the register

output to feed back into the LUT of the same ALM so that the register is packed with

its own fan-out LUT. This feature provides another mechanism for improved fitting.

The ALM can also drive out registered and unregistered versions of the LUT or adder

output.

ALM Operating Modes

The Arria GX ALM can operate in one of the following modes:

■

Normal mode

Extended LUT mode

Arithmetic mode

Shared arithmetic mode

Each mode uses ALM resources differently. Each mode has 11 available inputs to the

ALM (refer to Figure 2–28)the eight data inputs from the LAB local interconnect;

carry-in from the previous ALM or LAB; the shared arithmetic chain connection from

the previous ALM or LAB; and the register chain connectionare directed to different

destinations to implement the desired logic function. LAB-wide signals provide clock,

asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load,

and clock enable control for the register. These LAB-wide signals are available in all

ALM modes. For more information about LAB-wide control signals, refer to “LAB

Control Signals” on page 2–30.

The Quartus II software and supported third-party synthesis tools, in conjunction

with parameterized functions such as library of parameterized modules (LPM)

functions, automatically choose the appropriate mode for common functions such as

counters, adders, subtractors, and arithmetic functions. If required, you can also

create special-purpose functions that specify which ALM operating mode to use for

optimal performance.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–35

Adaptive Logic Modules

Normal Mode

Normal mode is suitable for general logic applications and combinational functions.

In this mode, up to eight data inputs from the LAB local interconnect are inputs to the

combinational logic. Normal mode allows two functions to be implemented in one

Arria GX ALM, or an ALM to implement a single function of up to six inputs. The

ALM can support certain combinations of completely independent functions and

various combinations of functions which have common inputs. Figure 2–30 shows the

supported LUT combinations in normal mode.

Figure 2–30. ALM in Normal Mode (Note 1)

dataf0

datae0

datac

dataa

datab

dataf0

datae0

datac

4-Input

LUT

5-Input

LUT

combout0

combout1

combout0

combout1

dataa

datab

datad

datae1

dataf1

4-Input

LUT

5-Input

LUT

datad

datae1

dataf1

dataf0

datae0

datac

dataa

datab

5-Input

LUT

dataf0

datae0

dataa

datab

datac

datad

combout0

combout1

6-Input

LUT

combout0

datad

datae1

dataf1

3-Input

LUT

dataf0

datae0

dataa

datab

datac

datad

6-Input

LUT

combout0

combout1

dataf0

datae0

datac

dataa

datab

5-Input

LUT

combout0

combout1

6-Input

LUT

datad

datae1

4-Input

LUT

datae1

dataf1

Note to Figure 2–30:

(1) Combinations of functions with less inputs than those shown are also supported. For example, combinations of functions with the following

number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, and so on.

Normal mode provides complete backward compatibility with four-input LUT

architectures. Two independent functions of four inputs or less can be implemented in

one Arria GX ALM. In addition, a five-input function and an independent three-input

function can be implemented without sharing inputs.

Arria GX Device Handbook, Volume 1

2–36

Chapter 2: Arria GX Architecture

Adaptive Logic Modules

To pack two five-input functions into one ALM, the functions must have at least two

common inputs. The common inputs are dataaand datab. The combination of a

four-input function with a five-input function requires one common input

(either dataaor datab).

To implement two six-input functions in one ALM, four inputs must be shared and

the combinational function must be the same. For example, a 4 × 2 crossbar switch

(two 4-to-1 multiplexers with common inputs and unique select lines) can be

implemented in one ALM, as shown in Figure 2–31. The shared inputs are dataa,

datab, datac, and datad, while the unique select lines are datae0and dataf0 for

function0, and datae1and dataf1for function1. This crossbar switch

consumes four LUTs in a four-input LUT-based architecture.

Figure 2–31. 4 × 2 Crossbar Switch Example

4 ´ 2 Crossbar Switch

Implementation in 1 ALM

sel0[1..0]

dataf0

datae0

dataa

datab

datac

datad

inputa

inputb

Six-Input

LUT

(Function0)

out0

combout0

combout1

inputc

inputd

out1

sel1[1..0]

Six-Input

LUT

(Function1)

datae1

dataf1

In a sparsely used device, functions that can be placed into one ALM can be

implemented in separate ALMs. The Quartus II Compiler spreads a design out to

achieve the best possible performance. As a device begins to fill up, the Quartus II

software automatically uses the full potential of the Arria GX ALM. The Quartus II

Compiler automatically searches for functions of common inputs or completely

independent functions to be placed into one ALM and to make efficient use of the

device resources. In addition, you can manually control resource usage by setting

location assignments. Any six-input function can be implemented utilizing inputs

dataa, datab, datac, datad, and either datae0and dataf0or datae1and

dataf1. If datae0and dataf0are used, the output is driven to register0,

and/or register0is bypassed and the data drives out to the interconnect using the

top set of output drivers (refer to Figure 2–32). If datae1and dataf1are used, the

output drives to register1and/or bypasses register1and drives to the

interconnect using the bottom set of output drivers. The Quartus II Compiler

automatically selects the inputs to the LUT. Asynchronous load data for the register

comes from the dataeor datafinput of the ALM. ALMs in normal mode support

register packing.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–37

Adaptive Logic Modules

Figure 2–32. Six-Input Function in Normal Mode Note (1), (2)

To general or

local routing

dataf0

datae0

dataa

datab

datac

datad

6-Input

LUT

To general or

local routing

D

Q

reg0

datae1

dataf1

(2)

To general or

local routing

Q

These inputs are available for register packing.

reg1

Notes to Figure 2–32:

(1) If datae1and dataf1are used as inputs to the six-input function, datae0and dataf0are available for register

packing.

(2) The dataf1input is available for register packing only if the six-input function is un-registered.

Extended LUT Mode

Extended LUT mode is used to implement a specific set of seven-input functions. The

set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four

inputs. Figure 2–33 shows the template of supported seven-input functions utilizing

extended LUT mode. In this mode, if the seven-input function is unregistered, the

unused eighth input is available for register packing. Functions that fit into the

template shown in Figure 2–33 occur naturally in designs. These functions often

appear in designs as “if-else” statements in Verilog HDL or VHDL code.

Figure 2–33. Template for Supported Seven-Input Functions in Extended LUT Mode

datae0

datac

dataa

datab

datad

5-Input

LUT

To general or

local routing

dataf0

combout0

To general or

local routing

D

Q

5-Input

LUT

reg0

datae1

dataf1

(1)

This input is available

for register packing.

Note to Figure 2–33:

(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available.

Arria GX Device Handbook, Volume 1

2–38

Chapter 2: Arria GX Architecture

Adaptive Logic Modules

Arithmetic Mode

Arithmetic mode is ideal for implementing adders, counters, accumulators, wide

parity functions, and comparators. An ALM in arithmetic mode uses two sets of 2

four-input LUTs along with two dedicated full adders. The dedicated adders allow

the LUTs to be available to perform pre-adder logic; therefore, each adder can add the

output of two four-input functions. The four LUTs share the dataaand datab

inputs. As shown in Figure 2–34, the carry-in signal feeds to adder0, and the

carry-out from adder0feeds to carry-in of adder1. The carry-out from adder1

drives to adder0of the next ALM in the LAB. ALMs in arithmetic mode can drive

out registered and/or unregistered versions of the adder outputs.

Figure 2–34. ALM in Arithmetic Mode

carry_in

datae0

adder0

4-Input

LUT

To general or

local routing

To general or

local routing

D

Q

dataf0

datac

datab

dataa

reg0

4-Input

LUT

adder1

4-Input

LUT

To general or

local routing

datad

datae1

To general or

local routing

D

Q

4-Input

LUT

reg1

dataf1

carry_out

While operating in arithmetic mode, the ALM can support simultaneous use of the

adder’s carry output along with combinational logic outputs. In this operation, adder

output is ignored. This usage of the adder with the combinational logic output

provides resource savings of up to 50% for functions that can use this ability. An

example of such functionality is a conditional operation, such as the one shown in

Figure 2–35. The equation for this example is:

Equation 2–1.

R = (X < Y) ? Y : X

To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If ‘X’ is less than

‘Y,’ the carry_outsignal is ‘1.’ The carry_outsignal is fed to an adder where it

drives out to the LAB local interconnect. It then feeds to the LAB-wide syncload

signal. When asserted, syncloadselects the syncdatainput. In this case, the data

‘Y’ drives the syncdatainputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the

syncloadsignal is deasserted and ‘X’ drives the data port of the registers.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–39

Adaptive Logic Modules

Figure 2–35. Conditional Operation Example

Adder output

is not used.

ALM 1

X[0]

Y[0]

Comb &

Adder

Logic

X[0]

R[0]

R[1]

To general or

local routing

D

Q

reg0

syncdata

syncload

X[1]

Y[1]

Comb &

Adder

Logic

X[1]

To general or

local routing

Q

reg1

Carry Chain

ALM 2

X[2]

Y[2]

Comb &

Adder

Logic

X[2]

R[2]

To general or

local routing

D

Q

reg0

syncload

Comb &

Adder

Logic

To local routing &

then to LAB-wide

syncload

carry_out

Arithmetic mode also offers clock enable, counter enable, synchronous up/down

control, add/subtract control, synchronous clear, and synchronous load. The LAB

local interconnect data inputs generate the clock enable, counter enable, synchronous

up/down and add/subtract control signals. These control signals can be used for the

inputs that are shared between the four LUTs in the ALM. The synchronous clear and

synchronous load options are LAB-wide signals that affect all registers in the LAB.

The Quartus II software automatically places any registers that are not used by the

counter into other LABs.

Carry Chain

Carry chain provides a fast carry function between the dedicated adders in arithmetic

or shared arithmetic mode. Carry chains can begin in either the first ALM or the fifth

ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local,

row, or column interconnects.

The Quartus II Compiler automatically creates carry chain logic during compilation,

or you can create it manually during design entry. Parameterized functions such as

LPM functions automatically take advantage of carry chains for the appropriate

functions. The Quartus II Compiler creates carry chains longer than 16 (8 ALMs in

arithmetic or shared arithmetic mode) by linking LABs together automatically. For

enhanced fitting, a long carry chain runs vertically allowing fast horizontal

connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as

a full column. To avoid routing congestion in one small area of the device when a high

fan-in arithmetic function is implemented, the LAB can support carry chains that only

use either the top half or bottom half of the LAB before connecting to the next LAB.

Arria GX Device Handbook, Volume 1

2–40

Chapter 2: Arria GX Architecture

Adaptive Logic Modules

The other half of the ALMs in the LAB is available for implementing narrower fan-in

functions in normal mode. Carry chains that use the top four ALMs in the first LAB

carries into the top half of the ALMs in the next LAB within the column. Carry chains

that use the bottom four ALMs in the first LAB carries into the bottom half of the

ALMs in the next LAB within the column. Every other column of the LABs are

top-half bypassable, while the other LAB columns are bottom-half bypassable. For

more information about carry chain interconnect, refer to “MultiTrack Interconnect”

on page 2–44.

Shared Arithmetic Mode

In shared arithmetic mode, the ALM can implement a three-input add. In this mode,

the ALM is configured with four 4-input LUTs. Each LUT either computes the sum of

three inputs or the carry of three inputs. The output of the carry computation is fed to

the next adder (either to adder1in the same ALM or to adder0of the next ALM in

the LAB) using a dedicated connection called the shared arithmetic chain. This shared

arithmetic chain can significantly improve the performance of an adder tree by

reducing the number of summation stages required to implement an adder tree.

Figure 2–36 shows the ALM in shared arithmetic mode.

Figure 2–36. ALM in Shared Arithmetic Mode

shared_arith_in

carry_in

4-Input

LUT

To general or

local routing

To general or

local routing

D

Q

datae0

datac

datab

dataa

reg0

4-Input

LUT

4-Input

LUT

To general or

local routing

datad

datae1

To general or

local routing

D

Q

4-Input

LUT

reg1

carry_out

shared_arith_out

Note to Figure 2–36:

(1) Inputs dataf0and dataf1are available for register packing in shared arithmetic mode.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–41

Adaptive Logic Modules

Adder trees are used in many different applications. For example, the summation of

partial products in a logic-based multiplier can be implemented in a tree structure.

Another example is a correlator function that can use a large adder tree to sum filtered

data samples in a given time frame to recover or to de-spread data which was

transmitted utilizing spread spectrum technology. An example of a three-bit add

operation utilizing the shared arithmetic mode is shown in Figure 2–37. The partial

sum (S[2..0]) and the partial carry (C[2..0]) is obtained using LUTs, while the

result (R[2..0]) is computed using dedicated adders.

Figure 2–37. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode

shared_arith_in = '0'

carry_in = '0'

3-Bit Add Example

ALM Implementation

ALM 1

X2 X1 X0

Y2 Y1 Y0

Z2 Z1 Z0

3-Input S0

1st stage add is

implemented in LUTs.

LUT

+

R0

2nd stage add is

implemented in adders.

S2 S1 S0

C2 C1 C0

X0

Y0

Z0

3-Input

LUT

+

C0

S1

R3 R2 R1 R0

X1

Y1

Z1

3-Input

LUT

Decimal

Equivalents

Binary Add

R1

1

0

1

0

1

0

1

0

6

5

C1

3-Input

LUT

2

+

0

1

0

1

+

1

2 x 6

13

ALM 2

1

0

1

S2

C2

'0'

3-Input

LUT

R2

X2

Y2

Z2

3-Input

LUT

3-Input

LUT

R3

3-Input

LUT

Shared Arithmetic Chain

In addition to dedicated carry chain routing, the shared arithmetic chain available in

shared arithmetic mode allows the ALM to implement a three-input add, which

significantly reduces the resources necessary to implement large adder trees or

correlator functions. Shared arithmetic chains can begin in either the first or fifth ALM

in a LAB. The Quartus II Compiler automatically links LABs to create shared

arithmetic chains longer than 16 (eight ALMs in arithmetic or shared arithmetic

mode). For enhanced fitting, a long shared arithmetic chain runs vertically allowing

fast horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic

chain can continue as far as a full column. Similar to carry chains, shared arithmetic

Arria GX Device Handbook, Volume 1

2–42

Chapter 2: Arria GX Architecture

Adaptive Logic Modules

chains are also top- or bottom-half bypassable. This capability allows the shared

arithmetic chain to cascade through half of the ALMs in a LAB while leaving the other

half available for narrower fan-in functionality. Every other LAB column is top-half

bypassable, while the other LAB columns are bottom-half bypassable. For more

information about shared arithmetic chain interconnect, refer to “MultiTrack

Interconnect” on page 2–44.

Register Chain

In addition to the general routing outputs, the ALMs in a LAB have register chain

outputs. Register chain routing allows registers in the same LAB to be cascaded

together. The register chain interconnect allows a LAB to use LUTs for a single

combinational function and the registers to be used for an unrelated shift register

implementation. These resources speed up connections between ALMs while saving

local interconnect resources (refer to Figure 2–38). The Quartus II Compiler

automatically takes advantage of these resources to improve utilization and

performance. For more information about register chain interconnect, refer to

“MultiTrack Interconnect” on page 2–44.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–43

Adaptive Logic Modules

Figure 2–38. Register Chain within a LAB (Note 1)

From Previous ALM

Within The LAB

reg_chain_in

To general or

local routing

To general or

local routing

adder0

D

Q

reg0

Combinational

Logic

To general or

local routing

adder1

D

Q

reg1

To general or

local routing

To general or

local routing

To general or

local routing

adder0

D

Q

reg0

Combinational

Logic

To general or

local routing

adder1

D

Q

reg1

To general or

local routing

reg_chain_out

To Next ALM

within the LAB

Note to Figure 2–38:

(1) The combinational or adder logic can be used to implement an unrelated, unregistered function.

Clear and Preset Logic Control

LAB-wide signals control the logic for the register’s clear and load/preset signals. The

ALM directly supports an asynchronous clear and preset function. The register preset

is achieved through the asynchronous load of a logic high. The direct asynchronous

preset does not require a NOTgate push-back technique. Arria GX devices support

simultaneous asynchronous load/preset and clear signals. An asynchronous clear

signal takes precedence if both signals are asserted simultaneously. Each LAB

supports up to two clears and one load/preset signal.

Arria GX Device Handbook, Volume 1

2–44

Chapter 2: Arria GX Architecture

MultiTrack Interconnect

In addition to the clear and load/preset ports, Arria GX devices provide a

device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set

before compilation in the Quartus II software controls this pin. This device-wide reset

overrides all other control signals.

MultiTrack Interconnect

In Arria GX architecture, the MultiTrack interconnect structure with DirectDrive

technology provides connections between ALMs, TriMatrix memory, DSP blocks, and

device I/O pins. The MultiTrack interconnect consists of continuous,

performance-optimized routing lines of different lengths and speeds used for inter-

and intra-design block connectivity. The Quartus II Compiler automatically places

critical design paths on faster interconnects to improve design performance.

DirectDrive technology is a deterministic routing technology that ensures identical

routing resource usage for any function regardless of placement in the device. The

MultiTrack interconnect and DirectDrive technology simplify the integration stage of

block-based designing by eliminating the re-optimization cycles that typically follow

design changes and additions.

The MultiTrack interconnect consists of row and column interconnects that span fixed

distances. A routing structure with fixed length resources for all devices allows

predictable and repeatable performance when migrating through different device

densities. Dedicated row interconnects route signals to and from LABs, DSP blocks,

and TriMatrix memory in the same row.

These row resources include:

■

Direct link interconnects between LABs and adjacent blocks

R4 interconnects traversing four blocks to the right or left

R24 row interconnects for high-speed access across the length of the device

The direct link interconnect allows a LAB, DSP block, or TriMatrix memory block to

drive into the local interconnect of its left and right neighbors and then back into

itself, providing fast communication between adjacent LABs and/or blocks without

using row interconnect resources.

The R4 interconnects span four LABs, three LABs and one M512 RAM block, two

LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of

a source LAB. These resources are used for fast row connections in a four-LAB region.

Every LAB has its own set of R4 interconnects to drive either left or right. Figure 2–39

shows R4 interconnect connections from a LAB.

R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row

IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4

interconnect. For R4 interconnects that drive to the right, the primary LAB and right

neighbor can drive onto the interconnect. For R4 interconnects that drive to the left,

the primary LAB and its left neighbor can drive onto the interconnect. R4

interconnects can drive other R4 interconnects to extend the range of LABs they can

drive. R4 interconnects can also drive C4 and C16 interconnects for connections from

one row to another. Additionally, R4 interconnects can drive R24 interconnects.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–45

MultiTrack Interconnect

Figure 2–39. R4 Interconnect Connections (Note 1), (2), (3)

Adjacent LAB can

Drive onto Another

LAB's R4 Interconnect

C4 and C16

Column Interconnects (1)

R4 Interconnect

Driving Right

R4 Interconnect

Driving Left

LAB

Neighbor

Primary

LAB (2)

LAB

Neighbor

Notes to Figure 2–39:

(1) C4 and C16 interconnects can drive R4 interconnects.

(2) This pattern is repeated for every LAB in the LAB row.

(3) The LABs in Figure 2–39 show the 16 possible logical outputs per LAB.

R24 row interconnects span 24 LABs and provide the fastest resource for long row

connections between LABs, TriMatrix memory, DSP blocks, and row IOEs. The R24

row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row

or column interconnects at every fourth LAB and do not drive directly to LAB local

interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4

interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The

column interconnect operates similarly to the row interconnect and vertically routes

signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of

LABs is served by a dedicated column interconnect.

These column resources include:

■

Shared arithmetic chain interconnects in a LAB

Carry chain interconnects in a LAB and from LAB to LAB

Register chain interconnects in a LAB

C4 interconnects traversing a distance of four blocks in up and down direction

C16 column interconnects for high-speed vertical routing through the device

Arria GX devices include an enhanced interconnect structure in LABs for routing

shared arithmetic chains and carry chains for efficient arithmetic functions. The

register chain connection allows the register output of one ALM to connect directly to

the register input of the next ALM in the LAB for fast shift registers. These

ALM-to-ALM connections bypass the local interconnect. The Quartus II Compiler

automatically takes advantage of these resources to improve utilization and

performance. Figure 2–40 shows shared arithmetic chain, carry chain, and register

chain interconnects.

Arria GX Device Handbook, Volume 1

2–46

Chapter 2: Arria GX Architecture

MultiTrack Interconnect

Figure 2–40. Shared Arithmetic Chain, Carry Chain and Register Chain Interconnects

Local Interconnect

Routing Among ALMs

in the LAB

ALM 1

Carry Chain & Shared

Arithmetic Chain

Routing to Adjacent ALM

Register Chain

Routing to Adjacent

ALM's Register Input

ALM 2

ALM 3

ALM 4

ALM 5

ALM 6

ALM 7

Local

Interconnect

ALM 8

C4 interconnects span four LABs, M512, or M4K blocks up or down from a source

LAB. Every LAB has its own set of C4 interconnects to drive either up or down.

Figure 2–41 shows the C4 interconnect connections from a LAB in a column. C4

interconnects can drive and be driven by all types of architecture blocks, including

DSP blocks, TriMatrix memory blocks, and column and row IOEs. For LAB

interconnection, a primary LAB or its LAB neighbor can drive a given C4

interconnect. C4 interconnects can drive each other to extend their range as well as

drive row interconnects for column-to-column connections.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–47

MultiTrack Interconnect

Figure 2–41. C4 Interconnect Connections (Note 1)

C4 Interconnect

Drives Local and R4

Interconnects

up to Four Rows

C4 Interconnect

Driving Up

LAB

Row

Interconnect

Adjacent LAB can

drive onto neighboring

LAB's C4 interconnect

Local

Interconnect

C4 Interconnect

Driving Down

Note to Figure 2–41:

(1) Each C4 interconnect can drive either up or down four rows.

C16 column interconnects span a length of 16 LABs and provide the fastest resource

for long column connections between LABs, TriMatrix memory blocks, DSP blocks,

and IOEs. C16 interconnects can cross M-RAM blocks and also drive to row and

column interconnects at every fourth LAB. C16 interconnects drive LAB local

interconnects via C4 and R4 interconnects and do not drive LAB local interconnects

directly. All embedded blocks communicate with the logic array similar to

LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks)

connects to row and column interconnects and has local interconnect regions driven

by row and column interconnects. These blocks also have direct link interconnects for

fast connections to and from a neighboring LAB. All blocks are fed by the row LAB

clocks, labclk[5..0].

Arria GX Device Handbook, Volume 1

2–48

Chapter 2: Arria GX Architecture

TriMatrix Memory

Table 2–10 lists the routing scheme for Arria GX device.

Table 2–10. Arria GX Device Routing Scheme

Destination

Source

Shared arithmetic chain

Carry chain

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

Register chain

Local interconnect

Direct link interconnect

R4 interconnect

R24 interconnect

C4 interconnect

C16 interconnect

ALM

M512 RAM block

M4K RAM block

M-RAM block

DSP blocks

Column IOE

Row IOE

TriMatrix Memory

TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM.

Although these memory blocks are different, they can all implement various types of

memory with or without parity, including true dual-port, simple dual-port, and

single-port RAM, ROM, and FIFO buffers. Table 2–11 lists the size and features of the

different RAM blocks.

Table 2–11. TriMatrix Memory Features (Part 1 of 2)

M512 RAM Block

(32 × 18 Bits)

M4K RAM Block

(128 × 36 Bits)

M-RAM Block

(4K × 144 Bits)

Memory Feature

Maximum performance

True dual-port memory

Simple dual-port memory

Single-port memory

Shift register

345 MHz

—

380 MHz

v

290 MHz

v

—

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–49

TriMatrix Memory

Table 2–11. TriMatrix Memory Features (Part 2 of 2)

M512 RAM Block

(32 × 18 Bits)

M4K RAM Block

(128 × 36 Bits)

M-RAM Block

(4K × 144 Bits)

Memory Feature

ROM

v

—

FIFO buffer

v

Pack mode

—

v

Byte enable

v

Address clock enable

Parity bits

—

v

Mixed clock mode

v

Memory initialization file (.mif)

Simple dual-port memory mixed width support

True dual-port memory mixed width support

Power-up conditions

Register clears

v

—

v

—

v

Outputs cleared

Output registers

Outputs cleared

Output registers

Outputs unknown

Output registers

Unknown output

Mixed-port read-during-write

Unknown output/old

data

Unknown output/old

data

64K × 8

64K × 9

4K × 1

2K × 2

512 × 1

256 × 2

128 × 4

64 × 8

32K × 16

32K × 18

16K × 32

16K × 36

8K × 64

1K × 4

512 × 8

512 × 9

256 × 16

256 × 18

128 × 32

128 × 36

Configurations

64 × 9

32 × 16

32 × 18

8K × 72

4K × 128

4K × 144

TriMatrix memory provides three different memory sizes for efficient application

support. The Quartus II software automatically partitions the user-defined memory

into the embedded memory blocks using the most efficient size combinations. You can

also manually assign the memory to a specific block size or a mixture of block sizes.

M512 RAM Block

The M512 RAM block is a simple dual-port memory block and is useful for

implementing small FIFO buffers, DSP, and clock domain transfer applications. Each

block contains 576 RAM bits (including parity bits). M512 RAM blocks can be

configured in the following modes:

■

Simple dual-port RAM

Single-port RAM

FIFO

■

ROM

Shift register

Arria GX Device Handbook, Volume 1

2–50

Chapter 2: Arria GX Architecture

TriMatrix Memory

When configured as RAM or ROM, you can use an initialization file to pre-load the

memory contents.

M512 RAM blocks can have different clocks on its inputs and outputs. The wren,

datain, and write address registers are all clocked together from one of the two

clocks feeding the block. The read address, rden, and output registers can be clocked

by either of the two clocks driving the block, allowing the RAM block to operate in

read and write or input and output clock modes. Only the output register can be

bypassed. The six labclksignals or local interconnect can drive the inclock,

outclock, wren, rden, and outclrsignals. Because of the advanced interconnect

between the LAB and M512 RAM blocks, ALMs can also control the wrenand rden

signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 2–42

shows the M512 RAM block control signal generation logic.

Figure 2–42. M512 RAM Block Control Signals

Dedicated

6

Row LAB

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

outclocken

inclocken

wren

Local

Interconnect

outclr

inclock

outclock

rden

The RAM blocks in Arria GX devices have local interconnects to allow ALMs and

interconnects to drive into RAM blocks. The M512 RAM block local interconnect is

driven by the R4, C4, and direct link interconnects from adjacent LABs. The M512

RAM blocks can communicate with LABs on either the left or right side through these

row interconnects or with LAB columns on the left or right side with the column

interconnects. The M512 RAM block has up to 16 direct link input connections from

the left adjacent LABs and another 16 from the right adjacent LAB. M512 RAM

outputs can also connect to left and right LABs through direct link interconnect. The

M512 RAM block has equal opportunity for access and performance to and from

LABs on either its left or right side. Figure 2–43 shows the M512 RAM block to logic

array interface.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–51

TriMatrix Memory

Figure 2–43. M512 RAM Block LAB Row Interface

C4 Interconnect

R4 Interconnect

16

Direct link

interconnect

to adjacent LAB

interconnect

to adjacent LAB

36

dataout

M4K RAM

Block

Direct link

interconnect

from adjacent LAB

datain

byte

enable

control

signals

clocks

address

6

M4K RAM Block Local

LAB Row Clocks

Interconnect Region

M4K RAM Blocks

The M4K RAM block includes support for true dual-port RAM. The M4K RAM block

is used to implement buffers for a wide variety of applications such as storing

processor code, implementing lookup schemes, and implementing larger memory

applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM

blocks can be configured in the following modes:

■

True dual-port RAM

Simple dual-port RAM

Single-port RAM

FIFO

ROM

Shift register

When configured as RAM or ROM, you can use an initialization file to pre-load the

memory contents.

M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the

two clocks feeding the block can clock M4K RAM block registers (renwe, address,

byte enable, datain, and outputregisters). Only the outputregister can be

bypassed. The six labclksignals or local interconnects can drive the control signals

for the A and B ports of the M4K RAM block. ALMs can also control the clock_a,

clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b

signals, as shown in Figure 2–44.

Arria GX Device Handbook, Volume 1

2–52

Chapter 2: Arria GX Architecture

TriMatrix Memory

Figure 2–44. M4K RAM Block Control Signals

Dedicated

6

Row LAB

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

clocken_b

clock_b

renwe_b

aclr_b

Local

Interconnect

renwe_a

aclr_a

clock_a

clocken_a

The R4, C4, and direct link interconnects from adjacent LABs drive the M4K RAM

block local interconnect. The M4K RAM blocks can communicate with LABs on either

the left or right side through these row resources or with LAB columns on either the

right or left with the column resources. Up to 16 direct link input connections to the

M4K RAM block are possible from the left adjacent LABs and another 16 are possible

from the right adjacent LAB. M4K RAM block outputs can also connect to left and

right LABs through direct link interconnect. Figure 2–45 shows the M4K RAM block

to logic array interface.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–53

TriMatrix Memory

Figure 2–45. M4K RAM Block LAB Row Interface

C4 Interconnect

R4 Interconnect

16

Direct link

interconnect

to adjacent LAB

interconnect

to adjacent LAB

36

dataout

M4K RAM

Block

Direct link

interconnect

from adjacent LAB

datain

byte

enable

control

signals

clocks

address

6

M4K RAM Block Local

LAB Row Clocks

Interconnect Region

M-RAM Block

The largest TriMatrix memory block, the M-RAM block, is useful for applications

where a large volume of data must be stored on-chip. Each block contains 589,824

RAM bits (including parity bits). The M-RAM block can be configured in the

following modes:

■

True dual-port RAM

Simple dual-port RAM

Single-port RAM

FIFO

You cannot use an initialization file to initialize the contents of a M-RAM block. All

M-RAM block contents power up to an undefined value. Only synchronous operation

is supported in the M-RAM block, so all inputs are registered. Output registers can be

bypassed.

Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs

and outputs. Either of the two clocks feeding the block can clock M-RAM block

registers (renwe, address, byte enable, datain, and output registers). You can

bypass the output register. The six labclksignals or local interconnect can drive the

control signals for the A and B ports of the M-RAM block. ALMs can also control the

clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and

clocken_bsignals, as shown in Figure 2–46.

Arria GX Device Handbook, Volume 1

2–54

Chapter 2: Arria GX Architecture

TriMatrix Memory

Figure 2–46. M-RAM Block Control Signals

Dedicated

Row LAB

6

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

clocken_a

renwe_a

clock_b

aclr_b

Local

Interconnect

clocken_b

clock_a

aclr_a

renwe_b

The R4, R24, C4, and direct link interconnects from adjacent LABs on either the right

or left side drive the M-RAM block local interconnect. Up to 16 direct link input

connections to the M-RAM block are possible from the left adjacent LABs and another

16 are possible from the right adjacent LAB. M-RAM block outputs can also connect to

left and right LABs through direct link interconnect. Figure 2–47 shows an example

floorplan for the EP1AGX90 device and the location of the M-RAM interfaces.

Figure 2–48 and Figure 2–49 show the interface between the M-RAM block and the

logic array.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–55

TriMatrix Memory

Figure 2–47. EP1AGX90 Device with M-RAM Interface Locations (Note 1)

M-RAM blocks interface to

LABs on right and left sides for

easy access to horizontal I/O pins

M-RAM

Block

M-RAM

Block

M-RAM

Block

M-RAM

Block

M4K

Blocks

M512

Blocks

DSP

Blocks

LABs

DSP

Blocks

Note to Figure 2–47:

(1) The device shown is an EP1AGX90 device. The number and position of M-RAM blocks vary in other devices.

Arria GX Device Handbook, Volume 1

2–56

Chapter 2: Arria GX Architecture

TriMatrix Memory

Figure 2–48. M-RAM Block LAB Row Interface (Note 1)

Row Unit Interface Allows LAB

Rows to Drive Port A Datain,

Dataout, Address and Control

Signals to and from M-RAM Block

Row Unit Interface Allows LAB

Rows to Drive Port B Datain,

Dataout, Address and Control

Signals to and from M-RAM Block

L0

L1

R0

R1

M-RAM Block

L2

L3

L4

L5

R2

R3

R4

R5

Port A

Port B

LAB Interface

Blocks

LABs in Row

M-RAM Boundary

LABs in Row

M-RAM Boundary

Note to Figure 2–48:

(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–57

TriMatrix Memory

Figure 2–49. M-RAM Row Unit Interface to Interconnect

C4 Interconnect

R4 and R24 Interconnects

M-RAM Block

LAB

Up to 16

dataout_a[ ]

16

datain_a[ ]

addressa[ ]

addr_ena_a

renwe_a

Up to 28

Direct Link

Interconnects

byteena [ ]

A

clocken_a

clock_a

aclr_a

Row Interface Block

M-RAM Block to

LAB Row Interface

Block Interconnect Region

Table 2–12 lists the input and output data signal connections along with the address

and control signal input connections to the row unit interfaces (L0 to L5 and R0 to R5).

Table 2–12. M-RAM Row Interface Unit Signals (Part 1 of 2)

Unit Interface Block

Input Signals

datain_a[14..0]

byteena_a[1..0]

datain_a[29..15]

byteena_a[3..2]

datain_a[35..30]

addressa[4..0]

addr_ena_a

Output Signals

dataout_a[11..0]

L0

dataout_a[23..12]

dataout_a[35..24]

L1

L2

L3

clock_a

clocken_a

renwe_a

aclr_a

addressa[15..5]

datain_a[41..36]

dataout_a[47..36]

Arria GX Device Handbook, Volume 1

2–58

Chapter 2: Arria GX Architecture

Digital Signal Processing Block

Table 2–12. M-RAM Row Interface Unit Signals (Part 2 of 2)

Unit Interface Block

Input Signals

datain_a[56..42]

byteena_a[5..4]

datain_a[71..57]

byteena_a[7..6]

datain_b[14..0]

byteena_b[1..0]

datain_b[29..15]

byteena_b[3..2]

datain_b[35..30]

addressb[4..0]

addr_ena_b

Output Signals

dataout_a[59..48]

L4

dataout_a[71..60]

dataout_b[11..0]

dataout_b[23..12]

dataout_b[35..24]

L5

R0

R1

R2

clock_b

clocken_b

renwe_b

aclr_b

addressb[15..5]

datain_b[41..36]

datain_b[56..42]

byteena_b[5..4]

datain_b[71..57]

byteena_b[7..6]

dataout_b[47..36]

dataout_b[59..48]

dataout_b[71..60]

R3

R4

R5

f

For more information about TriMatrix memory, refer to the TriMatrix Embedded

Memory Blocks in Arria GX Devices chapter.

Digital Signal Processing Block

The most commonly used DSP functions are finite impulse response (FIR) filters,

complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT)

functions, direct cosine transform (DCT) functions, and correlators. All of these use

the multiplier as the fundamental building block. Additionally, some applications

need specialized operations such as multiply-add and multiply-accumulate

operations. Arria GX devices provide DSP blocks to meet the arithmetic requirements

of these functions.

Each Arria GX device has two to four columns of DSP blocks to efficiently implement

DSP functions faster than ALM-based implementations. Each DSP block can be

configured to support up to:

■

Eight 9 × 9-bit multipliers

Four 18 × 18-bit multipliers

One 36 × 36-bit multiplier

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–59

Digital Signal Processing Block

As indicated, the Arria GX DSP block can support one 36 × 36-bit multiplier in a

single DSP block and is true for any combination of signed, unsigned, or mixed sign

multiplications.

Figure 2–50 shows one of the columns with surrounding LAB rows.

Figure 2–50. DSP Blocks Arranged in Columns

DSP Block

Column

DSP Block

4 LAB

Rows

Table 2–13 lists the number of DSP blocks in each Arria GX device. DSP block

multipliers can optionally feed an adder/subtractor or accumulator in the block

depending on the configuration, which makes routing to ALMs easier, saves ALM

routing resources, and increases performance because all connections and blocks are

in the DSP block.

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Chapter 2: Arria GX Architecture

Digital Signal Processing Block

Table 2–13. DSP Blocks in Arria GX Devices (Note 1)

Total 9 × 9

Multipliers

Total 18 × 18

Multipliers

Total 36 × 36

Multipliers

Device

DSP Blocks

EP1AGX20

10

14

26

32

44

80

40

56

10

14

26

32

44

EP1AGX35

112

EP1AGX50

208

104

128

176

EP1AGX60

256

EP1AGX90

352

Note to Table 2–13:

(1) This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger

multiplication functions.

Additionally, DSP block input registers can efficiently implement shift registers for

FIR filter applications. DSP blocks support Q1.15 format rounding and saturation.

Figure 2–51 shows a top-level diagram of the DSP block configured for 18 × 18-bit

multiplier mode.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–61

Digital Signal Processing Block

Figure 2–51. DSP Block Diagram for 18 × 18-Bit Configuration

Optional Serial Shift Register

Inputs from Previous

DSP Block

Multiplier Stage

Optional Stage Configurable

as Accumulator or Dynamic

Adder/Subtractor

Output Selection

Multiplexer

D

Q

ENA

CLRN

D

Q

ENA

CLRN

D

Q

ENA

CLRN

Addddeerr//

Suubbttrraaccttoorr//

Accccuummuullaattoorr

1

D

Q

ENA

CLRN

D

Q

ENA

CLRN

D

Q

ENA

CLRN

Summation

D

Q

ENA

CLRN

D

Q

Optional Output

Register Stage

Summation Stage

for Adding Four

Multipliers Together

ENA

CLRN

D

Q

ENA

CLRN

Adder/

Subtractor/

Accumulator

2

D

Q

ENA

CLRN

Optional Serial

Shift Register

Outputs to

Next DSP Block

in the Column

D

Q

Optional Pipeline

Register Stage

ENA

CLRN

D

Q

ENA

CLRN

Optional Input Register

Stage with Parallel Input or

Shift Register Configuration

to MultiTrack

Interconnect

Arria GX Device Handbook, Volume 1

2–62

Chapter 2: Arria GX Architecture

Digital Signal Processing Block

Modes of Operation

The adder, subtractor, and accumulate functions of a DSP block have four modes of

operation:

■

Simple multiplier

Multiply-accumulator

Two-multipliers adder

Four-multipliers adder

Table 2–14 shows the different number of multipliers possible in each DSP block

mode according to size. These modes allow the DSP blocks to implement numerous

applications for DSP including FFTs, complex FIR, FIR, 2D FIR filters, equalizers, IIR,

correlators, matrix multiplication, and many other functions. DSP blocks also support

mixed modes and mixed multiplier sizes in the same block. For example, half of one

DSP block can implement one 18 × 18-bit multiplier in multiply-accumulator mode,

while the other half of the DSP block implements four 9 × 9-bit multipliers in simple

multiplier mode.

Table 2–14. Multiplier Size and Configurations per DSP Block

DSP Block Mode

Multiplier

9 × 9

18 × 18

36 × 36

Eight multipliers with eight

product outputs

Four multipliers with four

product outputs

One multiplier with one

product output

Multiply-accumulator

Two-multipliers adder

Four-multipliers adder

Two 52-bit

multiply-accumulate blocks

—

Four two-multiplier adder (two Two two-multiplier adder (one

—

9 × 9 complex multiply)

18 × 18 complex multiply)

Two four-multiplier adder

One four-multiplier adder

DSP Block Interface

The Arria GX device DSP block input registers can generate a shift register that can

cascade down in the same DSP block column. Dedicated connections between DSP

blocks provide fast connections between shift register inputs to cascade shift register

chains. You can cascade registers within multiple DSP blocks for 9 × 9- or 18 × 18-bit

FIR filters larger than four taps, with additional adder stages implemented in ALMs.

If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or accumulator

stages are implemented in ALMs. Each DSP block can route the shift register chain

out of the block to cascade multiple columns of DSP blocks.

The DSP block is divided into four block units that interface with four LAB rows on

the left and right. Each block unit can be considered one complete 18 × 18-bit

multiplier with 36 inputs and 36 outputs. A local interconnect region is associated

with each DSP block. Like an LAB, this interconnect region can be fed with 16 direct

link interconnects from the LAB to the left or right of the DSP block in the same row.

R4 and C4 routing resources can access the DSP block’s local interconnect region.

The outputs also work similarly to LAB outputs. Eighteen outputs from the DSP block

can drive to the left LAB through direct link interconnects and 18 can drive to the

right LAB though direct link interconnects. All 36 outputs can drive to R4 and C4

routing interconnects. Outputs can drive right- or left-column routing.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–63

Digital Signal Processing Block

Figure 2–52 and Figure 2–53 show the DSP block interfaces to LAB rows.

Figure 2–52. DSP Block Interconnect Interface

DSP Block

OA[17..0]

OB[17..0]

R4, C4 & Direct

Link Interconnects

A1[17..0]

B1[17..0]

OC[17..0]

OD[17..0]

A2[17..0]

B2[17..0]

OE[17..0]

OF[17..0]

A3[17..0]

B3[17..0]

OG[17..0]

OH[17..0]

A4[17..0]

B4[17..0]

Arria GX Device Handbook, Volume 1

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Chapter 2: Arria GX Architecture

Digital Signal Processing Block

Figure 2–53. DSP Block Interface to Interconnect

Direct Link Interconnect

from Adjacent LAB

Direct Link Outputs

to Adjacent LABs

Direct Link Interconnect

from Adjacent LAB

C4 Interconnect

R4 Interconnect

36

DSP Block

Row Structure

LAB

36

16

LAB

18

16

12

36

Control

36

A[17..0]

B[17..0]

OA[17..0]

OB[17..0]

Row Interface

Block

DSP Block to

36 Inputs per Row

36 Outputs per Row

LAB Row Interface

Block Interconnect Region

A bus of 44 control signals feeds the entire DSP block. These signals include clocks,

asynchronous clears, clock enables, signed and unsigned control signals, addition and

subtraction control signals, rounding and saturation control signals, and accumulator

synchronous loads. The clock signals are routed from LAB row clocks and are

generated from specific LAB rows at the DSP block interface. The LAB row source for

control signals, data inputs, and outputs is shown in Table 2–15.

f

For more information about DSP blocks, refer to the DSP Blocks in Arria GX Devices

chapter.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–65

Digital Signal Processing Block

Table 2–15. DSP Block Signal Sources and Destinations

LAB Row at Interface

Control Signals Generated

clock0

Data Inputs

Data Outputs

aclr0

ena0

mult01_saturate

A1[17..0]

B1[17..0]

OA[17..0]

OB[17..0]

addnsub1_round/

accum_round

0

addnsub1

signa

sourcea

sourceb

clock1

aclr1

ena1

accum_saturate

mult01_round

accum_sload

sourcea

sourceb

mode0

A2[17..0]

B2[17..0]

OC[17..0]

OD[17..0]

1

clock2

aclr2

ena2

mult23_saturate

A3[17..0]

B3[17..0]

OE[17..0]

OF[17..0]

addnsub3_round/

accum_round

2

addnsub3

sign_b

sourcea

sourceb

clock3

aclr3

ena3

accum_saturate

mult23_round

accum_sload

sourcea

sourceb

mode1

A4[17..0]

B4[17..0]

OG[17..0]

OH[17..0]

3

Arria GX Device Handbook, Volume 1

2–66

Chapter 2: Arria GX Architecture

PLLs and Clock Networks

Arria GX devices provide a hierarchical clock structure and multiple PLLs with

advanced features. The large number of clocking resources in combination with the

clock synthesis precision provided by enhanced and fast PLLs provides a complete

clock management solution.

Global and Hierarchical Clocking

Arria GX devices provide 16 dedicated global clock networks and 32 regional clock

networks (eight per device quadrant). These clocks are organized into a hierarchical

clock structure that allows for up to 24 clocks per device region with low skew and

delay. This hierarchical clocking scheme provides up to 48 unique clock domains in

Arria GX devices.

There are 12 dedicated clock pins (CLK[15..12]and CLK[7..0]) to drive either the

global or regional clock networks. Four clock pins drive each side of the device except

the right side, as shown in Figure 2–54 and Figure 2–55. Internal logic and enhanced

and fast PLL outputs can also drive the global and regional clock networks. Each

global and regional clock has a clock control block, which controls the selection of the

clock source and dynamically enables or disables the clock to reduce power

consumption. Table 2–16 lists the global and regional clock features.

Table 2–16. Global and Regional Clock Features

Feature

Global Clocks

Regional Clocks

Number per device

16

32

Number available per

quadrant

16

8

Sources

Clock pins, PLL outputs, core routings,

inter-transceiver clocks

Clock pins, PLL outputs, core routings,

inter-transceiver clocks

Dynamic clock source

selection

v

—

Dynamic enable/disable

v

Global Clock Network

These clocks drive throughout the entire device, feeding all device quadrants. GCLK

networks can be used as clock sources for all resources in the device IOEs, ALMs, DSP

blocks, and all memory blocks. These resources can also be used for control signals,

such as clock enables and synchronous or asynchronous clears fed from the external

pin. The global clock networks can also be driven by internal logic for internally

generated global clocks and asynchronous clears, clock enables, or other control

signals with large fanout. Figure 2–54 shows the 12 dedicated CLKpins driving global

clock networks.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–67

PLLs and Clock Networks

Figure 2–54. Global Clocking

CLK[15..12]

Global Clock [15..0]

CLK[3..0]

Global Clock [15..0]

CLK[7..4]

Regional Clock Network

There are eight RCLK networks (RCLK[7..0]) in each quadrant of the Arria GX

device that are driven by the dedicated CLK[15..12]and CLK[7..0]input pins, by

PLL outputs, or by internal logic. The regional clock networks provide the lowest

clock delay and skew for logic contained in a single quadrant. The CLKpins

symmetrically drive the RCLKnetworks in a particular quadrant, as shown in

Figure 2–55.

Arria GX Device Handbook, Volume 1

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Chapter 2: Arria GX Architecture

PLLs and Clock Networks

Figure 2–55. Regional Clocks

CLK[15..12]

11 5

7

RCLK

[31..28]

[27..24]

Arria GX

Transceiver

Block

RCLK

[3..0]

RCLK

[23..20]

1

2

CLK[3..0]

RCLK

[7..4]

RCLK

[19..16]

Arria GX

Transceiver

Block

RCLK

[11..8]

RCLK

[15..12]

8

12 6

CLK[7..4]

Dual-Regional Clock Network

A single source (CLKpin or PLL output) can generate a dual-RCLK by driving two

RCLK network lines in adjacent quadrants (one from each quadrant), which allows

logic that spans multiple quadrants to use the same low skew clock. The routing of

this clock signal on an entire side has approximately the same speed but slightly

higher clock skew when compared with a clock signal that drives a single quadrant.

Internal logic-array routing can also drive a dual-regional clock. Clock pins and

enhanced PLL outputs on the top and bottom can drive horizontal dual-regional

clocks. Clock pins and fast PLL outputs on the left and right can drive vertical

dual-regional clocks, as shown in Figure 2–56. Corner PLLs cannot drive

dual-regional clocks.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–69

PLLs and Clock Networks

Figure 2–56. Dual-Regional Clocks

Clock Pins or PLL Clock Outputs

Can Drive Dual-Regional Network

Clock Pins or PLL Clock

Outputs Can Drive

CLK[15..12]

Dual-Regional Network

CLK[3..0]

PLLs

CLK[7..4]

Combined Resources

Within each quadrant, there are 24 distinct dedicated clocking resources consisting of

16 global clock lines and eight regional clock lines. Multiplexers are used with these

clocks to form buses to drive LAB row clocks, column IOE clocks, or row IOE clocks.

Another multiplexer is used at the LAB level to select three of the six row clocks to

feed the ALM registers in the LAB (refer to Figure 2–57).

Figure 2–57. Hierarchical Clock Networks Per Quadrant

Clocks Available

to a Quadrant

Column I/O Cell

or Half-Quadrant

IO_CLK[7..0]

Global Clock Network [15..0]

Regional Clock Network [7..0]

Clock [23..0]

Lab Row Clock [5..0]

Row I/O Cell

IO_CLK[7..0]

You can use the Quartus II software to control whether a clock input pin drives either

a GCLK, RCLK, or dual-RCLK network. The Quartus II software automatically selects

the clocking resources if not specified.

Arria GX Device Handbook, Volume 1

2–70

Chapter 2: Arria GX Architecture

PLLs and Clock Networks

Clock Control Block

Each GCLK, RCLK, and PLL external clock output has its own clock control block.

The control block has two functions:

■

Clock source selection (dynamic selection for global clocks)

Clock power-down (dynamic clock enable or disable)

■

Figure 2–58 through Figure 2–60 show the clock control block for the global clock,

regional clock, and PLL external clock output, respectively.

Figure 2–58. Global Clock Control Blocks

CLKp

Pins

PLL Counter

2

Outputs

CLKn

Internal

Logic

CLKSELECT[1..0]

2

(1)

Static Clock Select (2)

This multiplexer supports

User-Controllable

Dynamic Switching

Enable/

Disable

Internal

Logic

GCLK

Notes to Figure 2–58:

(1) These clock select signals can be dynamically controlled through internal logic when the device is operating in user mode.

(2) These clock select signals can only be set through a configuration file (SRAM Object File [.sof] or Programmer Object File [.pof]) and cannot be

dynamically controlled during user mode operation.

Figure 2–59. Regional Clock Control Blocks

CLKp

CLKn

(2)

PLL Counter

Outputs

2

Internal

Logic

Static Clock Select

(1)

Enable/

Disable

Internal

Logic

RCLK

Notes to Figure 2–59:

(1) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode

operation.

(2) Only the CLKnpins on the top and bottom of the device feed to regional clock select.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–71

PLLs and Clock Networks

Figure 2–60. External PLL Output Clock Control Blocks

PLL Counter

Outputs (c[5..0])

6

Static Clock Select

(1)

Enable/

Disable

Internal

Logic

IOE (2)

Internal

Logic

Static Clock

Select

(1)

PLL_OUT

Notes to Figure 2–60:

(1) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode

operation.

(2) The clock control block feeds to a multiplexer within the PLL_OUTpin’s IOE. The PLL_OUTpin is a dual-purpose pin. Therefore, this multiplexer

selects either an internal signal or the output of the clock control block.

For the global clock control block, clock source selection can be controlled either

statically or dynamically. You have the option of statically selecting the clock source

by using the Quartus II software to set specific configuration bits in the configuration

file (.sof or .pof) or controlling the selection dynamically by using internal logic to

drive the multiplexer select inputs. When selecting statically, the clock source can be

set to any of the inputs to the select multiplexer. When selecting the clock source

dynamically, you can either select between two PLL outputs (such as the C0or C1

outputs from one PLL), between two PLLs (such as the C0/C1clock output of one

PLL or the C0/C1c1ock output of the other PLL), between two clock pins (such as

CLK0or CLK1), or between a combination of clock pins or PLL outputs.

For the regional and PLL_OUTclock control block, clock source selection can only be

controlled statically using configuration bits. Any of the inputs to the clock select

multiplexer can be set as the clock source.

Arria GX clock networks can be disabled (powered down) by both static and dynamic

approaches. When a clock net is powered down, all logic fed by the clock net is in an

off-state thereby reducing the overall power consumption of the device. GCLK and

RCLK networks can be powered down statically through a setting in the

configuration file (.sof or .pof). Clock networks that are not used are automatically

powered down through configuration bit settings in the configuration file generated

by the Quartus II software. The dynamic clock enable or disable feature allows the

internal logic to control power up/down synchronously on GCLKand RCLKnets and

PLL_OUTpins. This function is independent of the PLL and is applied directly on the

clock network or PLL_OUTpin, as shown in Figure 2–58 through Figure 2–60.

Arria GX Device Handbook, Volume 1

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Chapter 2: Arria GX Architecture

PLLs and Clock Networks

Enhanced and Fast PLLs

Arria GX devices provide robust clock management and synthesis using up to four

enhanced PLLs and four fast PLLs. These PLLs increase performance and provide

advanced clock interfacing and clock frequency synthesis. With features such as clock

switchover, spread spectrum clocking, reconfigurable bandwidth, phase control, and

reconfigurable phase shifting, the Arria GX device’s enhanced PLLs provide you with

complete control of your clocks and system timing. The fast PLLs provide general

purpose clocking with multiplication and phase shifting as well as high-speed

outputs for high-speed differential I/O support. Enhanced and fast PLLs work

together with the Arria GX high-speed I/O and advanced clock architecture to

provide significant improvements in system performance and bandwidth.

The Quartus II software enables the PLLs and their features without requiring any

external devices. Table 2–17 lists the PLLs available for each Arria GX device and their

type.

Table 2–17. Arria GX Device PLL Availability (Note 1), (2)

Fast PLLs

Enhanced PLLs

Device

1

2

3 (3) 4 (3)

7

8

9 (3) 10 (3)

5

6

11

—

v

12

—

v

EP1AGX20

—

v

—

v

—

v

EP1AGX35

EP1AGX50 (4)

EP1AGX60 (5)

EP1AGX90

Notes to Table 2–17:

(1) The global or regional clocks in a fast PLL's transceiver block can drive the fast PLL input. A pin or other PLL must drive the global or regional

source. The source cannot be driven by internally generated logic before driving the fast PLL.

(2) EP1AGX20C, EP1AGX35C/D, EP1AGX50C and EP1AGX60C/D devices only have two fast PLLs (PLLs 1 and 2), but the connectivity from these

two PLLs to the global and regional clock networks remains the same as shown in this table.

(3) PLLs 3, 4, 9, and 10 are not available in Arria GX devices.

(4) 4 or 8 PLLs are available depending on C or D device and the package option.

(5) 4or 8 PLLs are available depending on C, D, or E device option.

Table 2–18 lists the enhanced PLL and fast PLL features in Arria GX devices.

Table 2–18. Arria GX PLL Features (Part 1 of 2)

Feature

Clock multiplication and division

Phase shift

Enhanced PLL

Fast PLL

m/(n × post-scale counter) (1)

m/(n × post-scale counter) (2)

Down to 125-ps increments (3), (4)

Clock switchover

v

v (5)

v

PLL reconfiguration

v

Reconfigurable bandwidth

Spread spectrum clocking

Programmable duty cycle

Number of internal clock outputs

Number of external clock outputs

v

—

v

6

4

Three differential/six single-ended

(6)

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–73

PLLs and Clock Networks

Table 2–18. Arria GX PLL Features (Part 2 of 2)

Feature

Enhanced PLL

One single-ended or differential (7), (8)

Fast PLL

Number of feedback clock inputs

—

Notes to Table 2–18:

(1) For enhanced PLLs, m, n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle.

(2) For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.

(3) The smallest phase shift is determined by the voltage controlled oscillator (V_CO) period divided by 8.

(4) For degree increments, Arria GX devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible

depending on the frequency and divide parameters.

(5) Arria GX fast PLLs only support manual clock switchover.

(6) Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate

txclkout.

(7) If the feedback input is used, you lose one (or two, if f_BINis differential) external clock output pin.

(8) Every Arria GX device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL.

Figure 2–61 shows a top-level diagram of the Arria GX device and PLL floorplan.

Figure 2–61. PLL Locations

CLK[15..12]

11

5

7

FPLL7CLK

1

2

CLK[3..0]

PLLs

FPLL8CLK

8

12

6

CLK[7..4]

Figure 2–62 and Figure 2–63 shows global and regional clocking from the fast PLL

outputs and side clock pins. The connections to the global and regional clocks from

the fast PLL outputs, internal drivers, and CLKpins on the left side of the device are

shown in Table 2–19.

Arria GX Device Handbook, Volume 1

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Chapter 2: Arria GX Architecture

PLLs and Clock Networks

Figure 2–62. Global and Regional Clock Connections from Center Clock Pins and Fast PLL Outputs (Note 1)

C0

C1

C2

C3

CLK0

CLK1

Fast

PLL 1

Logic Array

Signal Input

To Clock

Network

C0

C1

C2

C3

Fast

PLL 2

CLK2

CLK3

RCLK0

RCLK2

RCLK4

RCLK6

RCLK5 RCLK7

GCLK0

GCLK1

GCLK2

GCLK3

RCLK1

RCLK3

Note to Figure 2–62:

(1) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global

or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–75

PLLs and Clock Networks

Figure 2–63. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL Outputs (Note 1)

RCLK1

RCLK3

RCLK2

RCLK0

C0

C1

C2

C3

Fast

PLL 7

C0

C1

C2

C3

Fast

PLL 8

RCLK4

RCLK6

RCLK7

GCLK0

GCLK1

GCLK2

GCLK3

RCLK5

Note to Figure 2–63:

(1) The GCLK or RCLK in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional

source. The source cannot be driven by internally generated logic before driving the fast PLL.

Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 1 of 2)

Left Side Global & Regional

Clock Network Connectivity

Clock Pins

CLK0p

CLK1p

CLK2p

CLK3p

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

Drivers from Internal Logic

GCLKDRV0

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

GCLKDRV1

GCLKDRV2

GCLKDRV3

RCLKDRV0

RCLKDRV1

RCLKDRV2

RCLKDRV3

RCLKDRV4

RCLKDRV5

RCLKDRV6

Arria GX Device Handbook, Volume 1

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Chapter 2: Arria GX Architecture

PLLs and Clock Networks

Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 2 of 2)

Left Side Global & Regional

Clock Network Connectivity

RCLKDRV7

—

v

—

v

PLL 1 Outputs

c0

c1

c2

c3

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

PLL 2 Outputs

c0

c1

c2

c3

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

PLL 7 Outputs

c0

c1

c2

c3

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

PLL 8 Outputs

c0

c1

c2

c3

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–77

PLLs and Clock Networks

Figure 2–64 shows the global and regional clocking from enhanced PLL outputs and

top and bottom CLKpins.

Figure 2–64. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL Outputs (Note 1)

CLK15

CLK14

CLK13

CLK12

PLL5_FB

PLL11_FB

PLL 11

PLL 5

c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5

PLL5_OUT[2..0]p

PLL5_OUT[2..0]n

PLL11_OUT[2..0]p

PLL11_OUT[2..0]n

RCLK31

RCLK30

RCLK29

RCLK28

RCLK27

Regional

Clocks

RCLK26

RCLK25

RCLK24

G15

G14

G13

G12

Global

Clocks

G4

G5

G6

G7

RCLK8

RCLK9

RCLK10

RCLK11

Regional

Clocks

RCLK12

RCLK13

RCLK14

RCLK15

PLL12_OUT[2..0]p

PLL12_OUT[2..0]n

PLL6_OUT[2..0]p

PLL6_OUT[2..0]n

c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5

PLL 12

PLL 6

PLL12_FB

PLL6_FB

CLK4

CLK6

CLK5

CLK7

Note to Figure 2–64:

(1) If the design uses the feedback input, you might lose one (or two if FBIN is differential) external clock output pin.

The connections to the global and regional clocks from the top clock pins and

enhanced PLL outputs are shown in Table 2–20. The connections to the clocks from

the bottom clock pins are shown in Table 2–21.

Arria GX Device Handbook, Volume 1

2–78

Chapter 2: Arria GX Architecture

PLLs and Clock Networks

Table 2–20. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs

Top Side Global and

Regional Clock Network

Connectivity

Clock pins

CLK12p

CLK13p

CLK14p

CLK15p

CLK12n

CLK13n

CLK14n

CLK15n

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

Drivers from internal logic

GCLKDRV0

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

GCLKDRV1

GCLKDRV2

GCLKDRV3

RCLKDRV0

RCLKDRV1

RCLKDRV2

RCLKDRV3

RCLKDRV4

RCLKDRV5

RCLKDRV6

RCLKDRV7

Enhanced PLL5 outputs

c0

c1

c2

c3

c4

c5

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

Enhanced PLL 11 outputs

c0

c1

c2

c3

c4

c5

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–79

PLLs and Clock Networks

Table 2–21. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL Outputs

Bottom Side Global and

Regional Clock Network

Connectivity

Clock pins

CLK4p

CLK5p

CLK6p

CLK7p

CLK4n

CLK5n

CLK6n

CLK7n

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

Drivers from internal logic

GCLKDRV0

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

GCLKDRV1

GCLKDRV2

GCLKDRV3

RCLKDRV0

RCLKDRV1

RCLKDRV2

RCLKDRV3

RCLKDRV4

RCLKDRV5

RCLKDRV6

RCLKDRV7

Enhanced PLL 6 outputs

c0

c1

c2

c3

c4

c5

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

Enhanced PLL 12 outputs

c0

c1

c2

c3

c4

c5

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

Arria GX Device Handbook, Volume 1

2–80

Chapter 2: Arria GX Architecture

PLLs and Clock Networks

Enhanced PLLs

Arria GX devices contain up to four enhanced PLLs with advanced clock

management features. These features include support for external clock feedback

mode, spread-spectrum clocking, and counter cascading. Figure 2–65 shows a

diagram of the enhanced PLL.

Figure 2–65. Arria GX Enhanced PLL (Note 1)

From Adjacent PLL

Post-Scale

V

Phase Selection

CO

Selectable at Each

PLL Output Port

Counters

Clock

Switchover

Circuitry

Spread

Spectrum

/c0

/c1

/c2

Phase Frequency

Detector

INCLK[3..0]

4

8

6

Global

Clocks

/n

8

Charge

Loop

Filter

PFD

VCO

Pump

6

Regional

Clocks

Global or

Regional

Clock

/c3

/c4

/c5

I/O Buffers

(3)

/m

(2)

to I/O or general

routing

Lock Detect

& Filter

FBIN

VCO Phase Selection

Affecting All Outputs

Shaded Portions of the

PLL are Reconfigurable

Notes to Figure 2–65:

(1) Each clock source can come from any of the four clock pins that are physically located on the same side of the device as the PLL.

(2) If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin.

(3) Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.

(4) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock

control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally

generated global signal cannot drive the PLL.

Fast PLLs

Arria GX devices contain up to four fast PLLs with high-speed serial interfacing

ability. Fast PLLs offer high-speed outputs to manage the high-speed differential I/O

interfaces. Figure 2–66 shows a diagram of the fast PLL.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–81

I/O Structure

Figure 2–66. Arria GX Device Fast PLL

Post-Scale

Counters

VCO Phase Selection

Selectable at each PLL

Output Port

Clock

Switchover

Circuitry (4)

Phase

Frequency

Detector

diffioclk0 (2)

load_en0 (3)

Global or

regional clock (1)

÷c0

÷c1

÷c2

8

Charge

Pump

(3)

load_en1

Loop

Filter

÷k

÷n

PFD

VCO

4

Clock

Input

diffioclk1 (2)

4

Global clocks

4

8

Global or

regional clock (1)

Regional clocks

to DPA block

÷c3

÷m

8

Shaded Portions of the

PLL are Reconfigurable

Notes to Figure 2–66:

(1) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock

control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally

generated global signal cannot drive the PLL.

(2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES) circuitry. Arria GX devices only

support one rate of data transfer per fast PLL in high-speed differential I/O support mode.

(3) This signal is a differential I/O SERDES control signal.

(4) Arria GX fast PLLs only support manual clock switchover.

f

For more information about enhanced and fast PLLs, refer to the PLLs in Arria GX

Devices chapter. For more information about high-speed differential I/O support,

refer to “High-Speed Differential I/O with DPA Support” on page 2–99.

I/O Structure

Arria GX IOEs provide many features, including:

■

Dedicated differential and single-ended I/O buffers

3.3-V, 64-bit, 66-MHz PCI compliance

3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance

JTAG boundary-scan test (BST) support

On-chip driver series termination

OCT for differential standards

Programmable pull-up during configuration

Output drive strength control

Tri-state buffers

Bus-hold circuitry

Programmable pull-up resistors

Programmable input and output delays

Open-drain outputs

DQ and DQS I/O pins

DDR registers

Arria GX Device Handbook, Volume 1

2–82

Chapter 2: Arria GX Architecture

I/O Structure

The IOE in Arria GX devices contains a bidirectional I/O buffer, six registers, and a

latch for a complete embedded bidirectional single data rate or DDR transfer.

Figure 2–67 shows the Arria GX IOE structure. The IOE contains two input registers

(plus a latch), two output registers, and two output enable registers. The design can

use both input registers and the latch to capture DDR input and both output registers

to drive DDR outputs. Additionally, the design can use the output enable (OE)

register for fast clock-to-output enable timing. The negative edge-clocked OE register

is used for DDR SDRAM interfacing. The Quartus II software automatically

duplicates a single OE register that controls multiple output or bidirectional pins.

Figure 2–67. Arria GX IOE Structure

Logic Array

OE Register

OE

D

Q

OE Register

D

Q

Output Register

Output A

Output B

D

Q

CLK

Output Register

D

Q

Input Register

D

Q

Input A

Input B

Input Latch

Input Register

D

Q

D

Q

ENA

The IOEs are located in I/O blocks around the periphery of the Arria GX device.

There are up to four IOEs per row I/O block and four IOEs per column I/O block.

Row I/O blocks drive row, column, or direct link interconnects. Column I/O blocks

drive column interconnects.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–83

I/O Structure

Figure 2–68 shows how a row I/O block connects to the logic array.

Figure 2–68. Row I/O Block Connection to the Interconnect

R4 & R24

Interconnects

C4 Interconnect

I/O Block Local

Interconnect

32 Data & Control

Signals from

Logic Array (1)

32

LAB

Horizontal

I/O Block

io_dataina[3..0]

io_datainb[3..0]

Direct Link

Interconnect

to Adjacent LAB

Direct Link

Interconnect

to Adjacent LAB

Horizontal I/O

Block Contains

up to Four IOEs

io_clk[7:0]

LAB Local

Interconnect

Note to Figure 2–68:

(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and

io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables

io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four

synchronous clear and preset signals io_sclr/spreset[3..0].

Arria GX Device Handbook, Volume 1

2–84

Chapter 2: Arria GX Architecture

I/O Structure

Figure 2–69 shows how a column I/O block connects to the logic array.

Figure 2–69. Column I/O Block Connection to the Interconnect

32 Data &

Control Signals

from Logic Array (1)

Vertical I/O

Block Contains

up to Four IOEs

Vertical I/O Block

32

IO_dataina[3..0]

IO_datainb[3..0]

io_clk[7..0]

I/O Block

Local Interconnect

R4 & R24

Interconnects

LAB

LAB Local

Interconnect

C4 & C16

Interconnects

Note to Figure 2–69:

(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0]and

io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables

io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four

synchronous clear and preset signals io_sclr/spreset[3..0].

There are 32 control and data signals that feed each row or column I/O block. These

control and data signals are driven from the logic array. The row or column IOE

clocks, io_clk[7..0], provide a dedicated routing resource for low-skew,

high-speed clocks. I/O clocks are generated from global or regional clocks (refer to

“PLLs and Clock Networks” on page 2–66).

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–85

I/O Structure

Figure 2–70 shows the signal paths through the I/O block.

Figure 2–70. Signal Path Through the I/O Block

Row or Column

io_clk[7..0]

To Other

IOEs

io_dataina

To Logic

Array

io_datainb

oe

ce_in

io_oe

io_ce_in

io_ce_out

io_aclr

ce_out

Control

Signal

Selection

IOE

aclr/apreset

sclr/spreset

From Logic

Array

clk_in

io_sclr

io_clk

clk_out

io_dataouta

io_dataoutb

Each IOE contains its own control signal selection for the following control signals:

oe, ce_in, ce_out, aclr/apreset, sclr/spreset, clk_in, and clk_out.

Figure 2–71 shows the control signal selection.

Figure 2–71. Control Signal Selection per IOE (Note 1)

Dedicated I/O

Clock [7..0]

io_oe

Local

Interconnect

io_sclr

Local

Interconnect

io_aclr

Local

Interconnect

io_ce_out

Local

Interconnect

io_ce_in

io_clk

Local

Interconnect

ce_out

clk_out

sclr/spreset

Local

Interconnect

clk_in

ce_in

aclr/apreset

oe

Notes to Figure 2–71:

(1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oecan be global signals even though their control selection

multiplexers are not directly fed by the ioe_clk[7..0]signals. The ioe_clksignals can drive the I/O local interconnect, which then drives

the control selection multiplexers.

Arria GX Device Handbook, Volume 1

2–86

Chapter 2: Arria GX Architecture

I/O Structure

In normal bidirectional operation, you can use the input register for input data

requiring fast setup times. The input register can have its own clock input and clock

enable separate from the OE and output registers. The output register can be used for

data requiring fast clock-to-output performance. You can use the OE register for fast

clock-to-output enable timing. The OE and output register share the same clock

source and the same clock enable source from the local interconnect in the associated

LAB, dedicated I/O clocks, and the column and row interconnects. Figure 2–72 shows

the IOE in bidirectional configuration.

Figure 2–72. Arria GX IOE in Bidirectional I/O Configuration (Note 1)

ioe_clk[7..0]

Column, Row,

or Local

Interconnect

oe

OE Register

D

Q

clkout

ENA

CLRN/PRN

OE Register

t

Delay

CO

ce_out

V

CCIO

PCI Clamp (2)

V

CCIO

Programmable

Pull-Up

aclr/apreset

Resistor

Chip-Wide Reset

On-Chip

Termination

Output Register

Output

Pin Delay

D

Q

Drive Strength Control

Open-Drain Output

sclr/spreset

ENA

CLRN/PRN

Input Pin to

Logic Array Delay

Bus-Hold

Circuit

Input Pin to

Input Register Delay

Input Register

clkin

D

Q

ce_in

ENA

CLRN/PRN

Notes to Figure 2–72:

(1) All input signals to the IOE can be inverted at the IOE.

(2) The optional PCI clamp is only available on column I/O pins.

The Arria GX device IOE includes programmable delays that can be activated to

ensure input IOE register-to-logic array register transfers, input pin-to-logic array

register transfers, or output IOE register-to-pin transfers.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–87

I/O Structure

A path in which a pin directly drives a register can require the delay to ensure zero

hold time, whereas a path in which a pin drives a register through combinational logic

may not require the delay. Programmable delays exist for decreasing

input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can

program these delays to automatically minimize setup time while providing a zero

hold time. Programmable delays can increase the register-to-pin delays for output

and/or output enable registers. Programmable delays are no longer required to

ensure zero hold times for logic array register-to-IOE register transfers. The Quartus II

Compiler can create zero hold time for these transfers. Table 2–22 shows the

programmable delays for Arria GX devices.

Table 2–22. Arria GX Devices Programmable Delay Chain

Programmable Delays

Input pin to logic array delay

Input pin to input register delay

Output pin delay

Quartus II Logic Option

Input delay from pin to internal cells

Input delay from pin to input register

Delay from output register to output pin

Delay to output enable pin

Output enable register t_COdelay

IOE registers in Arria GX devices share the same source for clear or preset. You can

program preset or clear for each individual IOE. You can also program the registers to

power up high or low after configuration is complete. If programmed to power up

low, an asynchronous clear can control the registers. If programmed to power up

high, an asynchronous preset can control the registers. This feature prevents the

inadvertent activation of another device’s active-low input upon power-up. If one

register in an IOE uses a preset or clear signal, all registers in the IOE must use that

same signal if they require preset or clear. Additionally, a synchronous reset signal is

available for the IOE registers.

Double Data Rate I/O Pins

Arria GX devices have six registers in the IOE, which support DDR interfacing by

clocking data on both positive and negative clock edges. The IOEs in Arria GX devices

support DDR inputs, DDR outputs, and bidirectional DDR modes. When using the

IOE for DDR inputs, the two input registers clock double rate input data on

alternating edges. An input latch is also used in the IOE for DDR input acquisition.

The latch holds the data that is present during the clock high times, allowing both bits

of data to be synchronous with the same clock edge (either rising or falling).

Figure 2–73 shows an IOE configured for DDR input. Figure 2–74 shows the DDR

input timing diagram.

Arria GX Device Handbook, Volume 1

2–88

Chapter 2: Arria GX Architecture

I/O Structure

Figure 2–73. Arria GX IOE in DDR Input I/O Configuration (Note 1)

ioe_clk[7..0]

VCCIO

Column, Row,

or Local

Interconnect

PCI Clamp (4)

To DQS Logic

Block (3)

DQS Local

Bus (2)

VCCIO

Programmable

Pull-Up

Resistor

On-Chip

Termination

Input Pin to

Input RegisterDelay

sclr/spreset

Input Register

D

Q

clkin

ENA

CLRN/PRN

ce_in

Bus-Hold

Circuit

aclr/apreset

Chip-Wide Reset

Latch

D Q

Input Register

D

Q

ENA

CLRN/PRN

Notes to Figure 2–73:

(1) All input signals to the IOE can be inverted at the IOE.

(2) This signal connection is only allowed on dedicated DQ function pins.

(3) This signal is for dedicated DQS function pins only.

(4) The optional PCI clamp is only available on column I/O pins.

Figure 2–74. Input Timing Diagram in DDR Mode

Data at

input pin

B0

A0 B1 A1 B2 A2 B3 A3 B4

CLK

A0

B0

A1

B1

A2

B2

A3

B3

Input To

Logic Array

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–89

I/O Structure

When using the IOE for DDR outputs, the two output registers are configured to clock

two data paths from ALMs on rising clock edges. These output registers are

multiplexed by the clock to drive the output pin at a ×2 rate. One output register

clocks the first bit out on the clock high time, while the other output register clocks the

second bit out on the clock low time. Figure 2–75 shows the IOE configured for DDR

output. Figure 2–76 shows the DDR output timing diagram.

Figure 2–75. Arria GX IOE in DDR Output I/O Configuration Notes (1), (2)

ioe_clk[7..0]

Column, Row,

or Local

Interconnect

oe

OE Register

D

Q

clkout

ENA

CLRN/PRN

OE Register

Delay

ce_out

t

CO

aclr/apreset

sclr/spreset

V

CCIO

PCI Clamp (3)

Chip-Wide Reset

OE Register

V

CCIO

D

Q

Programmable

Pull-Up

Resistor

Used for

DDR, DDR2

SDRAM

ENA

CLRN/PRN

Output Register

D

Q

On-Chip

Termination

Output

Pin Delay

clk

ENA

CLRN/PRN

Drive Strength

Control

Open-Drain Output

Output Register

D

Q

Bus-Hold

Circuit

ENA

CLRN/PRN

Notes to Figure 2–75:

(1) All input signals to the IOE can be inverted at the IOE.

(2) The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an inverter at the OE register data port.

(3) The optional PCI clamp is only available on column I/O pins.

Arria GX Device Handbook, Volume 1

2–90

Chapter 2: Arria GX Architecture

I/O Structure

Figure 2–76. Output Timing Diagram in DDR Mode

CLK

A1

A2

B2

A3

B3

A4

B4

From Internal

Registers

B1

B1 A1 B2 A2 B3 A3 B4 A4

DDR output

The Arria GX IOE operates in bidirectional DDR mode by combining the DDR input

and DDR output configurations. The negative-edge-clocked OE register holds the OE

signal inactive until the falling edge of the clock to meet DDR SDRAM timing

requirements.

External RAM Interfacing

In addition to the six I/O registers in each IOE, Arria GX devices also have dedicated

phase-shift circuitry for interfacing with external memory interfaces, including DDR,

DDR2 SDRAM, and SDR SDRAM. In every Arria GX device, the I/O banks at the top

(Banks 3 and 4) and bottom (Banks 7 and 8) of the device support DQ and DQS signals

with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–23 shows the number

of DQ and DQS buses that are supported per device.

Table 2–23. DQS and DQ Bus Mode Support (Note 1)

Number of

×4 Groups

Number of

Device

EP1AGX20

EP1AGX35

Package

×8/×9 Groups

×16/×18 Groups

×32/×36 Groups

484-pin FineLine BGA

780-pin FineLine BGA

484-pin FineLine BGA

780-pin FineLine BGA

2

0

8

0

8

0

4

0

4

0

18

2

18

EP1AGX50/60

1,152-pin FineLine

BGA

36

18

8

4

1,152-pin FineLine

BGA

EP1AGX90

Note to Table 2–23:

(1) Numbers are preliminary until devices are available.

A compensated delay element on each DQS pin automatically aligns input DQS

synchronization signals with the data window of their corresponding DQ data

signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This

DQS bus is an additional resource to the I/O clocks and is used to clock DQ input

registers with the DQS signal.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–91

I/O Structure

The Arria GX device has two phase-shifting reference circuits, one on the top and one

on the bottom of the device. The circuit on the top controls the compensated delay

elements for all DQS pins on the top. The circuit on the bottom controls the

compensated delay elements for all DQS pins on the bottom.

Each phase-shifting reference circuit is driven by a system reference clock, which must

have the same frequency as the DQS signal. Clock pins CLK[15..12]pfeed phase

circuitry on the top of the device and clock pins CLK[7..4]pfeed phase circuitry on

the bottom of the device. In addition, PLL clock outputs can also feed the

phase-shifting reference circuits. Figure 2–77 shows the phase-shift reference circuit

control of each DQS delay shift on the top of the device. This same circuit is

duplicated on the bottom of the device.

Figure 2–77. DQS Phase-Shift Circuitry (Note 1), (2)

From PLL 5 (4)

CLK[15..12]p (3)

DQS

Dt

Phase-Shift

Circuitry

Dt

to IOE

Notes to Figure 2–77:

(1) There are up to 18 pairs of DQS pins available on the top or bottom of the Arria GX device. There are up to 10 pairs on the right side and 8 pairs

on the left side of the DQS phase-shift circuitry.

(2) The “t” module represents the DQS logic block.

(3) Clock pins CLK[15..12]pfeed phase-shift circuitry on the top of the device and clock pins CLK[7..4]pfeed the phase circuitry on the

bottom of the device. You can also use a PLL clock output as a reference clock to phase shift circuitry.

(4) You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS phase-shift circuitry on the bottom

of the device.

These dedicated circuits combined with enhanced PLL clocking and phase-shift

ability provide a complete hardware solution for interfacing to high-speed memory.

f

For more information about external memory interfaces, refer to the External Memory

Interfaces in Arria GX Devices chapter.

Programmable Drive Strength

The output buffer for each Arria GX device I/O pin has a programmable drive

strength control for certain I/O standards. The LVTTL, LVCMOS, SSTL, and HSTL

standards have several levels of drive strength that you can control. The default

setting used in the Quartus II software is the maximum current strength setting that is

used to achieve maximum I/O performance. For all I/O standards, the minimum

setting is the lowest drive strength that guarantees the I_OH/I_OLof the standard. Using

minimum settings provides signal slew rate control to reduce system noise and signal

overshoot.

Arria GX Device Handbook, Volume 1

2–92

Chapter 2: Arria GX Architecture

I/O Structure

Table 2–24 shows the possible settings for I/O standards with drive strength control.

Table 2–24. Programmable Drive Strength (Note 1)

I

_OH/ I_OLCurrent Strength

I_OH/ I_OLCurrent Strength

Setting (mA) for Row I/O

Pins

I/O Standard

3.3-V LVTTL

Setting (mA) for Column

I/O Pins

24, 20, 16, 12, 8, 4

16, 12, 8, 4

12, 8, 4

8, 4

3.3-V LVCMOS

2.5-V LVTTL/LVCMOS

1.8-V LVTTL/LVCMOS

1.5-V LVCMOS

12, 8, 4

8, 6, 4, 2

4, 2

12, 10, 8, 6, 4, 2

8, 6, 4, 2

SSTL-2 Class I

12, 8

SSTL-2 Class II

24, 20, 16

16

SSTL-18 Class I

SSTL-18 Class II

HSTL-18 Class I

HSTL-18 Class II

HSTL-15 Class I

HSTL-15 Class II

Note to Table 2–24:

12, 10, 8, 6, 4

20, 18, 16, 8

12, 10, 8, 6, 4

20, 18, 16

10, 8, 6, 4

—

12, 10, 8, 6, 4

—

12, 10, 8, 6, 4

20, 18, 16

8, 6, 4

—

(1) The Quartus II software default current setting is the maximum setting for each I/O standard.

Open-Drain Output

Arria GX devices provide an optional open-drain (equivalent to an open collector)

output for each I/O pin. This open-drain output enables the device to provide

system-level control signals (for example, interrupt and write enable signals) that can

be asserted by any of several devices.

Bus Hold

Each Arria GX device I/O pin provides an optional bus-hold feature. Bus-hold

circuitry can hold the signal on an I/O pin at its last-driven state. Because the

bus-hold feature holds the last-driven state of the pin until the next input signal is

present, an external pull-up or pull-down resistor is not needed to hold a signal level

when the bus is tri-stated.

Bus-hold circuitry also pulls undriven pins away from the input threshold voltage

where noise can cause unintended high-frequency switching. You can select this

feature individually for each I/O pin. The bus-hold output drives no higher than

V_CCIOto prevent overdriving signals. If the bus-hold feature is enabled, the

programmable pull-up option cannot be used. Disable the bus-hold feature when the

I/O pin has been configured for differential signals.

Bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately

7 k to pull the signal level to the last-driven state. This information is provided for

each V_CCIOvoltage level. Bus-hold circuitry is active only after configuration. When

going into user mode, the bus-hold circuit captures the value on the pin present at the

end of configuration.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–93

I/O Structure

f

For the specific sustaining current driven through this resistor and overdrive current

used to identify the next-driven input level, refer to the DC & Switching Characteristics

chapter.

Programmable Pull-Up Resistor

Each Arria GX device I/O pin provides an optional programmable pull-up resistor

during user mode. If you enable this feature for an I/O pin, the pull-up resistor

(typically 25 k) holds the output to the V_CCIOlevel of the output pin’s bank.

Advanced I/O Standard Support

Arria GX device IOEs support the following I/O standards:

■

3.3-V LVTTL/LVCMOS

2.5-V LVTTL/LVCMOS

1.8-V LVTTL/LVCMOS

1.5-V LVCMOS

3.3-V PCI

3.3-V PCI-X mode 1

LVDS

LVPECL (on input and output clocks only)

Differential 1.5-V HSTL class I and II

Differential 1.8-V HSTL class I and II

Differential SSTL-18 class I and II

Differential SSTL-2 class I and II

1.2-V HSTL class I and II

1.5-V HSTL class I and II

1.8-V HSTL class I and II

SSTL-2 class I and II

SSTL-18 class I and II

Arria GX Device Handbook, Volume 1

2–94

Chapter 2: Arria GX Architecture

I/O Structure

Table 2–25 describes the I/O standards supported by Arria GX devices.

Table 2–25. Arria GX Devices Supported I/O Standards

I/O Standard Type

Input Reference Output Supply

Board

Termination

Voltage (V_TT) (V)

Voltage

(V_REF) (V)

Voltage

(V_CCIO) (V)

LVTTL

LVCMOS

2.5 V

Single-ended

Differential

—

3.3

—

2.5

—

1.8 V

—

1.8

—

1.5-V LVCMOS

3.3-V PCI

—

1.5

—

3.3

—

3.3-V PCI-X mode 1

LVDS

—

3.3

—

2.5 (3)

3.3

—

LVPECL (1)

Differential

—

HyperTransport technology

Differential

—

2.5 (3)

1.5

—

Differential 1.5-V HSTL class I and II (2) Differential

Differential 1.8-V HSTL class I and II (2) Differential

0.75

0.90

1.25

0.6

0.75

0.9

0.90

1.25

0.75

0.90

1.25

0.6

0.75

0.9

0.90

1.25

1.8

Differential SSTL-18 class I and II (2)

Differential SSTL-2 class I and II (2)

1.2-V HSTL (4)

Differential

1.8

Differential

2.5

Voltage-referenced

1.2

1.5-V HSTL class I and II

1.8-V HSTL class I and II

SSTL-18 class I and II

1.5

1.8

SSTL-2 class I and II

2.5

Notes to Table 2–25:

(1) This I/O standard is only available on input and output column clock pins.

(2) This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock pins in I/O banks 9, 10, 11,

and 12.

(3) V_CCIOis 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 3, 4, 7, 8, 9, 10, 11, and 12).

(4) 1.2-V HSTL is only supported in I/O banks 4, 7, and 8.

f

For more information about the I/O standards supported by Arria GX I/O banks,

refer to the Selectable I/O Standards in Arria GX Devices chapter.

Arria GX devices contain six I/O banks and four enhanced PLL external clock output

banks, as shown in Figure 2–78. The two I/O banks on the left of the device contain

circuitry to support source-synchronous, high-speed differential I/O for LVDS inputs

and outputs. These banks support all Arria GX I/O standards except PCI or PCI-X

I/O pins, and SSTL-18 class II and HSTL outputs. The top and bottom I/O banks

support all single-ended I/O standards. Additionally, enhanced PLL external clock

output banks allow clock output capabilities such as differential support for SSTL and

HSTL.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–95

I/O Structure

Figure 2–78. Arria GX I/O Banks (Note 1), (2)

DQS ×8

PLL11

Bank 11

PLL5

PLL7 VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3

Bank 3

VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4

Bank 4

Bank 9

Transmitter: Bank 13

Receiver: Bank 13

REFCLK: Bank 13

This I/O bank supports LVDS

and LVPECL standards

for input clock operations. Differential HSTL

and differential SSTL standards

are supported for both input

and output operations. (3)

This I/O bank supports LVDS

and LVPECL standards for input clock

operation. Differential HSTL and

differential SSTL standards are

supported for both input and output

operations. (3)

I/O Banks 3, 4, 9, and 11 support all single-ended

I/O standards for both input and output operations.

All differential I/O standards are supported for both

input and output operations at I/O banks 9 and 11.

I/O banks 1 & 2 support LVTTL, LVCMOS,

2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I,

LVDS, pseudo-differential SSTL-2 and pseudo-differential

SSTL-18 class I standards for both input and output

operations. HSTL, SSTL-18 class II,

pseudo-differential HSTL and pseudo-differential

SSTL-18 class II standards are only supported for

input operations. (4)

Transmitter: Bank 14

Receiver: Bank 14

REFCLK: Bank 14

PLL1

PLL2

I/O banks 7, 8, 10 and 12 support all single-ended I/O

standards for both input and output operations. All differential

I/O standards are supported for both input and output operations

at I/O banks 10 and 12.

This I/O bank supports LVDS

and LVPECL standards for input clock operation.

Differential HSTL and differential

and LVPECL standards for input clock

operation. Differential HSTL and differential

SSTL standards are supported

Transmitter: Bank 15

Receiver: Bank 15

REFCLK: Bank 15

SSTL standards are supported

for both input and output operations. (3)

Bank 8

Bank 7

Bank 12

PLL12

Bank 10

PLL6

VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8

VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7

PLL8

DQS ×8

Notes to Figure 2–78:

(1) Figure 2–78 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.

(2) Depending on the size of the device, different device members have different numbers of V_REFgroups. For the exact locations, refer to the pin list

and the Quartus II software.

(3) Banks 9 through 12 are enhanced PLL external clock output banks.

(4) Horizontal I/O banks feature SERDES and DPA circuitry for high-speed differential I/O standards. For more information about differential I/O

standards, refer to the High-Speed Differential I/O Interfaces in Arria GX Devices chapter.

Each I/O bank has its own VCCIOpins. A single device can support

1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different V_CCIOlevel

independently. Each bank also has dedicated VREFpins to support the

voltage-referenced standards (such as SSTL-2).

Each I/O bank can support multiple standards with the same V_CCIOfor input and

output pins. Each bank can support one V_REFvoltage level. For example, when V_CCIOis

3.3 V, a bank can support LVTTL, LVCMOS, and 3.3-V PCI for inputs and outputs.

On-Chip Termination

Arria GX devices provide differential (for the LVDS technology I/O standard) and

on-chip series termination to reduce reflections and maintain signal integrity. There is

no calibration support for these on-chip termination resistors. On-chip termination

simplifies board design by minimizing the number of external termination resistors

required. Termination can be placed inside the package, eliminating small stubs that

can still lead to reflections.

Arria GX Device Handbook, Volume 1

2–96

Chapter 2: Arria GX Architecture

I/O Structure

Arria GX devices provide two types of termination:

■

On-chip differential termination (R_DOCT)

On-chip series termination (R_SOCT)

■

Table 2–26 lists the Arria GX OCT support per I/O bank.

Table 2–26. On-Chip Termination Support by I/O Banks

Top and Bottom Banks

(3, 4, 7, 8)

On-Chip Termination Support

I/O Standard Support

Left Bank (1, 2)

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL

v

—

v

—

v

—

v

—

v

2.5-V LVCMOS

1.8-V LVTTL

1.8-V LVCMOS

1.5-V LVTTL

Series termination

1.5-V LVCMOS

SSTL-2 class I and II

SSTL-18 class I

SSTL-18 class II

1.8-V HSTL class I

1.8-V HSTL class II

1.5-V HSTL class I

1.2-V HSTL

LVDS

Differential termination (1)

HyperTransport

technology

Note to Table 2–26:

(1) Clock pins CLK1and CLK3, and pins FPLL[7..8]CLKdo not support differential on-chip termination. Clock pins CLK0and

CLK2, do support differential on-chip termination. Clock pins in the top and bottom banks (CLK[4..7, 12..15]) do not

support differential on-chip termination.

On-Chip Differential Termination (R_DOCT)

Arria GX devices support internal differential termination with a nominal resistance

value of 100  for LVDS input receiver buffers. LVPECL input signals (supported on

clock pins only) require an external termination resistor. R_DOCT is supported across

the full range of supported differential data rates as shown in the High-Speed I/O

Specifications section of the DC & Switching Characteristics chapter.

f

For more information about R_DOCT, refer to the High-Speed Differential I/O Interfaces

with DPA in Arria GX Devices chapter.

For more information about tolerance specifications for R_DOCT, refer to the DC &

Switching Characteristics chapter.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–97

I/O Structure

On-Chip Series Termination (R_SOCT)

Arria GX devices support driver impedance matching to provide the I/O driver with

controlled output impedance that closely matches the impedance of the transmission

line. As a result, reflections can be significantly reduced. Arria GX devices support

R_SOCT for single-ended I/O standards with typical R_Svalues of 25 and 50 Once

matching impedance is selected, current drive strength is no longer selectable.

Table 2–26 shows the list of output standards that support R_SOCT.

f

For more information about R_SOCT supported by Arria GX devices, refer to the

Selectable I/O Standards in Arria GX Devices chapter.

For more information about tolerance specifications for OCT without calibration, refer

to the DC & Switching Characteristics chapter.

MultiVolt I/O Interface

The Arria GX architecture supports the MultiVolt I/O interface feature that allows

Arria GX devices in all packages to interface with systems of different supply

voltages. Arria GX VCCINTpins must always be connected to a 1.2-V power supply.

With a 1.2-V V_CCINTlevel, input pins are 1.2-, 1.5-, 1.8-, 2.5-, and 3.3-V tolerant. The

VCCIOpins can be connected to either a 1.2-, 1.5-, 1.8-, 2.5-, or 3.3-V power supply,

depending on the output requirements. The output levels are compatible with

systems of the same voltage as the power supply (for example, when VCCIOpins are

connected to a 1.5-V power supply, the output levels are compatible with 1.5-V

systems). Arria GX VCCPDpower pins must be connected to a 3.3-V power supply.

These power pins are used to supply the pre-driver power to the output buffers,

which increases the performance of the output pins. The VCCPDpins also power

configuration input pins and JTAG input pins.

Table 2–27 lists Arria GX MultiVolt I/O support.

Table 2–27. Arria GX MultiVolt I/O Support

(Note 1)

Input Signal (V)

1.8

Output Signal (V)

V_CCIO(V)

1.2

(4)

1.5

2.5

3.3

v (2)

v

1.2

1.5

—

1.8

—

2.5

—

v

3.3

—

v

5.0

—

v

1.2

1.5

1.8

2.5

3.3

v (2) v (2) v (2)

v (4)

v (3)

v

—

v

—

v (2)

v

—

v (3)

v

v (3) v (3) v (3)

v

v (3) v (3) v (3) v (3)

Notes to Table 2–27:

(1) To drive inputs higher than V_{C C IO}but less than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL and LVCMOS input levels to

overdrive input buffer option in the Quartus II software.

(2) The pin current may be slightly higher than the default value. You must verify that the driving device’s V_{O L}maximum and V_{O H}minimum voltages do

not violate the applicable Arria GX V_{I L}maximum and V_{I H}minimum voltage specifications.

(3) Although V_{CC I O}specifies the voltage necessary for the Arria GX device to drive out, a receiving device powered at a different level can still interface

with the Arria GX device if it has inputs that tolerate the V_{C C I O}value.

(4) Arria GX devices support 1.2-V HSTL. They do not support 1.2-V LVTTL and 1.2-V LVCMOS.

Arria GX Device Handbook, Volume 1

2–98

Chapter 2: Arria GX Architecture

I/O Structure

The TDOand nCEOpins are powered by V_CCIOof the bank that they reside. TDOis in

I/O bank 4 and nCEOis in I/O Bank 7. Ideally, the V_CCsupplies for the I/O buffers of

any two connected pins are at the same voltage level. This may not always be possible

depending on the V_CCIOlevel of TDOand nCEOpins on master devices and the

configuration voltage level chosen by V_CCSELon slave devices. Master and slave

devices can be in any position in the chain. The master device indicates that it is

driving out TDOor nCEOto a slave device. For multi-device passive configuration

schemes, the nCEOpin of the master device drives the nCEpin of the slave device. The

VCCSELpin on the slave device selects which input buffer is used for nCE. When

V_CCSELis logic high, it selects the 1.8-V/1.5-V buffer powered by V_CCIO. When V_CCSELis

logic low, it selects the 3.3-V/2.5-V input buffer powered by V_CCPD. The ideal case is to

have the V_CCIOof the nCEObank in a master device match the V_CCSELsettings for the

nCEinput buffer of the slave device it is connected to, but that may not be possible

depending on the application.

Table 2–28 contains board design recommendations to ensure that nCEOcan

successfully drive nCEfor all power supply combinations.

Table 2–28. Board Design Recommendations for nCEO and nCE Input Buffer Power

Arria GX nCEO V_CCIOVoltage Level in I/O Bank 7

nCE Input Buffer Power

in I/O Bank 3

V_{C C IO}= 3.3 V

V_{C C I O}= 2.5 V

V_{C C IO}= 1.8 V

V_{C C IO}= 1.5 V

V_{C C IO}= 1.2 V

VCCSELhigh

(V_{CC I O}Bank 3 = 1.5 V)

v (1), (2)

v (3), (4)

v (5)

v

VCCSELhigh

(V_{CC I O}Bank 3 = 1.8 V)

v (1), (2)

v (3), (4)

v (4)

v

Level shifter

required

VCCSELlow (nCE

powered by

v

v (6)

Level shifter

required

Level shifter

required

V

_{C C P D}= 3.3 V)

Notes to Table 2–28:

(1) Input buffer is 3.3-V tolerant.

(2) The nCEOoutput buffer meets V_{O H}(MIN) = 2.4 V.

(3) Input buffer is 2.5-V tolerant.

(4) The nCEOoutput buffer meets V_{O H}(MIN) = 2.0 V.

(5) Input buffer is 1.8-V tolerant.

(6) An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal.

For JTAG chains, the TDOpin of the first device drives the TDIpin of the second

device in the chain. The V_CCSELinput on JTAG input I/O cells (TCK, TMS, TDI, and

TRST) is internally hardwired to GND selecting the 3.3-V/2.5-V input buffer powered

by V_CCPD. The ideal case is to have the V_CCIOof the TDObank from the first device to

match the V_CCSELsettings for TDIon the second device, but that may not be possible

depending on the application. Table 2–29 contains board design recommendations to

ensure proper JTAG chain operation.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–99

High-Speed Differential I/O with DPA Support

Table 2–29. Supported TDO/TDI Voltage Combinations

Arria GX TDO V_{C CI O}Voltage Level in I/O Bank 4

TDI Input

Buffer Power

Device

Arria GX

V_{CC I O}= 3.3 V

V_{C C IO}= 2.5 V

V_{C C IO}= 1.8 V

V_{CC I O}= 1.5 V

V_{C C IO}= 1.2 V

Always V_{C CP D}

(3.3 V)

v (1)

v (2)

v (3)

Level shifter

required

Level shifter

required

VCC = 3.3 V

VCC = 2.5 V

VCC = 1.8 V

VCC = 1.5 V

v (1)

v (2)

v (3)

v

Level shifter

required

Level shifter

required

v (1), (4)

Level shifter

required

Level shifter

required

Non-Arria GX

v (2), (5)

Level shifter

required

Level shifter

required

v (6)

v

Notes to Table 2–29:

(1) The TDOoutput buffer meets V_OH(MIN) = 2.4 V.

(2) The TDOoutput buffer meets V_OH(MIN) = 2.0 V.

(3) An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal.

(4) Input buffer must be 3.3-V tolerant.

(5) Input buffer must be 2.5-V tolerant.

(6) Input buffer must be 1.8-V tolerant.

High-Speed Differential I/O with DPA Support

Arria GX devices contain dedicated circuitry for supporting differential standards at

speeds up to 840 Mbps. LVDS differential I/O standards are supported in the Arria

GX device. In addition, the LVPECL I/O standard is supported on input and output

clock pins on the top and bottom I/O banks.

The high-speed differential I/O circuitry supports the following high-speed I/O

interconnect standards and applications:

■

SPI-4 Phase 2 (POS-PHY Level 4)

SFI-4

Parallel RapidIO standard

There are two dedicated high-speed PLLs (PLL1 and PLL2) in the EP1AGX20 and

EP1AGX35 devices and up to four dedicated high-speed PLLs (PLL1, PLL2, PLL7,

and PLL8) in the EP1AGX50, EP1AGX60, and EP1AGX90 devices to multiply

reference clocks and drive high-speed differential SERDES channels in I/O banks 1

and 2.

Table 2–30 through Table 2–34 list the number of channels that each fast PLL can clock

in each of the Arria GX devices. In Table 2–30 through Table 2–34 the first row for each

transmitter or receiver provides the maximum number of channels that each fast PLL

can drive in its adjacent I/O bank (I/O Bank 1 or I/O Bank 2). The second row shows

the maximum number of channels that each fast PLL can drive in both I/O banks

(I/O Bank 1 and I/O Bank 2). For example, in the 780-pin FineLine BGA EP1AGX20

Arria GX Device Handbook, Volume 1

2–100

Chapter 2: Arria GX Architecture

High-Speed Differential I/O with DPA Support

device, PLL 1 can drive a maximum of 16 transmitter channels in I/O Bank 2 or a

maximum of 29 transmitter channels in I/O Banks 1 and 2. The Quartus II software

can also merge receiver and transmitter PLLs when a receiver is driving a transmitter.

In this case, one fast PLL can drive both the maximum numbers of receiver and

transmitter channels.

1

For more information, refer to the “Differential Pin Placement Guidelines” section in

the High-Speed Differential I/O Interfaces with DPA in Arria GX Devices chapter.

Table 2–30. EP1AGX20 Device Differential Channels (Note 1)

Center Fast PLLs

Package

Transmitter/Receiver

Total Channels

PLL1

16

PLL2

13

Transmitter

Receiver

29

31

29

31

13

16

484-pin FineLine BGA

17

14

17

16

13

Transmitter

Receiver

13

16

780-pin FineLine GBA

17

14

17

Note to Table 2–30:

(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.

Table 2–31. EP1AGX35 Device Differential Channels (Note 1)

Center Fast PLLs

Package

Transmitter/Receiver

Total Channels

PLL1

16

PLL2

13

Transmitter

29

13

16

484-pin FineLine BGA

Receiver

31

29

31

17

14

17

Transmitter

Receiver

16

13

16

780-pin FineLine BGA

17

14

17

Note to Table 2–31:

(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–101

High-Speed Differential I/O with DPA Support

Table 2–32. EP1AGX50 Device Differential Channels (Note 1)

Center Fast PLLs

PLL1

Corner Fast PLLs

PLL7

Transmitter/

Package

Total Channels

Receiver

PLL2

13

16

14

17

13

16

14

17

21

PLL8

—

21

—

21

—

Transmitter

29

16

13

17

14

16

13

17

14

21

—

21

—

21

—

484-pin

FineLine BGA

Receiver

31

29

31

42

Transmitter

Receiver

780-pin

FineLine BGA

Transmitter

Receiver

1,152-pin

FineLine BGA

Note to Table 2–32:

(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.

Table 2–33. EP1AGX60 Device Differential Channels (Note 1)

Center Fast PLLs

PLL1

Corner Fast PLLs

PLL7

Transmitter/

Receiver

Package

Total Channels

PLL2

13

16

14

17

13

16

14

17

21

PLL8

—

21

—

21

—

Transmitter

29

16

13

17

14

16

13

17

14

21

—

21

—

21

—

484-pin

FineLine BGA

Receiver

31

29

31

42

Transmitter

Receiver

780-pin

FineLine BGA

Transmitter

Receiver

1,152-pin

FineLine BGA

Note to Table 2–33:

(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.

Arria GX Device Handbook, Volume 1

2–102

Chapter 2: Arria GX Architecture

High-Speed Differential I/O with DPA Support

Table 2–34. EP1AGX90 Device Differential Channels (Note 1)

Corner Fast

Center Fast PLLs

PLLs

Package

Transmitter/Receiver Total Channels

PLL1

23

PLL2

22

PLL7

23

Transmitter

Receiver

45

47

22

23

—

1,152-pin FineLine

BGA

23

24

23

24

23

—

Note to Table 2–34:

(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.

Dedicated Circuitry with DPA Support

Arria GX devices support source-synchronous interfacing with LVDS signaling at up

to 840 Mbps. Arria GX devices can transmit or receive serial channels along with a

low-speed or high-speed clock.

The receiving device PLL multiplies the clock by an integer factor W = 1 through 32.

The SERDES factor J determines the parallel data width to deserialize from receivers

or to serialize for transmitters. The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10

and does not have to equal the PLL clock-multiplication W value. A design using the

dynamic phase aligner also supports all of these J factor values. For a J factor of 1, the

Arria GX device bypasses the SERDES block. For a J factor of 2, the Arria GX device

bypasses the SERDES block, and the DDR input and output registers are used in the

IOE. Figure 2–79 shows the block diagram of the Arria GX transmitter channel.

Figure 2–79. Arria GX Transmitter Channel

Data from R4, R24, C4, or

direct link interconnect

+

–

Up to 840 Mbps

10

Dedicated

Transmitter

Interface

Local

Interconnect

diffioclk

load_en

refclk

Fast

PLL

Regional or

global clock

Each Arria GX receiver channel features a DPA block for phase detection and

selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the

dynamic phase aligner without affecting the basic source-synchronous operation of

the channel. In addition, you can dynamically switch between using the DPA block or

bypassing the block via a control signal from the logic array.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–103

High-Speed Differential I/O with DPA Support

Figure 2–80 shows the block diagram of the Arria GX receiver channel.

Figure 2–80. GX Receiver Channel

Data to R4, R24, C4, or

direct link interconnect

+

–

Up to 840 Mbps

D

Q

Data Realignment

Circuitry

10

data

retimed_data

Dedicated

Receiver

Interface

DPA

Synchronizer

DPA_clk

Eight Phase Clocks

8

diffioclk

load_en

refclk

Fast

PLL

Regional or

global clock

An external pin or global or regional clock can drive the fast PLLs, which can output

up to three clocks: two multiplied high-speed clocks to drive the SERDES block

and/or external pin, and a low-speed clock to drive the logic array. In addition, eight

phase-shifted clocks from the V_COcan feed to the DPA circuitry.

f

For more information about fast PLL, refer to the PLLs in Arria GX Devices chapter.

The eight phase-shifted clocks from the fast PLL feed to the DPA block. The DPA

block selects the closest phase to the center of the serial data eye to sample the

incoming data. This allows the source-synchronous circuitry to capture incoming data

correctly regardless of channel-to-channel or clock-to-channel skew. The DPA block

locks to a phase closest to the serial data phase. The phase-aligned DPA clock is used

to write the data into the synchronizer.

The synchronizer sits between the DPA block and the data realignment and SERDES

circuitry. Because every channel using the DPA block can have a different phase

selected to sample the data, the synchronizer is needed to synchronize the data to the

high-speed clock domain of the data realignment and the SERDES circuitry.

For high-speed source-synchronous interfaces such as POS-PHY 4 and the Parallel

RapidIO standard, the source synchronous clock rate is not a byte- or SERDES-rate

multiple of the data rate. Byte alignment is necessary for these protocols because the

source synchronous clock does not provide a byte or word boundary as the clock is

one half the data rate, not one eighth. The Arria GX device’s high-speed differential

I/O circuitry provides dedicated data realignment circuitry for user-controlled byte

boundary shifting. This simplifies designs while saving ALM resources. You can use

an ALM-based state machine to signal the shift of receiver byte boundaries until a

specified pattern is detected to indicate byte alignment.

Arria GX Device Handbook, Volume 1

2–104

Chapter 2: Arria GX Architecture

High-Speed Differential I/O with DPA Support

Fast PLL and Channel Layout

The receiver and transmitter channels are interleaved as such that each I/O bank on

the left side of the device has one receiver channel and one transmitter channel per

LAB row. Figure 2–81 shows the fast PLL and channel layout in the EP1AGX20C,

EP1AGX35C/D, EP1AGX50C/D and EP1AGX60C/D devices. Figure 2–82 shows the

fast PLL and channel layout in EP1AGX60E and EP1AGX90E devices.

Figure 2–81. Fast PLL and Channel Layout in EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, EP1AGX60C/D Devices (Note 1)

4

LVDS

Clock

DPA

Clock

Quadrant

4

2

Fast

PLL 1

Fast

PLL 2

Quadrant

LVDS

Clock

DPA

Clock

4

Note to Figure 2–81:

(1) For the number of channels each device supports, refer to Table 2–30.

Figure 2–82. Fast PLL and Channel Layout in EP1AGX60E and EP1AGX90E Devices (Note 1)

Fast

PLL 7

2

4

LVDS

Clock

DPA

Clock

Quadrant

4

2

Fast

PLL 1

Fast

PLL 2

LVDS

Clock

DPA

Clock

Quadrant

4

2

Fast

PLL 8

Note to Figure 2–82:

(1) For the number of channels each device supports, refer to Table 2–30 through Table 2–34.

Arria GX Device Handbook, Volume 1

Chapter 2: Arria GX Architecture

2–105

Document Revision History

Table 2–35 shows the revision history for this chapter.

Table 2–35. Document Revision History

Date and Document Version

Changes Made

■ Document template update.

■ Minor text edits.

Summary of Changes

December 2009, v2.0

—

May 2008, v1.3

Added “Reverse Serial Pre-CDR Loopback”

and “Calibration Block” sub-sections to

“Transmitter Path” section.

—

August 2007, v1.2

June 2007, v1.1

May 2007 v1.0

Added “Referenced Documents” section.

Added GIGE information.

Initial release.

—

Arria GX Device Handbook, Volume 1

2–106

Chapter 2: Arria GX Architecture

Document Revision History

Arria GX Device Handbook, Volume 1

3. Configuration and Testing

AGX51003-2.0

Introduction

All Arria^®GX devices provide JTAG boundary-scan test (BST) circuitry that complies

with the IEEE Std. 1149.1. You can perform JTAG boundary-scan testing either before

or after, but not during configuration. Arria GX devices can also use the JTAG port for

configuration with the Quartus^®II software or hardware using either jam files (.jam)

or jam byte-code files (.jbc).

This chapter contains the following sections:

■

“IEEE Std. 1149.1 JTAG Boundary-Scan Support”

“SignalTap II Embedded Logic Analyzer” on page 3–3

“Configuration” on page 3–3

“Automated Single Event Upset (SEU) Detection” on page 3–8

IEEE Std. 1149.1 JTAG Boundary-Scan Support

Arria GX devices support I/O element (IOE) standard setting reconfiguration through

the JTAG BST chain. The JTAG chain can update the I/O standard for all input and

output pins any time before or during user-mode through the CONFIG_IO

instruction. You can use this capability for JTAG testing before configuration when

some of the Arria GX pins drive or receive from other devices on the board using

voltage-referenced standards. Because the Arria GX device may not be configured

before JTAG testing, the I/O pins may not be configured for appropriate electrical

standards for chip-to-chip communication. Programming these I/O standards via

JTAG allows you to fully test the I/O connections to other devices.

A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK,

and one optional pin, TRST. The TCKpin has an internal weak pull-down resistor,

while the TDI, TMS, and TRSTpins have weak internal pull-up resistors. The JTAG

input pins are powered by the 3.3-V V_CCPDpins. The TDOoutput pin is powered by the

V_CCIOpower supply in I/O bank 4.

Arria GX devices also use the JTAG port to monitor the logic operation of the device

with the SignalTap^®II embedded logic analyzer. Arria GX devices support the JTAG

instructions shown in Table 3–1.

1

Arria GX, Cyclone^®II, Cyclone, Stratix^®, Stratix II, Stratix GX , and Stratix II GX

devices must be within the first 17 devices in a JTAG chain. All of these devices have

the same JTAG controller. If any of the Stratix, Arria GX, Cyclone, and Cyclone II

devices are in the 18th or further position, they will fail configuration. This does not

affect the functionality of the SignalTap^®II embedded logic analyzer.

Arria GX Device Handbook, Volume 1

3–2

Chapter 3: Configuration and Testing

IEEE Std. 1149.1 JTAG Boundary-Scan Support

Table 3–1. Arria GX JTAG Instructions

JTAG Instruction

Instruction Code

Description

SAMPLE/PRELOAD

00 0000 0101

Allows a snapshot of signals at the device pins to be captured

and examined during normal device operation and permits an

initial data pattern to be output at the device pins. Also used by

the SignalTap II embedded logic analyzer.

EXTEST (1)

00 0000 1111

11 1111 1111

Allows external circuitry and board-level interconnects to be

tested by forcing a test pattern at the output pins and capturing

test results at the input pins.

BYPASS

Places the 1-bit bypass register between the TDIand TDOpins,

which allows the BST data to pass synchronously through

selected devices to adjacent devices during normal device

operation.

USERCODE

00 0000 0111

Selects the 32-bit USERCODEregister and places it between the

TDIand TDOpins, allowing the USERCODEto be serially shifted

out of TDO.

IDCODE

00 0000 0110

00 0000 1011

Selects the IDCODEregister and places it between TDIand TDO,

allowing IDCODEto be serially shifted out of TDO.

HIGHZ (1)

Places the 1-bit bypass register between the TDIand TDOpins,

which allows the BST data to pass synchronously through

selected devices to adjacent devices during normal device

operation, while tri-stating all of the I/O pins.

CLAMP (1)

00 0000 1010

Places the 1-bit bypass register between the TDIand TDOpins,

which allows the BST data to pass synchronously through

selected devices to adjacent devices during normal device

operation while holding I/O pins to a state defined by the data in

the boundary-scan register.

ICR instructions

—

Used when configuring an Arria GX device via the JTAG port with

a USB-Blaster^TM, MasterBlaster^TM, ByteBlasterMV^TM

,

EthernetBlaster^TM, or ByteBlaster II download cable, or when

using a .jam or .jbc via an embedded processor or JRunner^TM.

PULSE_NCONFIG

00 0000 0001

00 0000 1101

Emulates pulsing the nCONFIGpin low to trigger

reconfiguration even though the physical pin is unaffected.

CONFIG_IO (2)

Allows configuration of I/O standards through the JTAG chain for

JTAG testing. Can be executed before, during, or after

configuration. Stops configuration if executed during

configuration. Once issued, the CONFIG_IOinstruction holds

nSTATUSlow to reset the configuration device. nSTATUSis

held low until the IOE configuration register is loaded and the

TAP controller state machine transitions to the UPDATE_DR

state.

Notes to Table 3–1:

(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.

(2) For more information about using the CONFIG_IOinstruction, refer to the MorphIO: An I/O Reconfiguration Solution for Altera Devices

White Paper.

Arria GX Device Handbook, Volume 1

Chapter 3: Configuration and Testing

3–3

SignalTap II Embedded Logic Analyzer

The Arria GX device instruction register length is 10 bits and the USERCODEregister

length is 32 bits. Table 3–2 and Table 3–3 show the boundary-scan register length and

device IDCODEinformation for Arria GX devices.

Table 3–2. Arria GX Boundary-Scan Register Length

Device

Boundary-Scan Register Length

EP1AGX20

EP1AGX35

EP1AGX50

EP1AGX60

EP1AGX90

1320

1668

2016

Table 3–3. 2-Bit Arria GX Device IDCODE

IDCODE (32 Bits)

Device

Manufacturer Identity

Version (4 Bits)

Part Number (16 Bits)

LSB (1 Bit)

(11 Bits)

EP1AGX20

0000

0010 0001 0010 0001

0010 0001 0010 0010

0010 0001 0010 0011

000 0110 1110

1

EP1AGX35

EP1AGX50

EP1AGX60

EP1AGX90

SignalTap II Embedded Logic Analyzer

Arria GX devices feature the SignalTap II embedded logic analyzer, which monitors

design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry.

You can analyze internal logic at speed without bringing internal signals to the I/O

pins. This feature is particularly important for advanced packages, such as FineLine

BGA (FBGA) packages, because it can be difficult to add a connection to a pin during

the debugging process after a board is designed and manufactured.

Configuration

The logic, circuitry, and interconnects in the Arria GX architecture are configured with

CMOS SRAM elements. Altera^®FPGAs are reconfigurable and every device is tested

with a high coverage production test program so you do not have to perform fault

testing and can instead focus on simulation and design verification.

Arria GX devices are configured at system power up with data stored in an Altera

configuration device or provided by an external controller (for example, a MAX^®II

device or microprocessor). You can configure Arria GX devices using the fast passive

parallel (FPP), active serial (AS), passive serial (PS), passive parallel asynchronous

(PPA), and JTAG configuration schemes. Each Arria GX device has an optimized

interface that allows microprocessors to configure it serially or in parallel, and

synchronously or asynchronously. The interface also enables microprocessors to treat

Arria GX devices as memory and configure them by writing to a virtual memory

location, making reconfiguration easy.

Arria GX Device Handbook, Volume 1

3–4

Chapter 3: Configuration and Testing

Configuration

In addition to the number of configuration methods supported, Arria GX devices also

offer decompression and remote system upgrade features. The decompression feature

allows Arria GX FPGAs to receive a compressed configuration bitstream and

decompress this data in real-time, reducing storage requirements and configuration

time. The remote system upgrade feature allows real-time system upgrades from

remote locations of Arria GX designs. For more information, refer to “Configuration

Schemes” on page 3–5.

Operating Modes

The Arria GX architecture uses SRAM configuration elements that require

configuration data to be loaded each time the circuit powers up. The process of

physically loading the SRAM data into the device is called configuration. During

initialization, which occurs immediately after configuration, the device resets

registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are

tri-stated during power up, and before and during configuration. Together, the

configuration and initialization processes are called command mode. Normal device

operation is called user mode.

SRAM configuration elements allow you to reconfigure Arria GX devices in-circuit by

loading new configuration data into the device. With real-time reconfiguration, the

device is forced into command mode with a device pin. The configuration process

loads different configuration data, re-initializes the device, and resumes user-mode

operation. You can perform in-field upgrades by distributing new configuration files

either within the system or remotely.

PORSELis a dedicated input pin used to select power-on reset (POR) delay times of

12 ms or 100 ms during power up. When the PORSELpin is connected to ground, the

POR time is 100 ms. When the PORSELpin is connected to V_CC, the POR time is 12 ms.

The nIO_PULLUPpin is a dedicated input that chooses whether the internal pull-up

resistors on the user I/O pins and dual-purpose configuration I/O pins (nCSO, ASDO,

DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS, RUnLU, PGM[2..0], CLKUSR,

INIT_DONE, DEV_OE, DEV_CLR) are on or off before and during configuration. A

logic high (1.5, 1.8, 2.5, 3.3 V) turns off the weak internal pull-up resistors, while a

logic low turns them on.

Arria GX devices also offer a new power supply, V_CCPD, which must be connected to

3.3 V in order to power the 3.3-V/2.5-V buffer available on the configuration input

pins and JTAG pins. V_CCPDapplies to all the JTAG input pins (TCK, TMS, TDI, and

TRST) and the following configuration pins: nCONFIG, DCLK(when used as an input),

nIO_PULLUP, DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. The V_CCSEL

pin allows the V_CCIOsetting (of the banks where the configuration inputs reside) to be

independent of the voltage required by the configuration inputs. Therefore, when

selecting the V_CCIOvoltage, you do not have to take the VIL and VIH levels driven to

the configuration inputs into consideration. The configuration input pins, nCONFIG,

DCLK(when used as an input), nIO_PULLUP, RUnLU, nCE, nWS, nRS, CS, nCS, and

CLKUSR, have a dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V

input buffer. The V_CCSELinput pin selects which input buffer is used. The 3.3-V/2.5-V

input buffer is powered by V_CCPD, while the 1.8-V/1.5-V input buffer is powered by

V_CCIO

.

Arria GX Device Handbook, Volume 1

Chapter 3: Configuration and Testing

3–5

Configuration

V_CCSELis sampled during power up. Therefore, the V_CCSELsetting cannot change

on-the-fly or during a reconfiguration. The V_CCSELinput buffer is powered by V_CCINT

and must be hard-wired to V_CCPDor ground. A logic high V_CCSELconnection selects the

1.8-V/1.5-V input buffer, and a logic low selects the 3.3-V/2.5-V input buffer. V_CCSEL

should be set to comply with the logic levels driven out of the configuration device or

MAX II microprocessor.

If the design must support configuration input voltages of 3.3 V/2.5 V, set V_CCSELto a

logic low. You can set the V_CCIOvoltage of the I/O bank that contains the configuration

inputs to any supported voltage. If the design must support configuration input

voltages of 1.8 V/1.5 V, set V_CCSELto a logic high and the V_CCIOof the bank that

contains the configuration inputs to 1.8 V/1.5 V.

f

For more information about multi-volt support, including information about using

TDOand nCEOin multi-volt systems, refer to the Arria GX Architecture chapter.

Configuration Schemes

You can load the configuration data for an Arria GX device with one of five

configuration schemes (refer to Table 3–4), chosen on the basis of the target

application. You can use a configuration device, intelligent controller, or the JTAG

port to configure an Arria GX device. A configuration device can automatically

configure an Arria GX device at system power up.

You can configure multiple Arria GX devices in any of the five configuration schemes

by connecting the configuration enable (nCE) and configuration enable output (nCEO)

pins on each device. Arria GX FPGAs offer the following:

■

Configuration data decompression to reduce configuration file storage

Remote system upgrades for remotely updating Arria GX designs

■

Table 3–4 lists which configuration features can be used in each configuration scheme.

f

For more information about configuration schemes in Arria GX devices, refer to the

Configuring Arria GX Devices chapter.

Table 3–4. Arria GX Configuration Features (Part 1 of 2)

Configuration Scheme

Configuration Method

Decompression

Remote System Upgrade

MAX II device or microprocessor

and flash device

v (1)

v

FPP

AS

Enhanced configuration device

Serial configuration device

v (2)

v

v (3)

v

MAX II device or microprocessor

and flash device

v

PS

Enhanced configuration device

v

—

v

—

v

Download cable (4)

MAX II device or microprocessor

and flash device

PPA

Arria GX Device Handbook, Volume 1

3–6

Chapter 3: Configuration and Testing

Configuration

Table 3–4. Arria GX Configuration Features (Part 2 of 2)

Configuration Scheme

Configuration Method

Download cable (4)

Decompression

Remote System Upgrade

—

JTAG

MAX II device or microprocessor

and flash device

Notes for Table 3–4:

(1) In these modes, the host system must send a DCLKthat is 4× the data rate.

(2) The enhanced configuration device decompression feature is available, while the Arria GX decompression feature is not available.

(3) Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported.

(4) The supported download cables include the Altera USB-Blaster universal serial bus (USB) port download cable, MasterBlaster^™serial/USB

communications cable, ByteBlaster II parallel port download cable, ByteBlasterMV parallel port download cable, and the EthernetBlaster

download cable.

Device Configuration Data Decompression

Arria GX FPGAs support decompression of configuration data, which saves

configuration memory space and time. This feature allows you to store compressed

configuration data in configuration devices or other memory and transmit this

compressed bitstream to Arria GX FPGAs. During configuration, the Arria GX FPGA

decompresses the bitstream in real time and programs its SRAM cells. Arria GX

FPGAs support decompression in the FPP (when using a MAX II device or

microprocessor and flash memory), AS, and PS configuration schemes.

Decompression is not supported in the PPA configuration scheme nor in JTAG-based

configuration.

Remote System Upgrades

Shortened design cycles, evolving standards, and system deployments in remote

locations are difficult challenges faced by system designers. Arria GX devices can help

effectively deal with these challenges with their inherent re programmability and

dedicated circuitry to perform remote system updates. Remote system updates help

deliver feature enhancements and bug fixes without costly recalls, reduce time to

market, and extend product life.

Arria GX FPGAs feature dedicated remote system upgrade circuitry to facilitate

remote system updates. Soft logic (Nios^®processor or user logic) implemented in the

Arria GX device can download a new configuration image from a remote location,

store it in configuration memory, and direct the dedicated remote system upgrade

circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error

detection during and after the configuration process, recovers from any error

condition by reverting back to a safe configuration image, and provides error status

information. This dedicated remote system upgrade circuitry avoids system

downtime and is the critical component for successful remote system upgrades.

Remote system configuration is supported in the following Arria GX configuration

schemes: FPP, AS, PS, and PPA. You can also implement remote system configuration

in conjunction with Arria GX features such as real-time decompression of

configuration data for efficient field upgrades.

f

For more information about remote configuration in Arria GX devices, refer to the

Remote System Upgrades with Arria GX Devices chapter.

Arria GX Device Handbook, Volume 1

Chapter 3: Configuration and Testing

3–7

Configuration

Configuring Arria GX FPGAs with JRunner

The JRunner software driver configures Altera FPGAs, including Arria GX FPGAs,

through the ByteBlaster^™II or ByteBlasterMV cables in JTAG mode. The

programming input file supported is in Raw Binary File (.rbf) format. JRunner also

requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner

is targeted for embedded JTAG configuration. The source code is developed for the

Windows NT operating system (OS), but can be customized to run on other platforms.

f

For more information about the JRunner software driver, refer to the AN414: JRunner

Software Driver: An Embedded Solution for PLD JTAG Configuration and the source files

on the Altera website.

Programming Serial Configuration Devices with SRunner

You can program a serial configuration device in-system by an external

microprocessor using SRunner^TM. SRunner is a software driver developed for

embedded serial configuration device programming that can be easily customized to

fit into different embedded systems. SRunner software driver reads a raw

programming data file (.rpd) and writes to serial configuration devices. The serial

configuration device programming time using SRunner software driver is comparable

to the programming time when using the Quartus II software.

f

For more information about SRunner, refer to the AN418: SRunner: An Embedded

Solution for Serial Configuration Device Programming and the source code on the Altera

website.

For more information about programming serial configuration devices, refer to the

Serial Configuration Devices (EPCS1, EPCS4, EPCS64, and EPCS128) Data Sheet in the

Configuration Handbook.

Configuring Arria GX FPGAs with the MicroBlaster Driver

The MicroBlaster^™software driver supports a raw binary file (RBF) programming

input file and is ideal for embedded FPP or PS configuration. The source code is

developed for the Windows NT operating system, although it can be customized to

run on other operating systems.

f

For more information about the MicroBlaster software driver, refer to the Configuring

the MicroBlaster Fast Passive Parallel Software Driver White Paper or the AN423:

Configuring the MicroBlaster Passive Serial Software Driver.

PLL Reconfiguration

The phase-locked loops (PLLs) in the Arria GX device family support reconfiguration

of their multiply, divide, VCO-phase selection, and bandwidth selection settings

without reconfiguring the entire device. You can use either serial data from the logic

array or regular I/O pins to program the PLL’s counter settings in a serial chain. This

option provides considerable flexibility for frequency synthesis, allowing real-time

variation of the PLL frequency and delay. The rest of the device is functional while

reconfiguring the PLL.

Arria GX Device Handbook, Volume 1

3–8

Chapter 3: Configuration and Testing

Automated Single Event Upset (SEU) Detection

f

For more information about Arria GX PLLs, refer to the PLLs in Arria GX Devices

chapter.

Automated Single Event Upset (SEU) Detection

Arria GX devices offer on-chip circuitry for automated checking of single event upset

(SEU) detection. Some applications that require the device to operate error free at high

elevations or in close proximity to Earth’s North or South Pole requires periodic

checks to ensure continued data integrity. The error detection cyclic redundancy

check (CRC) feature controlled by the Device and Pin Options dialog box in the

Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of

the best options for mitigating SEU.

You can implement the error detection CRC feature with existing circuitry in Arria GX

devices, eliminating the need for external logic. Arria GX devices compute CRC

during configuration. The Arria GX device checks the computed-CRC against an

automatically computed CRC during normal operation. The CRC_ERRORpin reports

a soft error when configuration SRAM data is corrupted, triggering device

reconfiguration.

Custom-Built Circuitry

Dedicated circuitry is built into Arria GX devices to automatically perform error

detection. This circuitry constantly checks for errors in the configuration SRAM cells

while the device is in user mode. You can monitor one external pin for the error and

use it to trigger a reconfiguration cycle. You can select the desired time between

checks by adjusting a built-in clock divider.

Software Interface

Beginning with version 7.1 of the Quartus II software, you can turn on the automated

error detection CRC feature in the Device and Pin Options dialog box. This dialog

box allows you to enable the feature and set the internal frequency of the CRC

between 400 kHz to 50 MHz. This controls the rate that the CRC circuitry verifies the

internal configuration SRAM bits in the Arria GX FPGA.

f

For more information about CRC, refer to AN 357: Error Detection Using CRC in Altera

FPGAs.

Arria GX Device Handbook, Volume 1

Chapter 3: Configuration and Testing

3–9

Document Revision History

Table 3–5 lists the revision history for this chapter.

Table 3–5. Document Revision History

Date and Document Version

Changes Made

■ Document template update.

■ Minor text edits.

Summary of Changes

December 2009, v2.0

—

May 2009

v1.4

■ Removed “Temperature Sensing

Diode” section.

■ Updated Table 3–1 and Table 3–4.

May 2008

v1.3

Updated note in “Introduction”

section.

Minor text edits.

—

August 2007

v1.2

Added the “Referenced Documents”

section.

June 2007

v1.1

Deleted Signal Tap II information

from Table 3–1.

—

May 2007

v1.0

Initial Release

Arria GX Device Handbook, Volume 1

3–10

Chapter 3: Configuration and Testing

Document Revision History

Arria GX Device Handbook, Volume 1

4. DC and Switching Characteristics

AGX51004-2.0

Operating Conditions

Arria^®GX devices are offered in both commercial and industrial grades. Both

commercial and industrial devices are offered in –6 speed grade only.

This chapter contains the following sections:

■

“Operating Conditions”

“Power Consumption” on page 4–25

“I/O Timing Model” on page 4–26

“Typical Design Performance” on page 4–32

“Block Performance” on page 4–84

“IOE Programmable Delay” on page 4–86

“Maximum Input and Output Clock Toggle Rate” on page 4–87

“Duty Cycle Distortion” on page 4–95

“High-Speed I/O Specifications” on page 4–100

“PLL Timing Specifications” on page 4–103

“External Memory Interface Specifications” on page 4–105

“JTAG Timing Specifications” on page 4–106

Table 4–1 through Table 4–42 on page 4–25 provide information on absolute

maximum ratings, recommended operating conditions, DC electrical characteristics,

and other specifications for Arria GX devices.

Absolute Maximum Ratings

Table 4–1 contains the absolute maximum ratings for the Arria GX device family.

Table 4–1. Arria GX Device Absolute Maximum Ratings

Symbol Parameter

Supply voltage

(Note 1), (2), (3) (Part 1 of 2)

Conditions

Minimum

–0.5

Maximum

1.8

Units

V

V_CCINT

V_CCIO

V_CCPD

V_I

With respect to ground

Supply voltage

With respect to ground

–0.5

4.6

V

Supply voltage

With respect to ground

–0.5

4.6

V

DC input voltage (4)

DC output current, per pin

Storage temperature

—

–0.5

4.6

V

I_OUT

–25

40

mA

C

T_STG

No bias

–65

150

Arria GX Device Handbook, Volume 1

4–2

Chapter 4: DC and Switching Characteristics

Operating Conditions

Table 4–1. Arria GX Device Absolute Maximum Ratings

(Note 1), (2), (3) (Part 2 of 2)

Symbol

Parameter

Conditions

Minimum

Maximum

Units

T_J

Junction temperature

BGA packages under bias

–55

125

C

Notes to Table 4–1:

(1) For more information about operating requirements for Altera^®devices, refer to the Arria GX Device Family Data Sheet chapter.

(2) Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum

ratings for extended periods of time may have adverse affects on the device.

(3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.

(4) During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle. The DC case is equivalent to

100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.

Table 4–2. Maximum Duty Cycles in Voltage Transitions

(Note 1)

Symbol

V_I

Parameter

Condition

Maximum Duty Cycles (%)

V_I= 4.0 V

V_I= 4.1 V

V_I= 4.2 V

V_I= 4.3 V

V_I= 4.4 V

V_I= 4.5 V

100

90

50

30

17

10

Maximum duty cycles in

voltage transitions

Note to Table 4–2:

(1) During transition, the inputs may overshoot to the voltages shown based on the input duty cycle. The DC case is

equivalent to 100% duty cycle.

Recommended Operating Conditions

Table 4–3 lists the recommended operating conditions for the Arria GX device family.

Table 4–3. Arria GX Device Recommended Operating Conditions (Part 1 of 2) (Note 1) (Part 1 of 2)

Symbol

V_CCINT

Parameter

Conditions

Minimum

Maximum

Units

Supply voltage for internal

logic and input buffers

Rise time  100 ms (3)

1.15

1.25

V

Supply voltage for output

buffers, 3.3-V operation

Rise time  100 ms (3), (6)

Rise time  100 ms (3)

3.135

(3.00)

3.465

(3.60)

V

Supply voltage for output

buffers, 2.5-V operation

2.375

2.625

Supply voltage for output

buffers, 1.8-V operation

1.71

1.89

V_CCIO

Supply voltage for output

buffers, 1.5-V operation

1.425

1.15

1.575

1.25

Supply voltage for output

buffers, 1.2-V operation

Supply voltage for pre-drivers 100 s  rise time  100 ms (4)

as well as configuration and

3.135

3.465

V_CCPD

JTAG I/O buffers.

Input voltage

(refer to Table 4–2)

(2), (5)

–0.5

0

4.0

V

V_I

V_O

Output voltage

—

V_CCIO

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–3

Operating Conditions

Table 4–3. Arria GX Device Recommended Operating Conditions (Part 2 of 2)

(Note 1) (Part 2 of 2)

Symbol

Parameter

Conditions

For commercial use

Minimum

Maximum

Units

0

85

C

T_J

Operating junction temperature

For industrial use

–40

100

Notes to Table 4–3:

(1) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.

(2) During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle. The DC case is equivalent to

100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.

(3) Maximum V_CCrise time is 100 ms, and V_CCmust rise monotonically from ground to V_CC

.

(4) V_CCPDmust ramp-up from 0 V to 3.3 V within 100 s to 100 ms. If V_CCPDis not ramped up within this specified time, the Arria GX device will

not configure successfully. If the system does not allow for a V_CCPDramp-up time of 100 ms or less, hold nCONFIGlow until all power supplies

are reliable.

(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, can be driven before V_CCINT, V_CCPD, and V_CCIOare powered.

(6) V_CCIOmaximum and minimum conditions for PCI and PCI-X are shown in parentheses.

Transceiver Block Characteristics

Table 4–4 through Table 4–6 on page 4–4 contain transceiver block specifications.

Table 4–4. Arria GX Transceiver Block Absolute Maximum Ratings

(Note 1)

Symbol

V_CCA

Parameter

Conditions

Minimum

–0.5

Maximum

4.6

Units

Transceiver block supply voltage

Commercial and industrial

V

V_CCP

–0.5

1.8

V_CCR

–0.5

1.8

V_{CCT_B}

V_{CCL_B}

V_{CCH_B}

–0.5

1.8

–0.5

1.8

–0.5

2.4

Note to Table 4–4:

(1) The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is not violated.

Table 4–5. Arria GX Transceiver Block Operating Conditions

Symbol

V_CCA

Parameter

Conditions

Minimum Typical Maximum Units

Transceiver block supply voltage

Commercial and industrial

3.135

1.15

3.3

1.2

1.5

2K

3.465

1.25

V



V_CCP

V_CCR

1.15

1.25

V_{CCT_B}

V_{CCL_B}

1.15

1.25

1.15

1.25

1.15

1.25

V_{CCH_B}

Transceiver block supply voltage

Commercial and industrial

1.425

2K - 1%

1.575

2K +1%

R_REFB(1)

Reference resistor

Commercial and industrial

Note to Table 4–5:

(1) The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin.

Arria GX Device Handbook, Volume 1

4–4

Chapter 4: DC and Switching Characteristics

Operating Conditions

Table 4–6. Arria GX Transceiver Block AC Specification (Part 1 of 3)

–6 Speed Grade Commercial and

Industrial

Symbol / Description

Conditions

Units

Min

Typ

Max

Reference clock

Input reference clock frequency

Absolute V_{M A X}for a REFCLKPin

Absolute V_MINfor a REFCLKPin

Rise/Fall time

—

50

—

0.2

—

622.08

3.3

MHz

V

–0.3

—

V

—

UI

Duty cycle

45

55

%

Peak to peak differential input voltage V_ID

(diff p-p)

200

2000

mV

Spread spectrum clocking (1)

On-chip termination resistors

V_ICM(AC coupled)

0 to –0.5%

30

—

33

kHz



—

115 20%

1200 5%

—

mV

V

V_ICM(DC coupled) (2)

PCI Express

(PIPE) mode

0.25

0.55

—

2000 +/-1%



RREFB

Transceiver Clocks

Calibration block clock frequency

—

10

30

—

125

—

MHz

ns

Calibration block minimum power-down

pulse width

fixedclkclock frequency (3)

reconfigclock frequency

—

125 10%

—

MHz

SDI mode

2.5

50

—

Transceiver block minimum power-down

pulse width

—

100

—

ns

Receiver

Data rate

—

600

—

3125

2.0

Mbps

Absolute V_MAXfor a receiver pin (4)

Absolute V_MINfor a receiver pin

—

V

–0.4

—

Maximum peak-to-peak differential input

voltage V_ID(diff p-p)

Vicm = 0.85 V

3.3

Minimum peak-to-peak differential input

voltage V_ID(diff p-p)

DC Gain = 3 dB

—

160

—

mV

On-chip termination resistors

100 15%



Vicm = 0.85 V

setting

850 10% 850 10% 850 10%

mV

V_ICM(15)

Vicm = 1.2 V

setting

1200

10%

1200

10%

1200

10%

mV

BW = Low

BW = Med

BW = High

—

30

40

50

—

Bandwidth at 3.125 Gbps

MHz

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–5

Operating Conditions

Table 4–6. Arria GX Transceiver Block AC Specification (Part 2 of 3)

–6 Speed Grade Commercial and

Industrial

Symbol / Description

Conditions

Units

Min

—

Typ

35

50

60

Max

—

Bandwidth at 2.5 Gbps

BW = Low

BW = Med

BW = High

—

MHz

—

Return loss differential mode

Return loss common mode

Programmable PPM detector (5)

50 MHz to 1.25

GHz

(PCI Express)

–10

–6

dB

100 MHz to 2.5

GHz (XAUI)

50 MHz to 1.25

GHz

(PCI Express)

dB

100 MHz to 2.5

GHz (XAUI)

—

62.5, 100, 125, 200, 250, 300, 500,

1000

PPM

Run length (6)

—

80

UI

dB

mV

us

ns

Programmable equalization

Signal detect/loss threshold (7)

CDR LTR TIme (8), (9)

CDR Minimum T1b (9), (10)

LTD lock time (9), (11)

—

65

—

15

0

—

5

175

75

—

100

4000

Data lock time from rx_freqlocked(9),

(12)

—

4

us

dB

Programmable DC gain

0, 3, 6

Transmitter Buffer

Output Common Mode voltage (V_ocm

On-chip termination resistors

)

—

580 10%

108 10%

mV



50 MHz to 1.25

dB

GHz (PCI Express)

–10

312 MHz to 625

MHz (XAUI)

Return loss differential mode

Return loss common mode

625 MHz to

3.125GHz (XAUI)

–10

–6

dB

------------------------------------

decade slope

50 MHz to 1.25

GHz (PCI Express)

dB

Rise time

—

35

—

65

ps

Fall time

—

V_OD= 800 mV

—

Intra differential pair skew

15

Intra-transceiver block skew (×4) (13)

100

Arria GX Device Handbook, Volume 1

4–6

Chapter 4: DC and Switching Characteristics

Operating Conditions

Table 4–6. Arria GX Transceiver Block AC Specification (Part 3 of 3)

–6 Speed Grade Commercial and

Industrial

Symbol / Description

Conditions

Units

Min

Typ

Max

Transmitter PLL

VCO frequency range

—

500

—

3

1562.5

—

MHz

BW = Low

BW = Med

BW = High

BW = Low

BW = Med

BW = High

Bandwidth at 3.125 Gbps

5

—

9

—

1

—

Bandwidth at 2.5 Gbps

2

—

MHz

us

4

—

TX PLL lock time from gxb_powerdown

de-assertion (9), (14)

—

100

PCS

Interface speed per mode

Digital Reset Pulse Width

Notes to Table 4–6:

—

25

—

156.25

MHz

—

Minimum is 2 parallel clock cycles

(1) Spread spectrum clocking is allowed only in PCI Express (PIPE) mode if the upstream transmitter and the receiver share the same clock source.

(2) The reference clock DC coupling option is only available in PCI Express (PIPE) mode for the HCSL I/O standard.

(3) The fixedclkis used in PIPE mode receiver detect circuitry.

(4) The device cannot tolerate prolonged operation at this absolute maximum.

(5) The rate matcher supports only up to 300 PPM for PIPE mode and 100 PPM for GIGE mode.

(6) This parameter is measured by embedding the run length data in a PRBS sequence.

(7) Signal detect threshold detector circuitry is available only in PCI Express (PIPE mode).

(8) Time taken for rx_pll_lockedto go high from rx_analogresetdeassertion. Refer to Figure 4–1.

(9) For lock times specific to the protocols, refer to protocol characterization documents.

(10) Time for which the CDR needs to stay in LTR mode after rx_pll_lockedis asserted and before rx_locktodatais asserted in manual

mode. Refer to Figure 4–1.

(11) Time taken to recover valid data from GXB after the rx_locktodatasignal is asserted in manual mode. Measurement results are based on

PRBS31, for native data rates only. Refer to Figure 4–1.

(12) Time taken to recover valid data from GXB after the rx_freqlockedsignal goes high in automatic mode. Measurement results are based

on PRBS31, for native data rates only. Refer to Figure 4–2.

(13) This is applicable only to PCI Express (PIPE) ×4 and XAUI ×4 mode.

(14) Time taken to lock TX PLLfrom gxb_powerdowndeassertion.

(15) The 1.2 V RX VICM settings is intended for DC-coupled LVDS links.

Figure 4–1 shows the lock time parameters in manual mode. Figure 4–2 shows the

lock time parameters in automatic mode.

1

LTD = Lock to data

LTR = Lock to reference clock

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–7

Operating Conditions

Figure 4–1. Lock Time Parameters for Manual Mode

r x_analogreset

CDR status

LTR

LTD

r x_pl

l_lock

ed

r x_locktodata

Invalid Data

Valid data

r x_dataout

CDR LTR Time

LTD lock time

CDR Minimum T1b

Figure 4–2. Lock Time Parameters for Automatic Mode

LTR

LTD

CDR status

r x_freqlocked

Valid

data

Invalid

data

r x_dataout

Data lock time from rx_freqlocked

Arria GX Device Handbook, Volume 1

4–8

Chapter 4: DC and Switching Characteristics

Operating Conditions

Figure 4–3 and Figure 4–4 show differential receiver input and transmitter output

waveforms, respectively.

Figure 4–3. Receiver Input Waveform

Single-Ended Waveform

Positive Channel (p)

V

ID

Negative Channel (n)

Ground

V

CM

Differential Waveform

V

(diff peak-peak) = 2 x V (single-ended)

ID

V

ID

p − n = 0 V

V

ID

Figure 4–4. Transmitter Output Waveform

Single-Ended Waveform

Positive Channel (p)

V

OD

Negative Channel (n)

Ground

V

CM

Differential Waveform

V

(diff peak-peak) = 2 x V

(single-ended)

OD

V

OD

p − n = 0 V

V

OD

Table 4–7 lists the Arria GX transceiver block AC specification.

Table 4–7. Arria GX Transceiver Block AC Specification (Note 1), (2), (3) (Part 1 of 4)

–6 Speed Grade

Commercial & Units

Industrial

Description

Condition

XAUI Transmit Jitter Generation (4)

REFCLK= 156.25 MHz

Pattern = CJPAT

V_OD= 1200 mV

No Pre-emphasis

Total jitter at 3.125 Gbps

0.3

UI

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–9

Operating Conditions

Table 4–7. Arria GX Transceiver Block AC Specification (Note 1), (2), (3) (Part 2 of 4)

–6 Speed Grade

Commercial & Units

Industrial

Description

Condition

REFCLK= 156.25 MHz

Pattern = CJPAT

V_OD= 1200 mV

No Pre-emphasis

Deterministic jitter at 3.125 Gbps

0.17

UI

XAUI Receiver Jitter Tolerance (4)

Pattern = CJPAT

Total jitter

No Equalization

> 0.65

> 0.37

UI

DC Gain = 3 dB

Pattern = CJPAT

Deterministic jitter

No Equalization

DC Gain = 3 dB

Peak-to-peak jitter

Jitter frequency = 22.1 KHz

Jitter frequency = 1.875 MHz

Jitter frequency = 20 MHz

> 8.5

> 0.1

UI

PCI Express (PIPE) Transmitter Jitter Generation (5)

Compliance Pattern; V_OD= 800 mV;

Pre-emphasis = 49%

PCI Express (PIPE) Receiver Jitter Tolerance (5)

Compliance Pattern;

DC Gain = 3 db

Gigabit Ethernet (GIGE) Transmitter Jitter Generation (7)

Total Transmitter Jitter Generation

< 0.25

> 0.6

UI p-p

Total Receiver Jitter Tolerance

CRPAT: V_OD= 800 mV;

Total Transmitter Jitter Generation (TJ)

< 0.279

< 0.14

UI p-p

Pre-emphasis = 0%

CRPAT; V_OD= 800 mV;

Pre-emphasis = 0%

Deterministic Transmitter Jitter

Generation (DJ)

Gigabit Ethernet (GIGE) Receiver Jitter Tolerance

CJPAT Compliance Pattern;

Total Jitter Tolerance

> 0.66

> 0.4

UI p-p

DC Gain = 0 dB

CJPAT Compliance Pattern;

DC Gain = 0 dB

Deterministic Jitter Tolerance

Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Transmitter Jitter Generation (6)

CJPAT Compliance Pattern;

Total Transmitter Jitter Generation (TJ)

V_OD= 800 mV;

< 0.35

< 0.17

UI p-p

Pre-emphasis = 0%

CJPAT Compliance Pattern;

V_OD= 800 mV;

Deterministic Transmitter Jitter

Generation (DJ)

Pre-emphasis = 0%

Arria GX Device Handbook, Volume 1

4–10

Chapter 4: DC and Switching Characteristics

Operating Conditions

Table 4–7. Arria GX Transceiver Block AC Specification (Note 1), (2), (3) (Part 3 of 4)

Description Condition

–6 Speed Grade

Commercial & Units

Industrial

Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Receiver Jitter Tolerance (6)

CJPAT Compliance Pattern;

Total Jitter Tolerance

DC Gain = 0 dB

> 0.65

> 0.55

> 0.37

UI p-p

CJPAT Compliance Pattern;

DC Gain = 0 dB

Combined Deterministic and Random

Jitter Tolerance (J_DR)

CJPAT Compliance Pattern;

DC Gain = 0 dB

Deterministic Jitter Tolerance (J_D)

Jitter Frequency = 22.1 KHz

Jitter Frequency = 200 KHz

Jitter Frequency = 1.875 MHz

Jitter Frequency = 20 MHz

> 8.5

> 1.0

> 0.1

UI p-p

Sinusoidal Jitter Tolerance

SDI Transmitter Jitter Generation (8)

Data Rate = 1.485 Gbps (HD)

REFCLK= 74.25 MHz

Pattern = Color Bar

Vod = 800 mV

No Pre-emphasis

0.2

0.3

UIv

UI

Low-Frequency Roll-Off = 100 KHz

Alignment Jitter (peak-to-peak)

Data Rate = 2.97 Gbps (3G)

REFCLK= 148.5 MHz

Pattern = Color Bar

Vod = 800 mV

No Pre-emphasis

Low-Frequency Roll-Off = 100 KHz

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–11

Operating Conditions

Table 4–7. Arria GX Transceiver Block AC Specification (Note 1), (2), (3) (Part 4 of 4)

–6 Speed Grade

Commercial & Units

Industrial

Description

Condition

SDI Receiver Jitter Tolerance (8)

Jitter Frequency = 15 KHz

Data Rate = 2.97 Gbps (3G)

REFCLK= 148.5 MHz

Pattern = Single Line

Scramble Color Bar

No Equalization

> 2

UI

DC Gain = 0 dB

Jitter Frequency = 100 KHz

Data Rate = 2.97 Gbps (3G)

REFCLK= 148.5 MHz

Pattern = Single Line Scramble Color Bar

No Equalization

Sinusoidal Jitter Tolerance

(peak-to-peak)

> 0.3

DC Gain = 0 dB

Jitter Frequency = 148.5 MHz

Data Rate = 2.97 Gbps (3G)

REFCLK = 148.5 MHz

Pattern = Single Line

Scramble Color Bar

No Equalization

DC Gain = 0 dB

Jitter Frequency = 20 KHz

Data Rate = 1.485 Gbps (HD)

REFCLK= 74.25 MHz

Pattern = 75% Color Bar

No Equalization

> 1

UI

DC Gain = 0 dB

Sinusoidal Jitter Tolerance

(peak-to-peak)

Jitter Frequency = 100 KHz

Data Rate = 1.485 Gbps (HD)

REFCLK= 74.25 MHz

Pattern = 75% Color Bar

No Equalization

> 0.2

DC Gain = 0 dB

Notes to Table 4–7:

(1) Dedicated REFCLKpins were used to drive the input reference clocks.

(2) Jitter numbers specified are valid for the stated conditions only.

(3) Refer to the protocol characterization documents for detailed information.

(4) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.

(5) The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.

(6) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.

(7) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.

(8) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M specifications.

Arria GX Device Handbook, Volume 1

4–12

Chapter 4: DC and Switching Characteristics

Operating Conditions

Table 4–8 and Table 4–9 list the transmitter and receiver PCS latency for each mode,

respectively.

Table 4–8. PCS Latency (Note 1)

Transmitter PCS Latency

Byte TX State 8B/10B

Functional Mode

Configuration

TX Phase

Comp FIFO Serializer Machine Encoder

TX PIPE

Sum (2)

4–5

XAUI

—

1

2–3

3–4

1

0.5

—

0.5

1

×1, ×4, ×8

8-bit channel width

6–7

PIPE

×1, ×4, ×8

16-bit channel width

1

3–4

2–3

1

—

0.5

1

6–7

4–5

GIGE

—

1.25 Gbps, 2.5 Gbps,

3.125 Gbps

Serial RapidIO

0.5

HD10-bit channel width

—

2–3

1

—

1

4–5

SDI

HD, 3G 20-bit channel width

8-bit/10-bit channel width

16-bit/20-bit channel width

0.5

1

BASIC Single

Width

0.5

Notes to Table 4–8:

(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.

(2) The total latency number is rounded off in the Sum column.

Table 4–9. PCS Latency (Part 1 of 2) (Part 1 of 2)

Receiver PCS Latency

XAUI

PIPE

GIGE

—

2–2.5 2–2.5 5.5–6.5 0.5

1

1–2

2–3

—

1

14–17

21–25

×1, ×4

4–5

—

11–13

1

—

8-bit channel width

×1, ×4

2–2.5

4–5

2–2.5

5

—

5.5–6.5 0.5

—

1

2–3

1–2

1

13–16

19–23

6–7

16-bit channel width

—

11–13

—

1

—

Serial

RapidIO

1.25 Gbps, 2.5 Gbps,

3.125 Gbps

0.5

1

HD 10-bit channel width

—

9–10

6–7

SDI

HD, 3G 20-bit channel

width

2.5

—

0.5

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–13

Operating Conditions

Table 4–9. PCS Latency (Part 2 of 2) (Part 2 of 2)

Receiver PCS Latency

8/10-bit channel width;

4–5

—

11–13

—

1

—

1

1–2

1

19–23

with Rate Matcher

8/10-bit channel width;

without Rate Matcher

4–5

—

8–10

11–14

6–7

BASIC

Single

Width

16/20-bit channel width;

with Rate Matcher

2–2.5

5.5–6.5 0.5

0.5

16/20-bit channel width;

without Rate Matcher

—

Notes to Table 4–9:

(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.

(2) The total latency number is rounded off in the Sum column.

(3) The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set gap allowed by the

protocol, actual PPM difference between the reference clocks, and so forth.

Table 4–10 through Table 4–13 show the typical V_ODfor data rates from 600 Mbps to

3.125 Gbps. The specification is for measurement at the package ball.

Table 4–10. Typical V_ODSetting, TX Term = 100 

V_ODSetting (mV)

V_ccHTX = 1.5 V

400

600

800

1000

1200

V

_ODTypical (mV)

430

625

830

1020

1200

Table 4–11. Typical V_ODSetting, TX Term = 100 

V_ODSetting (mV)

V_ccHTX = 1.2 V

320

480

640

800

960

V

_ODTypical (mV)

344

500

664

816

960

Table 4–12. Typical Pre-Emphasis (First Post-Tap), (Note 1)

V_ccHTX = 1.5 V First Post Tap Pre-Emphasis Level

_ODSetting (mV)

V

1

2

3

4

5

TX Term = 100 

112%

400

24%

—

62%

31%

20%

184%

—

600

800

56%

86%

53%

122%

73%

—

35%

Arria GX Device Handbook, Volume 1

4–14

Chapter 4: DC and Switching Characteristics

Operating Conditions

Table 4–12. Typical Pre-Emphasis (First Post-Tap), (Note 1)

V_ccHTX = 1.5 V First Post Tap Pre-Emphasis Level

_ODSetting (mV)

1000

V

1

2

3

4

5

—

23%

17%

36%

25%

49%

35%

1200

Note to Table 4–12:

(1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.

Table 4–13. Typical Pre-Emphasis (First Post-Tap), (Note 1)

V_ccHTX = 1.2 V

_ODSetting (mV)

First Post Tap Pre-Emphasis Level

V

1

2

3

4

5

TX Term = 100 

320

24%

—

61%

31%

20%

—

114%

55%

35%

23%

18%

—

480

86%

54%

36%

25%

121%

72%

49%

35%

640

—

800

—

960

—

Note to Table 4–13:

(1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.

DC Electrical Characteristics

Table 4–14 lists the Arria GX device family DC electrical characteristics.

Table 4–14. Arria GX Device DC Operating Conditions (Part 1 of 2)

Symbol Parameter Conditions

(Note 1)

Device

Min

–10

Typ

—

Max

10

Units

A

I_I

Input pin leakage current V_I= V_CCIOmaxto 0 V (2)

All

Tri-stated I/O pin leakage V_O= V_CCIOmaxto 0 V (2)

current

All

—

10

A

I_OZ

V_I= ground, no load, no

toggling inputs

EP1AGX20/35

EP1AGX50/60

EP1AGX90

—

0.30

0.50

0.62

2.7

(3)

A

V_CCINTsupply current

(standby)

I_CCINT0

I_CCPD0

I_CCI00

T_J= 25 °C

A

V_I= ground, no load, no

toggling inputs

EP1AGX20/35

EP1AGX50/60

EP1AGX90

mA

V_CCPDsupply current

(standby)

3.6

T_J= 25 °C,

4.3

V

_CCPD= 3.3V

V_I= ground, no load, no

toggling inputs

EP1AGX20/35

EP1AGX50/60

EP1AGX90

—

4.0

(3)

mA

V_CCIOsupply current

(standby)

T_J= 25 °C

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–15

Operating Conditions

Table 4–14. Arria GX Device DC Operating Conditions (Part 2 of 2)

(Note 1)

Symbol

Parameter

Conditions

V_i= 0, V_CCIO= 3.3 V

V_i= 0, V_CCIO= 2.5 V

Device

—

Min

10

15

30

40

50

Typ

25

35

50

75

90

Max

50

Units

k

—

70

Value of I/O pin pull-up

resistor before and during V_i= 0, V_CCIO= 1.8 V

configuration

—

100

150

170

V_i= 0, V_CCIO= 1.5 V

—

R_CONF(4)

V_i= 0, V_CCIO= 1.2 V

—

Recommended value of

I/O pin external pull-down

resistor before and during

—

1

2

k

configuration

Notes to Table 4–14:

(1) Typical values are for T_A= 25 °C, V_CCINT= 1.2 V, and V_CCIO= 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V.

(2) This value is specified for normal device operation. The value may vary during power-up. This applies for all V_CCIOsettings (3.3, 2.5, 1.8, 1.5,

and 1.2 V).

(3) Maximum values depend on the actual TJ and design utilization. For maximum values, refer to the Excel-based PowerPlay Early Power Estimator

(available at PowerPlay Early Power Estimators (EPE) and Power Analyzer) or the Quartus^®II PowerPlay Power Analyzer feature for maximum

values. For more information, refer to “Power Consumption” on page 4–25.

(4) Pin pull-up resistance values will be lower if an external source drives the pin higher than V_CCIO

.

I/O Standard Specifications

Table 4–15 through Table 4–38 show the Arria GX device family I/O standard

specifications.

Table 4–15. LVTTL Specifications

Symbol

_CCIO(1)

Parameter

Conditions

Minimum

3.135

1.7

Maximum

3.465

4.0

Units

V

Output supply voltage

High-level input voltage

Low-level input voltage

—

V

V_IH

V_IL

–0.3

2.4

0.8

V_OH

V_OL

High-level output voltage I_OH= –4 mA (2)

Low-level output voltage I_OL= 4 mA (2)

—

0.45

Notes to Table 4–15:

(1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B.

(2) This specification is supported across all the programmable drive strength settings available for this I/O standard.

Table 4–16. LVCMOS Specifications

Symbol

_CCIO(1)

Parameter

Conditions

Minimum

3.135

1.7

Maximum

3.465

4.0

Units

V

Output supply voltage

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

—

V

V_IH

V_IL

—

–0.3

0.8

V_OH

V_OL

V_CCIO= 3.0, I_OH= –0.1 mA (2)

V_CCIO= 3.0, I_OL= 0.1 mA (2)

V_CCIO– 0.2

—

0.2

Notes to Table 4–16:

(1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B.

(2) This specification is supported across all the programmable drive strength available for this I/O standard.

Arria GX Device Handbook, Volume 1

4–16

Chapter 4: DC and Switching Characteristics

Operating Conditions

Table 4–17. 2.5-V I/O Specifications

Symbol

_CCIO(1)

Parameter

Output supply voltage

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Conditions

Minimum

2.375

1.7

Maximum

2.625

4.0

Units

V

—

V

V_IH

V_IL

—

–0.3

2.0

0.7

V_OH

V_OL

I_OH= –1 mA (2)

I_OL= 1 mA (2)

—

0.4

Notes to Table 4–17:

(1) The Arria GX device V_CCIOvoltage level support of 2.5 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard.

(2) This specification is supported across all the programmable drive settings available for this I/O standard.

Table 4–18. 1.8-V I/O Specifications

Symbol

_CCIO(1)

Parameter

Output supply voltage

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Conditions

Minimum

1.71

Maximum

1.89

Units

V

—

V

V_IH

V_IL

0.65 × V_CCIO

–0.3

2.25

—

0.35 × V_CCIO

—

V_OH

V_OL

I_OH= –2 mA (2)

I_OL= 2 mA (2)

V_CCIO– 0.45

—

0.45

Notes to Table 4–18:

(1) The Arria GX device V_CCIOvoltage level support of 1.8 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard.

(2) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in Arria GX Architecture

chapter.

Table 4–19. 1.5-V I/O Specifications

Symbol

_CCIO(1)

Parameter

Output supply voltage

Conditions

Minimum

1.425

Maximum

1.575

Units

V

—

V

V_IH

V_IL

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

0.65 V_CCIO

–0.3

V_CCIO+ 0.3

0.35 V_CCIO

—

V_OH

V_OL

I_OH= –2 mA (2)

I_OL= 2 mA (2)

0.75 V_CCIO

—

0.25 V_CCIO

Notes to Table 4–19:

(1) The Arria GX device V_CCIOvoltage level support of 1.5 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard.

(2) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX

Architecture chapter.

Figure 4–5 and Figure 4–6 show receiver input and transmitter output waveforms,

respectively, for all differential I/O standards (LVDS and LVPECL).

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–17

Operating Conditions

Figure 4–5. Receiver Input Waveforms for Differential I/O Standards

Single-Ended Waveform

Positive Channel (p) = V

IH

V

ID

Negative Channel (n) = V

Ground

IL

V

CM

Differential Waveform

V

ID

p − n = 0 V

V

ID

ID (Peak-to-Peak)

Figure 4–6. Transmitter Output Waveforms for Differential I/O Standards

Single-Ended Waveform

Positive Channel (p) = V

OH

V

OD

Negative Channel (n) = V

OL

V

CM

Ground

Differential Waveform

V

OD

p − n = 0 V

V

OD

Table 4–20. 2.5-V LVDS I/O Specifications

Symbol

V_CCIO

Parameter

Conditions

Minimum

Typical

Maximum Units

I/O supply voltage for left and right I/O

banks (1, 2, 5, and 6)

—

2.375

2.5

2.625

900

V

V_ID

Input differential voltage swing

(single-ended)

—

100

350

mV

V_ICM

V_OD

V_OCM

R_L

Input common mode voltage

—

200

250

1,250

—

1,800

450

mV

V

Output differential voltage (single-ended)

Output common mode voltage

R_L= 100 

1.125

—

1.375

Receiver differential input discrete

resistor (external to Arria GX devices)

—

90

100

110



Arria GX Device Handbook, Volume 1

4–18

Chapter 4: DC and Switching Characteristics

Operating Conditions

Table 4–21. 3.3-V LVDS I/O Specifications

Symbol

_CCIO(1)

Parameter

Conditions

Minimum

Typical Maximum Units

V

I/O supply voltage for top and bottom

PLL banks (9, 10, 11, and 12)

—

3.135

3.3

3.465

V

V_ID

Input differential voltage swing

(single-ended)

—

100

350

900

mV

V_ICM

V_OD

V_OCM

R_L

Input common mode voltage

—

200

250

840

90

1,250

—

1,800

710

mV



Output differential voltage (single-ended) R_L= 100 

Output common mode voltage

R_L= 100 

—

1,570

110

Receiver differential input discrete

resistor (external to Arria GX devices)

—

100

Note to Table 4–21:

(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V_CCINT, not V_CCIO. The PLL clock output/feedback

differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUTto 3.3 V.

Table 4–22. 3.3-V PCML Specifications

Symbol

Parameter

I/O supply voltage

Minimum

3.135

300

Typical

3.3

Maximum

3.465

Units

V

V_CCIO

V_ID

Input differential voltage swing

(single-ended)

—

600

mV

V_ICM

V_OD

Input common mode voltage

1.5

300

—

370

—

3.465

500

50

V

mV

V

Output differential voltage (single-ended)

Change in V_{O D}between high and low

Output common mode voltage

V_OD

V_OCM

2.5

—

2.85

—

3.3

50

V_OCM

V_T

Change in V_{O C M}between high and low

Output termination voltage

mV

V

—

V_{C CI O}

50

—

R₁

Output external pull-up resistors

45

55



R₂

45

50

55



Table 4–23. LVPECL Specifications

Parameter Conditions

V_CCIO(1)

Minimum

Typical

Maximum

Units Parameter

I/O supply voltage

—

3.135

300

1.0

3.3

3.465

1,000

2.5

V

mV

V

Input differential voltage swing

(single-ended)

V_ID

—

600

—

V_ICM

V_OD

Input common mode voltage

Output differential voltage

(single-ended)

R_L= 100 

525

—

970

mV

V_OCM

Output common mode voltage

R_L= 100 

1,650

90

—

2,250

110

mV

R_L

Receiver differential input resistor

—

100



Note to Table 4–23:

(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V_CCINT, not V_CCIO. The PLL clock output/feedback

differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUTto 3.3 V.

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–19

Operating Conditions

Table 4–24. 3.3-V PCI Specifications

Symbol

Parameter

Conditions

Minimum Typical

Maximum

3.6

Units

V_CCIO

V_IH

Output supply voltage

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

—

3.0

0.5 V_CCIO

–0.3

3.3

—

V

V_CCIO+ 0.5

0.3 V_CCIO

—

V_IL

V_OH

V_OL

I_OUT= –500 A 0.9 V_CCIO

I_OUT= 1,500 A

—

0.1 V_CCIO

Table 4–25. PCI-X Mode 1 Specifications

Symbol

Parameter

Output supply voltage

High-level input voltage

Low-level input voltage

Input pull-up voltage

Conditions

Minimum

3.0

Maximum

3.6

Units

V_CCIO

V_IH

—

V

—

0.5 V_CCIO

–0.3

V_CCIO+ 0.5

0.35 V_CCIO

—

V_IL

V_IPU

V_OH

V_OL

—

0.7 V_CCIO

0.9 V_CCIO

—

High-level output voltage

Low-level output voltage

I_OUT= –500 A

I_OUT= 1,500 A

—

0.1 V_CCIO

Table 4–26. SSTL-18 Class I Specifications

Symbol

V_CCIO

Parameter

Conditions

Minimum

1.71

Typical

1.8

0.9

V_REF

—

Maximum

1.89

Units

Output supply voltage

Reference voltage

—

V

V_REF

—

0.855

0.945

V_TT

Termination voltage

—

V_REF– 0.04

V_REF+ 0.125

—

V_REF+ 0.04

—

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

V_OH

High-level DC input voltage

Low-level DC input voltage

High-level AC input voltage

Low-level AC input voltage

High-level output voltage

Low-level output voltage

—

V_REF– 0.125

—

V_REF+ 0.25

—

V_REF– 0.25

—

I_OH= –6.7 mA (1)

I_OL= 6.7 mA (1)

V_TT+ 0.475

—

V_OL

—

V_TT– 0.475

Note to Table 4–26:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX

Architecture chapter.

Table 4–27. SSTL-18 Class II Specifications

Symbol

V_CCIO

Parameter

Output supply voltage

Reference voltage

Conditions

Minimum

1.71

Typical

1.8

0.9

V_REF

—

Maximum

1.89

Units

—

V

V_REF

0.855

0.945

V_TT

Termination voltage

V_REF– 0.04

V_REF+ 0.125

—

V_REF+ 0.04

—

V_IH(DC)

V_I_L(DC)

V_IH(AC)

V_IL(AC)

High-level DC input voltage

Low-level DC input voltage

High-level AC input voltage

Low-level AC input voltage

—

V_REF– 0.125

—

V_REF+ 0.25

—

V_REF– 0.25

Arria GX Device Handbook, Volume 1

4–20

Chapter 4: DC and Switching Characteristics

Operating Conditions

Table 4–27. SSTL-18 Class II Specifications

Symbol

V_OH

V_OL

Parameter

Conditions

Minimum

V_CCIO– 0.28

—

Typical

—

Maximum

—

Units

High-level output voltage

Low-level output voltage

I_OH= –13.4 mA (1)

I_OL= 13.4 mA (1)

V

—

0.28

Note to Table 4–27:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX

Architecture chapter.

Table 4–28. SSTL-18 Class I & II Differential Specifications

Symbol

V_CCIO

Parameter

Output supply voltage

Minimum

1.71

Typical

1.8

Maximum

1.89

Units

V

V_SWING(DC)

V_X(AC)

DC differential input voltage

0.25

—

AC differential input cross point

voltage

(V_CCIO/2) – 0.175

—

(V_CCIO/2) + 0.175

V

_SWING(AC)

AC differential input voltage

0.5

—

0.5 V_CCIO

200

—

V

V_ISO

Input clock signal offset voltage

V_ISO

Input clock signal offset voltage

variation

mV

V

_OX(AC)

AC differential cross point voltage

(V_CCIO/2) – 0.125

—

(V_CCIO/2) + 0.125

V

Table 4–29. SSTL-2 Class I Specifications

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

V_CCIO

V_TT

Output supply voltage

Termination voltage

—

2.375

V_REF– 0.04

1.188

2.5

V_REF

1.25

—

2.625

V_REF+ 0.04

1.313

V

V_REF

Reference voltage

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

V_OH

High-level DC input voltage

Low-level DC input voltage

High-level AC input voltage

Low-level AC input voltage

High-level output voltage

V_REF+ 0.18

–0.3

3.0

—

V_REF– 0.18

—

V_REF+ 0.35

—

V_REF– 0.35

I_OH= –8.1 mA

V_TT+ 0.57

—

(1)

V_OL

Low-level output voltage

I_OL= 8.1 mA (1)

—

V_TT– 0.57

V

Note to Table 4–29:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture

chapter.

Table 4–30. SSTL-2 Class II Specifications (Part 1 of 2)

Symbol

Parameter

Output supply voltage

Termination voltage

Reference voltage

Conditions

Minimum

2.375

Typical

2.5

Maximum

2.625

Units

V_CCIO

V_TT

—

V

V_REF– 0.04

1.188

V_REF

1.25

—

V_REF+ 0.04

1.313

V_REF

V_IH(DC)

High-level DC input

voltage

V_REF+ 0.18

V_CCIO+ 0.3

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–21

Operating Conditions

Table 4–30. SSTL-2 Class II Specifications (Part 2 of 2)

Symbol

V_IL(DC)

Parameter

Conditions

Minimum

Typical

Maximum

Units

Low-level DC input

voltage

—

–0.3

—

V_REF– 0.18

V

V_IH(AC)

V_IL(AC)

High-level AC input

voltage

—

V_REF+ 0.35

—

Low-level AC input

voltage

V_REF– 0.35

V_OH

High-level output voltage

Low-level output voltage

I_OH= –16.4 mA (1)

I_OL= 16.4 mA (1)

V_TT+ 0.76

—

V

V_OL

V_TT– 0.76

Note to Table 4–30:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture

chapter.

Table 4–31. SSTL-2 Class I & II Differential Specifications

Symbol Parameter

Output supply voltage

(Note 1)

Minimum

Typical

2.5

Maximum

Units

V

V_CCIO

2.375

2.625

V_SWING(DC)

V_X(AC)

V_SWING(AC)

V_ISO

DC differential input voltage

0.36

—

V

AC differential input cross point voltage

AC differential input voltage

(V_CCIO/2) – 0.2

—

(V_CCIO/2) + 0.2

V

0.7

—

V

Input clock signal offset voltage

0.5 V_CCIO

200

V

V_ISO

Input clock signal offset voltage

variation

mV

V

_OX(AC)

AC differential output cross point

voltage

(V_CCIO/2) – 0.2

—

(V_CCIO/2) + 0.2

V

Note to Table 4–31:

(1) This specification is supported across all the programmable drive settings available for this I/Ostandard as shown in the Arria GX Architecture

chapter.

Table 4–32. 1.2-V HSTL Specifications

Symbol

Parameter

Output supply voltage

Minimum

1.14

Typical

1.2

Maximum

1.26

Units

V_CCIO

V_REF

V

Reference voltage

0.48 V_CCIO

V_REF+ 0.08

–0.15

0.5 V_CCIO

—

0.52 V_CCIO

V_CCIO+ 0.15

V_REF– 0.08

V_CCIO+ 0.24

V_REF– 0.15

V_CCIO+ 0.15

V_REF– 0.15

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

V_OH

High-level DC input voltage

Low-level DC input voltage

High-level AC input voltage

Low-level AC input voltage

High-level output voltage

Low-level output voltage

—

V_REF+ 0.15

–0.24

—

V_REF+ 0.15

–0.15

—

V_OL

—

Arria GX Device Handbook, Volume 1

4–22

Chapter 4: DC and Switching Characteristics

Operating Conditions

Table 4–33. 1.5-V HSTL Class I Specifications

Symbol

Parameter

Conditions

Minimum

1.425

Typical

1.5

Maximum

1.575

0.788

—

Units

V_CCIO

V_REF

V_TT

Output supply voltage

—

V

Input reference voltage

Termination voltage

—

0.713

0.75

—

0.713

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

V_OH

DC high-level input voltage

DC low-level input voltage

AC high-level input voltage

AC low-level input voltage

High-level output voltage

Low-level output voltage

—

V_REF+ 0.1

–0.3

—

V_REF– 0.1

—

V_REF+ 0.2

—

V_REF– 0.2

—

I_OH= 8 mA (1)

I_OH= –8 mA (1)

V_CCIO– 0.4

—

V_OL

—

0.4

Note to Table 4–33:

(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture

chapter.

Table 4–34. 1.5-V HSTL Class II Specifications

Symbol

Parameter

Conditions

Minimum

1.425

Typical

1.50

0.75

—

Maximum

1.575

0.788

—

Units

V

V_CCIO

V_REF

V_TT

Output supply voltage

—

Input reference voltage

Termination voltage

—

0.713

V

—

0.713

V

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

V_OH

DC high-level input voltage

DC low-level input voltage

AC high-level input voltage

AC low-level input voltage

High-level output voltage

Low-level output voltage

—

V_REF+ 0.1

–0.3

V

—

V_REF– 0.1

—

V

V_REF+ 0.2

—

V

—

V_REF– 0.2

—

V

I_OH= 16 mA (1)

I_OH= –16 mA (1)

V_CCIO– 0.4

—

V

V_OL

—

0.4

V

Note to Table 4–34:

(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture

chapter.

Table 4–35. 1.5-V HSTL Class I & II Differential Specifications

Symbol

V_CCIO

Parameter

I/O supply voltage

Minimum

1.425

0.2

Typical

1.5

Maximum

1.575

—

Units

V

V_DIF(DC)

V_CM(DC)

V_DIF(AC)

V_OX(AC)

DC input differential voltage

DC common mode input voltage

AC differential input voltage

—

0.68

—

0.9

0.4

—

AC differential cross point

voltage

0.68

—

0.9

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–23

Operating Conditions

Table 4–36. 1.8-V HSTL Class I Specifications

Symbol

V_CCIO

Parameter

Conditions

Minimum

1.71

Typical

1.80

0.90

—

Maximum

1.89

Units

Output supply voltage

—

V

V_REF

Input reference voltage

Termination voltage

—

0.85

0.95

V_TT

—

0.85

0.95

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

V_OH

DC high-level input voltage

DC low-level input voltage

AC high-level input voltage

AC low-level input voltage

High-level output voltage

Low-level output voltage

—

V_REF+ 0.1

–0.3

—

V_REF– 0.1

—

V_REF+ 0.2

—

V_REF– 0.2

—

I_OH= 8 mA (1)

I_OH= –8 mA (1)

V_CCIO– 0.4

—

V_OL

—

0.4

Note to Table 4–36:

(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture

chapter.

Table 4–37. 1.8-V HSTL Class II Specifications

Symbol

V_CCIO

Parameter

Output supply voltage

Conditions

Minimum

1.71

Typical

1.80

0.90

—

Maximum

1.89

Units

—

V

V_REF

Input reference voltage

Termination voltage

—

0.85

0.95

V_TT

—

0.85

0.95

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

V_OH

DC high-level input voltage

DC low-level input voltage

AC high-level input voltage

AC low-level input voltage

High-level output voltage

Low-level output voltage

—

V_REF+ 0.1

–0.3

—

V_REF– 0.1

—

V_REF+ 0.2

—

V_REF– 0.2

—

I_OH= 16 mA (1)

I_OH= –16 mA (1)

V_CCIO– 0.4

—

V_OL

—

0.4

Note to Table 4–37:

(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture

chapter in volume 1 of the Arria GX Device Handbook.

Table 4–38. 1.8-V HSTL Class I & II Differential Specifications

Symbol

V_CCIO

Parameter

I/O supply voltage

Minimum

1.71

0.2

Typical

1.80

—

Maximum

1.89

—

Units

V

V_DIF(DC)

V_CM(DC)

V_DIF(AC)

V_OX(AC)

DC input differential voltage

DC common mode input voltage

AC differential input voltage

AC differential cross point voltage

0.78

0.4

—

1.12

—

0.68

—

0.9

Arria GX Device Handbook, Volume 1

4–24

Chapter 4: DC and Switching Characteristics

Operating Conditions

Bus Hold Specifications

Table 4–39 shows the Arria GX device family bus hold specifications.

Table 4–39. Bus Hold Parameters

V_CCIOLevel

1.8 V

Parameter

Conditions

1.2 V

1.5 V

2.5 V

3.3 V

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Low

sustaining

current

V_IN> V_IL

(maximum)

22.5

—

25

—

30

—

50

—

70

—

A

High

sustaining

current

V_IN< V_IH

(minimum)

–22.5

—

–25

—

–30

—

–50

—

–70

—

A

Lowoverdrive

current

0 V

<V_IN< V_CCIO

—

120

—

160

—

200

—

300

—

500

A

High

0 V <

–120

–160

–200

–300

–500

overdrive

current

V_IN< V_CCIO

Bus-hold trip

point

—

0.45

0.95

0.5

1.0

0.68 1.07

0.7

1.7

0.8

2.0

V

On-Chip Termination Specifications

Table 4–40 and Table 4–41 define the specification for internal termination resistance

tolerance when using series or differential on-chip termination.

Table 4–40. Series On-Chip Termination Specification for Top and Bottom I/O Banks

Resistance Tolerance

Symbol

Description

Conditions

Commercial Industrial

Units

Max

25- R_S3.3/2.5 Internal series termination without

calibration (25- setting

V_CCIO= 3.3/2.5V

V_CCIO= 1.8V

30

%

50- R_S3.3/2.5 Internal series termination without

calibration (50- setting

30

36

50

30

36

50

%

25- R_S1.8

50- R_S1.8

50- R_S1.5

50- R_S1.2

Internal series termination without

calibration (25- setting

Internal series termination without

calibration (50- setting

V_CCIO= 1.8V

Internal series termination without

calibration (50- setting

V_CCIO= 1.5V

Internal series termination without

V_CCIO= 1.2V

calibration (50- setting

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–25

Power Consumption

Table 4–41. Series On-Chip Termination Specification for Left I/O Banks

Resistance Tolerance

Symbol

Description

Conditions

Commercial

Industrial

Max

Units

Max

25- R_S3.3/2.5 Internal series termination without

calibration (25- setting

V_CCIO= 3.3/2.5V

V_CCIO= 3.3/2.5/1.8V

V_CCIO= 1.5V

30

36

25

%

50- R_S

3.3/2.5/1.8

Internal series termination without

calibration (50- setting

30

36

20

50- R_S1.5

Internal series termination without

calibration (50- setting

R_D

Internal differential termination for

V_CCIO= 2.5V

LVDS (100- setting)

Pin Capacitance

Table 4–42 shows the Arria GX device family pin capacitance.

Table 4–42. Arria GX Device Capacitance (Note 1)

Symbol

Parameter

Typical

Units

pF

C_IOTB

C_IOL

Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.

5.0

6.1

Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed differential

receiver and transmitter pins.

pF

C_CLKTB

C_CLKL

Input capacitance on top/bottom clock input pins: CLK[4..7]and CLK[12..15].

Input capacitance on left clock inputs: CLK0and CLK2.

6.0

6.1

3.3

6.7

pF

C_CLKL+

C_OUTFB

Input capacitance on left clock inputs: CLK1and CLK3.

Input capacitance on dual-purpose clock output/feedback pins in PLL banks 11 and 12.

Note to Table 4–42:

(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within 0.5 pF.

Power Consumption

Altera offers two ways to calculate power for a design: the Excel-based PowerPlay

early power estimator power calculator and the Quartus II PowerPlay power analyzer

feature.

The interactive Excel-based PowerPlay Early Power Estimator is typically used prior

to designing the FPGA in order to get an estimate of device power. The Quartus II

PowerPlay Power Analyzer provides better quality estimates based on the specifics of

the design after place-and-route is complete. The power analyzer can apply a

combination of user-entered, simulation-derived and estimated signal activities

which, combined with detailed circuit models, can yield very accurate power

estimates.

In both cases, these calculations should only be used as an estimation of power, not as

a specification.

Arria GX Device Handbook, Volume 1

4–26

Chapter 4: DC and Switching Characteristics

I/O Timing Model

f

For more information about PowerPlay tools, refer to the PowerPlay Early Power

Estimator and PowerPlay Power Analyzer page and the PowerPlay Power Analysis chapter

in volume 3 of the Quartus II Handbook.

For typical I_CCstandby specifications, refer to Table 4–14 on page 4–14 .

I/O Timing Model

The DirectDrive technology and MultiTrack interconnect ensures predictable

performance, accurate simulation, and accurate timing analysis across all Arria GX

device densities and speed grades. This section describes and specifies the

performance of I/Os.

All specifications are representative of worst-case supply voltage and junction

temperature conditions.

1

The timing numbers listed in the tables of this section are extracted from the

Quartus II software version 7.1.

Preliminary, Correlated, and Final Timing

Timing models can have either preliminary, correlated, or final status. The Quartus II

software issues an informational message during design compilation if the timing

models are preliminary. Table 4–43 lists the status of the Arria GX device timing

models.

■

Preliminary status means the timing model is subject to change. Initially, timing

numbers are created using simulation results, process data, and other known

parameters. These tests are used to make the preliminary numbers as close to the

actual timing parameters as possible.

■

Correlated numbers are based on actual device operation and testing. These

numbers reflect the actual performance of the device under worst-case voltage and

junction temperature conditions.

Final timing numbers are based on complete correlation to actual devices and

addressing any minor deviations from the correlated timing model. When the

timing models are final, all or most of the Arria GX family devices have been

completely characterized and no further changes to the timing model are

expected.

Table 4–43. Arria GX Device Timing Model Status

Device

EP1AGX20

EP1AGX35

EP1AGX50

EP1AGX60

EP1AGX90

Preliminary

Correlated

Final

v

—

v

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–27

I/O Timing Model

I/O Timing Measurement Methodology

Different I/O standards require different baseline loading techniques for reporting

timing delays. Altera characterizes timing delays with the required termination for

each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading

and the timing is specified up to the output pin of the FPGA device. The Quartus II

software calculates the I/O timing for each I/O standard with a default baseline

loading as specified by the I/O standards.

The following measurements are made during device characterization. Altera

measures clock-to-output delays (t_CO) at worst-case process, minimum voltage, and

maximum temperature (PVT) for default loading conditions shown in Table 4–44.

Use the following equations to calculate clock pin to output pin timing for Arria GX

devices:

Equation 4–1.

t_COfrom clock pin to I/O pin = delay from clock pad to I/O output

register + IOE output register clock-to-output delay + delay

from output register to output pin + I/O output delay

t_xz/t_zxfrom clock pin to I/O pin = delay from clock pad to I/O

output register + IOE output register clock-to-output delay +

delay from output register to output pin + I/O output delay +

output enable pin delay

Simulation using IBIS models is required to determine the delays on the PCB traces in

addition to the output pin delay timing reported by the Quartus II software and the

timing model in the device handbook.

1. Simulate the output driver of choice into the generalized test setup, using values

from Table 4–44.

2. Record the time to V_MEAS

.

3. Simulate the output driver of choice into the actual PCB trace and load, using the

appropriate IBIS model or capacitance value to represent the load.

4. Record the time to V_MEAS

.

5. Compare the results of steps 2 and 4. The increase or decrease in delay should be

added to or subtracted from the I/O Standard Output Adder delays to yield the

actual worst-case propagation delay (clock-to-output) of the PCB trace.

The Quartus II software reports the timing with the conditions shown in Table 4–44

using the above equation. Figure 4–7 shows the model of the circuit that is

represented by the output timing of the Quartus II software.

Arria GX Device Handbook, Volume 1

4–28

Chapter 4: DC and Switching Characteristics

I/O Timing Model

Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II

V

TT

V

CCIO

Output

R

C

p

T

L

R

S

Output

Buffer

R

D

V

n

MEAS

GND

Notes to Figure 4–7:

(1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay

need to be accounted for with IBIS model simulations.

(2) V_CCPDis 3.085 V unless otherwise specified.

(3) V_CCINTis 1.12 V unless otherwise specified.

Table 4–44. Output Timing Measurement Methodology for Output Pins (Note 1), (2), (3)

Measurement

Point

Loading and Termination

I/O Standard

V_CCIO

R_S()

R_D()

R_T()

V_TT(V) C_L(pF)

V_MEAS(V)

(V)

LVTTL (4)

—

25

—

25

50

25

—

50

25

50

25

50

25

50

25

—

50

25

50

25

50

25

50

3.135

2.375

1.710

1.425

2.970

2.325

1.660

1.375

1.140

2.325

1.660

1.375

1.660

—

0

1.5675

1.1875

0.855

0.7125

1.485

1.1625

0.83

LVCMOS (4)

—

2.5 V (4)

—

0

1.8 V (4)

—

0

1.5 V (4)

—

0

PCI (5)

—

10

0

PCI-X (5)

—

SSTL-2 Class I

1.123

0.790

0.648

—

SSTL-2 Class II

0

SSTL-18 Class I

0

SSTL-18 Class II

0

0.83

1.8-V HSTL Class I

1.8-V HSTL Class II

1.5-V HSTL Class I

1.5-V HSTL Class II

1.2-V HSTL with OCT

Differential SSTL-2 Class I

Differential SSTL-2 Class II

Differential SSTL-18 Class I

Differential SSTL-18 Class II

1.5-V differential HSTL Class I

1.5-V differential HSTL Class II

1.8-V differential HSTL Class I

0

0.83

0

0.83

0

0.6875

0.570

1.1625

0.83

0

1.123

0.790

0.648

0.790

0

0.83

0

0.6875

0.83

0

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–29

I/O Timing Model

Table 4–44. Output Timing Measurement Methodology for Output Pins (Note 1), (2), (3)

Measurement

Loading and Termination

Point

I/O Standard

V_CCIO

(V)

R_S()

R_D()

R_T()

V_TT(V) C_L(pF)

V_MEAS(V)

1.8-V differential HSTL Class II

LVDS

—

25

—

1.660

2.325

3.135

0.790

—

0

0.83

100

1.1625

1.5675

LVPECL

—

Notes to Table 4–44:

(1) Input measurement point at internal node is 0.5 V_CCINT

.

(2) Output measuring point for V_MEASat buffer output is 0.5 V_CCIO

.

(3) Input stimulus edge rate is 0 to V_CCin 0.2 ns (internal signal) from the driver preceding the I/O buffer.

(4) Less than 50-mV ripple on V_CCIOand V_CCPD, V_CCINT= 1.15 V with less than 30-mV ripple.

(5) V_CCPD= 2.97 V, less than 50-mV ripple on V_CCIOand V_CCPD, V_CCINT= 1.15 V.

Figure 4–8 and Figure 4–9 show the measurement setup for output disable and output

enable timing.

Figure 4–8. Measurement Setup for t_xz(Note 1)

t

, Driving High to Tristate

XZ

Enable

Disable

OE

Din

OE

Dout

½ V

CCINT

“1”

100 mv

Din

100 Ω

Dout

GND

t

hz

t

, Driving Low to Tristate

XZ

Enable

Disable

OE

½ V

CCINT

100 Ω

Dout

OE

Din

“0”

t

lz

V

CCIO

Dout

100 mv

Note to Figure 4–8:

(1) V_CCINTis 1.12 V for this measurement.

Arria GX Device Handbook, Volume 1

4–30

Chapter 4: DC and Switching Characteristics

I/O Timing Model

Figure 4–9. Measurement Setup for t_zx

t

, Tristate to Driving High

ZX

Disable Enable

½ V

CCINT

OE

Din

OE

Dout

“1”

Din

1 MΩ

t

Dout

zh

½ V

CCIO

t

, Tristate to Driving Low

ZX

Disable Enable

½ V

CCINT

OE

Din

1 MΩ

Dout

OE

Din

“0”

½ V

t

CCIO

zl

Dout

Table 4–45 specifies the input timing measurement setup.

Table 4–45. Timing Measurement Methodology for Input Pins (Note 1), (2), (3), (4) (Part 1 of 2)

Measurement Conditions

Measurement Point

I/O Standard

V_CCIO(V)

3.135

2.375

1.710

1.425

2.970

2.325

1.660

1.375

1.140

2.325

1.660

V_REF(V)

—

Edge Rate (ns)

VMEAS (V)

1.5675

1.1875

0.855

LVTTL (5)

LVCMOS (5)

2.5 V (5)

1.8 V (5)

1.5 V (5)

PCI (6)

3.135

2.375

1.710

1.425

2.970

2.325

1.660

1.375

1.140

2.325

1.660

—

0.7125

1.485

—

PCI-X (6)

—

1.485

SSTL-2 Class I

1.163

0.830

0.688

0.570

1.163

0.830

1.1625

0.83

SSTL-2 Class II

SSTL-18 Class I

SSTL-18 Class II

0.83

1.8-V HSTL Class I

1.8-V HSTL Class II

1.5-V HSTL Class I

1.5-V HSTL Class II

1.2-V HSTL with OCT

Differential SSTL-2 Class I

Differential SSTL-2 Class II

Differential SSTL-18 Class I

0.83

0.6875

0.570

1.1625

0.83

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–31

I/O Timing Model

Table 4–45. Timing Measurement Methodology for Input Pins (Note 1), (2), (3), (4) (Part 2 of 2)

Measurement Conditions

Measurement Point

I/O Standard

V_CCIO(V)

1.660

1.375

1.660

2.325

3.135

V_REF(V)

0.830

0.688

0.830

—

Edge Rate (ns)

VMEAS (V)

0.83

Differential SSTL-18 Class II

1.5-V differential HSTL Class I

1.5-V differential HSTL Class II

1.8-V differential HSTL Class I

1.8-V differential HSTL Class II

LVDS

1.660

1.375

1.660

0.100

0.6875

0.83

1.1625

1.5675

LVPECL

—

Notes to Table 4–45:

(1) Input buffer sees no load at buffer input.

(2) Input measuring point at buffer input is 0.5 V_CCIO

.

(3) Output measuring point is 0.5 V_CCat internal node.

(4) Input edge rate is 1 V/ns.

(5) Less than 50-mV ripple on V_CCIOand V_CCPD, V_CCINT= 1.15 V with less than 30-mV ripple.

(6) V_CCPD= 2.97 V, less than 50-mV ripple on V_CCIOand V_CCPD, V_CCINT= 1.15 V.

Clock Network Skew Adders

The Quartus II software models skew within dedicated clock networks such as global

and regional clocks. Therefore, the intra-clock network skew adder is not specified.

Table 4–46 specifies the intra clock skew between any two clock networks driving any

registers in the Arria GX device.

Table 4–46. Clock Network Specifications

Name

Description

Min

—

Typ

—

Max

50

Units

ps

Clock skew adder

EP1AGX20/35 (1)

Inter-clock network, same side

Inter-clock network, entire chip

Inter-clock network, same side

Inter-clock network, entire chip

Inter-clock network, same side

Inter-clock network, entire chip

100

50

ps

Clock skew adder

EP1AGX50/60 (1)

ps

100

55

ps

Clock skew adder

EP1AGX90 (1)

ps

110

ps

Note to Table 4–46:

(1) This is in addition to intra-clock network skew, which is modeled in the Quartus II software.

Default Capacitive Loading of Different I/O Standards

See Table 4–47 for default capacitive loading of different I/O standards.

Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part 1 of 2)

I/O Standard

Capacitive Load

Units

pF

LVTTL

LVCMOS

2.5 V

0

pF

Arria GX Device Handbook, Volume 1

4–32

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part 2 of 2)

I/O Standard

Capacitive Load

Units

pF

1.8 V

1.5 V

PCI

0

10

0

PCI-X

SSTL-2 Class I

SSTL-2 Class II

0

SSTL-18 Class I

0

SSTL-18 Class II

0

1.5-V HSTL Class I

0

1.5-V HSTL Class II

0

1.8-V HSTL Class I

0

1.8-V HSTL Class II

0

Differential SSTL-2 Class I

Differential SSTL-2 Class II

Differential SSTL-18 Class I

Differential SSTL-18 Class II

1.5-V differential HSTL Class I

1.5-V differential HSTL Class II

1.8-V differential HSTL Class I

1.8-V differential HSTL Class II

LVDS

0

Typical Design Performance

The following section describes the typical design performance for the Arria GX

device family.

User I/O Pin Timing

Table 4–48 through Table 4–77 show user I/O pin timing for Arria GX devices. I/O

buffer t_SU, t_H, and t_COare reported for the cases when I/O clock is driven by a

non-PLL global clock (GCLK) and a PLL driven global clock (GCLK-PLL). For t_SU, t_H,

and t_COusing regional clock, add the value from the adder tables listed for each device

to the GCLK/GCLK-PLLvalues for the device.

EP1AGX20 I/O Timing Parameters

Table 4–48 through Table 4–51 show the maximum I/O timing parameters for

EP1AGX20 devices for I/O standards which support general purpose I/O pins.

Table 4–48 describes the row pin delay adders when using the regional clock in

Arria GX devices.

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–33

Typical Design Performance

Table 4–48. EP1AGX20 Row Pin Delay Adders for Regional Clock

Fast Corner

–6 Speed

Grade

Parameter

Units

ns

Industrial

Commercial

RCLKinput

adder

0.117

0.273

0.019

RCLKPLL

input adder

0.011

–0.117

–0.011

ns

RCLK output

adder

–0.117

–0.011

–0.273

–0.019

ns

RCLKPLL

ns

output adder

Table 4–49 describes I/O timing specifications.

Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 1 of 3)

Fast Corner

–6 Speed

I/O Standard

Clock

Parameter

Units

Grade

Industrial

1.251

Commercial

GCLK

t_SU

t_H

1.251

–1.146

2.693

2.915

–2.638

6.021

–5.744

2.915

–2.638

6.021

–5.744

2.897

–2.620

6.003

–5.726

3.107

–2.830

6.213

–5.936

3.200

–2.923

6.306

–6.029

2.372

–2.095

5.480

–5.203

ns

–1.146

2.693

3.3-V LVTTL

GCLK PLL

GCLK

t_SU

t_H

–2.588

1.251

–2.588

1.251

t_SU

t_H

–1.146

2.693

–1.146

2.693

3.3-V LVCMOS

2.5 V

GCLK PLL

GCLK

t_SU

t_H

–2.588

1.261

–2.588

1.261

t_SU

t_H

–1.156

2.703

–1.156

2.703

GCLK PLL

GCLK

t_SU

t_H

–2.598

1.327

–2.598

1.327

t_SU

t_H

–1.222

2.769

–1.222

2.769

1.8 V

GCLK PLL

GCLK

t_SU

t_H

–2.664

1.330

–2.664

1.330

t_SU

t_H

–1.225

2.772

–1.225

2.772

1.5 V

GCLK PLL

GCLK

t_SU

t_H

–2.667

1.075

–2.667

1.075

t_SU

t_H

–0.970

2.517

–0.970

2.517

SSTL-2 CLASS I

GCLK PLL

t_SU

t_H

–2.412

Arria GX Device Handbook, Volume 1

4–34

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 2 of 3)

Fast Corner

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

1.075

Commercial

GCLK

t_SU

t_H

1.075

–0.970

2.517

2.372

–2.095

5.480

–5.203

2.479

–2.202

5.585

–5.308

2.479

–2.202

5.587

–5.310

2.479

–2.202

5.585

–5.308

2.479

–2.202

5.587

–5.310

2.607

–2.330

5.713

–5.436

2.607

–2.330

5.715

–5.438

2.903

–2.626

6.009

–5.732

2.903

–2.626

6.009

–5.732

ns

–0.970

2.517

SSTL-2 CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.412

1.113

–2.412

1.113

t_SU

t_H

–1.008

2.555

–1.008

2.555

SSTL-18 CLASS I

SSTL-18 CLASS II

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

1.5-V HSTL CLASS II

3.3-V PCI

GCLK PLL

GCLK

t_SU

t_H

–2.450

1.114

–2.450

1.114

t_SU

t_H

–1.009

2.556

–1.009

2.556

GCLK PLL

GCLK

t_SU

t_H

–2.451

1.113

–2.451

1.113

t_SU

t_H

–1.008

2.555

–1.008

2.555

GCLK PLL

GCLK

t_SU

t_H

–2.450

1.114

–2.450

1.114

t_SU

t_H

–1.009

2.556

–1.009

2.556

GCLK PLL

GCLK

t_SU

t_H

–2.451

1.131

–2.451

1.131

t_SU

t_H

–1.026

2.573

–1.026

2.573

GCLK PLL

GCLK

t_SU

t_H

–2.468

1.132

–2.468

1.132

t_SU

t_H

–1.027

2.574

–1.027

2.574

GCLK PLL

GCLK

t_SU

t_H

–2.469

1.256

–2.469

1.256

t_SU

t_H

–1.151

2.698

–1.151

2.698

GCLK PLL

GCLK

t_SU

t_H

–2.593

1.256

–2.593

1.256

t_SU

t_H

–1.151

2.698

–1.151

2.698

3.3-V PCI-X

GCLK PLL

t_SU

t_H

–2.593

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–35

Typical Design Performance

Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 3 of 3)

Fast Corner

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

1.106

Commercial

1.106

GCLK

t_SU

t_H

2.489

–2.212

5.564

ns

–1.001

2.530

–1.001

2.530

LVDS

GCLK PLL

t_SU

t_H

–2.425

–5.287

Table 4–50 describes I/O timing specifications.

Table 4–50. EP1AGX20 Row Pins output Timing Parameters (Part 1 of 2)

Fast Model

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.904

1.485

2.776

1.357

2.720

1.301

2.776

1.357

2.670

1.251

2.759

1.340

2.656

1.237

2.637

1.218

2.829

1.410

2.818

1.399

2.707

1.288

2.676

1.257

2.789

1.370

2.682

1.263

Commercial

2.904

1.485

2.776

1.357

2.720

1.301

2.776

1.357

2.670

1.251

2.759

1.340

2.656

1.237

2.637

1.218

2.829

1.410

2.818

1.399

2.707

1.288

2.676

1.257

2.789

1.370

2.682

1.263

3.3-V LVTTL

4 mA

8 mA

12 mA

4 mA

8 mA

4 mA

8 mA

12 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

GCLK

GCLK PLL

GCLK

t_CO

6.699

3.627

6.059

2.987

6.022

2.950

6.059

2.987

5.753

2.681

6.033

2.961

5.775

2.703

5.661

2.589

7.052

3.980

6.273

3.201

5.972

2.900

5.858

2.786

6.551

3.479

5.950

2.878

ns

3.3-V LVTTL

GCLK PLL

GCLK

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

2.5 V

1.8 V

1.5 V

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

Arria GX Device Handbook, Volume 1

4–36

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–50. EP1AGX20 Row Pins output Timing Parameters (Part 2 of 2)

Fast Model

Commercial

Drive

Strength

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

2.626

1.207

2.602

1.183

2.568

1.149

2.614

1.195

2.618

1.199

2.594

1.175

2.597

1.178

2.595

1.176

2.598

1.179

2.580

1.161

2.584

1.165

2.575

1.156

2.594

1.175

2.597

1.178

2.582

1.163

2.654

1.226

SSTL-2

CLASS I

8 mA

12 mA

16 mA

4 mA

6 mA

8 mA

10 mA

4 mA

6 mA

8 mA

10 mA

12 mA

4 mA

6 mA

8 mA

—

GCLK

GCLK PLL

GCLK

t_CO

2.626

1.207

2.602

1.183

2.568

1.149

2.614

1.195

2.618

1.199

2.594

1.175

2.597

1.178

2.595

1.176

2.598

1.179

2.580

1.161

2.584

1.165

2.575

1.156

2.594

1.175

2.597

1.178

2.582

1.163

2.654

1.226

5.614

2.542

5.538

2.466

5.407

2.335

5.556

2.484

5.485

2.413

5.468

2.396

5.447

2.375

5.466

2.394

5.430

2.358

5.426

2.354

5.415

2.343

5.414

2.342

5.443

2.371

5.429

2.357

5.421

2.349

5.613

2.530

ns

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

LVDS

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–37

Typical Design Performance

Table 4–51 describes I/O timing specifications.

Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 1 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.909

1.467

2.764

1.322

2.697

1.255

2.671

1.229

2.649

1.207

2.642

1.200

2.764

1.322

2.672

1.230

2.644

1.202

2.651

1.209

2.638

1.196

2.627

1.185

2.726

1.284

2.674

1.232

2.653

1.211

2.635

1.193

2.766

1.324

2.771

1.329

Commercial

2.909

1.467

2.764

1.322

2.697

1.255

2.671

1.229

2.649

1.207

2.642

1.200

2.764

1.322

2.672

1.230

2.644

1.202

2.651

1.209

2.638

1.196

2.627

1.185

2.726

1.284

2.674

1.232

2.653

1.211

2.635

1.193

2.766

1.324

2.771

1.329

GCLK

GCLK PLL

GCLK

t_CO

6.541

3.435

6.169

3.063

6.169

3.063

6.000

2.894

5.875

2.769

5.877

2.771

6.169

3.063

5.874

2.768

5.796

2.690

5.764

2.658

5.746

2.640

5.724

2.618

6.201

3.095

5.939

2.833

5.822

2.716

5.748

2.642

7.193

4.087

6.419

3.313

ns

3.3-V LVTTL

4 mA

8 mA

GCLK PLL

GCLK

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

8 mA

GCLK PLL

GCLK

3.3-V

LVCMOS

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

2.5 V

1.8 V

GCLK PLL

GCLK

8 mA

GCLK PLL

GCLK

12 mA

16 mA

2 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

4 mA

GCLK PLL

Arria GX Device Handbook, Volume 1

4–38

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 2 of 4)

Fast Corner

Commercial

Drive

Strength

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

2.695

1.253

2.697

1.255

2.651

1.209

2.652

1.210

2.746

1.304

2.682

1.240

2.685

1.243

2.644

1.202

2.629

1.184

2.612

1.167

2.590

1.145

2.591

1.146

2.587

1.142

2.626

1.184

2.630

1.185

2.609

1.164

2.614

1.169

2.608

1.163

2.597

1.152

GCLK

GCLK PLL

GCLK

t_CO

2.695

1.253

2.697

1.255

2.651

1.209

2.652

1.210

2.746

1.304

2.682

1.240

2.685

1.243

2.644

1.202

2.629

1.184

2.612

1.167

2.590

1.145

2.591

1.146

2.587

1.142

2.626

1.184

2.630

1.185

2.609

1.164

2.614

1.169

2.608

1.163

2.597

1.152

6.155

3.049

6.064

2.958

5.987

2.881

5.930

2.824

6.723

3.617

6.154

3.048

6.036

2.930

5.983

2.877

5.762

2.650

5.712

2.600

5.639

2.527

5.626

2.514

5.624

2.512

5.733

2.627

5.694

2.582

5.675

2.563

5.673

2.561

5.659

2.547

5.625

2.513

ns

1.8 V

1.5 V

6 mA

8 mA

GCLK PLL

GCLK

10 mA

12 mA

2 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

4 mA

GCLK PLL

GCLK

6 mA

GCLK PLL

GCLK

8 mA

GCLK PLL

GCLK

SSTL-2

CLASS I

8 mA

GCLK PLL

GCLK

SSTL-2

CLASS I

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

6 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

8 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

10 mA

12 mA

8 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–39

Typical Design Performance

Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 3 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.609

1.164

2.605

1.160

2.605

1.160

2.629

1.187

2.634

1.189

2.612

1.167

2.616

1.171

2.608

1.163

2.591

1.146

2.593

1.148

2.593

1.148

2.629

1.187

2.633

1.188

2.615

1.170

2.615

1.170

2.609

1.164

2.596

1.151

2.599

1.154

2.601

1.156

Commercial

2.609

1.164

2.605

1.160

2.605

1.160

2.629

1.187

2.634

1.189

2.612

1.167

2.616

1.171

2.608

1.163

2.591

1.146

2.593

1.148

2.593

1.148

2.629

1.187

2.633

1.188

2.615

1.170

2.615

1.170

2.609

1.164

2.596

1.151

2.599

1.154

2.601

1.156

GCLK

GCLK PLL

GCLK

t_CO

5.603

2.491

5.611

2.499

5.609

2.497

5.664

2.558

5.649

2.537

5.638

2.526

5.644

2.532

5.637

2.525

5.401

2.289

5.412

2.300

5.421

2.309

5.663

2.557

5.641

2.529

5.643

2.531

5.645

2.533

5.643

2.531

5.455

2.343

5.465

2.353

5.478

2.366

ns

SSTL-18

CLASS II

16 mA

18 mA

20 mA

4 mA

SSTL-18

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

6 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

8 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

10 mA

12 mA

16 mA

18 mA

20 mA

4 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

6 mA

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

8 mA

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

10 mA

12 mA

16 mA

18 mA

20 mA

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

Arria GX Device Handbook, Volume 1

4–40

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 4 of 4)

Fast Corner

Drive

–6 Speed

Units

I/O Standard

Clock

Parameter

Strength

Grade

Industrial

2.755

Commercial

—

GCLK

GCLK PLL

GCLK

t_CO

2.755

1.313

2.755

1.313

3.621

2.190

5.791

2.685

5.791

2.685

6.969

3.880

ns

3.3-V PCI

3.3-V PCI-X

LVDS

1.313

2.755

GCLK PLL

GCLK

1.313

3.621

GCLK PLL

2.190

Table 4–52 through Table 4–53 list EP1AGX20 regional clock (RCLK) adder values that

should be added to GCLKvalues. These adder values are used to determine I/O

timing when the I/O pin is driven using the regional clock. This applies for all I/O

standards supported by Arria GX with general purpose I/O pins.

Table 4–52 describes row pin delay adders when using the regional clock in Arria GX

devices.

Table 4–52. EP1AGX20 Row Pin Delay Adders for Regional Clock

Fast Corner

Parameter

–6 Speed Grade

Units

Industrial

0.117

Commercial

0.117

RCLKinput adder

0.273

0.019

ns

RCLKPLL input adder

RCLKoutput adder

RCLKPLL output adder

0.011

–0.117

–0.011

–0.117

–0.011

–0.273

–0.019

Table 4–53 lists column pin delay adders when using the regional clock in Arria GX

devices.

Table 4–53. EP1AGX20 Column Pin Delay Adders for Regional Clock

Fast Corner

Parameter

–6 Speed Grade

Units

Industrial

0.081

Commercial

0.081

RCLKinput adder

0.223

ns

RCLKPLL input

–0.012

–0.008

adder

RCLKoutput

adder

–0.081

1.11

–0.081

1.11

–0.224

2.658

ns

RCLKPLL output

adder

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–41

Typical Design Performance

EP1AGX35 I/O Timing Parameters

Table 4–54 through Table 4–57 list the maximum I/O timing parameters for

EP1AGX35 devices for I/O standards which support general purpose I/O pins.

Table 4–54 lists I/O timing specifications.

Table 4–54. EP1AGX35 Row Pins Input Timing Parameters (Part 1 of 2)

Fast Model

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

Commercial

1.561

t_SU

t_H

1.561

–1.456

2.980

3.556

–3.279

6.628

ns

GCLK

GCLK PLL

GCLK

–1.456

2.980

3.3-V LVTTL

t_SU

t_H

–2.875

1.561

–2.875

1.561

–6.351

3.556

t_SU

t_H

–1.456

2.980

–1.456

2.980

–3.279

6.628

3.3-V LVCMOS

2.5 V

t_SU

t_H

GCLK PLL

GCLK

–2.875

1.573

–2.875

1.573

–6.351

3.537

t_SU

t_H

–1.468

2.992

–1.468

2.992

–3.260

6.609

t_SU

t_H

GCLK PLL

GCLK

–2.887

1.639

–2.887

1.639

–6.332

3.744

t_SU

t_H

–1.534

3.058

–1.534

3.058

–3.467

6.816

1.8 V

t_SU

t_H

GCLK PLL

GCLK

–2.953

1.642

–2.953

1.642

–6.539

3.839

t_SU

t_H

–1.537

3.061

–1.537

3.061

–3.562

6.911

1.5 V

t_SU

t_H

GCLK PLL

GCLK

–2.956

1.385

–2.956

1.385

–6.634

3.009

t_SU

t_H

–1.280

2.804

–1.280

2.804

–2.732

6.081

SSTL-2 CLASS I

SSTL-2 CLASS II

SSTL-18 CLASS I

t_SU

t_H

GCLK PLL

GCLK

–2.699

1.385

–2.699

1.385

–5.804

3.009

t_SU

t_H

–1.280

2.804

–1.280

2.804

–2.732

6.081

t_SU

t_H

GCLK PLL

GCLK

–2.699

1.417

–2.699

1.417

–5.804

3.118

t_SU

t_H

–1.312

2.836

–1.312

2.836

–2.841

6.190

t_SU

t_H

GCLK PLL

–2.731

–5.913

Arria GX Device Handbook, Volume 1

4–42

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–54. EP1AGX35 Row Pins Input Timing Parameters (Part 2 of 2)

Fast Model

Industrial Commercial

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

t_SU

t_H

1.417

–1.312

2.836

1.417

–1.312

2.836

3.118

–2.841

6.190

ns

GCLK

GCLK PLL

GCLK

SSTL-18 CLASS II

t_SU

t_H

–2.731

1.417

–2.731

1.417

–5.913

3.118

t_SU

t_H

–1.312

2.836

–1.312

2.836

–2.841

6.190

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

1.5-V HSTL CLASS II

LVDS

t_SU

t_H

GCLK PLL

GCLK

–2.731

1.417

–2.731

1.417

–5.913

3.118

t_SU

t_H

–1.312

2.836

–1.312

2.836

–2.841

6.190

t_SU

t_H

GCLK PLL

GCLK

–2.731

1.443

–2.731

1.443

–5.913

3.246

t_SU

t_H

–1.338

2.862

–1.338

2.862

–2.969

6.318

t_SU

t_H

GCLK PLL

GCLK

–2.757

1.443

–2.757

1.443

–6.041

3.246

t_SU

t_H

–1.338

2.862

–1.338

2.862

–2.969

6.318

t_SU

t_H

GCLK PLL

GCLK

–2.757

1.341

–2.757

1.341

–6.041

3.088

t_SU

t_H

–1.236

2.769

–1.236

2.769

–2.811

6.171

t_SU

t_H

GCLK PLL

–2.664

–5.894

Table 4–55 lists I/O timing specifications.

Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 1 of 3)

Fast Corner

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

Commercial

1.251

t_SU

t_H

1.251

–1.146

2.693

2.915

–2.638

6.021

ns

GCLK

GCLK PLL

GCLK

–1.146

2.693

3.3-V LVTTL

t_SU

t_H

–2.588

1.251

–2.588

1.251

–5.744

2.915

t_SU

t_H

–1.146

2.693

–1.146

2.693

–2.638

6.021

3.3-V LVCMOS

t_SU

t_H

GCLK PLL

–2.588

–5.744

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–43

Typical Design Performance

Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 2 of 3)

Fast Corner

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

1.261

Commercial

1.261

t_SU

t_H

2.897

–2.620

6.003

ns

GCLK

GCLK PLL

GCLK

–1.156

2.703

–1.156

2.703

2.5 V

t_SU

t_H

–2.598

1.327

–2.598

1.327

–5.726

3.107

t_SU

t_H

–1.222

2.769

–1.222

2.769

–2.830

6.213

1.8 V

t_SU

t_H

GCLK PLL

GCLK

–2.664

1.330

–2.664

1.330

–5.936

3.200

t_SU

t_H

–1.225

2.772

–1.225

2.772

–2.923

6.306

1.5 V

t_SU

t_H

GCLK PLL

GCLK

–2.667

1.075

–2.667

1.075

–6.029

2.372

t_SU

t_H

–0.970

2.517

–0.970

2.517

–2.095

5.480

SSTL-2 CLASS I

SSTL-2 CLASS II

SSTL-18 CLASS I

SSTL-18 CLASS II

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

t_SU

t_H

GCLK PLL

GCLK

–2.412

1.075

–2.412

1.075

–5.203

2.372

t_SU

t_H

–0.970

2.517

–0.970

2.517

–2.095

5.480

t_SU

t_H

GCLK PLL

GCLK

–2.412

1.113

–2.412

1.113

–5.203

2.479

t_SU

t_H

–1.008

2.555

–1.008

2.555

–2.202

5.585

t_SU

t_H

GCLK PLL

GCLK

–2.450

1.114

–2.450

1.114

–5.308

2.479

t_SU

t_H

–1.009

2.556

–1.009

2.556

–2.202

5.587

t_SU

t_H

GCLK PLL

GCLK

–2.451

1.113

–2.451

1.113

–5.310

2.479

t_SU

t_H

–1.008

2.555

–1.008

2.555

–2.202

5.585

t_SU

t_H

GCLK PLL

GCLK

–2.450

1.114

–2.450

1.114

–5.308

2.479

t_SU

t_H

–1.009

2.556

–1.009

2.556

–2.202

5.587

t_SU

t_H

GCLK PLL

–2.451

–5.310

Arria GX Device Handbook, Volume 1

4–44

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 3 of 3)

Fast Corner

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

1.131

Commercial

t_SU

t_H

1.131

–1.026

2.573

2.607

–2.330

5.713

ns

GCLK

GCLK PLL

GCLK

–1.026

2.573

1.5-V HSTL CLASS I

t_SU

t_H

–2.468

1.132

–2.468

1.132

–5.436

2.607

t_SU

t_H

–1.027

2.574

–1.027

2.574

–2.330

5.715

1.5-V HSTL CLASS II

3.3-V PCI

t_SU

t_H

GCLK PLL

GCLK

–2.469

1.256

–2.469

1.256

–5.438

2.903

t_SU

t_H

–1.151

2.698

–1.151

2.698

–2.626

6.009

t_SU

t_H

GCLK PLL

GCLK

–2.593

1.256

–2.593

1.256

–5.732

2.903

t_SU

t_H

–1.151

2.698

–1.151

2.698

–2.626

6.009

3.3-V PCI-X

LVDS

t_SU

t_H

GCLK PLL

GCLK

–2.593

1.106

–2.593

1.106

–5.732

2.489

t_SU

t_H

–1.001

2.530

–1.001

2.530

–2.212

5.564

t_SU

t_H

GCLK PLL

–2.425

–5.287

Table 4–56 lists I/O timing specifications.

Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 1 of 3)

Fast Model

Industrial

Drive

–6 Speed

I/O Standard

Clock

Parameter

Units

Strength

Grade

Commercial

2.904

1.485

2.776

1.357

2.720

1.301

2.776

1.357

2.670

1.251

2.759

1.340

3.3-V LVTTL

4 mA

8 mA

12 mA

4 mA

8 mA

4 mA

GCLK

GCLK PLL

GCLK

t_CO

2.904

1.485

2.776

1.357

2.720

1.301

2.776

1.357

2.670

1.251

2.759

1.340

6.699

3.627

6.059

2.987

6.022

2.950

6.059

2.987

5.753

2.681

6.033

2.961

ns

3.3-V LVTTL

GCLK PLL

GCLK

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

2.5 V

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–45

Typical Design Performance

Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 2 of 3)

Fast Model

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.656

1.237

2.637

1.218

2.829

1.410

2.818

1.399

2.707

1.288

2.676

1.257

2.789

1.370

2.682

1.263

2.626

1.207

2.602

1.183

2.568

1.149

2.614

1.195

2.618

1.199

2.594

1.175

2.597

1.178

2.595

1.176

2.598

1.179

2.580

1.161

2.584

1.165

Commercial

2.656

1.237

2.637

1.218

2.829

1.410

2.818

1.399

2.707

1.288

2.676

1.257

2.789

1.370

2.682

1.263

2.626

1.207

2.602

1.183

2.568

1.149

2.614

1.195

2.618

1.199

2.594

1.175

2.597

1.178

2.595

1.176

2.598

1.179

2.580

1.161

2.584

1.165

GCLK

GCLK PLL

GCLK

t_CO

5.775

2.703

5.661

2.589

7.052

3.980

6.273

3.201

5.972

2.900

5.858

2.786

6.551

3.479

5.950

2.878

5.614

2.542

5.538

2.466

5.407

2.335

5.556

2.484

5.485

2.413

5.468

2.396

5.447

2.375

5.466

2.394

5.430

2.358

5.426

2.354

5.415

2.343

ns

2.5 V

1.8 V

1.5 V

8 mA

12 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

8 mA

12 mA

16 mA

4 mA

6 mA

8 mA

10 mA

4 mA

6 mA

8 mA

10 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

Arria GX Device Handbook, Volume 1

4–46

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 3 of 3)

Fast Model

Commercial

Drive

–6 Speed

Units

I/O Standard

Clock

Parameter

Strength

Grade

Industrial

2.575

1.156

2.594

1.175

2.597

1.178

2.582

1.163

2.654

1.226

GCLK

GCLK PLL

GCLK

t_CO

2.575

1.156

2.594

1.175

2.597

1.178

2.582

1.163

2.654

1.226

5.414

2.342

5.443

2.371

5.429

2.357

5.421

2.349

5.613

2.530

ns

1.8-V HSTL

CLASS I

12 mA

4 mA

6 mA

8 mA

—

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

LVDS

GCLK PLL

Table 4–57 lists I/O timing specifications.

Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 1 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.909

1.467

2.764

1.322

2.697

1.255

2.671

1.229

2.649

1.207

2.642

1.200

2.764

1.322

2.672

1.230

2.644

1.202

2.651

1.209

2.638

1.196

Commercial

2.909

1.467

2.764

1.322

2.697

1.255

2.671

1.229

2.649

1.207

2.642

1.200

2.764

1.322

2.672

1.230

2.644

1.202

2.651

1.209

2.638

1.196

3.3-V LVTTL

4 mA

GCLK

GCLK PLL

GCLK

t_CO

6.541

3.435

6.169

3.063

6.169

3.063

6.000

2.894

5.875

2.769

5.877

2.771

6.169

3.063

5.874

2.768

5.796

2.690

5.764

2.658

5.746

2.640

ns

3.3-V LVTTL

8 mA

GCLK PLL

GCLK

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

8 mA

GCLK PLL

GCLK

3.3-V

LVCMOS

12 mA

16 mA

20 mA

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–47

Typical Design Performance

Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 2 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.627

1.185

2.726

1.284

2.674

1.232

2.653

1.211

2.635

1.193

2.766

1.324

2.771

1.329

2.695

1.253

2.697

1.255

2.651

1.209

2.652

1.210

2.746

1.304

2.682

1.240

2.685

1.243

2.644

1.202

2.629

1.184

2.612

1.167

2.590

1.145

2.591

1.146

Commercial

2.627

1.185

2.726

1.284

2.674

1.232

2.653

1.211

2.635

1.193

2.766

1.324

2.771

1.329

2.695

1.253

2.697

1.255

2.651

1.209

2.652

1.210

2.746

1.304

2.682

1.240

2.685

1.243

2.644

1.202

2.629

1.184

2.612

1.167

2.590

1.145

2.591

1.146

3.3-V

LVCMOS

24 mA

4 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

10 mA

12 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

20 mA

GCLK

GCLK PLL

GCLK

t_CO

5.724

2.618

6.201

3.095

5.939

2.833

5.822

2.716

5.748

2.642

7.193

4.087

6.419

3.313

6.155

3.049

6.064

2.958

5.987

2.881

5.930

2.824

6.723

3.617

6.154

3.048

6.036

2.930

5.983

2.877

5.762

2.650

5.712

2.600

5.639

2.527

5.626

2.514

ns

2.5 V

1.8 V

1.5 V

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

Arria GX Device Handbook, Volume 1

4–48

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 3 of 4)

Fast Corner

Commercial

Drive

Strength

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

2.587

1.142

2.626

1.184

2.630

1.185

2.609

1.164

2.614

1.169

2.608

1.163

2.597

1.152

2.609

1.164

2.605

1.160

2.605

1.160

2.629

1.187

2.634

1.189

2.612

1.167

2.616

1.171

2.608

1.163

2.591

1.146

2.593

1.148

2.593

1.148

2.629

1.187

SSTL-2

CLASS II

24 mA

GCLK

GCLK PLL

GCLK

t_CO

2.587

1.142

2.626

1.184

2.630

1.185

2.609

1.164

2.614

1.169

2.608

1.163

2.597

1.152

2.609

1.164

2.605

1.160

2.605

1.160

2.629

1.187

2.634

1.189

2.612

1.167

2.616

1.171

2.608

1.163

2.591

1.146

2.593

1.148

2.593

1.148

2.629

1.187

5.624

2.512

5.733

2.627

5.694

2.582

5.675

2.563

5.673

2.561

5.659

2.547

5.625

2.513

5.603

2.491

5.611

2.499

5.609

2.497

5.664

2.558

5.649

2.537

5.638

2.526

5.644

2.532

5.637

2.525

5.401

2.289

5.412

2.300

5.421

2.309

5.663

2.557

ns

SSTL-18

CLASS I

4 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

6 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

8 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

10 mA

12 mA

8 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS II

16 mA

18 mA

20 mA

4 mA

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

6 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

8 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

10 mA

12 mA

16 mA

18 mA

20 mA

4 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–49

Typical Design Performance

Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 4 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.633

1.188

2.615

1.170

2.615

1.170

2.609

1.164

2.596

1.151

2.599

1.154

2.601

1.156

2.755

1.313

2.755

1.313

3.621

2.190

Commercial

2.633

1.188

2.615

1.170

2.615

1.170

2.609

1.164

2.596

1.151

2.599

1.154

2.601

1.156

2.755

1.313

2.755

1.313

3.621

2.190

1.5-V HSTL

CLASS I

6 mA

8 mA

10 mA

12 mA

16 mA

18 mA

20 mA

—

GCLK

GCLK PLL

GCLK

t_CO

5.641

2.529

5.643

2.531

5.645

2.533

5.643

2.531

5.455

2.343

5.465

2.353

5.478

2.366

5.791

2.685

5.791

2.685

6.969

3.880

ns

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

3.3-V PCI

3.3-V PCI-X

LVDS

GCLK PLL

GCLK

—

GCLK PLL

GCLK

—

GCLK PLL

Table 4–58 through Table 4–59 list EP1AGX35 regional clock (RCLK) adder values that

should be added to GCLKvalues. These adder values are used to determine I/O

timing when the I/O pin is driven using the regional clock. This applies for all I/O

standards supported by Arria GX with general purpose I/O pins.

Table 4–58 describes row pin delay adders when using the regional clock in Arria GX

devices.

Table 4–58. EP1AGX35 Row Pin Delay Adders for Regional Clock

Fast Corner

Parameter

–6 Speed Grade

Units

Industrial

0.126

Commercial

0.126

RCLKinput adder

0.281

0.018

ns

RCLKPLL input

0.011

adder

RCLKoutput adder

–0.126

–0.011

–0.126

–0.011

–0.281

–0.018

ns

RCLKPLL output

adder

Arria GX Device Handbook, Volume 1

4–50

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–59 lists column pin delay adders when using the regional clock in Arria GX

devices.

Table 4–59. EP1AGX35 Column Pin Delay Adders for Regional Clock

Fast Corner

Parameter

–6 Speed Grade

Units

Industrial

0.099

Commercial

0.099

RCLKinput adder

0.254

–0.01

–0.244

3.133

ns

RCLKPLL input adder

RCLKoutput adder

RCLKPLL output adder

–0.012

–0.086

1.253

–0.012

–0.086

1.253

EP1AGX50 I/O Timing Parameters

Table 4–60 through Table 4–63 list the maximum I/O timing parameters for

EP1AGX50 devices for I/O standards which support general purpose I/O pins.

Table 4–60 lists I/O timing specifications.

Table 4–60. EP1AGX50 Row Pins Input Timing Parameters (Part 1 of 2)

Fast Model

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

1.550

Commercial

1.550

GCLK

t_SU

t_H

3.542

–3.265

6.626

–6.349

3.542

–3.265

6.626

–6.349

3.523

–3.246

6.607

–6.330

3.730

–3.453

6.814

–6.537

3.825

–3.548

6.909

–6.632

ns

–1.445

2.978

–1.445

2.978

3.3-V LVTTL

GCLK PLL

GCLK

t_SU

t_H

–2.873

1.550

–2.873

1.550

t_SU

t_H

–1.445

2.978

–1.445

2.978

3.3-V LVCMOS

2.5 V

GCLK PLL

GCLK

t_SU

t_H

–2.873

1.562

–2.873

1.562

t_SU

t_H

–1.457

2.990

–1.457

2.990

GCLK PLL

GCLK

t_SU

t_H

–2.885

1.628

–2.885

1.628

t_SU

t_H

–1.523

3.056

–1.523

3.056

1.8 V

GCLK PLL

GCLK

t_SU

t_H

–2.951

1.631

–2.951

1.631

t_SU

t_H

–1.526

3.059

–1.526

3.059

1.5 V

GCLK PLL

t_SU

t_H

–2.954

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–51

Typical Design Performance

Table 4–60. EP1AGX50 Row Pins Input Timing Parameters (Part 2 of 2)

Fast Model

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

1.375

Commercial

1.375

GCLK

t_SU

t_H

2.997

–2.720

6.079

–5.802

2.997

–2.720

6.079

–5.802

3.104

–2.827

6.188

–5.911

3.106

–2.829

6.188

–5.911

3.104

–2.827

6.188

–5.911

3.106

–2.829

6.188

–5.911

3.232

–2.955

6.316

–6.039

3.234

–2.957

6.316

–6.039

3.088

–2.811

6.171

–5.894

ns

–1.270

2.802

–1.270

2.802

SSTL-2 CLASS

I

GCLK PLL

GCLK

t_SU

t_H

–2.697

1.375

–2.697

1.375

t_SU

t_H

–1.270

2.802

–1.270

2.802

SSTL-2 CLASS

II

GCLK PLL

GCLK

t_SU

t_H

–2.697

1.406

–2.697

1.406

t_SU

t_H

–1.301

2.834

–1.301

2.834

SSTL-18

CLASS I

GCLK PLL

GCLK

t_SU

t_H

–2.729

1.407

–2.729

1.407

t_SU

t_H

–1.302

2.834

–1.302

2.834

SSTL-18

CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.729

1.406

–2.729

1.406

t_SU

t_H

–1.301

2.834

–1.301

2.834

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

t_SU

t_H

–2.729

1.407

–2.729

1.407

t_SU

t_H

–1.302

2.834

–1.302

2.834

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.729

1.432

–2.729

1.432

t_SU

t_H

–1.327

2.860

–1.327

2.860

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

t_SU

t_H

–2.755

1.433

–2.755

1.433

t_SU

t_H

–1.328

2.860

–1.328

2.860

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.755

1.341

–2.755

1.341

t_SU

t_H

–1.236

2.769

–1.236

2.769

LVDS

GCLK PLL

t_SU

t_H

–2.664

Arria GX Device Handbook, Volume 1

4–52

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–61 lists I/O timing specifications.

Table 4–61. EP1AGX50 Column Pins Input Timing Parameters (Part 1 of 2)

Fast Corner

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

1.242

Commercial

1.242

GCLK

t_SU

t_H

2.902

–2.625

6.009

ns

–1.137

2.684

–1.137

2.684

3.3-V LVTTL

GCLK PLL

GCLK

t_SU

t_H

–2.579

1.242

–2.579

1.242

–5.732

2.902

t_SU

t_H

–1.137

2.684

–1.137

2.684

–2.625

6.009

3.3-V

LVCMOS

GCLK PLL

GCLK

t_SU

t_H

–2.579

1.252

–2.579

1.252

–5.732

2.884

t_SU

t_H

–1.147

2.694

–1.147

2.694

–2.607

5.991

2.5 V

1.8 V

1.5 V

GCLK PLL

GCLK

t_SU

t_H

–2.589

1.318

–2.589

1.318

–5.714

3.094

t_SU

t_H

–1.213

2.760

–1.213

2.760

–2.817

6.201

GCLK PLL

GCLK

t_SU

t_H

–2.655

1.321

–2.655

1.321

–5.924

3.187

t_SU

t_H

–1.216

2.763

–1.216

2.763

–2.910

6.294

GCLK PLL

GCLK

t_SU

t_H

–2.658

1.034

–2.658

1.034

–6.017

2.314

t_SU

t_H

–0.929

2.500

–0.929

2.500

–2.037

5.457

SSTL-2

CLASS I

GCLK PLL

GCLK

t_SU

t_H

–2.395

1.034

–2.395

1.034

–5.180

2.314

t_SU

t_H

–0.929

2.500

–0.929

2.500

–2.037

5.457

SSTL-2

CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.395

1.104

–2.395

1.104

–5.180

2.466

t_SU

t_H

–0.999

2.546

–0.999

2.546

–2.189

5.573

SSTL-18

CLASS I

GCLK PLL

GCLK

t_SU

t_H

–2.441

1.074

–2.441

1.074

–5.296

2.424

t_SU

t_H

–0.969

2.539

–0.969

2.539

–2.147

5.564

SSTL-18

CLASS II

GCLK PLL

t_SU

t_H

–2.434

–5.287

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–53

Typical Design Performance

Table 4–61. EP1AGX50 Column Pins Input Timing Parameters (Part 2 of 2)

Fast Corner

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

1.104

Commercial

1.104

GCLK

t_SU

t_H

2.466

–2.189

5.573

ns

–0.999

2.546

–0.999

2.546

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

t_SU

t_H

–2.441

1.074

–2.441

1.074

–5.296

2.424

t_SU

t_H

–0.969

2.539

–0.969

2.539

–2.147

5.564

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.434

1.122

–2.434

1.122

–5.287

2.594

t_SU

t_H

–1.017

2.564

–1.017

2.564

–2.317

5.701

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

t_SU

t_H

–2.459

1.094

–2.459

1.094

–5.424

2.557

t_SU

t_H

–0.989

2.557

–0.989

2.557

–2.280

5.692

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.452

1.247

–2.452

1.247

–5.415

2.890

t_SU

t_H

–1.142

2.689

–1.142

2.689

–2.613

5.997

3.3-V PCI

3.3-V PCI-X

LVDS

GCLK PLL

GCLK

t_SU

t_H

–2.584

1.247

–2.584

1.247

–5.720

2.890

t_SU

t_H

–1.142

2.689

–1.142

2.689

–2.613

5.997

GCLK PLL

GCLK

t_SU

t_H

–2.584

1.106

–2.584

1.106

–5.720

2.489

t_SU

t_H

–1.001

2.530

–1.001

2.530

–2.212

5.564

GCLK PLL

t_SU

t_H

–2.425

–5.287

Table 4–62 lists I/O timing specifications.

Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 1 of 3)

Fast Model

Drive

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Strength

Industrial

2.915

Commercial

3.3-V LVTTL

4 mA

GCLK

GCLK PLL

GCLK

t_CO

2.915

1.487

2.787

1.359

6.713

3.629

6.073

2.989

ns

1.487

3.3-V LVTTL

8 mA

2.787

GCLK PLL

1.359

Arria GX Device Handbook, Volume 1

4–54

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 2 of 3)

Fast Model

Commercial

Drive

Strength

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

2.731

1.303

2.787

1.359

2.681

1.253

2.770

1.342

2.667

1.239

2.648

1.220

2.840

1.412

2.829

1.401

2.718

1.290

2.687

1.259

2.800

1.372

2.693

1.265

2.636

1.209

2.612

1.185

2.578

1.151

2.625

1.197

2.628

1.201

2.604

1.177

2.607

1.180

3.3-V LVTTL

12 mA

4 mA

8 mA

4 mA

8 mA

12 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

8 mA

12 mA

16 mA

4 mA

6 mA

8 mA

10 mA

GCLK

GCLK PLL

GCLK

t_CO

2.731

1.303

2.787

1.359

2.681

1.253

2.770

1.342

2.667

1.239

2.648

1.220

2.840

1.412

2.829

1.401

2.718

1.290

2.687

1.259

2.800

1.372

2.693

1.265

2.636

1.209

2.612

1.185

2.578

1.151

2.625

1.197

2.628

1.201

2.604

1.177

2.607

1.180

6.036

2.952

6.073

2.989

5.767

2.683

6.047

2.963

5.789

2.705

5.675

2.591

7.066

3.982

6.287

3.203

5.986

2.902

5.872

2.788

6.565

3.481

5.964

2.880

5.626

2.544

5.550

2.468

5.419

2.337

5.570

2.486

5.497

2.415

5.480

2.398

5.459

2.377

ns

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

2.5 V

1.8 V

1.5 V

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–55

Typical Design Performance

Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 3 of 3)

Fast Model

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.606

1.178

2.608

1.181

2.590

1.163

2.594

1.167

2.585

1.158

2.605

1.177

2.607

1.180

2.592

1.165

2.654

1.226

Commercial

2.606

1.178

2.608

1.181

2.590

1.163

2.594

1.167

2.585

1.158

2.605

1.177

2.607

1.180

2.592

1.165

2.654

1.226

1.8-V HSTL

CLASS I

4 mA

6 mA

8 mA

10 mA

12 mA

4 mA

6 mA

8 mA

—

GCLK

GCLK PLL

GCLK

t_CO

5.480

2.396

5.442

2.360

5.438

2.356

5.427

2.345

5.426

2.344

5.457

2.373

5.441

2.359

5.433

2.351

5.613

2.530

ns

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

LVDS

GCLK PLL

Table 4–63 lists I/O timing specifications.

Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 1 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.948

1.476

2.797

1.331

2.722

1.264

2.694

1.238

2.670

1.216

2.660

1.209

2.797

1.331

Commercial

2.948

1.476

2.797

1.331

2.722

1.264

2.694

1.238

2.670

1.216

2.660

1.209

2.797

1.331

3.3-V LVTTL

4 mA

GCLK

GCLK PLL

GCLK

t_CO

6.608

3.447

6.203

3.075

6.204

3.075

6.024

2.906

5.896

2.781

5.895

2.783

6.203

3.075

ns

3.3-V LVTTL

8 mA

GCLK PLL

GCLK

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

Arria GX Device Handbook, Volume 1

4–56

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 2 of 4)

Fast Corner

Commercial

Drive

Strength

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

2.695

1.239

2.663

1.211

2.666

1.218

2.651

1.205

2.638

1.194

2.754

1.293

2.697

1.241

2.672

1.220

2.654

1.202

2.804

1.333

2.808

1.338

2.717

1.262

2.719

1.264

2.671

1.218

2.671

1.219

2.779

1.313

2.703

1.249

2.705

1.252

2.660

1.211

3.3-V

LVCMOS

8 mA

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK

GCLK PLL

GCLK

t_CO

2.695

1.239

2.663

1.211

2.666

1.218

2.651

1.205

2.638

1.194

2.754

1.293

2.697

1.241

2.672

1.220

2.654

1.202

2.804

1.333

2.808

1.338

2.717

1.262

2.719

1.264

2.671

1.218

2.671

1.219

2.779

1.313

2.703

1.249

2.705

1.252

2.660

1.211

5.893

2.780

5.809

2.702

5.776

2.670

5.758

2.652

5.736

2.630

6.240

3.107

5.963

2.845

5.837

2.728

5.760

2.654

7.295

4.099

6.479

3.325

6.195

3.061

6.098

2.970

6.012

2.893

5.953

2.836

6.815

3.629

6.210

3.060

6.118

2.942

6.014

2.889

ns

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

2.5 V

1.8 V

1.5 V

GCLK PLL

GCLK

8 mA

GCLK PLL

GCLK

12 mA

16 mA

2 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

4 mA

GCLK PLL

GCLK

6 mA

GCLK PLL

GCLK

8 mA

GCLK PLL

GCLK

10 mA

12 mA

2 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

4 mA

GCLK PLL

GCLK

6 mA

GCLK PLL

GCLK

8 mA

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–57

Typical Design Performance

Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 3 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.648

1.202

2.628

1.185

2.606

1.163

2.606

1.164

2.601

1.160

2.643

1.193

2.649

1.203

2.626

1.182

2.630

1.187

2.625

1.181

2.614

1.170

2.623

1.182

2.616

1.178

2.616

1.178

2.637

1.196

2.645

1.207

2.623

1.185

2.627

1.189

2.619

1.181

Commercial

2.648

1.202

2.628

1.185

2.606

1.163

2.606

1.164

2.601

1.160

2.643

1.193

2.649

1.203

2.626

1.182

2.630

1.187

2.625

1.181

2.614

1.170

2.623

1.182

2.616

1.178

2.616

1.178

2.637

1.196

2.645

1.207

2.623

1.185

2.627

1.189

2.619

1.181

SSTL-2

CLASS I

8 mA

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK

GCLK PLL

GCLK

t_CO

5.777

2.675

5.722

2.625

5.649

2.552

5.636

2.539

5.634

2.537

5.749

2.639

5.708

2.607

5.686

2.588

5.685

2.586

5.669

2.572

5.635

2.538

5.613

2.516

5.621

2.524

5.619

2.522

5.676

2.570

5.659

2.562

5.648

2.551

5.654

2.557

5.647

2.550

ns

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

6 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

8 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

10 mA

12 mA

8 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS II

16 mA

18 mA

20 mA

4 mA

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

6 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

8 mA

10 mA

12 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

Arria GX Device Handbook, Volume 1

4–58

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 4 of 4)

Fast Corner

Commercial

Drive

Strength

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

2.602

1.164

2.604

1.166

2.604

1.166

2.637

1.196

2.644

1.206

2.626

1.188

2.626

1.188

2.620

1.182

2.607

1.169

2.610

1.172

2.612

1.174

2.786

1.322

2.786

1.322

3.621

2.190

1.8-V HSTL

CLASS II

16 mA

18 mA

20 mA

4 mA

6 mA

8 mA

10 mA

12 mA

16 mA

18 mA

20 mA

—

GCLK

GCLK PLL

GCLK

t_CO

2.602

1.164

2.604

1.166

2.604

1.166

2.637

1.196

2.644

1.206

2.626

1.188

2.626

1.188

2.620

1.182

2.607

1.169

2.610

1.172

2.612

1.174

2.786

1.322

2.786

1.322

3.621

2.190

5.574

2.314

5.578

2.325

5.577

2.334

5.675

2.569

5.651

2.554

5.653

2.556

5.655

2.558

5.653

2.556

5.573

2.368

5.571

2.378

5.581

2.391

5.803

2.697

5.803

2.697

6.969

3.880

ns

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

3.3-V PCI

3.3-V PCI-X

LVDS

GCLK PLL

GCLK

—

GCLK PLL

GCLK

—

GCLK PLL

Table 4–64 through Table 4–65 list EP1AGX50 regional clock (RCLK) adder values that

should be added to the GCLKvalues. These adder values are used to determine I/O

timing when the I/O pin is driven using the regional clock. This applies for all I/O

standards supported by Arria GX with general purpose I/O pins.

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–59

Typical Design Performance

Table 4–64 lists row pin delay adders when using the regional clock in Arria GX

devices.

Table 4–64. EP1AGX50 Row Pin Delay Adders for Regional Clock

Fast Corner

Parameter

–6 Speed Grade

Units

Industrial

Commercial

RCLKinput adder

0.151

0.329

0.016

ns

RCLKPLL input adder

RCLKoutput adder

RCLKPLL output adder

0.011

–0.151

–0.011

–0.151

–0.011

–0.329

–0.016

Table 4–65 lists column pin delay adders when using the regional clock in Arria GX

devices.

Table 4–65. EP1AGX50 Column Pin Delay Adders for Regional Clock

Fast Corner

Parameter

–6 Speed Grade

Units

Industrial

0.146

Commercial

0.146

RCLKinput adder

0.334

–3.645

–0.336

4.488

ns

RCLKPLL input adder

RCLKoutput adder

RCLKPLL output adder

–1.713

–0.146

1.716

–1.713

–0.146

1.716

EP1AGX60 I/O Timing Parameters

Table 4–66 through Table 4–69 list the maximum I/O timing parameters for

EP1AGX60 devices for I/O standards which support general purpose I/O pins.

Table 4–66 lists I/O timing specifications.

Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 1 of 3)

Fast Model

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

Commercial

1.413

GCLK

t_SU

t_H

1.413

–1.308

2.975

3.113

–2.836

6.536

ns

–1.308

2.975

3.3-V LVTTL

GCLK PLL

GCLK

t_SU

t_H

–2.870

1.413

–2.870

1.413

–6.259

3.113

t_SU

t_H

–1.308

2.975

–1.308

2.975

–2.836

6.536

3.3-V LVCMOS

2.5 V

GCLK PLL

GCLK

t_SU

t_H

–2.870

1.425

–2.870

1.425

–6.259

3.094

t_SU

t_H

–1.320

2.987

–1.320

2.987

–2.817

6.517

GCLK PLL

t_SU

t_H

–2.882

–6.240

Arria GX Device Handbook, Volume 1

4–60

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 2 of 3)

Fast Model

Industrial Commercial

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

GCLK

t_SU

t_H

1.477

–1.372

3.049

1.477

–1.372

3.049

3.275

–2.998

6.718

ns

1.8 V

1.5 V

GCLK PLL

GCLK

t_SU

t_H

–2.944

1.480

–2.944

1.480

–6.441

3.370

t_SU

t_H

–1.375

3.052

–1.375

3.052

–3.093

6.813

GCLK PLL

GCLK

t_SU

t_H

–2.947

1.237

–2.947

1.237

–6.536

2.566

t_SU

t_H

–1.132

2.800

–1.132

2.800

–2.289

5.990

SSTL-2 CLASS I

GCLK PLL

GCLK

t_SU

t_H

–2.695

1.237

–2.695

1.237

–5.713

2.566

t_SU

t_H

–1.132

2.800

–1.132

2.800

–2.289

5.990

SSTL-2 CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.695

1.255

–2.695

1.255

–5.713

2.649

t_SU

t_H

–1.150

2.827

–1.150

2.827

–2.372

6.092

SSTL-18 CLASS I

SSTL-18 CLASS II

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

GCLK PLL

GCLK

t_SU

t_H

–2.722

1.255

–2.722

1.255

–5.815

2.649

t_SU

t_H

–1.150

2.827

–1.150

2.827

–2.372

6.092

GCLK PLL

GCLK

t_SU

t_H

–2.722

1.255

–2.722

1.255

–5.815

2.649

t_SU

t_H

–1.150

2.827

–1.150

2.827

–2.372

6.092

GCLK PLL

GCLK

t_SU

t_H

–2.722

1.255

–2.722

1.255

–5.815

2.649

t_SU

t_H

–1.150

2.827

–1.150

2.827

–2.372

6.092

GCLK PLL

GCLK

t_SU

t_H

–2.722

1.281

–2.722

1.281

–5.815

2.777

t_SU

t_H

–1.176

2.853

–1.176

2.853

–2.500

6.220

GCLK PLL

t_SU

t_H

–2.748

–5.943

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–61

Typical Design Performance

Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 3 of 3)

Fast Model

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

Commercial

1.281

GCLK

t_SU

t_H

1.281

–1.176

2.853

2.777

–2.500

6.220

ns

–1.176

2.853

1.5-V HSTL CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.748

1.208

–2.748

1.208

–5.943

2.664

t_SU

t_H

–1.103

2.767

–1.103

2.767

–2.387

6.083

LVDS

GCLK PLL

t_SU

t_H

–2.662

–5.806

Table 4–67 lists I/O timing specifications.

Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 1 of 3)

Fast Corner

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

1.124

Commercial

1.124

GCLK

t_SU

t_H

2.493

-2.216

5.928

-5.651

2.493

-2.216

5.928

-5.651

2.475

-2.198

5.910

-5.633

2.685

-2.408

6.120

-5.843

2.778

-2.501

6.213

-5.936

1.951

-1.674

5.388

-5.111

ns

–1.019

2.694

–1.019

2.694

3.3-V LVTTL

GCLK PLL

GCLK

t_SU

t_H

–2.589

1.124

–2.589

1.124

t_SU

t_H

–1.019

2.694

–1.019

2.694

3.3-V LVCMOS

2.5 V

GCLK PLL

GCLK

t_SU

t_H

–2.589

1.134

–2.589

1.134

t_SU

t_H

–1.029

2.704

–1.029

2.704

GCLK PLL

GCLK

t_SU

t_H

–2.599

1.200

–2.599

1.200

t_SU

t_H

–1.095

2.770

–1.095

2.770

1.8 V

GCLK PLL

GCLK

t_SU

t_H

–2.665

1.203

–2.665

1.203

t_SU

t_H

–1.098

2.773

–1.098

2.773

1.5 V

GCLK PLL

GCLK

t_SU

t_H

–2.668

0.948

–2.668

0.948

t_SU

t_H

–0.843

2.519

–0.843

2.519

SSTL-2 CLASS I

GCLK PLL

t_SU

t_H

–2.414

Arria GX Device Handbook, Volume 1

4–62

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 2 of 3)

Fast Corner

Industrial Commercial

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

GCLK

t_SU

t_H

0.948

–0.843

2.519

0.948

–0.843

2.519

–2.414

0.986

–0.881

2.556

–2.451

0.987

–0.882

2.558

–2.453

0.986

–0.881

2.556

–2.451

0.987

–0.882

2.558

–2.453

1.004

–0.899

2.574

–2.469

1.005

–0.900

2.576

–2.471

1.129

–1.024

2.699

–2.594

1.129

–1.024

2.699

–2.594

1.951

–1.674

5.388

–5.111

2.057

–1.780

5.492

–5.215

2.058

–1.781

5.495

–5.218

2.057

–1.780

5.492

–5.215

2.058

–1.781

5.495

–5.218

2.185

–1.908

5.620

–5.343

2.186

–1.909

5.623

–5.346

2.481

–2.204

5.916

–5.639

2.481

–2.204

5.916

–5.639

ns

SSTL-2 CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.414

0.986

t_SU

t_H

–0.881

2.556

SSTL-18 CLASS I

SSTL-18 CLASS II

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

1.5-V HSTL CLASS II

3.3-V PCI

GCLK PLL

GCLK

t_SU

t_H

–2.451

0.987

t_SU

t_H

–0.882

2.558

GCLK PLL

GCLK

t_SU

t_H

–2.453

0.986

t_SU

t_H

–0.881

2.556

GCLK PLL

GCLK

t_SU

t_H

–2.451

0.987

t_SU

t_H

–0.882

2.558

GCLK PLL

GCLK

t_SU

t_H

–2.453

1.004

t_SU

t_H

–0.899

2.574

GCLK PLL

GCLK

t_SU

t_H

–2.469

1.005

t_SU

t_H

–0.900

2.576

GCLK PLL

GCLK

t_SU

t_H

–2.471

1.129

t_SU

t_H

–1.024

2.699

GCLK PLL

GCLK

t_SU

t_H

–2.594

1.129

t_SU

t_H

–1.024

2.699

3.3-V PCI-X

GCLK PLL

t_SU

t_H

–2.594

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–63

Typical Design Performance

Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 3 of 3)

Fast Corner

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

Commercial

0.980

GCLK

t_SU

t_H

0.980

–0.875

2.557

2.062

–1.785

5.512

ns

–0.875

2.557

LVDS

GCLK PLL

t_SU

t_H

–2.452

–5.235

Table 4–68 lists I/O timing specifications.

Table 4–68. EP1AGX60 Row Pins Output Timing Parameters (Part 1 of 2)

Fast Model

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

3.052

1.490

2.924

1.362

2.868

1.306

2.924

1.362

2.818

1.256

2.907

1.345

2.804

1.242

2.785

1.223

2.991

1.419

2.980

1.408

2.869

1.297

2.838

1.266

2.951

1.379

2.844

1.272

Commercial

3.052

1.490

2.924

1.362

2.868

1.306

2.924

1.362

2.818

1.256

2.907

1.345

2.804

1.242

2.785

1.223

2.991

1.419

2.980

1.408

2.869

1.297

2.838

1.266

2.951

1.379

2.844

1.272

4 mA

8 mA

12 mA

4 mA

8 mA

4 mA

8 mA

12 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

GCLK

GCLK PLL

GCLK

t_CO

7.142

3.719

6.502

3.079

6.465

3.042

6.502

3.079

6.196

2.773

6.476

3.053

6.218

2.795

6.104

2.681

7.521

4.078

6.742

3.299

6.441

2.998

6.327

2.884

7.020

3.577

6.419

2.976

ns

3.3-V LVTTL

GCLK PLL

GCLK

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

2.5 V

GCLK PLL

GCLK

2.5 V

GCLK PLL

GCLK

GCLK PLL

GCLK

1.8 V

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

1.5 V

GCLK PLL

GCLK

GCLK PLL

Arria GX Device Handbook, Volume 1

4–64

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–68. EP1AGX60 Row Pins Output Timing Parameters (Part 2 of 2)

Fast Model

Commercial

Drive

Strength

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

2.774

1.211

2.750

1.187

2.716

1.153

2.776

1.204

2.780

1.208

2.756

1.184

2.759

1.187

2.757

1.185

2.760

1.188

2.742

1.170

2.746

1.174

2.737

1.165

2.756

1.184

2.759

1.187

2.744

1.172

2.787

1.228

8 mA

12 mA

16 mA

4 mA

6 mA

8 mA

10 mA

4 mA

6 mA

8 mA

10 mA

12 mA

4 mA

6 mA

8 mA

—

GCLK

GCLK PLL

GCLK

t_CO

2.774

1.211

2.750

1.187

2.716

1.153

2.776

1.204

2.780

1.208

2.756

1.184

2.759

1.187

2.757

1.185

2.760

1.188

2.742

1.170

2.746

1.174

2.737

1.165

2.756

1.184

2.759

1.187

2.744

1.172

2.787

1.228

6.057

2.633

5.981

2.557

5.850

2.426

6.025

2.582

5.954

2.511

5.937

2.494

5.916

2.473

5.935

2.492

5.899

2.456

5.895

2.452

5.884

2.441

5.883

2.440

5.912

2.469

5.898

2.455

5.890

2.447

6.037

2.618

ns

SSTL-2

CLASS I

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

LVDS

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–65

Typical Design Performance

Table 4–69 lists I/O timing specifications.

Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 1 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

3.036

1.466

2.891

1.321

2.824

1.254

2.798

1.228

2.776

1.206

2.769

1.199

2.891

1.321

2.799

1.229

2.771

1.201

2.778

1.208

2.765

1.195

2.754

1.184

2.853

1.283

2.801

1.231

2.780

1.210

2.762

1.192

2.893

1.323

2.898

1.328

Commercial

3.036

1.466

2.891

1.321

2.824

1.254

2.798

1.228

2.776

1.206

2.769

1.199

2.891

1.321

2.799

1.229

2.771

1.201

2.778

1.208

2.765

1.195

2.754

1.184

2.853

1.283

2.801

1.231

2.780

1.210

2.762

1.192

2.893

1.323

2.898

1.328

4 mA

GCLK

GCLK PLL

GCLK

t_CO

6.963

3.528

6.591

3.156

6.591

3.156

6.422

2.987

6.297

2.862

6.299

2.864

6.591

3.156

6.296

2.861

6.218

2.783

6.186

2.751

6.168

2.733

6.146

2.711

6.623

3.188

6.361

2.926

6.244

2.809

6.170

2.735

7.615

4.180

6.841

3.406

ns

3.3-V LVTTL

8 mA

GCLK PLL

GCLK

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

8 mA

GCLK PLL

GCLK

3.3-V

LVCMOS

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

2.5 V

1.8 V

GCLK PLL

GCLK

8 mA

GCLK PLL

GCLK

12 mA

16 mA

2 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

4 mA

GCLK PLL

Arria GX Device Handbook, Volume 1

4–66

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 2 of 4)

Fast Corner

Commercial

Drive

Strength

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

2.822

1.252

2.824

1.254

2.778

1.208

2.779

1.209

2.873

1.303

2.809

1.239

2.812

1.242

2.771

1.201

2.757

1.184

2.740

1.167

2.718

1.145

2.719

1.146

2.715

1.142

2.753

1.183

2.758

1.185

2.737

1.164

2.742

1.169

2.736

1.163

2.725

1.152

6 mA

GCLK

GCLK PLL

GCLK

t_CO

2.822

1.252

2.824

1.254

2.778

1.208

2.779

1.209

2.873

1.303

2.809

1.239

2.812

1.242

2.771

1.201

2.757

1.184

2.740

1.167

2.718

1.145

2.719

1.146

2.715

1.142

2.753

1.183

2.758

1.185

2.737

1.164

2.742

1.169

2.736

1.163

2.725

1.152

6.577

3.142

6.486

3.051

6.409

2.974

6.352

2.917

7.145

3.710

6.576

3.141

6.458

3.023

6.405

2.970

6.184

2.744

6.134

2.694

6.061

2.621

6.048

2.608

6.046

2.606

6.155

2.720

6.116

2.676

6.097

2.657

6.095

2.655

6.081

2.641

6.047

2.607

ns

1.8 V

8 mA

GCLK PLL

GCLK

10 mA

12 mA

2 mA

1.8 V

GCLK PLL

GCLK

GCLK PLL

GCLK

1.5 V

GCLK PLL

GCLK

4 mA

GCLK PLL

GCLK

6 mA

GCLK PLL

GCLK

8 mA

GCLK PLL

GCLK

8 mA

SSTL-2

CLASS I

GCLK PLL

GCLK

12 mA

16 mA

20 mA

24 mA

4 mA

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

6 mA

SSTL-18

CLASS I

GCLK PLL

GCLK

8 mA

SSTL-18

CLASS I

GCLK PLL

GCLK

10 mA

12 mA

8 mA

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–67

Typical Design Performance

Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 3 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.737

1.164

2.733

1.160

2.733

1.160

2.756

1.186

2.762

1.189

2.740

1.167

2.744

1.171

2.736

1.163

2.719

1.146

2.721

1.148

2.721

1.148

2.756

1.186

2.761

1.188

2.743

1.170

2.743

1.170

2.737

1.164

2.724

1.151

2.727

1.154

2.729

1.156

Commercial

2.737

1.164

2.733

1.160

2.733

1.160

2.756

1.186

2.762

1.189

2.740

1.167

2.744

1.171

2.736

1.163

2.719

1.146

2.721

1.148

2.721

1.148

2.756

1.186

2.761

1.188

2.743

1.170

2.743

1.170

2.737

1.164

2.724

1.151

2.727

1.154

2.729

1.156

16 mA

18 mA

20 mA

4 mA

GCLK

GCLK PLL

GCLK

t_CO

6.025

2.585

6.033

2.593

6.031

2.591

6.086

2.651

6.071

2.631

6.060

2.620

6.066

2.626

6.059

2.619

5.823

2.383

5.834

2.394

5.843

2.403

6.085

2.650

6.063

2.623

6.065

2.625

6.067

2.627

6.065

2.625

5.877

2.437

5.887

2.447

5.900

2.460

ns

SSTL-18

CLASS II

SSTL-18

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

6 mA

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

8 mA

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

10 mA

12 mA

16 mA

18 mA

20 mA

4 mA

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

6 mA

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

8 mA

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

10 mA

12 mA

16 mA

18 mA

20 mA

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

Arria GX Device Handbook, Volume 1

4–68

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 4 of 4)

Fast Corner

Drive

–6 Speed

Units

I/O Standard

Clock

Parameter

Strength

Grade

Industrial

2.882

Commercial

—

GCLK

GCLK PLL

GCLK

t_CO

2.882

1.312

2.882

1.312

3.746

2.185

6.213

2.778

6.213

2.778

7.396

3.973

ns

3.3-V PCI

3.3-V PCI-X

LVDS

1.312

2.882

GCLK PLL

GCLK

1.312

3.746

GCLK PLL

2.185

Table 4–70 through Table 4–71 list EP1AGX60 regional clock (RCLK) adder values that

should be added to the GCLKvalues. These adder values are used to determine I/O

timing when the I/O pin is driven using the regional clock. This applies for all I/O

standards supported by Arria GX with general purpose I/O pins.

Table 4–70 describes row pin delay adders when using the regional clock in Arria GX

devices.

Table 4–70. EP1AGX60 Row Pin Delay Adders for Regional Clock

Fast Corner

Parameter

–6 Speed Grade

Units

Industrial

0.138

Commercial

0.138

RCLKinput adder

0.311

–0.006

–0.311

0.006

ns

RCLKPLL input adder

RCLKoutput adder

RCLKPLL output adder

–0.003

–0.138

0.003

–0.003

–0.138

0.003

Table 4–71 lists column pin delay adders when using the regional clock in Arria GX

devices.

Table 4–71. EP1AGX60 Column Pin Delay Adders for Regional Clock

Fast Corner

Parameter

–6 Speed Grade

Units

Industrial

0.153

Commercial

0.153

RCLKinput adder

0.344

–2.338

–0.343

4.486

ns

RCLKPLL input adder

RCLKoutput adder

RCLKPLL output adder

–1.066

–0.153

1.721

–1.066

–0.153

1.721

EP1AGX90 I/O Timing Parameters

Table 4–72 through Table 4–75 list the maximum I/O timing parameters for

EP1AGX90 devices for I/O standards which support general purpose I/O pins.

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–69

Typical Design Performance

Table 4–72 lists I/O timing specifications.

Table 4–72. EP1AGX90 Row Pins Input Timing Parameters (Part 1 of 2)

Fast Model

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

1.295

Commercial

1.295

GCLK

t_SU

t_H

2.873

–2.596

7.017

–6.740

2.873

–2.596

7.017

–6.740

2.854

–2.577

6.998

–6.721

3.073

–2.796

7.191

–6.914

3.168

–2.891

7.286

–7.009

2.329

–2.052

6.466

–6.189

2.329

–2.052

6.466

–6.189

2.447

–2.170

6.565

–6.288

2.441

–2.164

6.597

–6.320

ns

–1.190

3.366

–1.190

3.366

3.3-V LVTTL

GCLK PLL

GCLK

t_SU

t_H

–3.261

1.295

–3.261

1.295

t_SU

t_H

–1.190

3.366

–1.190

3.366

3.3-V LVCMOS

2.5 V

GCLK PLL

t_SU

t_H

–3.261

1.307

–3.261

1.307

t_SU

t_H

GCLK

GCLK PLL

GCLK

–1.202

3.378

–1.202

3.378

t_SU

t_H

–3.273

1.381

–3.273

1.381

t_SU

t_H

–1.276

3.434

–1.276

3.434

1.8 V

t_SU

t_H

GCLK PLL

GCLK

–3.329

1.384

–3.329

1.384

t_SU

t_H

–1.279

3.437

–1.279

3.437

1.5 V

t_SU

t_H

GCLK PLL

GCLK

–3.332

1.121

–3.332

1.121

t_SU

t_H

–1.016

3.187

–1.016

3.187

SSTL-2 CLASS I

SSTL-2 CLASS II

SSTL-18 CLASS I

SSTL-18 CLASS II

t_SU

t_H

GCLK PLL

GCLK

–3.082

1.121

–3.082

1.121

t_SU

t_H

–1.016

3.187

–1.016

3.187

t_SU

t_H

GCLK PLL

GCLK

–3.082

1.159

–3.082

1.159

t_SU

t_H

–1.054

3.212

–1.054

3.212

t_SU

t_H

GCLK PLL

GCLK

–3.107

1.157

–3.107

1.157

t_SU

t_H

–1.052

3.235

–1.052

3.235

GCLK PLL

t_SU

t_H

–3.130

Arria GX Device Handbook, Volume 1

4–70

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–72. EP1AGX90 Row Pins Input Timing Parameters (Part 2 of 2)

Fast Model

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

1.159

Commercial

1.159

GCLK

t_SU

t_H

2.447

–2.170

6.565

–6.288

2.441

–2.164

6.597

–6.320

2.575

–2.298

6.693

–6.416

2.569

–2.292

6.725

–6.448

2.439

–2.162

6.566

–6.289

ns

–1.054

3.212

–1.054

3.212

1.8-V HSTL CLASS I

GCLK PLL

GCLK

t_SU

t_H

–3.107

1.157

–3.107

1.157

t_SU

t_H

–1.052

3.235

–1.052

3.235

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

1.5-V HSTL CLASS II

LVDS

GCLK PLL

GCLK

t_SU

t_H

–3.130

1.185

–3.130

1.185

t_SU

t_H

–1.080

3.238

–1.080

3.238

GCLK PLL

GCLK

t_SU

t_H

–3.133

1.183

–3.133

1.183

t_SU

t_H

–1.078

3.261

–1.078

3.261

GCLK PLL

GCLK

t_SU

t_H

–3.156

1.098

–3.156

1.098

t_SU

t_H

–0.993

3.160

–0.993

3.160

GCLK PLL

t_SU

t_H

–3.055

Table 4–73 lists I/O timing specifications.

\

Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 1 of 3)

Fast Corner

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

1.018

Commercial

1.018

GCLK

t_SU

t_H

2.290

–2.013

6.425

ns

–0.913

3.082

–0.913

3.082

3.3-V LVTTL

GCLK PLL

GCLK

t_SU

t_H

–2.977

1.018

–2.977

1.018

–6.148

2.290

t_SU

t_H

–0.913

3.082

–0.913

3.082

–2.013

6.425

3.3-V LVCMOS

2.5 V

GCLK PLL

GCLK

t_SU

t_H

–2.977

1.028

–2.977

1.028

–6.148

2.272

t_SU

t_H

–0.923

3.092

–0.923

3.092

–1.995

6.407

GCLK PLL

t_SU

t_H

–2.987

–6.130

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–71

Typical Design Performance

Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 2 of 3)

Fast Corner

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

1.094

Commercial

1.094

GCLK

t_SU

t_H

2.482

–2.205

6.617

ns

–0.989

3.158

–0.989

3.158

1.8 V

GCLK PLL

GCLK

t_SU

t_H

–3.053

1.097

–3.053

1.097

–6.340

2.575

t_SU

t_H

–0.992

3.161

–0.992

3.161

–2.298

6.710

1.5 V

GCLK PLL

GCLK

t_SU

t_H

–3.056

0.844

–3.056

0.844

–6.433

1.751

t_SU

t_H

–0.739

2.908

–0.739

2.908

–1.474

5.886

SSTL-2 CLASS I

SSTL-2 CLASS II

SSTL-18 CLASS I

SSTL-18 CLASS II

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

GCLK PLL

GCLK

t_SU

t_H

–2.803

0.844

–2.803

0.844

–5.609

1.751

t_SU

t_H

–0.739

2.908

–0.739

2.908

–1.474

5.886

GCLK PLL

GCLK

t_SU

t_H

–2.803

0.880

–2.803

0.880

–5.609

1.854

t_SU

t_H

–0.775

2.944

–0.775

2.944

–1.577

5.989

GCLK PLL

GCLK

t_SU

t_H

–2.839

0.883

–2.839

0.883

–5.712

1.858

t_SU

t_H

–0.778

2.947

–0.778

2.947

–1.581

5.993

GCLK PLL

GCLK

t_SU

t_H

–2.842

0.880

–2.842

0.880

–5.716

1.854

t_SU

t_H

–0.775

2.944

–0.775

2.944

–1.577

5.989

GCLK PLL

GCLK

t_SU

t_H

–2.839

0.883

–2.839

0.883

–5.712

1.858

t_SU

t_H

–0.778

2.947

–0.778

2.947

–1.581

5.993

GCLK PLL

GCLK

t_SU

t_H

–2.842

0.898

–2.842

0.898

–5.716

1.982

t_SU

t_H

–0.793

2.962

–0.793

2.962

–1.705

6.117

GCLK PLL

t_SU

t_H

–2.857

–5.840

Arria GX Device Handbook, Volume 1

4–72

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 3 of 3)

Fast Corner

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

0.901

Commercial

0.901

GCLK

t_SU

t_H

1.986

–1.709

6.121

ns

–0.796

2.965

–0.796

2.965

1.5-V HSTL CLASS II

GCLK PLL

GCLK

t_SU

t_H

–2.860

1.023

–2.860

1.023

–5.844

2.278

t_SU

t_H

–0.918

3.087

–0.918

3.087

–2.001

6.413

3.3-V PCI

3.3-V PCI-X

LVDS

GCLK PLL

GCLK

t_SU

t_H

–2.982

1.023

–2.982

1.023

–6.136

2.278

t_SU

t_H

–0.918

3.087

–0.918

3.087

–2.001

6.413

GCLK PLL

GCLK

t_SU

t_H

–2.982

0.891

–2.982

0.891

–6.136

1.920

t_SU

t_H

–0.786

2.963

–0.786

2.963

–1.643

6.066

GCLK PLL

t_SU

t_H

–2.858

–5.789

Table 4–74 lists I/O timing specifications.

Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 1 of 3)

Fast Model

Commercial

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

3.170

1.099

3.042

0.971

2.986

0.915

3.042

0.971

2.936

0.865

3.025

0.954

2.922

0.851

2.903

0.832

3.3-V LVTTL

4 mA

8 mA

12 mA

4 mA

8 mA

4 mA

8 mA

12 mA

GCLK

GCLK PLL

GCLK

t_CO

3.170

1.099

3.042

0.971

2.986

0.915

3.042

0.971

2.936

0.865

3.025

0.954

2.922

0.851

2.903

0.832

7.382

3.238

6.742

2.598

6.705

2.561

6.742

2.598

6.436

2.292

6.716

2.572

6.458

2.314

6.344

2.200

ns

3.3-V LVTTL

GCLK PLL

GCLK

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

2.5 V

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–73

Typical Design Performance

Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 2 of 3)

Fast Model

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

3.087

1.034

3.076

1.023

2.965

0.912

2.934

0.881

3.047

0.994

2.940

0.887

2.890

0.824

2.866

0.800

2.832

0.766

2.872

0.819

2.878

0.800

2.854

0.776

2.857

0.779

2.853

0.800

2.858

0.780

2.840

0.762

2.844

0.766

2.835

0.757

2.852

0.799

Commercial

3.087

1.034

3.076

1.023

2.965

0.912

2.934

0.881

3.047

0.994

2.940

0.887

2.890

0.824

2.866

0.800

2.832

0.766

2.872

0.819

2.878

0.800

2.854

0.776

2.857

0.779

2.853

0.800

2.858

0.780

2.840

0.762

2.844

0.766

2.835

0.757

2.852

0.799

1.8 V

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

8 mA

12 mA

16 mA

4 mA

6 mA

8 mA

10 mA

4 mA

6 mA

8 mA

10 mA

12 mA

4 mA

GCLK

GCLK PLL

GCLK

t_CO

7.723

3.605

6.944

2.826

6.643

2.525

6.529

2.411

7.222

3.104

6.621

2.503

6.294

2.157

6.218

2.081

6.087

1.950

6.227

2.109

6.162

2.006

6.145

1.989

6.124

1.968

6.137

2.019

6.107

1.951

6.103

1.947

6.092

1.936

6.091

1.935

6.114

1.996

ns

1.8 V

1.5 V

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS I

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

Arria GX Device Handbook, Volume 1

4–74

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 3 of 3)

Fast Model

Drive

–6 Speed

Units

I/O Standard

Clock

Parameter

Strength

Grade

Industrial

2.857

Commercial

6 mA

8 mA

—

GCLK

GCLK PLL

GCLK

t_CO

2.857

0.779

2.842

0.764

2.898

0.831

6.106

1.950

6.098

1.942

6.265

2.129

ns

1.5-V HSTL

CLASS I

0.779

2.842

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

0.764

2.898

LVDS

GCLK PLL

0.831

Table 4–75 lists I/O timing specifications.

Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 1 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

3.141

1.077

2.996

0.932

2.929

0.865

2.903

0.839

2.881

0.817

2.874

0.810

2.996

0.932

2.904

0.840

2.876

0.812

2.883

0.819

2.870

0.806

2.859

0.795

2.958

0.894

Commercial

3.141

1.077

2.996

0.932

2.929

0.865

2.903

0.839

2.881

0.817

2.874

0.810

2.996

0.932

2.904

0.840

2.876

0.812

2.883

0.819

2.870

0.806

2.859

0.795

2.958

0.894

3.3-V LVTTL

4 mA

GCLK

GCLK PLL

GCLK

t_CO

7.164

3.029

6.792

2.657

6.792

2.657

6.623

2.488

6.498

2.363

6.500

2.365

6.792

2.657

6.497

2.362

6.419

2.284

6.387

2.252

6.369

2.234

6.347

2.212

6.824

2.689

ns

3.3-V LVTTL

8 mA

GCLK PLL

GCLK

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

8 mA

GCLK PLL

GCLK

3.3-V

LVCMOS

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

3.3-V

LVCMOS

GCLK PLL

GCLK

2.5 V

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–75

Typical Design Performance

Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 2 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.906

0.842

2.885

0.821

2.867

0.803

2.998

0.934

3.003

0.939

2.927

0.863

2.929

0.865

2.883

0.819

2.884

0.820

2.978

0.914

2.914

0.850

2.917

0.853

2.876

0.812

2.859

0.797

2.842

0.780

2.820

0.758

2.821

0.759

2.817

0.755

2.858

0.794

Commercial

2.906

0.842

2.885

0.821

2.867

0.803

2.998

0.934

3.003

0.939

2.927

0.863

2.929

0.865

2.883

0.819

2.884

0.820

2.978

0.914

2.914

0.850

2.917

0.853

2.876

0.812

2.859

0.797

2.842

0.780

2.820

0.758

2.821

0.759

2.817

0.755

2.858

0.794

2.5 V

8 mA

12 mA

16 mA

2 mA

GCLK

GCLK PLL

GCLK

t_CO

6.562

2.427

6.445

2.310

6.371

2.236

7.816

3.681

7.042

2.907

6.778

2.643

6.687

2.552

6.610

2.475

6.553

2.418

7.346

3.211

6.777

2.642

6.659

2.524

6.606

2.471

6.381

2.250

6.331

2.200

6.258

2.127

6.245

2.114

6.243

2.112

6.356

2.221

ns

2.5 V

1.8 V

1.5 V

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

4 mA

GCLK PLL

GCLK

6 mA

GCLK PLL

GCLK

8 mA

GCLK PLL

GCLK

10 mA

12 mA

2 mA

GCLK PLL

GCLK

GCLK PLL

GCLK

GCLK PLL

GCLK

4 mA

GCLK PLL

GCLK

6 mA

GCLK PLL

GCLK

8 mA

GCLK PLL

GCLK

SSTL-2

CLASS I

8 mA

GCLK PLL

GCLK

SSTL-2

CLASS I

12 mA

16 mA

20 mA

24 mA

4 mA

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-2

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

Arria GX Device Handbook, Volume 1

4–76

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 3 of 4)

Fast Corner

Commercial

Drive

Strength

–6 Speed

Units

I/O Standard

Clock

Parameter

Grade

Industrial

2.860

0.798

2.839

0.777

2.844

0.782

2.838

0.776

2.827

0.765

2.839

0.777

2.835

0.773

2.835

0.773

2.861

0.797

2.864

0.802

2.842

0.780

2.846

0.784

2.838

0.776

2.821

0.759

2.823

0.761

2.823

0.761

2.861

0.797

2.863

0.801

2.845

0.783

SSTL-18

CLASS I

6 mA

GCLK

GCLK PLL

GCLK

t_CO

2.860

0.798

2.839

0.777

2.844

0.782

2.838

0.776

2.827

0.765

2.839

0.777

2.835

0.773

2.835

0.773

2.861

0.797

2.864

0.802

2.842

0.780

2.846

0.784

2.838

0.776

2.821

0.759

2.823

0.761

2.823

0.761

2.861

0.797

2.863

0.801

2.845

0.783

6.313

2.182

6.294

2.163

6.292

2.161

6.278

2.147

6.244

2.113

6.222

2.091

6.230

2.099

6.228

2.097

6.287

2.152

6.268

2.137

6.257

2.126

6.263

2.132

6.256

2.125

6.020

1.889

6.031

1.900

6.040

1.909

6.286

2.151

6.260

2.129

6.262

2.131

ns

SSTL-18

CLASS I

8 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

10 mA

12 mA

8 mA

GCLK PLL

GCLK

SSTL-18

CLASS I

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS II

16 mA

18 mA

20 mA

4 mA

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

SSTL-18

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

6 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

8 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

10 mA

12 mA

16 mA

18 mA

20 mA

4 mA

GCLK PLL

GCLK

1.8-V HSTL

CLASS I

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.8-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

6 mA

GCLK PLL

GCLK

1.5-V HSTL

CLASS I

8 mA

GCLK PLL

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–77

Typical Design Performance

Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 4 of 4)

Fast Corner

Drive

Strength

–6 Speed

Grade

I/O Standard

Clock

Parameter

Units

Industrial

2.845

0.783

2.839

0.777

2.826

0.764

2.829

0.767

2.831

0.769

2.987

0.923

2.987

0.923

3.835

1.769

Commercial

2.845

0.783

2.839

0.777

2.826

0.764

2.829

0.767

2.831

0.769

2.987

0.923

2.987

0.923

3.835

1.769

1.5-V HSTL

CLASS I

10 mA

12 mA

16 mA

18 mA

20 mA

—

GCLK

GCLK PLL

GCLK

t_CO

6.264

2.133

6.262

2.131

6.074

1.943

6.084

1.953

6.097

1.966

6.414

2.279

6.414

2.279

7.541

3.404

ns

1.5-V HSTL

CLASS I

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

1.5-V HSTL

CLASS II

GCLK PLL

GCLK

3.3-V PCI

3.3-V PCI-X

LVDS

GCLK PLL

GCLK

—

GCLK PLL

GCLK

—

GCLK PLL

Table 4–76 through Table 4–77 list the EP1AGX90 regional clock (RCLK) adder values

that should be added to the GCLKvalues. These adder values are used to determine

I/O timing when the I/O pin is driven using the regional clock. This applies for all

I/O standards supported by Arria GX with general purpose I/O pins.

Table 4–76 lists row pin delay adders when using the regional clock in Arria GX

devices.

Table 4–76. EP1AGX90 Row Pin Delay Adders for Regional Clock

Fast Corner

Parameter

–6 Speed Grade

Units

Industrial

0.175

Commercial

0.175

RCLK input adder

0.418

0.015

ns

RCLK PLL input adder

RCLK output adder

RCLK PLL output adder

0.007

–0.175

–0.007

–0.175

–0.007

–0.418

–0.015

Arria GX Device Handbook, Volume 1

4–78

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–77 lists column pin delay adders when using the regional clock in Arria GX

devices.

Table 4–77. EP1AGX90 Column Pin Delay Adders for Regional Clock

Fast Corner

Parameter

–6 Speed Grade

Units

Industrial

0.138

Commercial

0.138

RCLK input adder

0.354

–3.607

–0.353

5.188

ns

RCLK PLL input adder

RCLKoutput adder

–1.697

–0.138

1.966

–1.697

–0.138

RCLK PLL output adder

1.966

Dedicated Clock Pin Timing

Table 4–79 through Table 4–98 list clock pin timing for Arria GX devices when the

clock is driven by the global clock, regional clock, periphery clock, and a PLL.

Table 4–78 lists Arria GX clock timing parameters.

Table 4–78. Arria GX Clock Timing Parameters

Symbol

Parameter

t_CIN

Delay from clock pad to I/O input register

Delay from clock pad to I/O output register

Delay from PLL inclkpad to I/O input register

Delay from PLL inclkpad to I/O output register

t_COUT

t_PLLCIN

t_PLLCOUT

EP1AGX20 Clock Timing Parameters

Table 4–79 through Table 4–80 list the GCLKclock timing parameters for EP1AGX20

devices.

Table 4–79 lists clock timing specifications.

Table 4–79. EP1AGX20 Row Pins Global Clock Timing Parameters

Fast Model

Parameter

tcin

–6 Speed Grade

Units

Industrial

1.394

Commercial

1.394

3.161

3.155

0.091

0.085

ns

tcout

1.399

tpllcin

tpllcout

–0.027

–0.022

–0.027

–0.022

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–79

Typical Design Performance

Table 4–80 lists clock timing specifications.

Table 4–80. EP1AGX20 Row Pins Global Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.655

Commercial

1.655

3.726

0.655

ns

t_COUT

1.655

t_PLLCIN

t_PLLCOUT

0.236

Table 4–81 through Table 4–82 list the RCLKclock timing parameters for EP1AGX20

devices.

Table 4–81 lists clock timing specifications.

Table 4–81. EP1AGX20 Row Pins Regional Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.283

Commercial

1.283

2.901

2.895

0.077

0.071

ns

t_COUT

1.288

t_PLLCIN

t_PLLCOUT

–0.034

–0.029

–0.034

–0.029

Table 4–82 lists clock timing specifications.

Table 4–82. EP1AGX20 Row Pins Regional Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.569

Commercial

1.569

3.487

0.706

ns

t_COUT

1.569

t_PLLCIN

t_PLLCOUT

0.278

EP1AGX35 Clock Timing Parameters

Table 4–83 through Table 4–84 list the GCLKclock timing parameters for EP1AGX35

devices.

Table 4–83 lists clock timing specifications.

Table 4–83. EP1AGX35 Row Pins Global Clock Timing Parameters (Part 1 of 2)

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.394

Commercial

1.394

3.161

3.155

ns

t_COUT

1.399

Arria GX Device Handbook, Volume 1

4–80

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–83. EP1AGX35 Row Pins Global Clock Timing Parameters (Part 2 of 2)

Fast Model

Parameter

–6 Speed Grade

Units

Industrial

Commercial

–0.027

t_PLLCIN

t_PLLCOUT

–0.027

–0.022

0.091

0.085

ns

–0.022

Table 4–84 lists clock timing specifications.

Table 4–84. EP1AGX35 Row Pins Global Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.655

Commercial

1.655

3.726

0.655

ns

t_COUT

1.655

t_PLLCIN

t_PLLCOUT

0.236

Table 4–85 through Table 4–86 list the RCLK clock timing parameters for EP1AGX35

devices.

Table 4–85 lists clock timing specifications.

Table 4–85. EP1AGX35 Row Pins Regional Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.283

Commercial

1.283

2.901

2.895

0.077

0.071

ns

t_COUT

1.288

t_PLLCIN

t_PLLCOUT

–0.034

–0.029

–0.034

–0.029

Table 4–86 lists clock timing specifications.

Table 4–86. EP1AGX35 Row Pins Regional Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.569

Commercial

1.569

3.487

0.706

ns

t_COUT

1.569

t_PLLCIN

t_PLLCOUT

0.278

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–81

Typical Design Performance

EP1AGX50 Clock Timing Parameters

Table 4–87 through Table 4–88 list the GCLKclock timing parameters for EP1AGX50

devices.

Table 4–87 lists clock timing specifications.

Table 4–87. EP1AGX50 Row Pins Global Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.529

Commercial

1.529

3.587

3.581

0.181

0.175

ns

t_COUT

1.534

t_PLLCIN

t_PLLCOUT

–0.024

–0.019

–0.024

–0.019

Table 4–88 lists clock timing specifications.

Table 4–88. EP1AGX50 Row Pins Global Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.793

Commercial

1.793

4.165

0.758

ns

t_COUT

1.793

t_PLLCIN

t_PLLCOUT

0.238

Table 4–89 through Table 4–90 list the RCLKclock timing parameters for EP1AGX50

devices.

Table 4–89 lists clock timing specifications.

Table 4–89. EP1AGX50 Row Pins Regional Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.396

Commercial

1.396

3.287

3.281

0.195

0.189

ns

t_COUT

1.401

t_PLLCIN

t_PLLCOUT

–0.017

–0.012

–0.017

–0.012

Arria GX Device Handbook, Volume 1

4–82

Chapter 4: DC and Switching Characteristics

Typical Design Performance

Table 4–90 lists clock timing specifications.

Table 4–90. EP1AGX50 Row Pins Regional Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.653

Commercial

1.653

3.841

3.839

0.755

ns

t_COUT

1.651

t_PLLCIN

t_PLLCOUT

0.245

EP1AGX60 Clock Timing Parameters

Table 4–91 to Table 4–92 on page 4–82 list the GCLKclock timing parameters for

EP1AGX60 devices.

Table 4–91 lists clock timing specifications.

Table 4–91. EP1AGX60 Row Pins Global Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.531

Commercial

1.531

3.593

3.587

0.188

0.182

ns

t_COUT

1.536

t_PLLCIN

t_PLLCOUT

–0.023

–0.018

–0.023

–0.018

Table 4–92 lists clock timing specifications.

Table 4–92. EP1AGX60 Row Pins Global Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.792

Commercial

1.792

4.165

0.758

ns

t_COUT

1.792

t_PLLCIN

t_PLLCOUT

0.238

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–83

Typical Design Performance

Table 4–93 through Table 4–94 list the RCLKclock timing parameters for EP1AGX60

devices.

Table 4–93 lists clock timing specifications.

Table 4–93. EP1AGX60 Row Pins Regional Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.382

Commercial

1.382

3.268

3.262

0.174

0.168

ns

t_COUT

1.387

t_PLLCIN

t_PLLCOUT

–0.031

–0.026

–0.031

–0.026

Table 4–94 lists clock timing specifications.

Table 4–94. EP1AGX60 Row Pins Regional Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.649

Commercial

1.649

3.835

3.839

0.755

ns

t_COUT

1.651

t_PLLCIN

t_PLLCOUT

0.245

EP1AGX90 Clock Timing Parameters

Table 4–95 through Table 4–96 list the GCLKclock timing parameters for EP1AGX90

devices.

Table 4–95 lists clock timing specifications.

Table 4–95. EP1AGX90 Row Pins Global Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.630

Commercial

1.630

3.799

3.793

ns

t_COUT

1.635

t_PLLCIN

t_PLLCOUT

–0.422

–0.417

–0.422

–0.417

–0.310

–0.316

Arria GX Device Handbook, Volume 1

4–84

Chapter 4: DC and Switching Characteristics

Block Performance

Table 4–96 lists clock timing specifications.

Table 4–96. EP1AGX90 Row Pins Global Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.904

Commercial

1.904

4.376

0.254

ns

t_COUT

1.904

t_PLLCIN

t_PLLCOUT

–0.153

Table 4–97 through Table 4–98 list the RCLKclock timing parameters for EP1AGX90

devices.

Table 4–97 lists clock timing specifications.

Table 4–97. EP1AGX90 Row Pins Regional Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.462

Commercial

1.462

3.407

3.401

ns

t_COUT

1.467

t_PLLCIN

t_PLLCOUT

–0.430

–0.425

–0.430

–0.425

–0.322

–0.328

Table 4–98 lists clock timing specifications.

Table 4–98. EP1AGX90 Row Pins Regional Clock Timing Parameters

Fast Model

Parameter

t_CIN

–6 Speed Grade

Units

Industrial

1.760

Commercial

1.760

4.011

0.303

ns

t_COUT

1.760

t_PLLCIN

t_PLLCOUT

–0.118

Block Performance

Table 4–99 shows the Arria GX performance for some common designs. All

performance values were obtained with the Quartus II software compilation of library

of parameterized modules (LPM) or MegaCore functions for finite impulse response

(FIR) and fast Fourier transform (FFT) designs.

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–85

Block Performance

Table 4–99 lists performance notes.

Table 4–99. Arria GX Performance Notes

Resources Used

Performance

Applications

TriMatrix

Memory Blocks

ALUTs

DSP Blocks

–6 Speed Grade

16-to-1

multiplexer

5

0

168.41

32-to-1

11

0

334.11

LE

multiplexer

16-bit counter

64-bit counter

Simple dual-port

16

64

0

1

0

374.0

168.41

348.0

TriMatrix Memory

RAM 32 x 18 bit

M512 block

FIFO 32 x 18 bit

0

1

0

333.22

344.71

Simple dual-port

RAM 128 x 36 bit

TriMatrix Memory

M4K block

True dual-port

0

1

2

1

2

1

0

348.0

244.0

292.0

244.0

247.0

292.0

254.0

292.0

251.0

317.36

292.0

251.0

254.0

292.0

251.0

RAM 128 x 18 bit

Single port RAM

4K x 144 bit

Simple dual-port

RAM 4K x 144 bit

True dual-port

RAM 4K x 144 bit

Single port RAM

8K x 72 bit

TriMatrix Memory Simple dual-port

MegaRAM block

RAM 8K x 72 bit

Single port RAM

16K x 36 bit

Simple dual-port

RAM 16K x 36 bit

True dual-port

RAM 16K x 36 bit

Single port RAM

32K x 18 bit

Simple dual-port

RAM 32K x 18 bit

True dual-port

RAM 32K x 18 bit

Single port RAM

64K x 9 bit

Simple dual-port

RAM 64K x 9 bit

True dual-port

RAM 64K x 9 bit

Arria GX Device Handbook, Volume 1

4–86

Chapter 4: DC and Switching Characteristics

IOE Programmable Delay

Table 4–99. Arria GX Performance Notes

Resources Used

Performance

Applications

TriMatrix

Memory Blocks

ALUTs

DSP Blocks

–6 Speed Grade

9 x 9-bit

multiplier

0

1

335.35

18 x 18-bit

multiplier

0

2

4

8

4

285.0

335.35

174.4

285.0

163.0

18 x 18-bit

multiplier

DSP block

36 x 36-bit

multiplier

36 x 36-bit

multiplier

18-bit 4-tap FIR

filter

8-bit 16-tap

Larger Designs

parallel FIR filter

IOE Programmable Delay

For IOE programmable delay, refer to Table 4–100 through Table 4–101.

Table 4–100 lists IOE programmable delays.

Table 4–100. Arria GX IOE Programmable Delay on Row Pins

Fast Model

Industrial Commercial

–6 Speed Grade

Available

Settings

Parameter

Paths Affected

Units

Min

Max

Offset

Min

Offset

Max

Offset

Min

Max

Offset

Input delay

from pin to

internal cells

Pad to I/O dataout

to core

8

64

2

0

1.782

0

1.782

2.054

0.332

0

4.124

4.689

0.717

ns

Input delay

from pin to

input register

Pad to I/O input

register

0

2.054

0.332

0

Delay from I/O output register

output

register to

output pin

to pad

txz/tzx

Output

enable pin

delay

2

0

0.32

0

0.32

0

0.693

ns

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–87

Maximum Input and Output Clock Toggle Rate

Table 4–101 lists IOE programmable delays.

Table 4–101. Arria GX IOE Programmable Delay on Column Pins

Fast Model

Industrial Commercial

Min Max Min Max

–6 Speed Grade

Available

Settings

Parameter

Paths Affected

Units

Min

Max

Offset

Offset Offset Offset Offset Offset

Input delay

from pin to

internal cells

Pad to I/O dataout to

core

8

64

2

0

1.781

2.053

0.332

0

1.781

2.053

0.332

0

4.132

4.697

0.717

ns

Input delay

from pin to

input register

Pad to I/O input register

Delay from

output

I/O output register to

pad

register to

output pin

Output

enable pin

delay

txz/tzx

2

0

0.32

0

0.32

0

0.693

ns

Maximum Input and Output Clock Toggle Rate

Maximum clock toggle rate is defined as the maximum frequency achievable for a

clock type signal at an I/O pin. The I/O pin can be a regular I/O pin or a dedicated

clock I/O pin.

The maximum clock toggle rate is different from the maximum data bit rate. If the

maximum clock toggle rate on a regular I/O pin is 300 MHz, the maximum data bit

rate for dual data rate (DDR) could be potentially as high as 600 Mbps on the same

I/O pin.

Table 4–105, Table 4–106, and Table 4–107 provide output toggle rates at the default

capacitive loading. Use the Quartus II software to obtain output toggle rates at loads

different from the default capacitive loading.

Table 4–102 shows the maximum input clock toggle rates for Arria GX device column

I/O pins.

Table 4–102. Arria GX Maximum Input Toggle Rate for Column I/O Pins

I/O Standards

3.3-V LVTTL

–6 Speed Grade

Units

MHz

420

467

3.3-V LVCMOS

2.5 V

1.8 V

1.5 V

SSTL-2 CLASS I

SSTL-2 CLASS II

SSTL-18 CLASS I

Arria GX Device Handbook, Volume 1

4–88

Chapter 4: DC and Switching Characteristics

Maximum Input and Output Clock Toggle Rate

Table 4–102. Arria GX Maximum Input Toggle Rate for Column I/O Pins

I/O Standards

SSTL-18 CLASS II

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

1.5-V HSTL CLASS II

3.3-V PCI

–6 Speed Grade

Units

MHz

467

420

3.3-V PCI-X

Table 4–103 shows the maximum input clock toggle rates for Arria GX device row I/O

pins.

Table 4–103. Arria GX Maximum Input Toggle Rate for Row I/O Pins

I/O Standards

3.3-V LVTTL

–6 Speed Grade

Units

MHz

420

467

392

3.3-V LVCMOS

2.5 V

1.8 V

1.5 V

SSTL-2 CLASS I

SSTL-2 CLASS II

SSTL-18 CLASS I

SSTL-18 CLASS II

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

1.5-V HSTL CLASS II

LVDS

Table 4–104 shows the maximum input clock toggle rates for Arria GX device

dedicated clock pins.

Table 4–104. Arria GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 1 of 2)

I/O Standards

3.3-V LVTTL

–6 Speed Grade

Units

MHz

373

467

373

3.3-V LVCMOS

2.5 V

1.8 V

1.5 V

SSTL-2 CLASS I

SSTL-2 CLASS II

3.3-V PCI

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–89

Maximum Input and Output Clock Toggle Rate

Table 4–104. Arria GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 2 of 2)

I/O Standards

–6 Speed Grade

Units

MHz

3.3-V PCI-X

373

467

233

467

SSTL-18 CLASS I

SSTL-18 CLASS II

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

1.5-V HSTL CLASS II

1.2-V HSTL

DIFFERENTAL SSTL-2

DIFFERENTIAL 2.5-V

SSTL CLASS II

DIFFERENTIAL 1.8-V

SSTL CLASS I

467

MHz

DIFFERENTIAL 1.8-V

SSTL CLASS II

DIFFERENTIAL 1.8-V

HSTL CLASS I

DIFFERENTIAL 1.8-V

HSTL CLASS II

DIFFERENTIAL 1.5-V

HSTL CLASS I

467

233

MHz

DIFFERENTIAL 1.5-V

HSTL CLASS II

DIFFERENTIAL 1.2-V

HSTL

LVDS

640

373

MHz

LVDS (1)

Note to Table 4–104:

(1) This set of numbers refers to the VIO dedicated input clock pins.

Table 4–105 shows the maximum output clock toggle rates for Arria GX device

column I/O pins.

Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 1 of 3)

I/O Standards

Drive Strength

4 mA

–6 Speed Grade

Units

MHz

196

303

393

486

570

626

8 mA

12 mA

3.3-V LVTTL

16 mA

20 mA

24 mA

Arria GX Device Handbook, Volume 1

4–90

Chapter 4: DC and Switching Characteristics

Maximum Input and Output Clock Toggle Rate

Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 2 of 3)

I/O Standards

Drive Strength

4 mA

–6 Speed Grade

215

411

626

819

874

934

168

355

514

766

97

Units

MHz

8 mA

12 mA

16 mA

20 mA

24 mA

4 mA

3.3-V LVCMOS

8 mA

2.5 V

1.8 V

1.5 V

12 mA

16 mA

2 mA

4 mA

215

336

486

706

925

168

303

350

392

280

327

280

327

140

186

280

373

140

327

373

420

280

420

561

607

6 mA

8 mA

10 mA

12 mA

2 mA

4 mA

6 mA

8 mA

SSTL-2 CLASS I

SSTL-2 CLASS II

12 mA

16 mA

20 mA

24 mA

4 mA

6 mA

SSTL-18 CLASS I

SSTL-18 CLASS II

1.8-V HSTL CLASS I

8 mA

10 mA

12 mA

8 mA

16 mA

18 mA

20 mA

4 mA

6 mA

8 mA

10 mA

12 mA

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–91

Maximum Input and Output Clock Toggle Rate

Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 3 of 3)

I/O Standards

Drive Strength

16 mA

18 mA

20 mA

4 mA

–6 Speed Grade

Units

MHz

420

467

514

280

420

561

607

654

514

561

626

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

1.5-V HSTL CLASS II

6 mA

8 mA

10 mA

12 mA

16 mA

18 mA

20 mA

—

3.3-V PCI

3.3-V PCI-X

—

Table 4–106 shows the maximum output clock toggle rates for Arria GX device row

I/O pins.

Table 4–106. Arria GX Maximum Output Toggle Rate for Row I/O Pins

I/O Standards

Drive Strength

4 mA

–6 Speed Grade

196

Units

MHz

3.3-V LVTTL

8 mA

303

12 mA

4 mA

393

215

3.3-V LVCMOS

2.5 V

8 mA

411

4 mA

168

8 mA

355

12 mA

2 mA

514

97

4 mA

215

1.8 V

1.5 V

6 mA

336

8 mA

486

2 mA

168

4 mA

303

8 mA

280

SSTL-2 CLASS I

SSTL-2 CLASS II

12 mA

16 mA

4 mA

327

280

140

6 mA

186

SSTL-18 CLASS I

8 mA

280

10 mA

373

Arria GX Device Handbook, Volume 1

4–92

Chapter 4: DC and Switching Characteristics

Maximum Input and Output Clock Toggle Rate

Table 4–106. Arria GX Maximum Output Toggle Rate for Row I/O Pins

I/O Standards

Drive Strength

4 mA

–6 Speed Grade

Units

MHz

280

420

561

607

280

420

561

598

6 mA

1.8-V HSTL CLASS I

8 mA

10 mA

12 mA

4 mA

1.5-V HSTL CLASS I

LVDS

6 mA

8 mA

—

Table 4–107 lists maximum output clock rate for dedicated clock pins.

Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 1 of 4)

I/O Standards

Drive Strength

4 mA

–6 Speed Grade

196

Units

MHz

8 mA

303

12 mA

16 mA

20 mA

24 mA

4 mA

393

3.3-V LVTTL

486

570

626

215

8 mA

411

12 mA

16 mA

20 mA

24 mA

4 mA

626

3.3-V LVCMOS

819

874

934

168

8 mA

355

2.5 V

12 mA

16 mA

2 mA

514

766

97

4 mA

215

6 mA

336

1.8 V

8 mA

486

10 mA

12 mA

2 mA

706

925

168

4 mA

303

1.5 V

6 mA

350

8 mA

392

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–93

Maximum Input and Output Clock Toggle Rate

Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 2 of 4)

I/O Standards

Drive Strength

8 mA

–6 Speed Grade

280

327

280

327

140

186

280

373

140

327

373

420

280

420

561

607

420

467

514

280

420

561

607

654

514

561

278

280

327

280

327

Units

MHz

SSTL-2 CLASS I

12 mA

16 mA

20 mA

24 mA

4 mA

SSTL-2 CLASS II

6 mA

SSTL-18 CLASS I

SSTL-18 CLASS II

8 mA

10 mA

12 mA

8 mA

16 mA

18 mA

20 mA

4 mA

6 mA

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

8 mA

10 mA

12 mA

16 mA

18 mA

20 mA

4 mA

6 mA

8 mA

10mA

12 mA

16 mA

18 mA

20 mA

24 mA

8 mA

1.5-V HSTL CLASS II

DIFFERENTIAL SSTL-2

12 mA

16 mA

20 mA

24 mA

DIFFERENTIAL 2.5-V

SSTL CLASS II

Arria GX Device Handbook, Volume 1

4–94

Chapter 4: DC and Switching Characteristics

Maximum Input and Output Clock Toggle Rate

Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 3 of 4)

I/O Standards

Drive Strength

–6 Speed Grade

140

186

280

373

140

327

373

420

280

420

561

607

420

467

514

280

420

561

607

654

514

561

278

626

280

116

280

327

280

420

Units

MHz

4 mA

6 mA

DIFFERENTIAL 1.8-V

SSTL CLASS I

8 mA

10 mA

12 mA

8 mA

16 mA

DIFFERENTIAL 1.8-V

SSTL CLASS II

18 mA

20 mA

4 mA

6 mA

DIFFERENTIAL 1.8-V

HSTL CLASS I

8 mA

10 mA

12 mA

16 mA

DIFFERENTIAL 1.8-V

HSTL CLASS II

18 mA

20 mA

4 mA

6 mA

DIFFERENTIAL 1.5-V

HSTL CLASS I

8 mA

10 mA

12 mA

16 mA

18 mA

DIFFERENTIAL 1.5-V

HSTL CLASS II

20 mA

24 mA

3.3-V PCI

—

3.3-V PCI-X

LVDS

—

HYPERTRANSPORT

LVPECL

—

3.3-V LVTTL

SERIES_25_OHMS

SERIES_50_OHMS

SERIES_25_OHMS

SERIES_50_OHMS

SERIES_25_OHMS

SERIES_50_OHMS

SERIES_25_OHMS

SERIES_50_OHMS

3.3-V LVCMOS

2.5 V

1.8 V

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–95

Duty Cycle Distortion

Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 4 of 4)

I/O Standards

Drive Strength

–6 Speed Grade

Units

MHz

1.5 V

SERIES_50_OHMS

SERIES_25_OHMS

SERIES_50_OHMS

SERIES_25_OHMS

SERIES_50_OHMS

SERIES_25_OHMS

SERIES_50_OHMS

SERIES_25_OHMS

373

467

327

420

561

420

467

233

467

SSTL-2 CLASS I

SSTL-2 CLASS II

SSTL-18 CLASS I

SSTL-18 CLASS II

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.5-V HSTL CLASS I

1.2-V HSTL

DIFFERENTIAL SSTL-2

DIFFERENTIAL 2.5-V

SSTL CLASS II

DIFFERENTIAL 1.8-V

SSTL CLASS I

SERIES_50_OHMS

SERIES_25_OHMS

SERIES_50_OHMS

SERIES_25_OHMS

SERIES_50_OHMS

327

420

561

420

467

233

MHz

DIFFERENTIAL 1.8-V

SSTL CLASS II

DIFFERENTIAL 1.8-V

HSTL CLASS I

DIFFERENTIAL 1.8-V

HSTL CLASS II

DIFFERENTIAL 1.5-V

HSTL CLASS I

DIFFERENTIAL 1.2-V

HSTL

Duty Cycle Distortion

Duty cycle distortion (DCD) describes how much the falling edge of a clock is off from

its ideal position. The ideal position is when both the clock high time (CLKH) and the

clock low time (CLKL) equal half of the clock period (T), as shown in Figure 4–10.

DCD is the deviation of the non-ideal falling edge from the ideal falling edge, such as

D1 for the falling edge A and D2 for the falling edge B (refer to Figure 4–10). The

maximum DCD for a clock is the larger value of D1 and D2.

Arria GX Device Handbook, Volume 1

4–96

Chapter 4: DC and Switching Characteristics

Duty Cycle Distortion

Figure 4–10. Duty Cycle Distortion

Ideal Falling Edge

CLKH = T/2

CLKL = T/2

D1

D2

Falling Edge A

Falling Edge B

Clock Period (T)

DCD expressed in absolution derivation, for example, D1 or D2 in Figure 4–10, is

clock-period independent. DCD can also be expressed as a percentage, and the

percentage number is clock-period dependent. DCD as a percentage is defined as:

(T/2 – D1) / T (the low percentage boundary)

(T/2 + D2) / T (the high percentage boundary)

DCD Measurement Techniques

DCD is measured at an FPGA output pin driven by registers inside the corresponding

I/O element (IOE) block. When the output is a single data rate signal (non-DDIO),

only one edge of the register input clock (positive or negative) triggers output

transitions (Figure 4–11). Therefore, any DCD present on the input clock signal or

caused by the clock input buffer or different input I/O standard does not transfer to

the output signal.

Figure 4–11. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs

However, when the output is a double data rate input/output (DDIO) signal, both

edges of the input clock signal (positive and negative) trigger output transitions

(Figure 4–12). Therefore, any distortion on the input clock and the input clock buffer

affect the output DCD.

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–97

Duty Cycle Distortion

Figure 4–12. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs

When an FPGA PLL generates the internal clock, the PLL output clocks the IOE block.

As the PLL only monitors the positive edge of the reference clock input and internally

re-creates the output clock signal, any DCD present on the reference clock is filtered

out. Therefore, the DCD for a DDIO output with PLL in the clock path is better than

the DCD for a DDIO output without PLL in the clock path.

Table 4–108 through Table 4–113 show the maximum DCD in absolution derivation

for different I/O standards on Arria GX devices. Examples are also provided that

show how to calculate DCD as a percentage.

Table 4–108. Maximum DCD for Non-DDIO Output on Row I/O Pins

Maximum DCD (ps) for Non-DDIO Output

Row I/O Output Standard

–6 Speed Grade

Units

ps

3.3-V LVTTTL

3.3-V LVCMOS

2.5 V

275

155

135

180

195

145

125

85

1.8 V

1.5-V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

SSTL-18 Class I

1.8-V HSTL Class I

1.5-V HSTL Class I

LVDS

100

115

80

Here is an example for calculating the DCD as a percentage for a non-DDIO output on

a row I/O:

If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum DCD is 125 ps

(see Table 4–109). If the clock frequency is 267 MHz, the clock period T is:

T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps

Arria GX Device Handbook, Volume 1

4–98

Chapter 4: DC and Switching Characteristics

Duty Cycle Distortion

To calculate the DCD as a percentage:

(T/2 – DCD) / T = (3,745 ps/2 – 125 ps) / 3,745 ps = 46.66% (for low boundary)

(T/2 + DCD) / T = (3,745 ps/2 + 125 ps) / 3,745 ps = 53.33% (for high boundary)

Therefore, the DCD percentage for the output clock at 267 MHz is from 46.66% to

53.33%.

Table 4–109. Maximum DCD for Non-DDIO Output on Column I/O Pins

Maximum DCD (ps)

for Non-DDIO Output

Column I/O Output Standard I/O Standard

Units

–6 Speed Grade

3.3-V LVTTL

220

175

155

110

215

135

130

115

100

110

115

80

ps

3.3-V LVCMOS

2.5 V

1.8 V

1.5-V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

SSTL-18 Class I

SSTL-18 Class II

1.8-V HSTL Class I

1.8-V HSTL Class II

1.5-V HSTL Class I

1.5-V HSTL Class II

1.2-V HSTL-12

LVPECL

200

80

Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path Note (1)

Input I/O Standard (No PLL in the Clock Path)

Maximum DCD (ps) for

Row DDIO Output I/O

Standard

TTL/CMOS

SSTL-2

SSTL/HSTL

LVDS

Units

3.3/2.5V

1.8/1.5V

495

2.5V

170

120

105

90

1.8/1.5V

160

110

95

3.3V

105

75

3.3-V LVTTL

440

390

375

325

430

355

350

335

330

ps

3.3-V LVCMOS

2.5 V

450

430

90

1.8 V

385

100

155

75

135

100

85

1.5-V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

SSTL-18 Class I

1.8-V HSTL Class I

1.5-V HSTL Class I

490

160

85

410

405

80

70

90

390

65

105

110

105

385

60

70

390

60

70

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–99

Duty Cycle Distortion

Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path Note (1)

Input I/O Standard (No PLL in the Clock Path)

Maximum DCD (ps) for

Row DDIO Output I/O

Standard

TTL/CMOS

SSTL-2

SSTL/HSTL

LVDS

Units

3.3/2.5V

180

1.8/1.5V

2.5V

1.8/1.5V

3.3V

LVDS

180

ps

Note to Table 4–110:

(1) Table 4–110 assumes the input clock has zero DCD.

Table 4–111. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path

(Note 1)

Input IO Standard (No PLL in the Clock Path)

Maximum DCD (ps) for

DDIO Column Output I/O

Standard

TTL/CMOS

SSTL-2

SSTL/HSTL

Units

3.3/2.5V

440

390

375

325

430

355

350

335

320

330

180

1.8/1.5V

495

450

430

385

490

410

405

390

375

385

390

360

180

2.5V

170

120

105

90

1.8/1.5V

160

110

95

3.3-V LVTTL

ps

3.3-V LVCMOS

2.5 V

1.8 V

100

155

75

1.5-V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

SSTL-18 Class I

SSTL-18 Class II

1.8-V HSTL Class I

1.8-V HSTL Class II

1.5-V HSTL Class I

1.5-V HSTL Class II

LVPECL

160

85

80

70

65

70

80

60

70

60

70

60

70

90

100

180

Note to Table 4–111:

(1) Table 4–111 assumes the input clock has zero DCD.

Table 4–112. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path

Arria GX Devices (PLL Output

Feeding DDIO)

Maximum DCD (ps) for Row DDIO Output I/O Standard

Units

–6 Speed Grade

3.3-V LVTTL

3.3-V LVCMOS

2.5V

105

75

ps

90

1.8V

100

75

1.5-V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

70

Arria GX Device Handbook, Volume 1

4–100

Chapter 4: DC and Switching Characteristics

High-Speed I/O Specifications

Table 4–112. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path

Arria GX Devices (PLL Output

Feeding DDIO)

Maximum DCD (ps) for Row DDIO Output I/O Standard

Units

–6 Speed Grade

SSTL-18 Class I

1.8-V HSTL Class I

1.5-V HSTL Class I

LVDS

65

70

ps

70

180

Table 4–113. Maximum DCD for DDIO Output on Column I/O Pins With PLL in the Clock Path

Arria GX Devices (PLL Output

Maximum DCD (ps) for Column

DDIO Output I/O Standard

Feeding DDIO)

Units

–6 Speed Grade

3.3-V LVTTL

160

110

95

ps

3.3-V LVCMOS

2.5V

1.8V

100

155

75

1.5-V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

SSTL-18 Class I

SSTL-18 Class II

1.8-V HSTL Class I

1.8-V HSTL Class II

1.5-V HSTL Class I

1.5-V HSTL Class II

1.2-V HSTL

70

65

80

70

100

155

180

LVPECL

High-Speed I/O Specifications

Table 4–114 lists high-speed timing specifications definitions.

Table 4–114. High-Speed Timing Specifications and Definitions (Part 1 of 2)

High-Speed Timing Specifications

t_C

f_{HS C LK}

J

Definitions

High-speed receiver/transmitter input and output clock period.

High-speed receiver/transmitter input and output clock frequency.

Deserialization factor (width of parallel data bus).

PLL multiplication factor.

W

t_{RI S E}

t_{FA LL}

Low-to-high transmission time.

High-to-low transmission time.

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–101

High-Speed I/O Specifications

Table 4–114. High-Speed Timing Specifications and Definitions (Part 2 of 2)

High-Speed Timing Specifications

Definitions

The timing budget allowed for skew, propagation delays, and data sampling window.

Timing unit interval (TUI)

(TUI = 1/(Receiver Input Clock Frequency × Multiplication Factor) = t_C/w).

Maximum/minimum LVDS data transfer rate (f_{HS DR}= 1/TUI), non-DPA.

Maximum/minimum LVDS data transfer rate (f_{HS DR DP A}= 1/TUI), DPA.

f_{HS D R}

f_{HS D RD PA}

Channel-to-channel skew (TCCS)

The timing difference between the fastest and slowest output edges, including t_{C O}

variation and clock skew. The clock is included in the TCCS measurement.

Sampling window (SW)

The period of time during which the data must be valid in order to capture it

correctly. The setup and hold times determine the ideal strobe position within the

sampling window.

Input jitter

Output jitter

t_{DU TY}

Peak-to-peak input jitter on high-speed PLLs.

Peak-to-peak output jitter on high-speed PLLs.

Duty cycle on high-speed transmitter output clock.

Lock time for high-speed transmitter and receiver PLLs.

t_{LO CK}

Table 4–115 shows the high-speed I/O timing specifications.

Table 4–115. High-Speed I/O Specifications (Part 1 of 2)Note (1), (2)

–6 Speed Grade

Symbol

Conditions

Units

Min

16

Typ

—

50

—

Max

420

500

640

840

700

500

840

200

—

W = 2 to 32 (LVDS, HyperTransport technology) (3)

W = 1 (SERDES bypass, LVDS only)

W = 1 (SERDES used, LVDS only)

MHz

Mbps

ps

f_{HS C LK}(clock frequency)

f_{HS C LK}= f_{H S DR}/ W

16

150

(4)

150

—

J = 4 to 10 (LVDS, HyperTransport technology)

J = 2 (LVDS, HyperTransport technology)

J = 1 (LVDS only)

f_{HS D R}(data rate)

f_{HS D RD PA}(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)

TCCS

All differential I/O standards

SW

All differential I/O standards

440

—

ps

Output jitter

Output t_{R I SE}

Output t_{F AL L}

t_{DU TY}

—

190

290

55

ps

All differential I/O standards

—

ps

All differential I/O standards

—

ps

—

45

%

DPA run length

DPA jitter tolerance

—

6,400

—

UI

Data channel peak-to-peak jitter

0.44

UI

Arria GX Device Handbook, Volume 1

4–102

Chapter 4: DC and Switching Characteristics

High-Speed I/O Specifications

Table 4–115. High-Speed I/O Specifications (Part 2 of 2)Note (1), (2)

–6 Speed Grade

Units

Symbol

Conditions

Min

Typ

Max

Standard

SPI-4

Training Pattern

Transition

Density

—

000000000011

11111111

10%

256

—

Number of

repetitions

DPA lock time

Parallel Rapid

I/O

00001111

10010000

10101010

01010101

25%

50%

100%

—

256

—

Miscellaneous

Notes to Table 4–115:

(1) When J = 4 to 10, the SERDES block is used.

(2) When J = 1 or 2, the SERDES block is bypassed.

(3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150  input clock frequency × W  1,040.

(4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource

(global, regional, or local) used. The I/O differential buffer and input register do not have a minimum toggle rate.

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–103

PLL Timing Specifications

Table 4–116 and Table 4–117 describe the Arria GX PLL specifications when operating

in both the commercial junction temperature range (0 to 85 C) and the industrial

junction temperature range (–40 to 100 C), except for the clock switchover and

phase-shift stepping features. These two features are only supported from the 0 to

100 C junction temperature range.

Table 4–116. Enhanced PLL Specifications (Part 1 of 2)

Name Description

Input clock frequency

Min

2

Typ

—

Max

500

420

60

Units

MHz

%

f_IN

f_INPFD

f_INDUTY

f_ENDUTY

Input frequency to the PFD

2

Input clock duty cycle

40

External feedback input clock duty cycle

60

%

Input or external feedback clock input jitter

tolerance in terms of period jitter.

—

0.5

1.0

—

ns (peak-to-peak)

Bandwidth  0.85 MHz

t_INJITTER

Input or external feedback clock input jitter

tolerance in terms of period jitter.

Bandwidth  0.85 MHz

t_OUTJITTER

t_FCOMP

Dedicated clock output period jitter

External feedback compensation time

50

—

100

—

250

10

ps (p-p)

ns

Output frequency for internal global or regional

clock

f_OUT

1.5 (2)

—

550

100

—

MHz

ns

f_SCANCLK

t_CONFIGEPLL

Scanclk frequency

Time required to reconfigure scan chains for

EPLLs

—

174/f_SCANCLK

f_{OUT_EXT}

f_OUTDUTY

PLL external clock output frequency

Duty cycle for external clock output

1.5 (2)

(1)

MHz

%

45

50

55

Time required for the PLL to lock from the time

it is enabled or the end of device configuration

t_LOCK

—

0.03

1

ms

Time required for the PLL to lock dynamically

after automatic clock switchover between two

identical clock frequencies

t_DLOCK

—

1

ms

Frequency range where the clock switchover

performs properly

f_SWITCHOVER

1.5

500

MHz

f_CLBW

f_VCO

f_SS

PLL closed-loop bandwidth

0.13

300

100

1.2

—

16.9

840

500

MHz

kHz

PLL VCO operating range

Spread-spectrum modulation frequency

Percent down spread for a given clock

frequency

% spread

0.4

0.5

0.6

%

t_{PLL_PSERR}

t_ARESET

Accuracy of PLL phase shift

—

10

—

30

—

ps

ns

Minimum pulse width on aresetsignal.

Minimum pulse width on the aresetsignal

when using PLL reconfiguration. Reset the PLL

after scandonegoes high.

t_{ARESET_RECONFIG}

500

—

ns

Arria GX Device Handbook, Volume 1

4–104

Chapter 4: DC and Switching Characteristics

PLL Timing Specifications

Table 4–116. Enhanced PLL Specifications (Part 2 of 2)

Name

Description

Min

Typ

Max

Units

The time required for the wait after the

reconfiguration is done and the areset is

applied.

t_RECONFIGWAIT

—

2

us

Notes to Table 4–116:

(1) This is limited by the I/O f_MAX

.

(2) If the counter cascading feature of the PLL is used, there is no minimum output clock frequency.

Table 4–117. Fast PLL Specifications (Part 1 of 2)

Name

Description

Min

Typ

Max

Units

f_IN

Input clock frequency

16.08

—

640

MHz

Input frequency to the

PFD

f_INPFD

f_INDUTY

16.08

40

—

500

60

MHz

%

Input clock duty cycle

Input clock jitter

tolerance in terms of

period jitter.

—

0.5

1.0

—

ns (p-p)

Bandwidth 2 MHz

t_INJITTER

Input clock jitter

tolerance in terms of

period jitter.

Bandwidth  0.2 MHz

Upper VCO frequency

range

300

150

—

840

420

550

840

MHz

f_VCO

Lower VCO frequency

range

PLL output frequency

to GCLKor RCLK

4.6875

150

f_OUT

PLL output frequency

to LVDS or DPA clock

PLL clock output

frequency to regular

I/O

f_{OUT_EXT}

4.6875

—

(1)

MHz

Time required to

reconfigure scan

chains for fast PLLs

t_CONFIGPLL

—

75/f_SCANCLK

—

28

ns

PLL closed-loop

bandwidth

f_CLBW

1.16

5

MHz

Time required for the

PLL to lock from the

time it is enabled or

the end of the device

configuration

t_LOCK

—

0.03

1

ms

Accuracy of PLL phase

shift

t_{PLL_PSERR}

t_ARESET

—

10

—

30

—

ps

ns

Minimum pulse width

on aresetsignal.

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–105

External Memory Interface Specifications

Table 4–117. Fast PLL Specifications (Part 2 of 2)

Name

Description

Min

Typ

Max

Units

Minimum pulse width

on the aresetsignal

when using PLL

reconfiguration. Reset

the PLL after

t_{ARESET_RECONFIG}

500

—

ns

scandonegoes high.

Note to Table 4–117:

(1) This is limited by the I/O f_MAX

.

External Memory Interface Specifications

Table 4–118 through Table 4–122 list Arria GX device specifications for the dedicated

circuitry used for interfacing with external memory devices.

Table 4–118. DLL Frequency Range Specifications

Frequency Mode

Frequency Range (MHz)

100 to 175

0

1

2

150 to 230

200 to 310

Table 4–119. DQS Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) , (Note 1)

Number of DQS Delay Buffer Stages (2)

Commercial (ps)

Industrial (ps)

1

80

110

130

180

210

2

110

130

160

3

4

Notes to Table 4–119:

(1) Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on two delay stages under

commercial conditions is 200 ps peak-to-peak or 100 ps.

(2) Delay stages used for requested DQS phase shift are reported in a project’s Compilation Report in the Quartus II

software.

Table 4–120. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t_{DQS_PSERR}

)

Number of DQS Delay Buffer Stages

–6 Speed Grade (ps)

1

2

3

4

35

70

105

140

Arria GX Device Handbook, Volume 1

4–106

Chapter 4: DC and Switching Characteristics

JTAG Timing Specifications

Table 4–121. DQS Bus Clock Skew Adder Specifications (t_{DQS_CLOCK_SKEW_ADDER}

)

Mode

DQS Clock Skew Adder (ps)

4 DQ per DQS

9 DQ per DQS

18 DQ per DQS

36 DQ per DQS

40

70

75

95

Table 4–122. DQS Phase Offset Delay Per Stage (ps) Note (1), (2), (3)

Positive Offset

Negative Offset

Speed Grade

Min

Max

Min

Max

–6

10

16

8

12

Notes to Table 4–122:

(1) The delay settings are linear.

(2) The valid settings for phase offset are –32 to +31.

(3) The typical value equals the average of the minimum and maximum values.

JTAG Timing Specifications

Figure 4–13 shows the timing requirements for the JTAG signals

Figure 4–13. Arria GX JTAG Waveforms.

TMS

TDI

t_JCP

t_JCH

t _JCL

t_JPH

t_JPSU

TCK

TDO

t_JPXZ

t_JPZX

t_JPCO

t_JSSU

t_JSH

Signal

to be

Captured

t_JSCO

t_JSZX

t_JSXZ

Signal

to be

Driven

Arria GX Device Handbook, Volume 1

Chapter 4: DC and Switching Characteristics

4–107

JTAG Timing Specifications

Table 4–123 lists the JTAG timing parameters and values for Arria GX devices.

Table 4–123. Arria GX JTAG Timing Parameters and Values

Symbol Parameter

t_JCPTCK clock period

Min

30

12

4

Max

—

9

Units

ns

t_JCH

TCK clock high time

t_JCL

TCK clock low time

t_JPSU

t_JPH

JTAG port setup time

JTAG port hold time

5

t_JPCO

t_JPZX

t_JPXZ

t_JSSU

t_JSH

JTAG port clock to output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

Capture register setup time

Capture register hold time

Update register clock to output

—

4

9

ns

—

12

ns

5

t_JSCO

—

Update register high impedance to valid

output

t_JSZX

t_JSXZ

—

12

ns

Update register valid output to high

impedance

Arria GX Device Handbook, Volume 1

4–108

Chapter 4: DC and Switching Characteristics

Document Revision History

Table 4–124 lists the revision history for this chapter.

Table 4–124. Document Revision History

Date and Document Version

Changes Made

Summary of Changes

December 2009, v2.0

■ Updated Table 4–104, Table 4–105,

and Table 4–106.

—

■ Document template update.

■ Minor text edits.

■ Updated Table 4–6 and Table 4–7.

April 2009

v1.4

—

■ Updated “Maximum Input and Output

Clock Toggle Rate” section.

Updated:

■ Table 4–5

■ Table 4–7

■ Table 4–8

■ Table 4–9

■ Table 4–10

■ Table 4–11

■ Table 4–12

■ Table 4–13

■ Table 4–14

■ Table 4–15

■ Table 4–16

■ Table 4–17

■ Table 4–43

■ Table 4–116

■ Table 4–117

Updated:

—

May 2008

v1.3

—

■ Figure 4–4

Minor text edits.

Removed “Preliminary” from each page.

—

Removed “Preliminary” note from

Tables 4–44, 4–45, and 4–47.

August 2007 v1.2

—

Added “Referenced Documents” section.

Updated Table 4–99.

—

June 2007

v1.1

Added GIGE information.

Initial release.

May 2007

v1.0

—

Arria GX Device Handbook, Volume 1

5. Reference and Ordering Information

AGX51005-2.0

Software

Arria^®GX devices are supported by the Altera^®Quartus^®II design software, which

provides a comprehensive environment for system-on-a-programmable-chip (SOPC)

design. The Quartus II software includes HDL and schematic design entry,

compilation and logic synthesis, full simulation and advanced timing analysis,

SignalTap^®II logic analyzer, and device configuration.

f

For more information about the Quartus II software features, refer to the Quartus II

Development Software Handbook .

The Quartus II software supports the Windows XP/2000/NT, Sun Solaris 8/9, Linux

Red Hat v7.3, Linux Red Hat Enterprise 3, and HP-UX operating systems. It also

supports seamless integration with industry-leading EDA tools through the

NativeLink interface.

Device Pin-Outs

f

Arria GX device pin-outs are available on the Altera web site at www.altera.com.

Ordering Information

Figure 5–1 describes the ordering codes for Arria GX devices.

f

For more information on a specific package, refer to the Package Information for Arria

GX Devices chapter.

Arria GX Device Handbook, Volume 1

5–2

Chapter 5: Reference and Ordering Information

Document Revision History

Figure 5–1. Arria GX Device Packaging Ordering Information

EP1AGX

20

C

F

484

C

6

N

Family Signature

Optional Suffix

EP1AGX : Arria GX

Indicates specific device options or

shipment method.

N:

Lead-free devices

Device Type

20

35

50

60

90

Speed Grade

6

Operating Temperature

Number of

Transceiver

Channels

C: Commercial temperature (T = 0˚ C to 85˚ C)

J

I:

Industrial temperature (T = -40˚ C to 100˚ C)

J

Pin Count

C: 4

D: 8

E: 12

484

780

1152

Package Type

F:

FineLine BGA (FBGA)

Document Revision History

Table 5–1 shows the revision history for this chapter.

Table 5–1. Document Revision History

Date and Document

Version

Changes Made

Summary of Changes

December 2009, v2.0 ■ Document template update.

■ Minor text edits.

—

August 2007, v1.1

May 2007, v1.0

Added the “Referenced Documents” section.

Initial Release.

—

Arria GX Device Handbook, Volume 1

Additional Information

About this Handbook

This handbook provides comprehensive information about the Altera^®Arria^®GX

family of devices.

How to Contact Altera

For the most up-to-date information about Altera products, see the following table.

Contact

Contact (Note 1)

Technical support

Method

Website

Email

Address

www.altera.com/support

www.altera.com/training

custrain@altera.com

Technical training

Product literature

Non-technical support (General)

(Software Licensing)

Note:

Email

www.altera.com/literature

nacomp@altera.com

Email

authorization@altera.com

(1) You can also contact your local Altera sales office or sales representative.

Typographic Conventions

The following table shows the typographic conventions that this document uses.

Visual Cue

Meaning

Bold Type with Initial Capital

Letters

Indicates command names and dialog box titles. For example, Save As dialog box.

bold type

Indicates directory names, project names, disk drive names, file names, file name

extensions, dialog box options, software utility names, and other GUI labels. For

example, \qdesigns directory, d: drive, and chiptrip.gdf file.

Italic Type with Initial Capital Letters Indicates document titles. For example, AN 519: Stratix IV Design Guidelines.

Italic type

Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and

<project name>.pof file.

Initial Capital Letters

“Subheading Title”

Indicates keyboard keys and menu names. For example, Delete key and the Options

menu.

Quotation marks indicate references to sections within a document and titles of

Quartus II Help topics. For example, “Typographic Conventions.”

Arria GX Device Handbook, Volume 1

Info–2

Additional Information

Visual Cue

Meaning

Courier type

Indicates signal, port, register, bit, block, and primitive names. For example, data1,

tdi, and input. Active-low signals are denoted by suffix n. For example,

resetn.

Indicates command line commands and anything that must be typed exactly as it

appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.

Also indicates sections of an actual file, such as a Report File, references to parts of

files (for example, the AHDL keyword SUBDESIGN), and logic function names (for

example, TRI).

1., 2., 3., and

a., b., c., and so on.

Numbered steps indicate a list of items when the sequence of the items is important,

such as the steps listed in a procedure.

■

Bullets indicate a list of items when the sequence of the items is not important.

The hand points to information that requires special attention.

1

c

A caution calls attention to a condition or possible situation that can damage or

destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you

injury.

w

r

The angled arrow instructs you to press Enter.

f

The feet direct you to more information about a particular topic.

Arria GX Device Handbook, Volume 1


型号：	EP1AGX60EF780C6N
厂家：	ALTERA CORPORATION
描述：	Section I. Arria GX Device Data Sheet 第一节的Arria GX器件数据手册可编程逻辑
文件：	总234页 (文件大小：3509K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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