5M80ZM64I5 [ALTERA]
Flash PLD, 14ns, 64-Cell, CMOS, PBGA64, 4.50 X 4.50 MM, 0.50 MM PITCH, MBGA-64;
| 型号： | 5M80ZM64I5 |
| 厂家： | 
ALTERA CORPORATION |
| 描述： | Flash PLD, 14ns, 64-Cell, CMOS, PBGA64, 4.50 X 4.50 MM, 0.50 MM PITCH, MBGA-64 时钟 可编程逻辑 |
| 文件： | 总30页 (文件大小：447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3. DC and Switching Characteristics for
MAX V Devices
May 2011
MV51003-1.2
MV51003-1.2
This chapter covers the electrical and switching characteristics for MAX® V devices.
Electrical characteristics include operating conditions and power consumptions. This
chapter also describes the timing model and specifications.
You must consider the recommended DC and switching conditions described in this
chapter to maintain the highest possible performance and reliability of the MAX V
devices.
This chapter contains the following sections:
■
■
■
“Operating Conditions” on page 3–1
“Power Consumption” on page 3–10
“Timing Model and Specifications” on page 3–10
Operating Conditions
Table 3–1 through Table 3–15 on page 3–9 list information about absolute maximum
ratings, recommended operating conditions, DC electrical characteristics, and other
specifications for MAX V devices.
Absolute Maximum Ratings
Table 3–1 lists the absolute maximum ratings for the MAX V device family.
Table 3–1. Absolute Maximum Ratings for MAX V Devices (Note 1), (2)
Symbol
VCCINT
Parameter
Internal supply voltage
I/O supply voltage
Conditions
Minimum
–0.5
Maximum
2.4
Unit
V
With respect to ground
VCCIO
VI
—
–0.5
4.6
V
DC input voltage
—
—
–0.5
4.6
V
IOUT
TSTG
TAMB
DC output current, per pin
Storage temperature
Ambient temperature
–25
25
mA
°C
°C
No bias
–65
150
Under bias (3)
–65
135
TQFP and BGA packages
under bias
TJ
Junction temperature
—
135
°C
Notes to Table 3–1:
(1) For more information, refer to the Operating Requirements for Altera Devices Data Sheet.
(2) Conditions beyond those listed in Table 3–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum
ratings for extended periods of time may have adverse affects on the device.
(3) For more information about “under bias” conditions, refer to Table 3–2.
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
MAX V Device Handbook
May 2011
Subscribe
3–2
Chapter 3: DC and Switching Characteristics for MAX V Devices
Operating Conditions
Recommended Operating Conditions
Table 3–2 lists recommended operating conditions for the MAX V device family.
Table 3–2. Recommended Operating Conditions for MAX V Devices
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
1.8-V supply voltage for internal logic and
in-system programming (ISP)
VCCINT (1)
MAX V devices
1.71
1.89
V
Supply voltage for I/O buffers, 3.3-V
operation
—
—
—
—
—
3.00
2.375
1.71
3.60
2.625
1.89
V
V
V
V
V
Supply voltage for I/O buffers, 2.5-V
operation
Supply voltage for I/O buffers, 1.8-V
operation
VCCIO (1)
Supply voltage for I/O buffers, 1.5-V
operation
1.425
1.14
1.575
1.26
Supply voltage for I/O buffers, 1.2-V
operation
VI
Input voltage
(2), (3), (4)
—
–0.5
0
4.0
VCCIO
85
V
VO
Output voltage
V
Commercial range
Industrial range
Extended range (5)
0
°C
°C
°C
TJ
Operating junction temperature
–40
–40
100
125
Notes to Table 3–2:
(1) MAX V device ISP and/or user flash memory (UFM) programming using JTAG or logic array is not guaranteed outside the recommended
operating conditions (for example, if brown-out occurs in the system during a potential write/program sequence to the UFM, Altera recommends
that you read back the UFM contents and verify it against the intended write data).
(2) The minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods
shorter than 20 ns.
(3) During transitions, the inputs may overshoot to the voltages shown below based on the input duty cycle. The DC case is equivalent to 100%
duty cycle. For more information about 5.0-V tolerance, refer to the Using MAX V Devices in Multi-Voltage Systems chapter.
VIN
Max. Duty Cycle
4.0 V 100% (DC)
4.1 V 90%
4.2 V 50%
4.3 V 30%
4.4 V 17%
4.5 V 10%
(4) All pins, including the clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered.
(5) For the extended temperature range of 100 to 125°C, MAX V UFM programming (erase/write) is only supported using the JTAG interface. UFM
programming using the logic array interface is not guaranteed in this range.
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–3
Operating Conditions
Programming/Erasure Specifications
Table 3–3 lists the programming/erasure specifications for the MAX V device family.
Table 3–3. Programming/Erasure Specifications for MAX V Devices
Parameter
Erase and reprogram cycles
Note to Table 3–3:
Block
Minimum
Typical
—
Maximum
1000 (1)
100
Unit
UFM
Configuration flash memory (CFM)
—
—
Cycles
Cycles
—
(1) This value applies to the commercial grade devices. For the industrial grade devices, the value is 100 cycles.
DC Electrical Characteristics
Table 3–4 lists DC electrical characteristics for the MAX V device family.
Table 3–4. DC Electrical Characteristics for MAX V Devices (Note 1) (Part 1 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
II
Input pin leakage current VI = VCCIO max to 0 V (2)
–10
—
10
µA
Tri-stated I/O pin leakage
VO = VCCIO max to 0 V (2)
current
IOZ
–10
—
25
27
25
10
µA
µA
µA
µA
5M40Z, 5M80Z, 5M160Z, and
5M240Z (Commercial grade)
(4), (5)
—
90
5M240Z (Commercial grade)
(6)
—
96
5M40Z, 5M80Z, 5M160Z, and
5M240Z (Industrial grade)
(5), (7)
VCCINT supply current
(standby) (3)
—
139
ICCSTANDBY
5M240Z (Industrial grade) (6)
—
—
27
27
152
96
µA
µA
5M570Z (Commercial grade)
(4)
5M570Z (Industrial grade) (7)
5M1270Z and 5M2210Z
VCCIO = 3.3 V
—
—
—
—
27
2
152
—
µA
mA
mV
mV
400
190
—
Hysteresis for Schmitt
trigger input (9)
VSCHMITT (8)
VCCIO = 2.5 V
—
VCCINT supply current
during power-up (10)
ICCPOWERUP
MAX V devices
—
—
40
mA
VCCIO = 3.3 V (11)
VCCIO = 2.5 V (11)
5
—
—
—
—
—
25
40
k
k
k
k
k
10
25
45
80
Value of I/O pin pull-up
resistor during user
mode and ISP
RPULLUP
V
CCIO = 1.8 V (11)
VCCIO = 1.5 V (11)
CCIO = 1.2 V (11)
60
95
V
130
May 2011 Altera Corporation
MAX V Device Handbook
3–4
Chapter 3: DC and Switching Characteristics for MAX V Devices
Operating Conditions
Table 3–4. DC Electrical Characteristics for MAX V Devices (Note 1) (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
I/O pin pull-up resistor
current when I/O is
unprogrammed
IPULLUP
—
—
—
300
µA
Input capacitance for
user I/O pin
CIO
—
—
—
—
—
—
8
8
pF
pF
Input capacitance for
dual-purpose GCLK/user
I/O pin
CGCLK
Notes to Table 3–4:
(1) Typical values are for TA = 25°C, VCCINT = 1.8 V and VCCIO = 1.2, 1.5, 1.8, 2.5, or 3.3 V.
(2) This value is specified for normal device operation. The value may vary during power-up. This applies to all VCCIO settings (3.3, 2.5, 1.8, 1.5,
and 1.2 V).
(3) VI = ground, no load, and no toggling inputs.
(4) Commercial temperature ranges from 0°C to 85°C with the maximum current at 85°C.
(5) Not applicable to the T144 package of the 5M240Z device.
(6) Only applicable to the T144 package of the 5M240Z device.
(7) Industrial temperature ranges from –40°C to 100°C with the maximum current at 100°C.
(8) This value applies to commercial and industrial range devices. For extended temperature range devices, the VSCHMITT typical value is 300 mV
for VCCIO = 3.3 V and 120 mV for VCCIO = 2.5 V.
(9) The TCKinput is susceptible to high pulse glitches when the input signal fall time is greater than 200 ns for all I/O standards.
(10) This is a peak current value with a maximum duration of tCONFIG time.
(11) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO
.
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–5
Operating Conditions
Output Drive Characteristics
Figure 3–1 shows the typical drive strength characteristics of MAX V devices.
Figure 3–1. Output Drive Characteristics of MAX V Devices (Note 1)
MAX V Output Drive IOH Characteristics
(Maximum Drive Strength)
MAX V Output Drive IOL Characteristics
(Maximum Drive Strength)
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
3.3-V VCCIO
3.3-V VCCIO
2.5-V VCCIO
2.5-V VCCIO
1.8-V VCCIO
1.8-V VCCIO
1.5-V VCCIO
1.2-V VCCIO (2)
1.5-V VCCIO
1.2-V VCCIO (2)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Voltage (V)
Voltage (V)
MAX V Output Drive IOL Characteristics
(Minimum Drive Strength)
MAX V Output Drive IOH Characteristics
(Minimum Drive Strength)
30
25
20
15
10
5
35
3.3-V VCCIO
3.3-V VCCIO
30
25
20
15
10
5
2.5-V VCCIO
2.5-V VCCIO
1.8-V VCCIO
1.5-V VCCIO
1.8-V VCCIO
1.5-V VCCIO
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Voltage (V)
Voltage (V)
Notes to Figure 3–1:
(1) The DC output current per pin is subject to the absolute maximum rating of Table 3–1 on page 3–1.
(2) 1.2-V VCCIO is only applicable to the maximum drive strength.
I/O Standard Specifications
Table 3–5 through Table 3–13 on page 3–8 list the I/O standard specifications for the
MAX V device family.
Table 3–5. 3.3-V LVTTL Specifications for MAX V Devices
Symbol
VCCIO
Parameter
I/O supply voltage
Conditions
Minimum
3.0
Maximum
3.6
Unit
V
—
VIH
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
—
1.7
4.0
V
VIL
—
–0.5
2.4
0.8
V
VOH
IOH = –4 mA (1)
IOL = 4 mA (1)
—
V
VOL
—
0.45
V
Note to Table 3–5:
(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the
MAX V Device Architecture chapter.
May 2011 Altera Corporation
MAX V Device Handbook
3–6
Chapter 3: DC and Switching Characteristics for MAX V Devices
Operating Conditions
Table 3–6. 3.3-V LVCMOS Specifications for MAX V Devices
Symbol
VCCIO
Parameter
I/O supply voltage
Conditions
Minimum
3.0
Maximum
3.6
Unit
V
—
—
—
VIH
VIL
High-level input voltage
Low-level input voltage
1.7
4.0
V
–0.5
0.8
V
V
CCIO = 3.0,
IOH = –0.1 mA (1)
CCIO = 3.0,
IOL = 0.1 mA (1)
VOH
High-level output voltage
Low-level output voltage
VCCIO – 0.2
—
—
V
V
V
VOL
0.2
Note to Table 3–6:
(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the
MAX V Device Architecture chapter.
Table 3–7. 2.5-V I/O Specifications for MAX V Devices
Symbol
VCCIO
Parameter
I/O supply voltage
Conditions
—
Minimum
2.375
1.7
Maximum
2.625
4.0
Unit
V
VIH
VIL
High-level input voltage
Low-level input voltage
—
V
—
–0.5
2.1
0.7
V
IOH = –0.1 mA (1)
IOH = –1 mA (1)
IOH = –2 mA (1)
IOL = 0.1 mA (1)
IOL = 1 mA (1)
IOL = 2 mA (1)
—
V
VOH
High-level output voltage
Low-level output voltage
2.0
—
V
1.7
—
V
—
0.2
V
VOL
—
0.4
V
—
0.7
V
Note to Table 3–7:
(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the
MAX V Device Architecture chapter.
Table 3–8. 1.8-V I/O Specifications for MAX V Devices
Symbol
VCCIO
Parameter
I/O supply voltage
Conditions
Minimum
1.71
Maximum
1.89
Unit
V
—
VIH
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
—
0.65 × VCCIO
–0.3
2.25 (2)
0.35 × VCCIO
—
V
VIL
—
V
VOH
IOH = –2 mA (1)
IOL = 2 mA (1)
VCCIO – 0.45
—
V
VOL
0.45
V
Notes to Table 3–8:
(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the
MAX V Device Architecture chapter.
(2) This maximum VIH reflects the JEDEC specification. The MAX V input buffer can tolerate a VIH maximum of 4.0, as specified by the VI parameter
in Table 3–2 on page 3–2.
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–7
Operating Conditions
Table 3–9. 1.5-V I/O Specifications for MAX V Devices
Symbol
VCCIO
Parameter
I/O supply voltage
Conditions
Minimum
1.425
Maximum
1.575
Unit
V
—
VIH
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
—
0.65 × VCCIO
–0.3
VCCIO + 0.3 (2)
0.35 × VCCIO
—
V
VIL
—
V
VOH
IOH = –2 mA (1)
IOL = 2 mA (1)
0.75 × VCCIO
—
V
VOL
0.25 × VCCIO
V
Notes to Table 3–9:
(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the
MAX V Device Architecture chapter.
(2) This maximum VIH reflects the JEDEC specification. The MAX V input buffer can tolerate a VIH maximum of 4.0, as specified by the VI parameter
in Table 3–2 on page 3–2.
Table 3–10. 1.2-V I/O Specifications for MAX V Devices
Symbol
VCCIO
Parameter
I/O supply voltage
Conditions
Minimum
1.14
Maximum
1.26
Unit
V
—
VIH
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
—
0.8 × VCCIO
–0.3
VCCIO + 0.3
0.25 × VCCIO
—
V
VIL
—
V
VOH
IOH = –2 mA (1)
IOL = 2 mA (1)
0.75 × VCCIO
—
V
VOL
0.25 × VCCIO
V
Note to Table 3–10:
(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the
MAX V Device Architecture chapter.
Table 3–11. 3.3-V PCI Specifications for MAX V Devices (Note 1)
Symbol
VCCIO
Parameter
I/O supply voltage
Conditions
Minimum
3.0
Typical
3.3
—
Maximum
3.6
Unit
—
—
V
V
V
V
V
VIH
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
0.5 × VCCIO
–0.5
VCCIO + 0.5
0.3 × VCCIO
—
VIL
—
—
VOH
IOH = –500 µA
IOL = 1.5 mA
0.9 × VCCIO
—
—
VOL
—
0.1 × VCCIO
Note to Table 3–11:
(1) 3.3-V PCI I/O standard is only supported in Bank 3 of the 5M1270Z and 5M2210Z devices.
Table 3–12. LVDS Specifications for MAX V Devices (Note 1)
Symbol
VCCIO
Parameter
I/O supply voltage
Conditions
Minimum
2.375
247
Typical
2.5
Maximum
2.625
Unit
V
—
—
—
VOD
VOS
Differential output voltage swing
Output offset voltage
—
600
mV
V
1.125
1.25
1.375
Note to Table 3–12:
(1) Supports emulated LVDS output using a three-resistor network (LVDS_E_3R).
May 2011 Altera Corporation
MAX V Device Handbook
3–8
Chapter 3: DC and Switching Characteristics for MAX V Devices
Operating Conditions
Table 3–13. RSDS Specifications for MAX V Devices (Note 1)
Symbol
VCCIO
Parameter
I/O supply voltage
Conditions
Minimum
2.375
247
Typical
2.5
Maximum
2.625
Unit
V
—
—
—
VOD
VOS
Differential output voltage swing
Output offset voltage
—
600
mV
V
1.125
1.25
1.375
Note to Table 3–13:
(1) Supports emulated RSDS output using a three-resistor network (RSDS_E_3R).
Bus Hold Specifications
Table 3–14 lists the bus hold specifications for the MAX V device family.
Table 3–14. Bus Hold Specifications for MAX V Devices
VCCIO Level
1.8 V
Parameter
Conditions
1.2 V
1.5 V
2.5 V
3.3 V
Unit
Min Max Min Max Min Max Min Max Min Max
Low sustaining
current
V
IN > VIL (maximum) 10
—
—
20
–20
—
—
—
30
–30
—
—
—
50
–50
—
—
—
70
–70
—
—
—
µA
µA
µA
High sustaining
current
VIN < VIH (minimum) –10
Low overdrive
current
0 V < VIN < VCCIO
0 V < VIN < VCCIO
—
—
130
–130
160
–160
200
–200
300
–300
500
High overdrive
current
—
—
—
—
–500 µA
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–9
Operating Conditions
Power-Up Timing
Table 3–15 lists the power-up timing characteristics for the MAX V device family.
Table 3–15. Power-Up Timing for MAX V Devices
Symbol
Parameter
Device
Temperature Range
Commercial and industrial
Extended
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
200
300
200
300
200
300
200
300
300
400
300
400
300
400
450
500
450
500
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
5M40Z
Commercial and industrial
Extended
5M80Z
5M160Z
Commercial and industrial
Extended
Commercial and industrial
Extended
5M240Z (2)
5M240Z (3)
5M570Z
The amount of time from
when minimum VCCINT is
reached until the device
enters user mode (1)
Commercial and industrial
Extended
tCONFIG
Commercial and industrial
Extended
Commercial and industrial
Extended
5M1270Z (4)
5M1270Z (5)
5M2210Z
Commercial and industrial
Extended
Commercial and industrial
Extended
Notes to Table 3–15:
(1) For more information about power-on reset (POR) trigger voltage, refer to the Hot Socketing and Power-On Reset in MAX V Devices chapter.
(2) Not applicable to the T144 package of the 5M240Z device.
(3) Only applicable to the T144 package of the 5M240Z device.
(4) Not applicable to the F324 package of the 5M1270Z device.
(5) Only applicable to the F324 package of the 5M1270Z device.
May 2011 Altera Corporation
MAX V Device Handbook
3–10
Chapter 3: DC and Switching Characteristics for MAX V Devices
Power Consumption
Power Consumption
You can use the Altera® PowerPlay Early Power Estimator and PowerPlay Power
Analyzer to estimate the device power.
f For more information about these power analysis tools, refer to the PowerPlay Early
Power Estimator for Altera CPLDs User Guide and the PowerPlay Power Analysis chapter
in volume 3 of the Quartus II Handbook.
Timing Model and Specifications
MAX V devices timing can be analyzed with the Altera Quartus® II software, a variety
of industry-standard EDA simulators and timing analyzers, or with the timing model
shown in Figure 3–2.
MAX V devices have predictable internal delays that allow you to determine the
worst-case timing of any design. The software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis for device-wide
performance evaluation.
Figure 3–2. Timing Model for MAX V Devices
Output and Output Enable
Data Delay
tR4
tIODR
tIOE
Data-In/LUT Chain
Output Routing
Delay
User
Flash
Memory
Logic Element
LUT Delay
Output
Delay
tOD
tXZ
tZX
tC4
tLUT
tCOMB
tFASTIO
tCO
tSU
tH
tPRE
tCLR
Input Routing
Delay
I/O Input Delay
tIN
Register Control
Delay
I/O Pin
tDL
tC
From Adjacent LE
tGLOB
INPUT
Combinational Path Delay
I/O Pin
Global Input Delay
To Adjacent LE
Register Delays
Data-Out
You can derive the timing characteristics of any signal path from the timing model
and parameters of a particular device. You can calculate external timing parameters,
which represent pin-to-pin timing delays, as the sum of the internal parameters.
f For more information, refer to AN629: Understanding Timing in Altera CPLDs.
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–11
Timing Model and Specifications
Preliminary and Final Timing
This section describes the performance, internal, external, and UFM timing
specifications. All specifications are representative of the worst-case supply voltage
and junction temperature conditions.
Timing models can have either preliminary or final status. The Quartus II software
issues an informational message during the design compilation if the timing models
are preliminary. Table 3–16 lists the status of the MAX V device timing models.
Preliminary status means the timing model is subject to change. Initially, timing
numbers are created using simulation results, process data, and other known
parameters. These tests are used to make the preliminary numbers as close to the
actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing. These
numbers reflect the actual performance of the device under the worst-case voltage
and junction temperature conditions.
Table 3–16. Timing Model Status for MAX V Devices
Device
5M40Z
Final
v
5M80Z
v
5M160Z
5M240Z
5M570Z
5M1270Z
5M2210Z
v
v
v
v
v
Performance
Table 3–17 lists the MAX V device performance for some common designs. All
performance values were obtained with the Quartus II software compilation of
megafunctions.
Table 3–17. Device Performance for MAX V Devices (Part 1 of 2)
Performance
Resources Used
5M40Z/ 5M80Z/ 5M160Z/
Resource
Used
Design Size and
Function
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
Unit
UFM
Blocks
Mode
LEs
C4
C5, I5
C4
C5, I5
16-bit counter (1)
64-bit counter (1)
16-to-1 multiplexer
32-to-1 multiplexer
16-bit XORfunction
—
—
—
—
—
16
64
11
24
5
0
0
0
0
0
184.1
83.2
17.4
12.5
9.0
118.3
80.5
20.4
25.3
16.1
247.5
154.8
8.0
201.1
125.8
9.3
MHz
MHz
ns
LE
9.0
11.4
8.2
ns
6.6
ns
16-bit decoder with
single address line
—
5
0
9.2
16.1
6.6
8.2
ns
May 2011 Altera Corporation
MAX V Device Handbook
3–12
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–17. Device Performance for MAX V Devices (Part 2 of 2)
Resources Used
Performance
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
Resource
Used
Design Size and
Function
5M240Z/ 5M570Z
Unit
UFM
Blocks
Mode
LEs
C4
C5, I5
C4
C5, I5
512 × 16
512 × 16
None
3
1
1
10.0
9.7
10.0
9.7
10.0
8.0
10.0
8.0
MHz
MHz
SPI (2)
37
UFM
Parallel
(3)
I2C (3)
512 × 8
73
1
1
(4)
(4)
(4)
(4)
MHz
kHz
512 × 16
142
100 (5)
100 (5)
100 (5)
100 (5)
Notes to Table 3–17:
(1) This design is a binary loadable up counter.
(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of logic elements (LEs) used.
(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.
(4) This design is asynchronous.
(5) The I2C megafunction is verified in hardware up to 100-kHz serial clock line rate.
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis independent of device
density. Table 3–18 through Table 3–25 on page 3–19 list the MAX V device internal
timing microparameters for LEs, input/output elements (IOEs), UFM blocks, and
MultiTrack interconnects.
f For more information about each internal timing microparameters symbol, refer to
AN629: Understanding Timing in Altera CPLDs.
Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part 1 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
Symbol
Parameter
Unit
C4
C5, I5
Max
C4
C5, I5
Min
Max
Min
Min
Max
Min
Max
LE combinational look-up
table (LUT) delay
tLUT
—
1,215
—
2,247
—
742
—
914
ps
tCOMB
tCLR
Combinational path delay
LE register clear delay
LE register preset delay
—
401
401
243
—
—
545
545
309
—
—
309
309
192
—
—
381
381
236
—
ps
ps
ps
tPRE
—
—
—
—
LE register setup time
before clock
tSU
tH
260
0
—
—
321
0
—
—
271
0
—
—
333
0
—
—
ps
ps
ps
LE register hold time
after clock
LE register
clock-to-output delay
tCO
—
380
—
494
—
305
—
376
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–13
Timing Model and Specifications
Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part 2 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
C4 C5, I5
Symbol
Parameter
Unit
C4
C5, I5
Min
253
—
Max
—
Min
339
—
Max
Min
216
—
Max
—
Min
266
—
Max
Minimum clock high or
low time
tCLKHL
tC
—
—
ps
ps
Register control delay
1,356
1,741
1,114
1,372
Table 3–19. IOE Internal Timing Microparameters for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
C4 C5, I5
Symbol
Parameter
Unit
C4
C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Data output delay from
adjacent LE to I/O block
tFASTIO
tIN
—
170
—
428
—
207
—
254
ps
ps
I/O input pad and buffer
delay
—
—
907
—
—
986
—
—
920
—
—
1,132
2,430
I/O input pad and buffer
tGLOB (1) delay used as global
2,261
3,322
1,974
ps
signal pin
Internally generated
tIOE
—
—
—
530
318
—
—
—
1,410
509
—
—
—
374
291
—
—
—
460
358
ps
ps
ps
output enable delay
tDL
Input routing delay
Output delay buffer and
pad delay
tOD (2)
1,319
1,543
1,383
1,702
Output buffer disable
delay
tXZ (3)
tZX (4)
—
—
1,045
1,160
—
—
1,276
1,353
—
—
982
—
—
1,209
1,604
ps
ps
Output buffer enable
delay
1,303
Notes to Table 3–19:
(1) Delay numbers for tGLOB differ for each device density and speed grade. The delay numbers for tGLOB, shown in Table 3–19, are based on a 5M240Z
device target.
(2) For more information about delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–34 on page 3–24
and Table 3–35 on page 3–25.
(3) For more information about tXZ delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–22 on
page 3–15 and Table 3–23 on page 3–15.
(4) For more information about tZX delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–20 on
page 3–14 and Table 3–21 on page 3–14.
May 2011 Altera Corporation
MAX V Device Handbook
3–14
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–20 through Table 3–23 list the adder delays for tZX and tXZ microparameters
when using an I/O standard other than 3.3-V LVTTL with 16 mA drive strength.
Table 3–20. tZX IOE Microparameter Adders for Fast Slew Rate for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
Standard
Unit
C4
C5, I5
C4 C5, I5
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
16 mA
8 mA
8 mA
4 mA
14 mA
7 mA
6 mA
3 mA
4 mA
2 mA
3 mA
20 mA
—
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
72
74
101
0
125
0
0
0
3.3-V LVCMOS
72
74
101
155
545
721
2012
1590
3269
2860
–18
155
155
125
191
671
888
126
196
608
681
1162
1245
1889
72
127
197
610
685
2.5-V LVTTL /
LVCMOS
1.8-V LVTTL /
LVCMOS
2477
1957
4024
3520
–22
1157
1244
1856
74
1.5-V LVCMOS
1.2-V LVCMOS
3.3-V PCI
LVDS
126
126
127
191
RSDS
—
127
191
Table 3–21. tZX IOE Microparameter Adders for Slow Slew Rate for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
C4 C5, I5
5M240Z/ 5M570Z
C5, I5
Max
Standard
Unit
C4
Min
—
—
—
—
—
—
—
—
—
—
—
—
Max
5,951
6,534
5,951
6,534
9,110
9,830
21,800
23,020
39,120
40,670
69,505
6,534
Min
—
—
—
—
—
—
—
—
—
—
—
—
Min
—
—
—
—
—
—
—
—
—
—
—
—
Max
6,012
8,785
6,012
8,785
10,072
12,945
21,185
24,597
34,517
39,717
55,800
35
Min
—
—
—
—
—
—
—
—
—
—
—
—
Max
5,743
8,516
5,743
8,516
9,803
12,676
20,916
24,328
34,248
39,448
55,531
44
16 mA
8 mA
8 mA
4 mA
14 mA
7 mA
6 mA
3 mA
4 mA
2 mA
3 mA
20 mA
6,063
6,662
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
6,063
3.3-V LVCMOS
6,662
9,237
2.5-V LVTTL /
LVCMOS
9,977
21,787
23,037
39,067
40,617
70,461
6,662
1.8-V LVTTL /
LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.3-V PCI
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–15
Timing Model and Specifications
Table 3–22. tXZ IOE Microparameter Adders for Fast Slew Rate for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
Standard
Unit
C4
C5, I5
C4 C5, I5
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
16 mA
8 mA
8 mA
4 mA
14 mA
7 mA
6 mA
3 mA
4 mA
2 mA
3 mA
20 mA
—
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
–69
0
–69
0
–74
0
–91
0
3.3-V LVCMOS
–69
–7
–69
–10
–69
37
–74
–46
–82
–7
–91
–56
2.5-V LVTTL /
LVCMOS
–66
45
–101
–8
1.8-V LVTTL /
LVCMOS
34
25
119
339
464
817
80
147
418
571
1,006
99
166
190
300
–69
–7
155
179
283
–69
–10
–10
1.5-V LVCMOS
1.2-V LVCMOS
3.3-V PCI
LVDS
–46
–46
–56
–56
RSDS
—
–7
Table 3–23. tXZ IOE Microparameter Adders for Slow Slew Rate for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
Standard
Unit
C4
C5, I5
C4 C5, I5
Min
—
—
—
—
—
—
—
—
—
—
—
—
Max
171
112
171
112
213
166
441
496
765
903
1,159
112
Min
—
—
—
—
—
—
—
—
—
—
—
—
Max
174
116
174
116
213
166
438
494
755
897
Min
—
—
—
—
—
—
—
—
—
—
—
—
Max
73
Min
—
—
—
—
—
—
—
—
—
—
—
—
Max
–132
553
16 mA
8 mA
8 mA
4 mA
14 mA
7 mA
6 mA
3 mA
4 mA
2 mA
3 mA
20 mA
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
758
73
–132
553
3.3-V LVCMOS
758
32
–173
509
2.5-V LVTTL /
LVCMOS
714
96
–109
758
1.8-V LVTTL /
LVCMOS
963
238
1,319
400
303
33
1.5-V LVCMOS
1,114
195
1.2-V LVCMOS
3.3-V PCI
1,130
116
373
May 2011 Altera Corporation
MAX V Device Handbook
3–16
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
1
The default slew rate setting for MAX V devices in the Quartus II design software is
“fast”.
Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 1 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
Symbol
Parameter
Unit
C4
C5, I5
C4 C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Address register clock
period
tACLK
100
—
100
—
100
—
100
—
ns
ns
Address register shift
signal setup to address
register clock
tASU
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
Address register shift
signal hold to address
register clock
tAH
ns
ns
Address register data in
setup to address register
clock
tADS
Address register data in
hold from address
register clock
tADH
tDCLK
tDSS
20
100
60
—
—
—
20
100
60
—
—
—
20
100
60
—
—
—
20
100
60
—
—
—
ns
ns
ns
Data register clock period
Data register shift signal
setup to data register
clock
Data register shift signal
hold from data register
clock
tDSH
20
20
—
—
20
20
—
—
20
20
—
—
20
20
—
—
ns
ns
Data register data in
setup to data register
clock
tDDS
Data register data in hold
from data register clock
tDDH
tDP
20
0
—
—
20
0
—
—
20
0
—
—
20
0
—
—
ns
ns
Program signal to data
clock hold time
Maximum delay between
program rising edge to
UFM busysignal rising
edge
tPB
—
960
—
960
—
960
—
960
ns
Minimum delay allowed
from UFM busysignal
going low to program
signal going low
tBP
20
—
—
20
—
—
20
—
—
20
—
—
ns
µs
Maximum length of busy
pulse during a program
tPPMX
100
100
100
100
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–17
Timing Model and Specifications
Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 2 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
Symbol
Parameter
Unit
C4
C5, I5
C4 C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Minimum erasesignal
to address clock hold
time
tAE
0
—
0
—
0
—
0
—
ns
ns
Maximum delay between
the eraserising edge to
the UFM busysignal
rising edge
tEB
—
20
960
—
—
20
960
—
—
20
960
—
—
20
960
—
Minimum delay allowed
from the UFM busy
signal going low to
tBE
ns
erasesignal going low
Maximum length of busy
pulse during an erase
tEPMX
—
—
500
5
—
—
500
5
—
—
500
5
—
—
500
5
ms
ns
Delay from data register
clock to data register
output
tDCO
Delay from OSC_ENA
signal reaching UFM to
rising clock of OSC
leaving the UFM
tOE
180
—
—
65
—
180
—
—
65
—
180
—
—
65
—
180
—
—
65
—
ns
ns
ns
Maximum read access
time
tRA
Maximum delay between
the OSC_ENArising edge
to the erase/program
signal rising edge
tOSCS
250
250
250
250
Minimum delay allowed
from the
erase/programsignal
going low to OSC_ENA
signal going low
tOSCH
250
—
250
—
250
—
250
—
ns
May 2011 Altera Corporation
MAX V Device Handbook
3–18
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Figure 3–3 through Figure 3–5 show the read, program, and erase waveforms for
UFM block timing parameters listed in Table 3–24.
Figure 3–3. UFM Read Waveform
ARShft
tAH
9 Address Bits
tACLK
tASU
ARClk
ARDin
DRShft
DRClk
tADH
tADS
16 Data Bits
tDSH
tDCLK
tDSS
tDCO
DRDin
DRDout
OSC_ENA
Program
Erase
Busy
Figure 3–4. UFM Program Waveform
9 Address Bits
tACLK
ARShft
ARClk
tAH
tADH
tASU
ARDin
DRShft
DRClk
DRDin
DRDout
tADS
16 Data Bits
tDCLK
tDSH
tDSS
tDDH
tDDS
tOSCH
tOSCS
OSC_ENA
Program
tPB
Erase
tBP
Busy
tPPMX
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–19
Timing Model and Specifications
Figure 3–5. UFM Erase Waveform
9 Address Bits
ARShft
ARClk
tACLK
tAH
tASU
tADH
ARDin
DRShft
DRClk
DRDin
DRDout
tADS
OSC_ENA
tOSCS
tOSCH
Program
Erase
tEB
tBE
Busy
tEPMX
Table 3–25. Routing Delay Internal Timing Microparameters for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
Routing
Unit
C4
C5, I5
C4
C5, I5
Min
—
Max
860
Min
—
Max
Min
—
Max
561
445
731
Min
—
Max
690
548
899
tC4
1,973
1,479
2,947
ps
ps
ps
tR4
—
655
—
—
—
tLOCAL
—
1,143
—
—
—
External Timing Parameters
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in Table 3–32 on page 3–23 through Table 3–36 on page 3–25.
f For more information about each external timing parameters symbol, refer to
AN629: Understanding Timing in Altera CPLDs.
May 2011 Altera Corporation
MAX V Device Handbook
3–20
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–26 lists the external I/O timing parameters for the 5M40Z, 5M80Z, 5M160Z,
and 5M240Z devices.
Table 3–26. Global Clock External I/O Timing Parameters for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z Devices
(Note 1), (2)
C4
C5, I5
Symbol
tPD1
Parameter
Condition
Unit
Min
—
Max
7.9
5.8
—
Min
—
Max
14.0
8.5
—
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
10 pF
10 pF
—
ns
ns
ns
ns
ns
ps
ps
tPD2
tSU
tH
—
—
2.4
0
4.6
0
Global clock hold time
—
—
—
tCO
tCH
tCL
Global clock to output delay
Global clock high time
10 pF
—
2.0
253
253
6.6
—
2.0
339
339
8.6
—
Global clock low time
—
—
—
Minimum global clock period for
16-bit counter
tCNT
fCNT
—
—
5.4
—
—
8.4
—
—
ns
Maximum global clock frequency for 16-bit
counter
184.1
118.3
MHz
Notes to Table 3–26:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
(2) Not applicable to the T144 package of the 5M240Z device.
Table 3–27 lists the external I/O timing parameters for the T144 package of the
5M240Z device.
Table 3–27. Global Clock External I/O Timing Parameters for the 5M240Z Device (Note 1), (2)
C4
C5, I5
Symbol
tPD1
Parameter
Condition
Unit
Min
—
Max
9.5
5.7
—
Min
—
Max
17.7
8.5
—
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
10 pF
10 pF
—
ns
ns
ns
ns
ns
ps
ps
tPD2
tSU
tH
—
—
2.2
0
4.4
0
Global clock hold time
—
—
—
tCO
tCH
tCL
Global clock to output delay
Global clock high time
10 pF
—
2.0
253
253
6.7
—
2.0
339
339
8.7
—
Global clock low time
—
—
—
Minimum global clock period for 16-bit
counter
tCNT
fCNT
—
—
5.4
—
—
8.4
—
—
ns
Maximum global clock frequency for 16-bit
counter
184.1
118.3
MHz
Notes to Table 3–27:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
(2) Only applicable to the T144 package of the 5M240Z device.
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–21
Timing Model and Specifications
Table 3–28 lists the external I/O timing parameters for the 5M570Z device.
Table 3–28. Global Clock External I/O Timing Parameters for the 5M570Z Device (Note 1)
C4
C5, I5
Symbol
tPD1
Parameter
Condition
Unit
Min
—
Max
9.5
5.7
—
Min
—
Max
17.7
8.5
—
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
10 pF
10 pF
—
ns
ns
ns
ns
ns
ps
ps
tPD2
tSU
tH
—
—
2.2
0
4.4
0
Global clock hold time
—
—
—
tCO
tCH
tCL
Global clock to output delay
Global clock high time
10 pF
—
2.0
253
253
6.7
—
2.0
339
339
8.7
—
Global clock low time
—
—
—
Minimum global clock period for 16-bit
counter
tCNT
fCNT
—
—
5.4
—
—
8.4
—
—
ns
Maximum global clock frequency for 16-bit
counter
184.1
118.3
MHz
Note to Table 3–28:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
Table 3–29 lists the external I/O timing parameters for the 5M1270Z device.
Table 3–29. Global Clock External I/O Timing Parameters for the 5M1270Z Device (Note 1), (2)
C4
C5, I5
Symbol
tPD1
Parameter
Condition
Unit
Min
—
Max
8.1
4.8
—
Min
—
Max
10.0
5.9
—
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
10 pF
10 pF
—
ns
ns
ns
ns
ns
ps
ps
tPD2
tSU
tH
—
—
1.5
0
1.9
0
Global clock hold time
—
—
—
tCO
tCH
tCL
Global clock to output delay
Global clock high time
10 pF
—
2.0
216
216
5.9
—
2.0
266
266
7.3
—
Global clock low time
—
—
—
Minimum global clock period for 16-bit
counter
tCNT
fCNT
—
—
4.0
—
—
5.0
—
—
ns
Maximum global clock frequency for 16-bit
counter
247.5
201.1
MHz
Notes to Table 3–29:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
(2) Not applicable to the F324 package of the 5M1270Z device.
May 2011 Altera Corporation
MAX V Device Handbook
3–22
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–30 lists the external I/O timing parameters for the F324 package of the
5M1270Z device.
Table 3–30. Global Clock External I/O Timing Parameters for the 5M1270Z Device (Note 1), (2)
C4
C5, I5
Symbol
tPD1
Parameter
Condition
Unit
Min
—
Max
9.1
4.8
—
Min
—
Max
11.2
5.9
—
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
10 pF
10 pF
—
ns
ns
ns
ns
ns
ps
ps
tPD2
tSU
tH
—
—
1.5
0
1.9
0
Global clock hold time
—
—
—
tCO
tCH
tCL
Global clock to output delay
Global clock high time
10 pF
—
2.0
216
216
6.0
—
2.0
266
266
7.4
—
Global clock low time
—
—
—
Minimum global clock period for 16-bit
counter
tCNT
fCNT
—
—
4.0
—
—
5.0
—
—
ns
Maximum global clock frequency for 16-bit
counter
247.5
201.1
MHz
Notes to Table 3–30:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
(2) Only applicable to the F324 package of the 5M1270Z device.
Table 3–31 lists the external I/O timing parameters for the 5M2210Z device.
Table 3–31. Global Clock External I/O Timing Parameters for the 5M2210Z Device (Note 1)
C4
C5, I5
Symbol
tPD1
Parameter
Condition
Unit
Min
—
Max
9.1
4.8
—
Min
—
Max
11.2
5.9
—
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
10 pF
10 pF
—
ns
ns
ns
ns
ns
ps
ps
tPD2
tSU
tH
—
—
1.5
0
1.9
0
Global clock hold time
—
—
—
tCO
tCH
tCL
Global clock to output delay
Global clock high time
10 pF
—
2.0
216
216
6.0
—
2.0
266
266
7.4
—
Global clock low time
—
—
—
Minimum global clock period for 16-bit
counter
tCNT
fCNT
—
—
4.0
—
—
5.0
—
—
ns
Maximum global clock frequency for 16-bit
counter
247.5
201.1
MHz
Note to Table 3–31:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–23
Timing Model and Specifications
External Timing I/O Delay Adders
The I/O delay timing parameters for the I/O standard input and output adders and
the input delays are specified by speed grade, independent of device density.
Table 3–32 through Table 3–36 on page 3–25 list the adder delays associated with I/O
pins for all packages. If you select an I/O standard other than 3.3-V LVTTL, add the
input delay adder to the external tSU timing parameters listed in Table 3–26 on
page 3–20 through Table 3–31. If you select an I/O standard other than 3.3-V LVTTL
with 16 mA drive strength and fast slew rate, add the output delay adder to the
external tCO and tPD listed in Table 3–26 on page 3–20 through Table 3–31.
Table 3–32. External Timing Input Delay Adders for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
C4 C5, I5
I/O Standard
Unit
C4
C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Without Schmitt
Trigger
—
0
—
0
—
0
—
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
With Schmitt
Trigger
—
—
—
—
—
—
—
—
—
387
0
—
—
—
—
—
—
—
—
—
442
0
—
—
—
—
—
—
—
—
—
480
0
—
—
—
—
—
—
—
—
—
591
0
Without Schmitt
Trigger
3.3-V LVCMOS
With Schmitt
Trigger
387
42
442
42
480
246
787
695
1,334
2,324
0
591
303
968
855
Without Schmitt
Trigger
2.5-V LVTTL /
LVCMOS
With Schmitt
Trigger
429
378
681
1,055
0
483
368
658
1.8-V LVTTL / Without Schmitt
LVCMOS
Trigger
Without Schmitt
Trigger
1.5-V LVCMOS
1,642
2,860
0
Without Schmitt
Trigger
1.2-V LVCMOS
3.3-V PCI
1,010
0
Without Schmitt
Trigger
Table 3–33. External Timing Input Delay tGLOB Adders for GCLK Pins for MAX V Devices (Part 1 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
I/O Standard
Unit
C4
C5, I5
C4
C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Without Schmitt
Trigger
—
0
—
0
—
0
—
0
ps
ps
3.3-V LVTTL
With Schmitt
Trigger
—
387
—
442
—
400
—
493
May 2011 Altera Corporation
MAX V Device Handbook
3–24
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–33. External Timing Input Delay tGLOB Adders for GCLK Pins for MAX V Devices (Part 2 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
I/O Standard
Unit
C4
C5, I5
C4
C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Without Schmitt
Trigger
—
0
—
0
—
0
—
0
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVCMOS
With Schmitt
Trigger
—
—
—
—
—
—
—
387
242
429
378
681
1,055
0
—
—
—
—
—
—
—
442
242
483
368
658
—
—
—
—
—
—
—
400
287
550
459
1,111
2,067
7
—
—
—
—
—
—
—
493
353
677
565
Without Schmitt
Trigger
2.5-V LVTTL /
LVCMOS
With Schmitt
Trigger
1.8-V LVTTL / Without Schmitt
LVCMOS
Trigger
Without Schmitt
Trigger
1.5-V LVCMOS
1,368
2,544
9
Without Schmitt
Trigger
1.2-V LVCMOS
3.3-V PCI
1,010
0
Without Schmitt
Trigger
Table 3–34. External Timing Output Delay and tOD Adders for Fast Slew Rate for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
C4 C5, I5
5M240Z/ 5M570Z
I/O Standard
Unit
C4
C5, I5
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
16 mA
8 mA
8 mA
4 mA
14 mA
7 mA
6 mA
3 mA
4 mA
2 mA
3 mA
20 mA
—
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
39
58
84
104
0
0
0
0
3.3-V LVCMOS
39
58
84
104
195
309
909
122
196
624
686
1,188
1,279
1,911
39
129
188
624
694
158
251
738
850
1,376
1,517
2,206
4
2.5-V LVTTL / LVCMOS
1.8-V LVTTL / LVCMOS
1.5-V LVCMOS
1,046
1,694
1,867
2,715
5
1,184
1,280
1,883
58
1.2-V LVCMOS
3.3-V PCI
LVDS
122
122
129
158
158
195
RSDS
—
129
195
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–25
Timing Model and Specifications
Table 3–35. External Timing Output Delay and tOD Adders for Slow Slew Rate for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
C5, I5
Max
I/O Standard
Unit
C4
C4
C5, I5
Max
Min
—
—
—
—
—
—
—
—
—
—
—
—
Max
5,913
6,488
5,913
6,488
9,088
9,808
21,758
23,028
39,068
40,578
69,332
6,488
Min
—
—
—
—
—
—
—
—
—
—
—
—
Min
—
—
—
—
—
—
—
—
—
—
—
—
Max
6,612
7,313
6,612
7,313
10,021
10,881
21,134
22,399
34,499
36,281
55,796
339
Min
—
—
—
—
—
—
—
—
—
—
—
—
16 mA
8 mA
8 mA
4 mA
14 mA
7 mA
6 mA
3 mA
4 mA
2 mA
3 mA
20 mA
6,043
6,645
6,043
6,645
9,222
9,962
21,782
23,032
39,032
40,542
70,257
6,645
6,293
6,994
6,293
6,994
9,702
10,562
20,815
22,080
34,180
35,962
55,477
418
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL / LVCMOS
1.8-V LVTTL / LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.3-V PCI
Table 3–36. IOE Programmable Delays for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
C4 C5, I5
5M240Z/ 5M570Z
C5, I5
Max
Parameter
Unit
C4
Min
Max
Min
Min
Max
Min
Max
Input Delay from Pin to Internal
Cells = 1
—
1,858
—
2,214
616
—
1,592
—
1,960
ps
ps
Input Delay from Pin to Internal
Cells = 0
—
569
—
—
115
—
142
May 2011 Altera Corporation
MAX V Device Handbook
3–26
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Maximum Input and Output Clock Rates
Table 3–37 and Table 3–38 list the maximum input and output clock rates for standard
I/O pins in MAX V devices.
Table 3–37. Maximum Input Clock Rate for I/Os for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z/5M1270Z/
I/O Standard
Unit
5M2210Z
C4, C5, I5
304
Without Schmitt Trigger
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
3.3-V LVTTL
With Schmitt Trigger
304
Without Schmitt Trigger
With Schmitt Trigger
304
3.3-V LVCMOS
2.5-V LVTTL
304
Without Schmitt Trigger
With Schmitt Trigger
304
304
Without Schmitt Trigger
With Schmitt Trigger
304
2.5-V LVCMOS
304
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.3-V PCI
Without Schmitt Trigger
Without Schmitt Trigger
Without Schmitt Trigger
Without Schmitt Trigger
Without Schmitt Trigger
200
200
150
120
304
Table 3–38. Maximum Output Clock Rate for I/Os for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z/5M1270Z/
5M2210Z
I/O Standard
Unit
C4, C5, I5
304
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.3-V PCI
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
304
304
304
200
200
150
120
304
LVDS
304
RSDS
200
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–27
Timing Model and Specifications
LVDS and RSDS Output Timing Specifications
Table 3–39 lists the emulated LVDS output timing specifications for MAX V devices.
Table 3–39. Emulated LVDS Output Timing Specifications for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z/5M1270Z/
5M2210Z
Parameter
Mode
Unit
C4, C5, I5
Min
Max
304
304
304
304
304
304
304
304
304
304
55
10
9
8
7
6
5
4
3
2
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
45
—
—
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
Data rate (1), (2)
tDUTY
Total jitter (3)
tRISE
0.2
UI
450
450
ps
tFALL
ps
Notes to Table 3–39:
(1) The performance of the LVDS_E_3R transmitter system is limited by the lower of the two—the maximum data rate supported by LVDS_E_3R
I/O buffer or 2x (FMAX of the ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through
the Quartus II timing analysis of the complete design.
(2) For the input clock pin to achieve 304 Mbps, use I/O standard with VCCIO of 2.5 V and above.
(3) This specification is based on external clean clock source.
May 2011 Altera Corporation
MAX V Device Handbook
3–28
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–40 lists the emulated RSDS output timing specifications for MAX V devices.
Table 3–40. Emulated RSDS Output Timing Specifications for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z/5M1270Z/
5M2210Z
Parameter
Mode
Unit
C4, C5, I5
Min
Max
200
200
200
200
200
200
200
200
200
200
55
10
9
8
7
6
5
4
3
2
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
45
—
—
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
Data rate (1)
tDUTY
Total jitter (2)
tRISE
0.2
UI
450
450
ps
tFALL
ps
Notes to Table 3–40:
(1) For the input clock pin to achieve 200 Mbps, use I/O standard with VCCIO of 1.8 V and above.
(2) This specification is based on external clean clock source.
MAX V Device Handbook
May 2011 Altera Corporation
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–29
Timing Model and Specifications
JTAG Timing Specifications
Figure 3–6 shows the timing waveform for the JTAG signals for the MAX V device
family.
Figure 3–6. JTAG Timing Waveform for MAX V Devices
TMS
TDI
t
JCP
t
t
JPH
JPSU
t
t
JCL
JCH
TCK
TDO
t
t
t
JPXZ
JPZX
JPCO
t
t
JSSU
JSH
Signal
to be
Captured
t
t
t
JSXZ
JSZX
JSCO
Signal
to be
Driven
Table 3–41 lists the JTAG timing parameters and values for the MAX V device family.
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 1 of 2)
Symbol
Parameter
TCKclock period for VCCIO1 = 3.3 V
TCKclock period for VCCIO1 = 2.5 V
TCKclock period for VCCIO1 = 1.8 V
TCKclock period for VCCIO1 = 1.5 V
TCKclock high time
Min
55.5
62.5
100
143
20
Max
—
—
—
—
—
—
—
—
15
15
15
—
—
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP (1)
tJCH
tJCL
TCK clock low time
20
tJPSU
tJPH
JTAG port setup time (2)
8
JTAG port hold time
10
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output (2)
JTAG port high impedance to valid output (2)
JTAG port valid output to high impedance (2)
Capture register setup time
—
—
—
8
Capture register hold time
10
tJSCO
tJSZX
Update register clock to output
Update register high impedance to valid output
—
—
May 2011 Altera Corporation
MAX V Device Handbook
3–30
Chapter 3: DC and Switching Characteristics for MAX V Devices
Document Revision History
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
tJSXZ
Notes to Table 3–41:
(1) Minimum clock period specified for 10 pF load on the TDOpin. Larger loads on TDOdegrades the maximum TCKfrequency.
Update register valid output to high impedance
—
25
ns
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and
1.5-V LVCMOS operation, the tJPSU minimum is 6 ns and tJPCO, tJPZX, and tJPXZ are maximum values at 35 ns.
Document Revision History
Table 3–42 lists the revision history for this chapter.
Table 3–42. Document Revision History
Date
May 2011
Version
1.2
Changes
Updated Table 3–2, Table 3–15, Table 3–16, and Table 3–33.
Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40.
Initial release.
January 2011
1.1
December 2010
1.0
MAX V Device Handbook
May 2011 Altera Corporation
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Flash PLD, 7.9ns, 64-Cell, CMOS, PBGA68, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, MBGA-68
INTEL
5M80ZM68C4N
Flash PLD, 7.9ns, 64-Cell, CMOS, PBGA68, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, MBGA-68
ALTERA
5M80ZM68C5N
Flash PLD, 14ns, 64-Cell, CMOS, PBGA68, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, MBGA-68
INTEL
5M80ZM68C5N
Flash PLD, 14ns, 64-Cell, CMOS, PBGA68, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, MBGA-68
ALTERA
5M80ZM68I5N
Flash PLD, 14ns, 64-Cell, CMOS, PBGA68, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, MBGA-68
INTEL
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