5CGTD9_技术文档

Cyclone V Device Handbook Volume 1: Device Overview

and Datasheet

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

101 Innovation Drive

San Jose, CA 95134

www.altera.com

Document last updated for Altera Complete Design Suite version:

Document publication date:

11.1

February 2012

CV-5V1-1.2

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

ISO

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

Contents

Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Chapter 1. Overview for Cyclone V Device Family

Cyclone V Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Cyclone V Family Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Low-Power Serial Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8

PMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9

PCS Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9

PCIe Gen1 and Gen2 Hard IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11

FPGA GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11

External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12

Adaptive Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12

Variable-Precision DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13

Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14

Dynamic and Partial Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15

Clock Networks and PLL Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15

Enhanced Configuration and Configuration via Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17

SoC FPGA with HPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17

Features of the HPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18

System Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18

HPS–FPGA AXI Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19

HPS SDRAM Controller Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19

FPGA Configuration and Processor Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19

Hardware and Software Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–20

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23

Chapter 2. Device Datasheet for Cyclone V Devices

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Internal Weak Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Transceiver Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Core Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

DSP Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

High-Speed I/O Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

DQS Logic Block and Memory Output Clock Jitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . 2–24

OCT Calibration Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

iv

Contents

Duty Cycle Distortion (DCD) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

Configuration Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

POR Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

JTAG Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

DCLK-to-DATA[] Ratio (r) for FPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

FPP Configuration Timing when DCLK to DATA[] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

FPP Configuration Timing when DCLK to DATA[] > 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

AS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Remote System Upgrades Circuitry Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

User Watchdog Internal Oscillator Frequency Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

Programmable IOE Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–40

Additional Information

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter Revision Dates

The chapters in this document, Cyclone V Device Handbook, were revised on the

following dates. Where chapters or groups of chapters are available separately, part

numbers are listed.

Chapter 1. Overview for Cyclone V Device Family

Revised: February 2012

Part Number: CV-51001-1.2

Chapter 2. Device Datasheet for Cyclone V Devices

Revised:

February 2012

Part Number: CV-51002-1.2

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

vi

Chapter Revision Dates

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

1. Overview for Cyclone V Device Family

February 2012

CV-51001-1.2

Cyclone^®V devices are designed to simultaneously accommodate the shrinking

power consumption, cost, and time-to-market requirements; and the increasing

bandwidth requirements for high-volume and cost-sensitive applications.

The Cyclone V devices are ideal for small form factor applications that are cost- and

power-sensitive in the wireless, wireline, military, broadcast, industrial, consumer,

and communications industries.

The Cyclone V device family is available in six variants:

■

Cyclone V E—optimized for the lowest system cost and power requirement for a

wide spectrum of general logic and digital signal processing (DSP) applications.

Cyclone V GX—optimized for the lowest cost and power requirement for

614-megabits per second (Mbps) to 3.125-gigabits per second (Gbps) transceiver

applications.

■

Cyclone V GT—the FPGA industry’s lowest cost and lowest power requirement

for 5-Gbps transceiver applications.

Cyclone V SE—system-on-a-chip (SoC) FPGA with integrated Cyclone V FPGA

and ARM^®-based hard processor system (HPS).

Cyclone V SX—SoC FPGA with integrated Cyclone V FPGA, ARM-based HPS,

and 3.125-Gbps transceivers.

Cyclone V ST—SoC FPGA with integrated Cyclone V FPGA, ARM-based HPS,

and 5-Gbps transceivers.

The Cyclone V SoC FPGA variants feature an FPGA integrated with an HPS that

consists of a dual-core ARM Cortex^™-A9 MPCore^™processor, a rich set of peripherals,

and a shared multiport SDRAM controller.

The Cyclone V device family provides the following key advantages:

■

Up to 40% lower power consumption than the previous generation device—built

on TSMC’s 28-nm low power (28LP) process and includes an abundance of hard

intellectual properties (IP).

■

Improved logic integration and differentiation capabilities—features a new

8-input adaptive logic module (ALM), up to 11.6 megabits (Mb) of dedicated

memory, and variable-precision DSP blocks.

■

Increased bandwidth capacity—a combined result of the new 3-Gbps and 5-Gbps

transceivers, and the hard memory controllers.

Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard IP, and

an FPGA in a single Cyclone V SoC FPGA—supports over 100 Gbps peak

bandwidth with integrated data coherency between the processor and the FPGA.

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012

Subscribe

1–2

Chapter 1: Overview for Cyclone V Device Family

Cyclone V Features Summary

Some of the key features of the Cyclone V devices include:

■

Built-in hard IP blocks

■

Support for all mainstream single-ended and differential I/O standards including

3.3 V at up to 16 mA drive strengths

■

HPS for the Cyclone V SE, SX, and ST variants

Comprehensive design protection features to protect your valuable IP investments

Lowest system cost advantage—requires only two core voltages to operate, are

available in low-cost wirebond packaging, and includes innovative cost saving

features such as Configuration via Protocol (CvP) and partial reconfiguration

Table 1–1 lists a summary of the Cyclone V features.

Table 1–1. Summary of Features for Cyclone V Devices (Part 1 of 2)

Feature

Technology

Details

■ TSMC’s 28-nm low power (28LP) process technology

■ 1.1-V core voltage

■ 614 Mbps to 5.0 Gbps integrated transceiver speed

■ Transmitter pre-emphasis and receiver equalization

■ Dynamic partial reconfiguration of individual channels

■ 875 Mbps LVDS receiver and 840 Mbps LVDS transmitter

■ 400 MHz/800 Mbps external memory interface

■ On-chip termination (OCT)

Low-power

high-speed serial

interface

FPGA

General-purpose

I/Os (GPIOs)

■ 3.3-V support with up to 16 mA drive strength

Embedded

transceiver I/O

PCI Express^®(PCIe^®) Gen2 (x1 or x2) and Gen1 (x1, x2, or x4) hard IP with

multifunction support, endpoint, and root port

■ Native support for three signal processing precision levels (three 9 x 9s, two

18 x 19s, or one 27 x 27 multiplier) in the same variable-precision DSP block

Hard IP blocks

Variable-precision

DSP

■ 64-bit accumulator and cascade

■ Embedded internal coefficient memory

■ Preadder/subtractor for improved efficiency

Memory controller DDR3, DDR2, LPDDR, and LPDDR2

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for Cyclone V Device Family

1–3

Cyclone V Features Summary

Table 1–1. Summary of Features for Cyclone V Devices (Part 2 of 2)

Feature

Details

■ Dual-core ARM Cortex-A9 MPCore processor—up to 800 MHz maximum frequency with support

for symmetric and asymmetric multiprocessing

■ Interface peripherals—10/100/1000 Ethernet media access control (MAC), USB 2.0 On-The-GO

(OTG) controller, serial peripheral interface (SPI), Quad SPI flash controller, NAND flash controller,

SD/MMC/SDIO controller, UART, controller area network (CAN), I2C interface, and up to 71 HPS I/O

interfaces

HPS

■ System peripherals—general-purpose and watchdog timers, direct memory access (DMA)

(Cyclone V SE, SX,

and ST devices

only)

controller, FPGA configuration manager, and clock and reset managers

■ On-chip RAM and boot ROM

■ HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA

bridges that allow the FPGA fabric to master transactions to slaves in the HPS, and vice versa.

■ FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport

front end (MPFE) of the HPS SDRAM controller

■ ARM CoreSight^™JTAG debug access port, trace port, and on-chip trace storage

High-performance

FPGA fabric

Enhanced 8-input ALM with four registers

■ M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)

Internal memory

blocks

■ Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25% of

the ALMs as MLAB memory

■ Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

■ Integer mode and fractional mode

Phase-locked

loops (PLLs)

■ 550 MHz global clock network

Clock networks

■ Global, quadrant, and peripheral clock networks

■ Clock networks that are not used can be powered down to reduce dynamic power

■ Partial and dynamic reconfiguration of the FPGA

■ CvP

■ Active serial (AS) x1 and x4, fast passive parallel (FPP) x8 and x16, passive serial (PS), and JTAG

Configuration

options

■ Enhanced advanced encryption standard (AES) design security features

■ Tamper protection

■ Wirebond low-halogen packages

■ Multiple device densities with compatible package footprints for seamless migration between

Packaging

different device densities

■ RoHS-compliant options

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–4

Chapter 1: Overview for Cyclone V Device Family

Cyclone V Family Plan

Table 1–2 and Table 1–3 list the Cyclone V E, GX, and GT maximum resource counts.

Table 1–2. Maximum Resource Counts for Cyclone V E Devices—Preliminary

Cyclone V E Device

Resource

5CEA2

9,434

25,000

1,700

196

25

5CEA4

18,113

48,000

2,700

270

5CEA5

28,868

76,500

3,800

440

5CEA7

56,415

149,500

6,500

836

5CEA9

113,585

301,000

11,600

1,717

342

ALM

Logic Element (LE)

Block Memory (Kb)

MLAB Memory (Kb)

Variable-precision DSP Block

18 x 19 Multiplier

Fractional PLL

72

124

156

50

144

248

312

684

4

6

GPIO

288

100

1

288

272

480

448

LVDS

100

122

Hard Memory Controller

1

2

Table 1–3. Maximum Resource Counts for Cyclone V GX and GT Devices—Preliminary

Cyclone V GX Device

Resource

Cyclone V GT Device

5CGXC3 5CGXC4 5CGXC5 5CGXC7 5CGXC9 5CGTD5 5CGTD7 5CGTD9

ALM

11,698

31,000

1,400

147

42

18,868

50,000

2,500

295

70

28,868

76,500

3,800

440

124

248

6

56,415

113,585

28,868

76,500

3,800

440

124

248

6

56,415

113,585

LE

149,500 301,000

Block Memory (Kb)

MLAB Memory (Kb)

Variable-precision DSP Block

18 x 19 Multiplier

Fractional PLL ⁽¹⁾

3-Gbps Transceiver

5-Gbps Transceiver

GPIO

6,500

836

156

312

7

11,600

1,717

342

684

8

6,500

836

156

312

7

11,600

1,717

342

684

8

84

140

6

4

3

6

9

12

—

6

9

12

224

48

368

90

368

100

2

480

122

2

560

122

2

368

100

2

480

122

2

560

122

2

LVDS

PCIe Hard IP Block

Hard Memory Controller

Note to Table 1–3:

1

2

1

2

(1) The maximum fractional PLLs listed include general purpose PLLs and transceiver PLLs.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for Cyclone V Device Family

1–5

Cyclone V Family Plan

Table 1–4 and Table 1–5 list the Cyclone V SE, SX, and ST maximum resource counts.

Table 1–4. Maximum Resource Counts for Cyclone V SE Devices—Preliminary

Cyclone V SE Devices

Resource

5CSEA2

9,434

25,000

1,400

138

36

5CSEA4

15,094

40,000

2,240

220

58

5CSEA5

32,075

85,000

3,972

480

87

5CSEA6

41,509

110,000

5,140

621

112

224

6

ALM

LE

Block Memory (Kb)

MLAB Memory (Kb)

Variable-precision DSP Block

18 x 19 Multiplier

FPGA Fractional PLL

HPS PLL

72

116

5

174

6

4

3

FPGA GPIO

124

188

31

124

188

31

288

188

72

288

188

72

HPS I/O

LVDS

FPGA Memory Controller

HPS Memory Controller

—

1

ARM Cortex-A9 MPCore Processor Single- or dual-core Single- or dual-core Single- or dual-core Single- or dual-core

Table 1–5. Maximum Resource Counts for Cyclone V SX and ST Devices—Preliminary (Part 1 of 2)

Cyclone V SX Device

Cyclone V ST Device

5CSTD5 5CSTD6

32,075 41,509

Resource

5CSXC4

15,094

40,000

2,240

220

58

5CSXC5

32,075

85,000

3,972

480

87

5CSXC6

41,509

110,000

5,140

621

112

224

6

ALM

LE

85,000

3,972

480

87

110,000

5,140

621

112

224

6

Block Memory (Kb)

MLAB Memory (Kb)

Variable-precision DSP Block

18 x 19 Multiplier

FPGA Fractional PLL ⁽¹⁾

HPS PLL

116

5

174

6

174

6

3

3-Gbps Transceiver

5-Gbps Transceiver

FPGA GPIO

6

9

—

9

124

188

31

288

188

72

288

188

72

288

188

72

288

188

72

HPS I/O

LVDS

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–6

Chapter 1: Overview for Cyclone V Device Family

Cyclone V Family Plan

Table 1–5. Maximum Resource Counts for Cyclone V SX and ST Devices—Preliminary (Part 2 of 2)

Cyclone V SX Device

Cyclone V ST Device

Resource

PCIe Hard IP Block

5CSXC4

5CSXC5

5CSXC6

5CSTD5

5CSTD6

2

FPGA Memory Controller

HPS Memory Controller

ARM Cortex-A9 MPCore Processor

Note to Table 1–5:

1

Dual-core

(1) The maximum FPGA fractional PLLs listed include FPGA general purpose PLLs and transceiver PLLs.

Table 1–6 lists the Cyclone V E, GX, and GT package plan that shows the GPIO count,

the maximum number of transceivers available, and the vertical migration capability

for each device package and density.

Table 1–6. Package Plan for Cyclone V E, GX, and GT Devices—Preliminary ⁽¹⁾

F256 U324 U484 F484

F672

(27 mm)

F896

(31 mm)

F1152

(35 mm)

(17 mm) (15 mm) (19 mm) (23 mm)

Device

5CEA2

5CEA4

144

—

176

—

3

288

272

240

—

3

288

272

240

224

208

240

224

240

224

—

3

—

560

—

560

—

6

—

9

—

12

—

12

5CEA5

—

5CEA7

—

336

—

480

448

—

5CEA9

—

5CGXC3 ⁽²⁾

5CGXC4 ⁽²⁾

5CGXC5 ⁽²⁾

5CGXC7 ⁽²⁾

5CGXC9 ⁽²⁾

5CGTD5 ⁽³⁾

5CGTD7 ⁽³⁾

5CGTD9 ⁽³⁾

Notes to Table 1–6:

112

—

208

224

240

—

6

336

368

336

—

6

—

6

9

480

448

—

6

9

12

—

9

—

240

—

6

—

6

9

480

448

—

6

9

12

(1) The arrows indicate the package vertical migration capability. You can also migrate your design across device densities in the same packaging

option if the devices have the same dedicated pins, configuration pins, and power pins.

(2) The transceiver counts listed are for 3-Gbps transceivers.

(3) The transceiver counts listed are for 5-Gbps transceivers.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for Cyclone V Device Family

1–7

Cyclone V Family Plan

Table 1–7 lists the Cyclone V SE, SX, and ST package plan that shows the FPGA GPIO

and HPS I/O counts, the maximum number of transceivers available, and the vertical

migration capability for each device package and density.

Table 1–7. Package Plan for Cyclone V SE, SX, and ST Devices—Preliminary ⁽¹⁾

U484 U672

F896

(31 mm)

(19 mm) (23 mm)

Device

GPIO

66

—

XCVR

—

HPS I/O

161

—

GPIO

124

—

XCVR

—

6

HPS I/O

188

—

GPIO

—

XCVR

—

9

HPS I/O

—

5CSEA2

5CSEA4

—

5CSEA5

—

288

—

188

—

5CSEA6

—

5CSXC4 ⁽²⁾

5CSXC5 ⁽²⁾

5CSXC6 ⁽²⁾

5CSTD5 ⁽³⁾

5CSTD6 ⁽³⁾

Notes to Table 1–7:

—

6

288

188

—

6

9

—

9

—

9

(1) The arrows indicate the package vertical migration capability. You can also migrate your design across device densities in the same packaging

option if the devices have the same dedicated pins, configuration pins, and power pins.

(2) The transceiver counts listed are for 3-Gbps transceivers.

(3) The transceiver counts listed are for 5-Gbps transceivers.

1

To verify the pin migration compatibility, use the Pin Migration View window in the

Quartus II software Pin Planner.

f

For more information about the verifying the pin migration compatibility, refer to the

“I/O Management” chapter in the Quartus II Handbook.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–8

Chapter 1: Overview for Cyclone V Device Family

Low-Power Serial Transceivers

Cyclone V devices deliver the industry’s lowest power 5-Gbps transceivers at an

estimated 88 mW maximum power consumption per channel. Cyclone V transceivers

are designed to be compliant for a wide range of protocols and data rates. The

transceivers are positioned on the left outer edge of the device, as shown in

Figure 1–1. The transceiver channels consist of the physical medium attachment

(PMA), physical coding sublayer (PCS), and clock networks.

Figure 1–1. Device Chip Overview for Cyclone V GX and GT Devices ⁽¹⁾

I/O, LVDS, and Memory Interface

Hard Memory Controller

Transceiver

PMA

Hard

PCS

Transceiver

PMA

Hard

PCS

Transceiver

PMA

Hard

PCS

Transceiver

Individual Channels

Distributed Memory

Core Logic Fabric and MLABs

M10K Internal Memory Blocks

Variable-Precision DSP Blocks

Hard Memory Controller

I/O, LVDS, and Memory Interface

Note to Figure 1–1:

(1) This figure represents a Cyclone V device with transceivers. Other Cyclone V devices may have a different floor plan than the one shown here.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for Cyclone V Device Family

1–9

Low-Power Serial Transceivers

PMA Support

To prevent core and I/O noise from coupling into the transceivers, the PMA block is

isolated from the rest of the chip—ensuring optimal signal integrity. For the

transceivers, you can use the channel PLL of an unused receiver PMA as an additional

transmit PLL.

Table 1–8 lists the PMA features of the transceiver.

Table 1–8. PMA Features of the Transceivers in Cyclone V Devices

Features

Capability

Up to 16” FR4 PCB fabric drive capability at up to 5 Gbps

Superior jitter tolerance

Backplane support

PLL-based clock recovery

Programmable deserialization and word alignment Flexible deserialization width and configurable word alignment pattern

Up to 6 dB of pre-emphasis, up to 4 dB of equalization, and no

Equalization and pre-emphasis

decision feedback equalizer (DFE)

Ring oscillator transmit PLLs

Input reference clock range

614 Mbps to 5 Gbps

20 MHz to 400 MHz

Allows the reconfiguration of a single channel without affecting the

operation of other channels

Transceiver dynamic reconfiguration

PCS Support

The Cyclone V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, or 40-bit

interface, depending on the transceiver data rate and protocol. Cyclone V devices

contain PCS hard IP to support PCIe Gen1 and Gen2, XAUI, Gbps Ethernet (GbE),

Serial RapidIO^®(SRIO), and Common Public Radio Interface (CPRI). Most of the

other standard and proprietary protocols from 614 Mbps to 5.0 Gbps are supported.

Table 1–9 lists the PCS features of the transceiver.

Table 1–9. PCS Features of the Transceivers in Cyclone V Devices (Part 1 of 2)

PCS Support

Data Rates (Gbps)

Transmitter Datapath

■ Phase compensation FIFO

■ Byte serializer

Receiver Datapath

■ Word aligner

■ Deskew FIFO

■ 8B/10B encoder

■ Rate-match FIFO

■ 8B/10B decoder

■ Byte deserializer

■ Byte ordering

3-Gbps and 5-Gbps

Basic

■ Transmitter bit-slip

0.614 to 5.0

■ Receiver phase compensation

FIFO

■ Dedicated PCIe PHY IP core

PCIe Gen1: x1, x2, x4

PCIe Gen2: x1, x2 ⁽¹⁾

2.5 and 5.0

1.25

■ PIPE 2.0 interface to the core logic ■ PIPE 2.0 interface to the core logic

■ Custom PHY IP core with preset

feature

GbE

■ GbE transmitter synchronization

■ GbE receiver synchronization state

state machine

machine

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–10

Chapter 1: Overview for Cyclone V Device Family

Low-Power Serial Transceivers

Table 1–9. PCS Features of the Transceivers in Cyclone V Devices (Part 2 of 2)

PCS Support

Data Rates (Gbps)

Transmitter Datapath

■ Dedicated XAUI PHY IP core

■ XAUI synchronization state

Receiver Datapath

■ Dedicated XAUI PHY IP core

■ XAUI synchronization state

XAUI

3.125

machine for bonding four channels

machine for realigning four

channels

■ Custom PHY IP core with preset

feature

SRIO 1.3 and 2.1

1.25 to 3.125

■ SRIO version 2.1-compliant x2

and x4 channel bonding

and x4 deskew state machine

SDI, SD/HD, and

3G-SDI

0.27 ⁽²⁾, 1.485, and ■ Custom PHY IP core with preset

■ Custom PHY IP core with preset

2.97

feature

■ Custom PHY IP core with preset

feature

Serial ATA Gen1 and

Gen2

1.5 and 3.0

■ Electrical idle

■ Signal detect

■ Wider spread of asynchronous

SSC

■ Dedicated deterministic latency

PHY IP core

CPRI 4.1 ⁽³⁾

OBSAI RP3

0.6144 to 4.9152

0.768 to 3.072

■ Transmitter (TX) manual bit-slip

■ Receiver (RX) deterministic

mode

latency state machine

■ Dedicated deterministic latency

PHY IP core

■ TX manual bit-slip mode

■ RX deterministic latency state

machine

■ Custom PHY IP core

V-by-One HS

Up to 3.75

Custom PHY IP core

■ Wider spread of asynchronous

SSC

■ Custom PHY IP core

DisplayPort 1.2 ⁽⁴⁾

1.62 and 2.7

Custom PHY IP core

■ Wider spread of asynchronous

SSC

■ Dedicated XAUI PHY IP core

■ XAUI synchronization state

machine for realigning four

channels

HiGig

3.75

machine for bonding four channels

Custom PHY IP core with preset

feature

Custom PHY IP core with preset

feature

JESD204A

0.3125 ⁽²⁾to 3.125

Notes to Table 1–9:

(1) PCIe Gen2 is supported only for Cyclone V GT devices.

(2) The 0.27-Gbps and 0.3125-Gbps data rates are supported using oversampling user logic that you must implement in the FPGA fabric.

(3) High-voltage output mode (1000-BASE-CX) is not supported.

(4) Pending characterization.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for Cyclone V Device Family

1–11

PCIe Gen1 and Gen2 Hard IP

Cyclone V GX, GT, SX, and ST devices contain PCIe hard IP—consisting of the MAC,

data link, and transaction layers—that is designed for performance, ease-of-use, and

increased functionality. The PCIe hard IP supports PCIe Gen2 end point and root port

for x1 and x2 lanes configuration, and Gen1 end point and root port for up to x4 lane

configuration.

The PCIe endpoint support includes multifunction support for up to eight functions,

as shown in Figure 1–2. The integrated multifunction support reduces the FPGA logic

requirements by up to 20 K LEs for PCIe designs that require multiple peripherals.

Figure 1–2. PCIe Multifunction for Cyclone V Devices

External System

Cyclone V Device

Host CPU

PCIe Link

Root

Complex

Local

Peripheral 1

Local

Peripheral 2

The Cyclone V PCIe hard IP operates independently from the core logic. This

independent operation allows the PCIe link to wake up and complete link training in

less than 100 ms while the Cyclone V device completes loading the programming file

for the rest of the device. In addition, the PCIe hard IP in the Cyclone V device

provides improved end-to-end datapath protection using ECC.

FPGA GPIOs

Cyclone V devices offer highly configurable GPIOs. The following list describes the

many features of the GPIOs:

■

Programmable bus hold and weak pull-up.

■

LVDS output buffer with programmable differential output voltage (V_OD) and

programmable pre-emphasis.

■

Dynamic on-chip parallel termination (R_TOCT) for all I/O banks with OCT

calibration to limit the termination impedance variation to 15%.

On-chip dynamic termination that has the ability to swap between serial and

parallel termination, depending on whether there is read or write on a common

bus for signal integrity.

■

Unused voltage reference (VREF) pins that can be configured as user I/Os.

Easy timing closure support using the hard read FIFO in the input register path,

and delay-locked loop (DLL) delay chain with fine and coarse architecture.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–12

Chapter 1: Overview for Cyclone V Device Family

External Memory

Cyclone V devices support up to two hard memory controllers for DDR3, DDR2,

LPDDR2, and LPDDR SDRAM devices. Each controller supports 8- to 32-bit

components of up to 4 gigabits (Gb) in density with two chip selects and optional

ECC. Cyclone V devices also support soft memory controllers for DDR3, DDR2,

LPDDR2, and LPDDR SDRAM for maximum flexibility.

Table 1–10 lists the performance of the external memory interface in Cyclone V

devices.

Table 1–10. External Memory Interface Performance in Cyclone V Devices

Interface

Voltage (V)

1.5

Hard Controller (MHz) Soft Controller (MHz)

DDR3 SDRAM

DDR3L SDRAM

DDR3U SDRAM

400

333

400

333

200

300

200

1.35

1.25

1.8

DDR2 SDRAM

1.5

LPDDR2 SDRAM

LPDDR SDRAM

1.2

1.8

Adaptive Logic Module

Cyclone V devices use a 28-nm ALM as the basic building block of the logic fabric.

The ALM, as shown in Figure 1–3, uses an 8-input fracturable look-up table (LUT)

with four dedicated registers to help improve timing closure in register-rich designs

and achieve an even higher design packing capability than previous generations.

You can configure up to 25% of the ALMs in Cyclone V devices as distributed

memory using MLABs. For more information, refer to “Embedded Memory” on

page 1–14.

Figure 1–3. ALM for Cyclone V Devices

Cyclone V Device

Reg

1

2

Full

Adder

3

4

5

6

7

Reg

Adaptive

LUT

Reg

8

Full

Adder

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for Cyclone V Device Family

1–13

Variable-Precision DSP Block

Cyclone V devices feature a variable-precision DSP block that you can configure to

support signal processing with precisions ranging from 9 x 9, 18 x 19, and 27 x 27 bits

natively.

You can configure each DSP block during compilation as independent three 9 x 9, two

18 x 19, or one 27 x 27 multipliers. With a dedicated 64-bit cascade bus, you can

cascade multiple variable-precision DSP blocks to implement even higher precision

DSP functions efficiently.

The variable-precision DSP block also supports these features:

■

A 64-bit accumulator that is the largest in the industry.

A hard preadder that is available in both 18- and 27-bit modes.

Cascaded output adders for efficient systolic finite impulse response (FIR) filters.

Internal coefficient register banks, 8 deep, for each multiplier in 18- or 27-bit mode.

Fully independent multiplier operation.

A second accumulator feedback register to accommodate complex

multiply-accumulate functions.

■

Efficient support for single- and double-precision floating point arithmetic.

The inferability of all modes by the Quartus^®II design software.

Table 1–11 lists the relevant DSP block configurations for a few usage examples.

Table 1–11. Variable-Precision DSP Block Configurations for Cyclone V Devices

Usage Multiplier Size (Bit)

Low precision fixed point for video applications Three 9 x 9

Two 18 x 19

DSP Block Resource

1 variable-precision DSP block

Medium precision fixed point in FIR filters

FIR filters and general DSP usage

Two 18 x 19 with accumulate 1 variable-precision DSP block

High precision fixed- or floating-point implementations One 27 x 27 with accumulate 1 variable-precision DSP block

Table 1–12 lists the variable-precision DSP resources by bit precision for each

Cyclone V device.

Table 1–12. Number of Multipliers in Cyclone V Devices (Part 1 of 2)

Independent Input and Output

Multiplications Operator

18 x 18

Multiplier

Adder

Summed

with 36-bit

Input

Variable-

precision

DSP Block

18 x 19

Multiplier

Adder Mode

Variant

Device

9 x 9

18 x 19

Multiplier

27 x 27

Multiplier

5CEA2

5CEA4

5CEA5

5CEA7

5CEA9

25

72

75

216

50

25

72

25

72

25

72

144

248

312

684

Cyclone V E

124

156

342

372

124

156

342

124

156

342

124

156

342

468

1,026

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–14

Chapter 1: Overview for Cyclone V Device Family

Embedded Memory

Table 1–12. Number of Multipliers in Cyclone V Devices (Part 2 of 2)

Independent Input and Output

Multiplications Operator

18 x 18

Multiplier

Adder

Summed

with 36-bit

Input

Variable-

precision

DSP Block

18 x 19

Multiplier

Adder Mode

Variant

Device

9 x 9

18 x 19

27 x 27

Multiplier

5CGXC3

5CGXC4

5CGXC5

5CGXC7

5CGXC9

5CGTD5

5CGTD7

5CGTD9

5CSEA2

5CSEA4

5CSEA5

5CSEA6

5CSXC4

5CSXC5

5CSXC6

5CSTD5

5CSTD6

42

70

126

210

372

468

1,026

372

468

1,026

108

174

261

336

108

174

261

336

84

42

70

42

70

42

70

140

248

312

684

248

312

684

73

Cyclone V GX

124

156

342

124

156

342

36

124

156

342

124

156

342

36

124

156

342

124

156

342

36

124

156

342

124

156

342

36

Cyclone V GT

Cyclone V SE

58

116

173

224

73

58

87

112

36

112

36

112

36

112

36

Cyclone V SX

Cyclone V ST

58

116

173

224

58

87

112

Embedded Memory

The Cyclone V embedded memory blocks are flexible and designed to provide an

optimal amount of small- and large-sized memory arrays. Cyclone V devices contain

two types of embedded memory blocks:

■

640-bit MLAB blocks—ideal for wide and shallow memory arrays. The MLAB

operates at up to 300 MHz.

■

10-Kb M10K blocks—ideal for larger memory arrays while still providing a large

number of independent ports. The M10K embedded memory operates at up to

380 MHz.

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 1: Overview for Cyclone V Device Family

1–15

Dynamic and Partial Reconfiguration

Table 1–13 lists the supported memory configurations for Cyclone V devices.

Table 1–13. Embedded Memory Block Configurations for Cyclone V Devices

Memory Block

Depth (bits)

Programmable Widths

MLAB

32

256

512

1K

x1, x2, x4, x8, x9, x10, x16, x18, or x20

x40 or x32

x20 or x16

x10 or x8

x5 or x4

x2

M10K

2K

4K

8K

x1

Dynamic and Partial Reconfiguration

The dynamic reconfiguration feature allows you to dynamically change the

transceiver data rates, PMA settings, or protocols of a channel, without affecting data

transfer on adjacent channels. This feature is ideal for applications that require

on-the-fly multiprotocol or multirate support. You can reconfigure the PMA and PCS

blocks with dynamic reconfiguration.

Partial reconfiguration allows you to reconfigure part of the device while other

sections of the device remain operational. This capability is important in systems with

critical uptime requirements because it allows you to make updates or adjust

functionality without disrupting services.

Apart from lowering cost and power consumption, partial reconfiguration increases

the effective logic density of the device because placing device functions that do not

operate simultaneously is not necessary. Instead, you can store these functions in

external memory and load them whenever the functions are required. This capability

reduces the size of the device because it allows multiple applications on a single

device—saving the board space and reducing the power consumption.

Altera simplifies the time-intensive task of partial reconfiguration by building this

capability on top of the proven incremental compile and design flow in the Quartus II

design software. With the Altera^®solution, you do not need to know all the intricate

device architecture details to perform a partial reconfiguration.

Partial reconfiguration is supported through the FPP x16 configuration interface. You

can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to

enable simultaneous partial reconfiguration of both the device core and transceivers.

Clock Networks and PLL Clock Sources

The Cyclone V clock network architecture is based on Altera’s proven global,

quadrant, and peripheral clock structure, which is supported by dedicated clock input

pins and fractional PLLs. Cyclone V devices have 16 global clock networks capable of

up to 550 MHz operation. The Quartus II software identifies all unused sections of the

clock network and powers them down, which reduces power consumption.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–16

Chapter 1: Overview for Cyclone V Device Family

Enhanced Configuration and Configuration via Protocol

Cyclone V devices have up to eight PLLs, each with nine output counters that you can

use to reduce PLL usage in two ways:

■

Reduce the number of oscillators that are required on your board by using

fractional PLLs.

■

Reduce the number of clock pins that are used in the device by synthesizing

multiple clock frequencies from a single reference clock source.

Cyclone V devices use a fractional PLL architecture in addition to the historical

integer PLL. If you use the fractional PLL mode, you can use the PLLs for precision

fractional-N frequency synthesis—removing the need for off-chip reference clock

sources in your design. The transceiver fractional PLLs that are not used by the

transceiver I/Os can be used as general purpose fractional PLLs by the FPGA fabric.

Apart from frequency synthesis, on-chip clock deskew, jitter attenuation, counter

reconfiguration, programmable output clock duty cycles, PLL cascading, and

reference clock switchover, the PLLs in the Cyclone V devices also support the

following key features:

■

Programmable bandwidth

User-mode reconfiguration of PLLs

Low power mode for each fractional PLL

Reference clock switchover

Dynamic phase shift

Direct, source synchronous, ZDB, external feedback, and LVDS compensation

Enhanced Configuration and Configuration via Protocol

Cyclone V devices support 3.3-V programming voltage and several configuration

modes. Table 1–14 lists the configuration modes and features supported by the

Cyclone V devices.

Table 1–14. Configuration Modes and Features for Cyclone V Devices

Maximum

Data

Width

(Bit)

Maximum

Remote

System

Update

Clock

Rate

Design

Security

Partial

Reconfiguration

Mode

DataRate Decompression

(Mbps)

(MHz)

AS through the EPCS

and EPCQ serial

configuration device

x1, x4

80

—

v

—

PS through CPLD or

external microcontroller

x1

125

—

v

—

16-bit only

v

Parallel

flash loader

FPP

x8, x16

x1, x2,

x4 ⁽¹⁾

CvP (PCIe)

—

33

—

33

—

v

JTAG

x1

—

Note to Table 1–14:

(1) The number of lanes instead of bit.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for Cyclone V Device Family

1–17

Power Management

Instead of using an external flash or ROM, you can configure the Cyclone V devices

through PCIe using CvP. The CvP mode offers the fastest configuration rate and

flexibility with the easy-to-use PCIe hard IP block interface. The Cyclone V CvP

implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

Power Management

Leveraging the FPGA architectural features, process technology advancements, and

transceivers that are designed for power efficiency, the Cyclone V devices consume

less power than previous generation Cyclone FPGAs:

■

Total device core power consumption—less by up to 40%.

Transceiver channel power consumption—less by up to 50%.

■

Additionally, Cyclone V devices contain several hard IP blocks that reduce logic

resources and deliver substantial power savings of up to 25% less power than

equivalent soft implementations.

SoC FPGA with HPS

Each SoC FPGA combines an FPGA fabric and an HPS in a single device. This

combination delivers the flexibility of programmable logic with the power and cost

savings of hard IP in these ways:

■

Reduces board space, system power, and bill of materials cost by eliminating a

discrete embedded processor

Allows you to differentiate the end product in both hardware and software, and to

support virtually any interface standard

Extends the product life and revenue through in-field hardware and software

updates

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–18

Chapter 1: Overview for Cyclone V Device Family

SoC FPGA with HPS

Features of the HPS

The HPS consists of a dual-core ARM Cortex-A9 MPCore processor, a rich set of

peripherals, and a shared multiport SDRAM memory controller, as shown in

Figure 1–4.

Figure 1–4. HPS with Dual-Core ARM Cortex-A9 MPCore Processor

Configuration

Controller

Lightweight

HPS-to-FPGA

FPGA Fabric

FPGA-to-HPS HPS-to-FPGA

FPGA-to-HPS SDRAM

FPGA

Manager

HPS

Ethernet

MAC (2x)

ARM Cortex-A9 MPCore

CPU0

(ARM Cortex-A9

with NEON/FPU,

CPU1

(ARM Cortex-A9

with NEON/FPU,

USB

OTG (2x)

64 KB

Boot

ROM

32 KB Instruction Cache, 32 KB Instruction Cache,

32 KB Data Cache, and 32 KB Data Cache, and

Memory Management Unit) Memory Management Unit)

NAND Flash

Controller

Multiport

DDR SDRAM

Controller

with

SD/MMC/SDIO

Controller

Level 3

Interconnect

ACP

SCU

Optional ECC

DMA

Controller

L2 Cache (512 KB)

64 KB

On-Chip

RAM

ETR

(Trace)

Debug

Access Port

Low Speed Peripherals

(Timers, GPIOs, UART, SPI, I2C, CAN, Quad SPI Flash Controller, System Manager, Clock Manager, Reset Manager, and Scan Manager)

System Peripherals

Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC/SDIO

controller module has an integrated DMA controller. For modules without an

integrated DMA controller, an additional DMA controller module provides up to

eight channels of high-bandwidth data transfers. The debug access port provides

interfaces to industry standard JTAG debug probes and supports ARM CoreSight

debug and core traces to facilitate software development.

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 1: Overview for Cyclone V Device Family

1–19

SoC FPGA with HPS

HPS–FPGA AXI Bridges

The HPS–FPGA bridges, which support the Advanced Microcontroller Bus

Architecture (AMBA^®) Advanced eXtensible Interface (AXI^™) specifications, consist

of the following bridges:

■

FPGA-to-HPS AXI bridge—a high-performance bus supporting 32-, 64-, and

128-bit data widths that allows the FPGA fabric to master transactions to the slaves

in the HPS

HPS-to-FPGA AXI bridge—a high-performance bus supporting 32-, 64-, and

128-bit data widths that allows the HPS to master transactions to the slaves in the

FPGA fabric.

Lightweight HPS-to-FPGA AXI bridge—a lower performance 32-bit width bus

that allows the HPS to master transactions to the slaves in the FPGA fabric.

The HPS–FPGA AXI bridges also allow the FPGA fabric to access the memory shared

by one or both microprocessors, and provide asynchronous clock crossing with the

clock from the FPGA fabric.

HPS SDRAM Controller Subsystem

The HPS SDRAM controller subsystem contains a multiport SDRAM memory

controller and DDR PHY that are shared between the FPGA fabric (through the

FPGA-to-HPS SDRAM interface), the level 2 (L2) cache, and the level 3 (L3) system

interconnect. The FPGA-to-HPS SDRAM interface supports AMBA AXI and Avalon^®

Memory-Mapped (Avalon-MM) interface standards, and provides up to four ports

with separate read and write directions.

To maximize memory performance, the SDRAM controller subsystem supports

command and data reordering, deficit round-robin arbitration with aging, and

high-priority bypass features. The SDRAM controller subsytem supports DDR2,

DDR3, LPDDR, or LPDDR2 devices up to 4 Gb in density and runs up to 400 MHz

(800 Mbps data rate).

For easy migration, the FPGA-to-HPS SDRAM interface is compatible with the

interface of the soft SDRAM memory controller IPs and hard SDRAM memory

controllers in the FPGA fabric.

FPGA Configuration and Processor Booting

The FPGA fabric and HPS in the SoC FPGA are powered independently. You can

reduce the clock frequencies or gate the clocks to reduce dynamic power, or shut

down the entire FPGA fabric to reduce total system power.

You can configure the FPGA fabric and boot the HPS independently, in any order,

providing you with more design flexibility:

■

You can boot the HPS before you power up and configure the FPGA fabric. After

the system is running, the HPS reconfigures the FPGA fabric at any time under

program control or through the FPGA configuration controller.

You can power up both the HPS and the FPGA fabric together, configure the FPGA

fabric first, and then upload the boot code to the HPS from the FPGA fabric.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–20

Chapter 1: Overview for Cyclone V Device Family

SoC FPGA with HPS

Hardware and Software Development

For hardware development, you can configure the HPS and connect your soft logic in

the FPGA fabric to the HPS interfaces using the Qsys system integration tool in the

Quartus II software.

For software development, the ARM-based SoC FPGA devices inherit the rich

software development ecosystem available for the ARM Cortex-A9 MPCore

processor. The software development process for Altera SoC FPGAs follows the same

steps as those for other SoC devices. Altera also provides support for the Linux and

VxWorks^®operating systems.

You can begin device-specific firmware and software development on the Altera

SoC FPGA Virtual Target. The Virtual Target is a fast PC-based functional simulation

of a target development system—a model of a complete development board that runs

on a PC. The Virtual Target enables the development of device-specific production

software that can run unmodified on actual hardware.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for Cyclone V Device Family

1–21

Ordering Information

Figure 1–5 and Figure 1–6 show sample ordering codes and list the options available

for Cyclone V E, GX, and GT devices.

Figure 1–5. Ordering Information for Cyclone V E Devices—Preliminary

PackageType

F

: FineLine BGA (FBGA)

: Ultra FineLine BGA (UBGA)

Embedded Hard IPs

U

B

: No hard PCIe or hard

memory controller

OperatingTemperature

C

I

: Commercial temperature (T_J= 0° C to 85° C)

: Industrial temperature (T_J= -40° C to 100° C)

: Automotive temperature (T_J= -40° C to 125° C)

F

: No hard PCIe and maximum

2 hard memory controllers

A

Family Signature

Optional Suffix

Indicates specific device

options or shipment method

5C

E

F

A9

F

31

C

7

N

5C : Cyclone V

Family Variant

N

: Lead-free packaging

E

: Enhanced logic/memory

Member Code

FPGA Fabric Speed Grade

Package Code

6 (fastest)

FBGA PackageType

17 : 256 pins

23 : 484 pins

27 : 672 pins

31 : 896 pins

7

8

A2 : 25,000 logic elements

A4 : 48,000 logic elements

A5 : 76,500 logic elements

A7 : 149,500 logic elements

A9 : 301,000 logic elements

UBGA PackageType

15 : 324 pins

19 : 484 pins

Figure 1–6. Ordering Information for Cyclone V GX and GT Devices—Preliminary

PackageType

Transceiver Count

F

: FineLine BGA (FBGA)

: Ultra FineLine BGA (UBGA)

B

C

D

E

: 3

: 6

: 9

: 12

U

Embedded Hard IPs

B

: No hard PCIe or hard

memory controller

OperatingTemperature

C

I

: Commercial temperature (T_J= 0° C to 85° C)

: Industrial temperature (T_J= -40° C to 100° C)

: Automotive temperature (T_J= -40° C to 125° C)

F

: Maximum 2 hard PCIe and

2 hard memory controllers

A

Family Signature

Optional Suffix

Indicates specific device

options or shipment method

5C

GT

F

D9

E

5

F

35

C

7

N

5C : Cyclone V

Family Variant

N

: Lead-free packaging

GX : 3-Gbps transceivers

GT : 5-Gbps transceivers

Package Code

FPGA Fabric Speed Grade

FBGA PackageType

23 : 484 pins

27 : 672 pins

6 (fastest)

7

8

Member Code

GX Variant

C3 : 31,000 logic elements

Transceiver Speed Grade

31 : 896 pins

35 : 1,152 pins

5

6

7

: 5 Gbps

: 3.125 Gbps

: 2.5 Gbps

C4 : 50,000 logic elements

C5 : 76,500 logic elements

C7 : 149,500 logic elements

C9 : 301,000 logic elements

UBGA PackageType

15 : 324 pins

19 : 484 pins

GT Variant

D5 : 76,500 logic elements

D7 : 149,500 logic elements

D9 : 301,000 logic elements

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–22

Chapter 1: Overview for Cyclone V Device Family

Ordering Information

Figure 1–7 and Figure 1–8 show sample ordering codes and list the options available

for Cyclone V SE, SX, and ST Devices.

‘

Figure 1–7. Ordering Information for Cyclone V SE Devices—Preliminary

PackageType

OperatingTemperature

F

: FineLine BGA (FBGA)

: Ultra FineLine BGA (UBGA)

C

I

: Commercial temperature (T_J= 0° C to 85° C)

: Industrial temperature (T_J= -40° C to 100° C)

: Automotive temperature (T_J= -40° C to 125° C)

U

A

Embedded Hard IPs

B

: No hard PCIe or hard

memory controller

Processor Cores

1

2

: Single-core

: Dual-core

M : No hard PCIe and 1 hard

memory controller

Family Signature

5C : Cyclone V

Optional Suffix

Indicates specific device

options or shipment method

5C

SE

M

A6

F

31

C

6

2

N

Family Variant

N : Lead-free packaging

ES : Engineering sample

SE : SoC FPGA with enhanced logic/memory

Package Code

FPGA Fabric Speed Grade

Member Code

FBGA PackageType

31 : 896 pins

6 (fastest)

A2 : 25,000 logic elements

A4 : 40,000 logic elements

A5 : 85,000 logic elements

A6 : 110,000 logic elements

7

8

UBGA PackageType

19 : 484 pins

23 : 672 pins

Figure 1–8. Ordering Information for Cyclone V SX and ST Devices—Preliminary

PackageType

F

: FineLine BGA (FBGA)

: Ultra FineLine BGA (UBGA)

U

OperatingTemperature

Embedded Hard IPs

C

I

: Commercial temperature (T_J= 0° C to 85° C)

: Industrial temperature (T_J= -40° C to 100° C)

: Automotive temperature (T_J= -40° C to 125° C)

M : No hard PCIe and 1 hard

memory controller

Transceiver Count

A

F

: Maximum 2 hard PCIe

controllers and 1 hard

memory controller

C

D

: 6

: 9

Processor Cores

2

: Dual-core

Family Signature

Optional Suffix

Indicates specific device

options or shipment method

5C

ST

F

D6

D

4

F

31

C

6

2

N

5C : Cyclone V

Family Variant

N

: Lead-free packaging

ES : Engineering sample

SX : SoC FPGA with 3-Gbps transceivers

ST : SoC FPGA with 5-Gbps transceivers

Package Code

FPGA Fabric Speed Grade

FBGA PackageType

31 : 896 pins

Member Code

SX Variant

C4 : 40,000 logic elements

C5 : 85,000 logic elements

C6 : 110,000 logic elements

6 (fastest)

7

8

UBGA PackageType

23 : 672 pins

Transceiver Speed Grade

4

6

: 5 Gbps

: 3.125 Gbps

ST Variant

D5 : 85,000 logic elements

D6 : 110,000 logic elements

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 1: Overview for Cyclone V Device Family

1–23

Document Revision History

Table 1–15 lists the revision history for this document.

Table 1–15. Document Revision History

Date

Version

Changes

■ Updated Table 1–2, Table 1–3, and Table 1–6.

■ Updated “Cyclone V Family Plan” on page 1–4 and “Clock Networks and PLL Clock

February 2012

1.2

Sources” on page 1–15.

■ Updated Figure 1–1 and Figure 1–6.

■ Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and Table 1–6.

■ Updated Figure 1–4, Figure 1–5, Figure 1–6, Figure 1–7, and Figure 1–8.

■ Updated “System Peripherals” on page 1–18, “HPS–FPGA AXI Bridges” on page 1–19,

“HPS SDRAM Controller Subsystem” on page 1–19, “FPGA Configuration and Processor

Booting” on page 1–19, and “Hardware and Software Development” on page 1–20.

November 2011

October 2011

1.1

1.0

■ Minor text edits.

Initial release.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

1–24

Chapter 1: Overview for Cyclone V Device Family

Document Revision History

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

2. Device Datasheet for Cyclone V

Devices

February 2012

CV-51002-1.2

This chapter describes the electrical characteristics, switching characteristics, and

configuration specifications for Cyclone^®V devices. Electrical characteristics include

operating conditions and power consumption. Switching characteristics list the

transceiver specifications, and core and periphery performance. Configuration

specifications cover power-on reset (POR) specifications, various configuration mode

timing parameters, remote system upgrades timing, and user watchdog internal

oscillator frequency specification. This chapter also describes I/O timing, including

programmable I/O element (IOE) delay and programmable output buffer delay.

f

For more information about the densities and packages of devices in the Cyclone V

family, refer to the Overview for Cyclone V Device Family chapter.

Electrical Characteristics

The following sections describe the electrical characteristics of Cyclone V devices.

Operating Conditions

Cyclone V devices are rated according to a set of defined parameters. To maintain the

highest possible performance and reliability of the Cyclone V devices, you must

consider the operating requirements described in this chapter.

Cyclone V devices are offered in commercial and industrial grades. Commercial

devices are offered in –6 (fastest), –7, and –8 speed grades. Industrial and automotive

devices are offered in the –7 speed grade.

Absolute Maximum Ratings

Absolute maximum ratings define the maximum operating conditions for Cyclone V

devices. The values are based on experiments conducted with the devices and

theoretical modeling of breakdown and damage mechanisms. The functional

operation of the device is not implied for these conditions.

c Conditions other than those listed in Table 2–1 may cause permanent damage to the

device. Additionally, device operation at the absolute maximum ratings for extended

periods of time may have adverse effects on the device.

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012

Subscribe

2–2

Chapter 2: Device Datasheet for Cyclone V Devices

Electrical Characteristics

Table 2–1 lists the Cyclone V absolute maximum ratings.

Table 2–1. Absolute Maximum Ratings for Cyclone V Devices—Preliminary

Symbol

V_CC

Description

Core voltage and periphery circuitry power supply

Configuration pins power supply

Auxiliary supply

Minimum

–0.5

–25

Maximum

1.35

3.75

3.9

Unit

V

V_CCPGM

V_{CC_AUX}

V_CCBAT

V_CCPD

V_CCIO

V

Battery back-up power supply for design security volatile key register

I/O pre-driver power supply

I/O power supply

V

V_{CCA_FPLL}

V_{CCH_GXB}

V_{CCE_GXB}

V_{CCL_GXB}

V_I

PLL analog power supply

3.75

1.21

4

V

Transceiver high voltage power

Transceiver power

V

Clock network power

V

DC input voltage

V

I_OUT

DC output current per pin

40

mA

°C

T_J

Operating junction temperature

Storage temperature (No bias)

–55

125

T_STG

–65

150

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in Table 2–2 and

undershoot to -2.0 V for input currents less than 100 mA and periods shorter than

20 ns.

Table 2–2 lists the maximum allowed input overshoot voltage and the duration of the

overshoot voltage as a percentage of device lifetime. The maximum allowed

overshoot duration is specified as a percentage of high time over the lifetime of the

device. A DC signal is equivalent to 100% duty cycle. For example, a signal that

overshoots to 3.95 V can only be at 3.95 V for ~5% over the lifetime of the device; for a

device lifetime of 10 years, this amounts to half a year.

Table 2–2. Maximum Allowed Overshoot During Transitions for Cyclone V Devices—Preliminary

Symbol

Description

Condition (V)

Overshoot Duration as % of High Time

Unit

%

3.7

3.75

3.8

100

59.79

33.08

18.45

10.36

5.87

%

3.85

3.9

%

Vi (AC)

AC input voltage

%

3.95

4

%

3.34

%

4.05

4.1

1.92

%

1.11

%

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–3

Electrical Characteristics

Recommended Operating Conditions

Recommended operating conditions are the functional operation limits for the AC

and DC parameters for Cyclone V devices.

Table 2–3 lists the steady-state voltage values expected from Cyclone V devices.

Power supply ramps must all be strictly monotonic, without plateaus.

Table 2–3. Recommended Operating Conditions for Cyclone V Devices—Preliminary

Symbol

Description

Condition

Minimum

Typical

Maximum

Unit

Core voltage, periphery circuitry power

supply, transceiver physical coding

sublayer (PCS) power supply, and

transceiver PCI Express^®(PCIe^®) hard IP

digital power supply

V_CC

—

1.07

1.1

1.13

V

V_{CC_AUX}

Auxiliary supply

—

2.375

3.135

2.85

2.5

3.3

3.0

2.5

3.3

3.0

2.5

1.8

1.5

1.35

1.25

1.2

3.3

3.0

2.5

1.8

2.5

2.625

3.465

3.15

V

I/O pre-driver (3.3 V) power supply

I/O pre-driver (3.0 V) power supply

I/O pre-driver (2.5 V) power supply

I/O buffers (3.3 V) power supply

I/O buffers (3.0 V) power supply

I/O buffers (2.5 V) power supply

I/O buffers (1.8 V) power supply

I/O buffers (1.5 V) power supply

I/O buffers (1.35 V) power supply

I/O buffers (1.25 V) power supply

I/O buffers (1.2 V) power supply

Configuration pins (3.3 V) power supply

Configuration pins (3.0 V) power supply

Configuration pins (2.5 V) power supply

Configuration pins (1.8 V) power supply

PLL analog voltage regulator power supply

V_CCPD

2.375

3.135

2.85

2.625

3.465

3.15

2.375

1.71

2.625

1.89

V_CCIO

1.425

1.283

1.19

1.575

1.418

1.31

1.14

1.26

3.135

2.85

3.465

3.15

V_CCPGM

2.375

1.71

2.625

1.89

(1)

V_{CCA_FPLL}

2.375

2.625

Battery back-up power supply

(For design security volatile key register)

(2)

V_CCBAT

—

1.2

—

3.0

V

V_I

DC input voltage

Output voltage

—

–0.5

0

—

3.6

V_CCIO

85

V

V_O

—

V

Commercial

Industrial

Automotive

0

°C

T_J

Operating junction temperature

–40

100

125

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–4

Chapter 2: Device Datasheet for Cyclone V Devices

Electrical Characteristics

Table 2–3. Recommended Operating Conditions for Cyclone V Devices—Preliminary

Symbol

Description

Condition

Minimum

Typical

Maximum

Unit

Standard POR

(PORSEL=0)

200 µs

—

100 ms

—

t_RAMP

Power supply ramp time

Fast POR

(PORSEL=1)

200 µs

—

4 ms

—

Notes to Table 2–3:

(1) PLL digital voltage is regulated from V_{CCA_FPLL}

.

(2) If you do not use the design security feature in Cyclone V devices, connect V_CCBATto a 1.5-V, 2.5-V, or 3.0-V power supply. The power-on reset

(POR) circuitry monitors V_CCBAT. Cyclone V devices do not exit POR if V_CCBATstays low.

Table 2–4 lists the transceiver power supply recommended operating conditions for

Cyclone V GX devices.

Table 2–4. Transceiver Power Supply Operating Conditions for Cyclone V GX Devices—Preliminary

Symbol

V_{CCH_GXBL}

V_{CCE_GXBL}

V_{CCL_GXBL}

Description

Minimum

2.375

1.07

Typical

2.5

Maximum

2.625

1.13

Unit

V

Transceiver high voltage power (left side)

Transmitter and receiver power (left side)

Clock network power (left side)

1.1

V

1.07

1.1

1.13

V

Table 2–5 lists the steady-state voltage values expected from Cyclone V

system-on-a-chip (SoC) FPGA with ARM^®-based hard processor system (HPS). Power

supply ramps must all be strictly monotonic, without plateaus.

Table 2–5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices—Preliminary

Symbol

V_{CC_HPS}

Description

Minimum

Typical

Maximum

Unit

HPS core voltage and periphery circuitry power

supply

1.07

1.1

1.13

V

HPS I/O pre-driver (3.3 V) power supply

HPS I/O pre-driver (3.0 V) power supply

HPS I/O pre-driver (2.5 V) power supply

HPS I/O buffers (3.3 V) power supply

3.135

2.85

3.3

3.0

2.5

3.3

3.0

2.5

1.8

1.5

1.2

3.3

3.0

2.5

1.8

2.5

3.465

3.15

V

V_{CCPD_HPS}

2.375

3.135

2.85

2.625

3.465

3.15

HPS I/O buffers (3.0 V) power supply

HPS I/O buffers (2.5 V) power supply

2.375

1.71

2.625

1.89

V_{CCIO_HPS}

HPS I/O buffers (1.8 V) power supply

HPS I/O buffers (1.5 V) power supply

1.425

1.14

1.575

1.26

HPS I/O buffers (1.2 V) power supply

HPS reset and clock input pins (3.3 V) power supply

HPS reset and clock input pins (3.0 V) power supply

HPS reset and clock input pins (2.5 V) power supply

HPS reset and clock input pins (1.8 V) power supply

HPS PLL analog voltage regulator power supply

3.135

2.85

3.465

3.15

V_{CCRSTCLK_HPS}

2.375

1.71

2.625

1.89

V_{CCPLL_HPS}

2.375

2.625

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–5

Electrical Characteristics

DC Characteristics

This section lists the supply current, I/O pin leakage current, input pin capacitance,

on-chip termination tolerance, and hot socketing specifications.

Supply Current

Standby current is the current drawn from the respective power rails used for power

budgeting. Use the Excel-based Early Power Estimator (EPE) to estimate supply

current for your design because these currents vary greatly with the resources you

use.

f

For more information about power estimation tools, refer to the PowerPlay Early Power

Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II

Handbook.

I/O Pin Leakage Current

Table 2–6 lists the Cyclone V I/O pin leakage current specifications.

Table 2–6. I/O Pin Leakage Current for Cyclone V Devices—Preliminary

Symbol

I_I

I_OZ

Description

Input pin

Tri-stated I/O pin

Conditions

V_I= 0 V to V_CCIOMAX

V_O= 0 V to V_CCIOMAX

Min

–30

Typ

—

Max

30

Unit

µA

—

30

µA

Bus Hold Specifications

Table 2–7 lists the Cyclone V device bus hold specifications.

Table 2–7. Bus Hold Parameters for Cyclone V Devices—Preliminary (Part 1 of 2) ⁽¹⁾

_CCIO(V)

V

Parameter Symbol Conditions

1.2

1.5

1.8

2.5

3.0

3.3

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Bus-hold,

low,

sustaining

current

V_IN> V_IL

(max.)

I_SUSL

I_SUSH

I_ODL

8

—

12

–12

—

30

–30

—

50

–50

—

70

–70

—

70

–70

—

µA

Bus-hold,

high,

sustaining

current

V_IN< V_IH

(min.)

–8

—

Bus-hold,

low,

overdrive

current

0V < V_IN<

V_CCIO

125

–125

175

–175

200

–200

300

–300

500

–500

500 µA

–500 µA

Bus-hold,

high,

overdrive

current

0V < V_IN<

V_CCIO

I_ODH

—

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–6

Chapter 2: Device Datasheet for Cyclone V Devices

Electrical Characteristics

Table 2–7. Bus Hold Parameters for Cyclone V Devices—Preliminary (Part 2 of 2) ⁽¹⁾

_CCIO(V)

V

Parameter Symbol Conditions

1.2

1.5

1.8

2.5

3.0

3.3

Unit

Min Max Min

Max Min Max Min Max Min Max Min Max

Bus-hold

trip point

V_TRIP

—

0.3

0.9 0.375 1.125 0.68 1.07 0.7

1.7

0.8

2

0.8

2

V

Note to Table 2–7:

(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.

On-Chip Termination (OCT) Specifications

If you enable OCT calibration, calibration is automatically performed at power up for

I/O pins connected to the calibration block. Calibration accuracy for the calibrated

on-chip series termination (R_SOCT) and on-chip parallel termination (R_TOCT) are

applicable at the moment of calibration. When process, voltage, and temperature

(PVT) conditions change after calibration, the tolerance may change.

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Cyclone V Devices

2–7

Electrical Characteristics

Table 2–8 lists the Cyclone V OCT termination calibration accuracy specifications.

Table 2–8. OCT Calibration Accuracy Specifications for Cyclone V Devices—Preliminary ⁽¹⁾

Calibration Accuracy

Symbol

Description

Conditions (V)

Unit

C6

C7, I7

C8, A7

Speed Grade Speed Grade Speed Grade

Internal series termination

with calibration

(25-Ω setting)

V_CCIO= 3.0, 2.5,

1.8, 1.5, 1.2

25-Ω R_S

15

%

Internal series termination

with calibration

(50-Ω setting)

V

_CCIO= 3.0, 2.5,

1.8, 1.5, 1.2

50-Ω R_S

Internal series termination

V_CCIO= 1.5, 1.35,

1.25, 1.2

34-Ω and 40-Ω R_Swith calibration

(34-Ω and 40-Ω setting)

Internal series termination

with calibration

(48-Ω, 60-Ω, and 80-Ω

setting)

48-Ω, 60-Ω, and

80-Ω R_S

V_CCIO= 1.2

15

%

Internal parallel

termination with calibration

(50-Ω setting)

V

_CCIO= 2.5, 1.8,

1.5, 1.2

50-Ω R_T

-10 to +40

Internal parallel

termination with calibration V_CCIO= 1.5, 1.35,

(20-Ω, 30-Ω, 40-Ω,

60-Ω, and 120-Ω setting)

20-Ω, 30-Ω,

40-Ω, 60-Ω, and

120-Ω R_T

1.25

Internal parallel

60-Ω and 120-Ω R_Ttermination with calibration

V_CCIO= 1.2

-10 to +40

15

-10 to +40

15

-10 to +40

15

%

(60-Ω and 120-Ω setting)

Internal left shift series

termination with calibration

(25-Ω R_{S_left_shift}setting)

V

_CCIO= 3.0, 2.5,

1.8, 1.5, 1.2

25-Ω R_{S_left_shift}

Note to Table 2–8:

(1) OCT calibration accuracy is valid at the time of calibration only.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–8

Chapter 2: Device Datasheet for Cyclone V Devices

Electrical Characteristics

Table 2–9 lists the Cyclone V OCT without calibration resistance tolerance to PVT

changes.

Table 2–9. OCT Without Calibration Resistance Tolerance Specifications for Cyclone V Devices—Preliminary

Resistance Tolerance

Symbol

Description

Conditions (V)

Unit

C6

C7, I7

C8, A7

Speed Grade Speed Grade Speed Grade

Internal series termination

without calibration

(25-Ω setting)

25-Ω R_S

V_CCIO= 3.0 and 2.5

V_CCIO= 1.8 and 1.5

V_CCIO= 1.2

30

35

30

35

25

40

%

Internal series termination

without calibration

(25-Ω setting)

25-Ω R_S

50-Ω R_S

100-Ω R_D

Internal series termination

without calibration

(25-Ω setting)

50

Internal series termination

without calibration (50-Ω

setting)

V_CCIO= 3.0 and 2.5

V_CCIO= 1.8 and 1.5

V_CCIO= 1.2

40

Internal series termination

without calibration

(50-Ω setting)

40

Internal series termination

without calibration

(50-Ω setting)

50

Internal differential

termination (100-Ω

setting)

V_CCIO= 2.5

TBD

OCT calibration is automatically performed at power up for the OCT-enabled I/O

pins. Table 2–10 lists OCT variation with temperature and voltage after power-up

calibration. Use Table 2–10 to determine the OCT variation after power-up calibration

and Equation 2–1 to determine the OCT variation without recalibration.

Equation 2–1. OCT Variation Without Recalibration—Preliminary ^{(1), (2), (3), (4), (5), (6)}

dR

dT

dR

dV







------

-------

× ΔV

R_OCT= R

1 + 

× ΔT



^SCAL

Notes to Equation 2–1:

(1) The R_OCTvalue calculated from Equation 2–1 shows the range of OCT resistance with the variation of temperature

and V_CCIO

.

(2) R_SCALis the OCT resistance value at power-up.

(3) ΔT is the variation of temperature with respect to the temperature at power up.

(4) ΔV is the variation of voltage with respect to V_CCIOat power up.

(5) dR/dT is the percentage change of R_SCALwith temperature.

(6) dR/dV is the percentage change of R_SCALwith voltage.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–9

Electrical Characteristics

Table 2–10 lists the OCT variation after the power-up calibration.

Table 2–10. OCT Variation after Power-Up Calibration for Cyclone V Devices—Preliminary ⁽¹⁾

Symbol

Description

V_CCIO(V)

3.0

Typical

0.0297

0.0344

0.0499

0.0744

0.1241

0.189

Unit

2.5

OCT variation with voltage without

recalibration

dR/dV

1.8

%/mV

%/°C

1.5

1.2

3.0

2.5

0.208

OCT variation with temperature

without recalibration

dR/dT

1.8

0.266

1.5

0.273

1.2

0.317

Note to Table 2–10:

(1) Valid for a V_CCIOrange of 5% and a temperature range of 0° to 85°C.

Pin Capacitance

Table 2–11 lists the Cyclone V device family pin capacitance.

Table 2–11. Pin Capacitance for Cyclone V Devices

Symbol

C_IOTB

Description

Value

Unit

pF

Input capacitance on top and bottom I/O pins

Input capacitance on left and right I/O pins

5.5

C_IOLR

pF

C_OUTFB

Input capacitance on dual-purpose clock output and feedback pins

pF

Hot Socketing

Table 2–12 lists the hot socketing specifications for Cyclone V devices.

Table 2–12. Hot Socketing Specifications for Cyclone V Devices—Preliminary

Symbol

I_{IOPIN (DC)}

Description

DC current per I/O pin

Maximum

300 μA

(1)

I_{IOPIN (AC)}

AC current per I/O pin

8 mA

I_{XCVR-TX (DC)}

DC current per transceiver transmitter (TX) pin

DC current per transceiver receiver (RX) pin

100 mA

50 mA

I_{XCVR-RX (DC)}

Note to Table 2–12:

(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |I_IOPIN| = C dv/dt, in which C is the I/O pin

capacitance and dv/dt is the slew rate.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–10

Chapter 2: Device Datasheet for Cyclone V Devices

Electrical Characteristics

Internal Weak Pull-Up Resistor

Table 2–13 lists the weak pull-up resistor values for Cyclone V devices.

(1), (2)

Table 2–13. Internal Weak Pull-Up Resistor Values for Cyclone V Devices—Preliminary

Symbol

Description

Conditions (V) ⁽³⁾

Typ ⁽⁴⁾

25

Unit

kΩ

V_CCIO= 3.3 5%

V

_CCIO= 3.0 5%

_CCIO= 2.5 5%

25

Value of the I/O pin pull-up resistor before and during

configuration, as well as user mode if you have enabled the

programmable pull-up resistor option.

V_CCIO= 1.8 5%

_CCIO= 1.5 5%

_CCIO= 1.35 5%

V_CCIO= 1.25 5%

_CCIO= 1.2 5%

25

R_PU

V

25

V

25

V

25

Notes to Table 2–13:

(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins.

(2) The internal weak pull-down feature is only available for the JTAG TCKpin. The typical value for this internal weak pull-down resistor is

approximately 25 kΩ.

(3) Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO

.

(4) These specifications are valid with 10% tolerances to cover changes over PVT.

I/O Standard Specifications

Table 2–14 through Table 2–19 list the input voltage (V_IHand V_IL), output voltage

(V_OHand V_OL), and current drive characteristics (I_OHand I_OL) for various I/O

standards supported by Cyclone V devices. These tables also list the Cyclone V device

family I/O standard specifications. The V_OLand V_OHvalues are valid at the

corresponding I_OHand I_OL, respectively.

For an explanation of terms used in Table 2–14 through Table 2–19, refer to “Glossary”

on page 2–37.

Table 2–14. Single-Ended I/O Standards for Cyclone V Devices—Preliminary (Part 1 of 2)

V

_CCIO(V)

V_IL(V)

Max

V_IH(V)

V_OL(V)

Max

V_OH(V)

Min

I/O

Standard

I_OL

I_OH

(mA) (mA)

Min Typ Max Min

Min

Max

3.3-V

LVTTL

3.135 3.3 3.465 –0.3

0.8

1.7

3.6

0.45

0.2

0.4

2.4

V_CCIO– 0.2

2.4

4

2

–4

–2

3.3-V

LVCMOS

3.135 3.3 3.465 –0.3

1.7

3.6

3.0-V

LVTTL

2.85

3

3.15 –0.3

3.0-V

LVCMOS

2.85

0.8

0.2

V_CCIO– 0.2 0.1 –0.1

3.0-V PCI

3

3.15

—

0.3 x V_CCIO

0.5 x V_CCIO

V_CCIO+ 0.3

3.6

0.1 x V_CCIO0.9 x V_CCIO

1.5 –0.5

3.0-V PCI-X 2.85

0.35 x V_CCIO0.5 x V_CCIO

0.7 1.7

2.5 V

1.8 V

2.375 2.5 2.625 –0.3

0.4

2

1

2

–1

–2

1.71 1.8 1.89 –0.3 0.35 x V_CCIO0.65 x V_CCIOV_CCIO+ 0.3

0.45

V_CCIO– 0.45

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–11

Electrical Characteristics

Table 2–14. Single-Ended I/O Standards for Cyclone V Devices—Preliminary (Part 2 of 2)

V

_CCIO(V)

V_IL(V)

Max

V_IH(V)

V_OL(V)

Max

V_OH(V)

Min

I/O

Standard

I_OL

I_OH

(mA) (mA)

Min Typ Max Min

Min

Max

1.5 V

1.2 V

1.425 1.5 1.575 –0.3 0.35 x V_CCIO0.65 x V_CCIOV_CCIO+ 0.3 0.25 x V_CCIO0.75 x V_CCIO

1.14 1.2 1.26 –0.3 0.35 x V_CCIO0.65 x V_CCIOV_CCIO+ 0.3 0.25 x V_CCIO0.75 x V_CCIO

2

–2

Table 2–15. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Cyclone V Devices—Preliminary

V_CCIO(V)

Typ

V_REF(V)

Typ

V_TT(V)

Typ

I/O

Standard

Min

Max

Min

Max

Min

Max

SSTL-2

Class I, II

2.375

2.5

1.8

1.5

2.625 0.49 x V_CCIO0.5 x V_CCIO0.51 x V_CCIO

1.89 0.833 0.9 0.969

1.575 0.49 x V_CCIO0.5 x V_CCIO0.51 x V_CCIO0.49 x V_CCIO

V_REF– 0.04

V_REF

V_REF+ 0.04

SSTL-18

Class I, II

1.71

V

_REF– 0.04

V_REF+ 0.04

SSTL-15

Class I, II

1.425

0.5 x V_CCIO0.51 x V_CCIO

SSTL 135

Class I, II

1.283 1.35 1.418 0.49 x V_CCIO0.5 x V_CCIO0.51 x V_CCIO0.49 x V_CCIO

SSTL 125

Class I, II

1.19

1.71

1.25

1.8

1.26 0.49 x V_CCIO0.5 x V_CCIO0.51 x V_CCIO0.49 x V_CCIO

HSTL-18

Class I, II

1.89

0.85

0.68

0.9

0.95

0.9

—

V_CCIO/2

_CCIO/2

—

HSTL-15

Class I, II

1.425

1.5

1.575

0.75

V

HSTL-12

Class I, II

1.14

1.2

1.26 0.47 x V_CCIO0.5 x V_CCIO0.53 x V_CCIO

1.3 0.49 x V_CCIO0.5 x V_CCIO0.51 x V_CCIO

—

V_CCIO/2

—

HSUL-12

Table 2–16. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Cyclone V Devices—Preliminary (Part

1 of 2)

V_IL(DC)(V)

Max

V_IH(DC)(V)

V_IL(AC)(V)

Max

V_IH(AC)(V)

Min

V_OL(V)

Max

V_OH(V)

Min

I/O

Standard

I_ol

(mA)

I_oh

(mA)

Min

Max

SSTL-2

Class I

–0.3 V_REF– 0.15 V_REF+ 0.15 V_CCIO+ 0.3 V_REF– 0.31 V_REF+ 0.31 V_TT– 0.608 V_TT+ 0.608

8.1

–8.1

–16.2

–6.7

–13.4

–8

SSTL-2

Class II

–0.3

—

V

_REF– 0.15 V_REF+ 0.15 V_CCIO+ 0.3 V_REF– 0.31 V_REF+ 0.31 V_TT– 0.81

V_TT+ 0.81

16.2

6.7

SSTL-18

Class I

V_REF

0.125

–

V

_REF+ 0.125 V_CCIO+ 0.3 V_REF– 0.25 V_REF+ 0.25 V_TT– 0.603 V_TT+ 0.603

SSTL-18

Class II

V_REF

0.125

–

_REF+ 0.125 V_CCIO+ 0.3 V_REF– 0.25 V_REF+ 0.25

0.28

V_CCIO– 0.28 13.4

SSTL-15

Class I

V_REF

0.175

–

V_REF– 0.1

_REF– 0.1

V_REF– 0.09 V_REF+ 0.09

V_REF+ 0.1

—

V

_REF+ 0.175 0.2 x V_CCIO0.8 x V_CCIO

8

SSTL-15

Class II

V_REF

0.175

–

—

V

V_REF+ 0.1

—

_REF+ 0.175 0.2 x V_CCIO0.8 x V_CCIO

16

–16

SSTL 135

V_REF– 0.16 V_REF+ 0.16

TBD ⁽¹⁾

TBD ⁽¹⁾TBD ⁽¹⁾

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–12

Chapter 2: Device Datasheet for Cyclone V Devices

Electrical Characteristics

Table 2–16. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Cyclone V Devices—Preliminary (Part

2 of 2)

V_IL(DC)(V)

Max

V_REF– 0.85 V_REF+ 0.85

V_IH(DC)(V)

V_IL(AC)(V)

Max

V_IH(AC)(V)

Min

V_OL(V)

V_OH(V)

I/O

I_ol

I_oh

Standard

(mA)

Min

Max

TBD ⁽¹⁾

Min

TBD ⁽¹⁾

SSTL 125

—

V_REF– 0.15 V_REF+ 0.15

TBD ⁽¹⁾TBD ⁽¹⁾

HSTL-18

Class I

—

V

_REF– 0.1

V_REF+ 0.1

—

V_REF– 0.2

V_REF+ 0.2

0.4

V_CCIO– 0.4

8

16

8

–8

–16

–8

HSTL-18

Class II

HSTL-15

Class I

HSTL-15

Class II

16

8

–16

–8

HSTL-12

Class I

–0.1

5

V

_REF– 0.08 V_REF+ 0.08 V_CCIO+ 0.15 V_REF– 0.15 V_REF+ 0.15 0.25 x V_CCIO0.75 x V_CCIO

V_REF– 0.08 V_REF+ 0.08 V_CCIO+ 0.15 V_REF– 0.15 V_REF+ 0.15 0.25 x V_CCIO0.75 x V_CCIO

V_REF– 0.13 V_REF+ 0.13 V_REF– 0.22 V_REF+ 0.22 0.1 x V_CCIO0.9 x V_CCIO

HSTL-12

Class II

–0.1

5

16

–16

TBD

HSUL-12

—

(1)

Note to Table 2–16:

(1) Pending silicon characterization.

Table 2–17. Differential SSTL I/O Standards for Cyclone V Devices—Preliminary

V

_CCIO(V)

V_SWING(DC)(V)

Min Max

V_X(AC)(V)

Typ

V_SWING(AC)(V)

V_OX(AC)(V)

Typ Max

I/O

Standard

Min Typ Max

Min

Max

Min

Max

Min

SSTL-2

Class I, II

V_CCIO

0.6

+

V_CCIO/2

– 0.2

V_CCIO/2

+ 0.2

V_CCIOV_CCIO/2

+ 0.6 – 0.15

V_CCIO/2

+ 0.15

2.375 2.5 2.625 0.3

1.71 1.8 1.89 0.25

1.425 1.5 1.575 0.2

—

0.62

—

V

_CCIO/2

–

V

_CCIO/2

–

V_CCIO/2

+

0.125

SSTL-18

Class I, II

V_CCIO

0.6

+

V_CCIO/2

+ 0.175

V_CCIO

+ 0.6

—

0.5

—

0.175

0.125

SSTL-15

Class I, II

–0.2

—

-0.15

—

0.15

–0.35 0.35

—

V_CCIO/2

—

V_REF

–

V_REF

+

TBD

V_REF

– 0.15

V_REF

+ 0.15

SSTL 135 1.283 1.35 1.45

SSTL 125 1.19 1.25 1.31

0.2

V_CCIO/2

(1)

0.135

TBD

—

(1)

Note to Table 2–17:

(1) Pending silicon characterization.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–13

Electrical Characteristics

Table 2–18. Differential HSTL I/O Standards for Cyclone V Devices—Preliminary

V_CCIO(V)

Typ

V_DIF(DC)(V)

V_X(AC)(V)

Typ

V_CM(DC)(V)

Typ

V_DIF(AC)(V)

Min Max

I/O

Standard

Min

Max Min Max

Min

Max

Min

Max

HSTL-18

Class I, II

1.71

1.8

1.89 0.2

—

0.78

—

1.12

0.78

—

1.12

0.4

0.3

—

HSTL-15

Class I, II

1.425 1.5 1.575 0.2

0.68

—

0.9

—

0.68

0.9

HSTL-12

Class I, II

V_CCIO

+ 0.3

0.5 x

V_CCIO

0.4 x V 0.5 x

CCIO

0.6 x

V_CCIO

+ 0.48

1.14

1.2

1.26 0.16

V_CCIO

0.5 x

V_CCIO

+0.12

0.5 x V_CCIO0.5 x

– 0.12 V_CCIO

0.4 x V 0.5 x

CCIO

0.6 x

V_CCIO

HSUL-12

1.3 0.26 0.26

0.44 0.44

V_CCIO

(1)

Table 2–19. Differential I/O Standard Specifications for Cyclone V Devices—Preliminary

(2)

V_CCIO(V)

V_ID(mV)

V_ICM(DC)(V)

V_OD(V)

V_OCM(V)

I/O Standard

Min Typ Max Min

Condition

Max Min Max

Min Typ Max Min Typ Max

Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard.

For transmitter, receiver, and reference clock I/O pin specifications, refer to Table 2–20 on page 2–14.

PCML

2.5 V LVDS

2.375 2.5 2.625 100

V

_CM= 1.25 V

—

0.05 1.8 0.247

0.3 1.4 0.1

—

0.6 1.125 1.25 1.375

RSDS (HIO) 2.375 2.5 2.625 100

0.2 0.6

0.5

1.2

1.4

Mini-LVDS

2.375 2.5 2.625 200

(HIO)

—

600 0.4 1.325 0.25

—

0.6

1

1.2

1.4

LVPECL

SLVS

2.375 2.5 2.625 300

2.375 2.5 2.625 100

—

0.6

1.8

—

V

_CM= 1.25 V

0.05 1.8

Notes to Table 2–19:

(1) The 1.4-V and 1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 2–14.

(2) RL range: 90 ≤ RL ≤ 110 Ω

Power Consumption

Altera offers two ways to estimate power consumption for a design—the Excel-based

Early Power Estimator (EPE) and the Quartus^®II PowerPlay Power Analyzer feature.

1

You typically use the interactive Excel-based EPE before designing the FPGA to get a

magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer

provides better quality estimates based on the specifics of the design after you

complete place-and-route. The PowerPlay Power Analyzer can apply a combination

of user-entered, simulation-derived, and estimated signal activities that, when

combined with detailed circuit models, yields very accurate power estimates.

f

For more information about power estimation tools, refer to the PowerPlay Early Power

Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II

Handbook.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–14

Chapter 2: Device Datasheet for Cyclone V Devices

Switching Characteristics

This section provides performance characteristics of Cyclone V core and periphery

blocks for commercial grade devices.

These characteristics can be designated as preliminary or final.

■

Preliminary characteristics are obtained using simulation results, process data,

and other known parameters. The title of these tables show the designation as

“Preliminary.”

Final numbers are based on actual silicon characterization and testing. The

numbers reflect the actual performance of the device under worst-case silicon

process, voltage, and junction temperature conditions. There are no designations

on finalized tables.

Transceiver Performance Specifications

This section describes transceiver performance specifications.

Table 2–20 lists the Cyclone V GX transceiver specifications.

Table 2–20. Transceiver Specifications for Cyclone V GX Devices—Preliminary (Part 1 of 3)

C6

C7, I7

C8, A7

Symbol/

Description

Speed Grade

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Reference Clock

Supported I/O

Standards

1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL ⁽¹⁾, HCSL, and LVDS

Input frequency from

REFCLKinput pins

—

27

45

—

550

55

27

45

—

550

55

27

45

—

550

55

MHz

%

Duty cycle

Peak-to-peak

differential input voltage

200

2000

200

2000

200

2000

mV

Spread-spectrum

modulating clock

frequency

PCIe

30

—

33

30

—

33

30

—

33

kHz

—

0 to

Spread-spectrum

downspread

—

–0.5%

On-chip termination

resistors

—

100

Ω

(2)

V_ICM(AC coupled)

1.1

1.1 ⁽²⁾

1.1

V

HCSL I/O

standard for the

PCIe reference

clock

V_ICM(DC coupled)

R_REF

250

—

550

—

250

—

550

—

250

—

550

—

mV

2000

1%

2000

1%

2000

1%

—

Ω

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–15

Switching Characteristics

Table 2–20. Transceiver Specifications for Cyclone V GX Devices—Preliminary (Part 2 of 3)

C6

C7, I7

C8, A7

Symbol/

Description

Speed Grade

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Transceiver Clocks

fixedclkclock

frequency

Avalon^®Memory-

Mapped (Avalon-MM)

PHY management clock

frequency

PCIe

Receiver Detect

—

125

—

125

—

125

—

MHz

< 150

Receiver

Supported I/O

Standards

1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS

Data rate

—

614

—

3125

1.2

614

—

3125

1.2

614

—

2500

1.2

Mbps

V

Absolute V_MAXfor a

receiver pin ⁽³⁾

Absolute V_MINfor a

receiver pin

—

–0.4

—

–0.4

—

–0.4

—

V

Maximum peak-to-peak

differential input voltage

V_ID(diff p-p) before

1.6

device configuration

Maximum peak-to-peak

differential input voltage

V_ID(diff p-p) after

—

85

—

2.2

—

85

—

2.2

—

85

—

2.2

—

V

device configuration

Minimum differential

eye opening at the

receiver serial input

mV

(4)

pins

85−Ω setting

100−Ω setting

120−Ω setting

150-Ω setting

—

85

—

85

—

85

—

Ω

100

120

150

100

120

150

100

120

150

Differential on-chip

termination resistors

Differential and

common mode return

loss

PCIe Gen1,

GIGE

Compliant

—

Programmable PPM

detector ⁽⁵⁾

—

62.5, 100, 125, 200, 250, 300, 500, and 1000

ppm

UI

Run Length

—

200

4

—

200

4

—

200

4

Programmable

equalization

dB

DC Gain Setting

= 0

—

0

3

—

0

3

—

0

3

—

dB

Programmable DC gain

DC Gain Setting

= 1

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–16

Chapter 2: Device Datasheet for Cyclone V Devices

Switching Characteristics

Table 2–20. Transceiver Specifications for Cyclone V GX Devices—Preliminary (Part 3 of 3)

C6

C7, I7

C8, A7

Symbol/

Description

Speed Grade

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Transmitter

Supported I/O

Standards

1.5 V PCML

Data rate

V_OCM

—

614

—

30

—

650

85

3125

—

614

—

30

—

650

85

3125

—

614

—

30

—

650

85

2500

—

Mbps

mV

Ω

85−Ω setting

100−Ω setting

120−Ω setting

150-Ω setting

—

100

120

150

—

100

120

150

—

100

120

150

—

Ω

Differential on-chip

termination resistors

—

Ω

—

Ω

(6)

Rise time

160

ps

(6)

Fall time

—

ps

CMU PLL

Supported data range

—

614

—

3125

614

—

3125

614

—

2500

Mbps

Transceiver-FPGA Fabric Interface

Interface speed

—

25

—

187.5

25

—

163.84

25

—

156.25

MHz

(single-width mode)

Interface speed

—

163.84

(double-width mode)

Notes to Table 2–20:

(1) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.

(2) The reference clock common mode voltage is equal to the V_{CCR_GXB}power supply level.

(3) The device cannot tolerate prolonged operation at this absolute maximum.

(4) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the

Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.

(5) The rate matcher supports only up to 300 parts per million (ppm).

(6) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–17

Switching Characteristics

Table 2–21 lists the Cyclone V GX transceiver block jitter specifications.

Table 2–21. Transceiver Block Jitter Specifications for Cyclone V GX Devices—Preliminary

C6

C7, I7

C8, A7

Symbol/

Description

Speed Grade

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min Typ

Max

(1)

PCIe Transmit Jitter Generation

Total jitter at

2.5 Gbps (Gen1)

Compliance pattern

—

0.25

—

0.25

—

0.25

UI

(1)

PCIe Receiver Jitter Tolerance

Total jitter at

2.5 Gbps (Gen1)

Compliance pattern

> 0.6

(2)

GIGE Transmit Jitter Generation

Deterministic jitter

(peak-to-peak)

Pattern = CRPAT

—

0.14

—

0.14

—

0.14

UI

Total jitter

(peak-to-peak)

Pattern = CRPAT

0.279

—

0.279

(2)

GIGE Receiver Jitter Tolerance

Deterministic jitter

tolerance

(peak-to-peak)

Pattern = CJPAT

> 0.4

UI

Combined

deterministic and

random jitter

tolerance

Pattern = CJPAT

> 0.66

(peak-to-peak)

Notes to Table 2–21:

(1) The jitter numbers for PIPE are compliant to the PCIe Base Specification 2.0.

(2) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–18

Chapter 2: Device Datasheet for Cyclone V Devices

Switching Characteristics

Core Performance Specifications

This section describes the clock tree, phase-locked loop (PLL), digital signal

processing (DSP), and memory block specifications.

Clock Tree Specifications

Table 2–22 lists the clock tree specifications for Cyclone V devices.

Table 2–22. Clock Tree Performance for Cyclone V Devices—Preliminary

Performance

Unit

C6

C7, I7

Speed Grade

C8, A7

Speed Grade

Symbol

Speed Grade

Global clock and Regional clock

Peripheral clock

550

155

550

460

155

MHz

155

PLL Specifications

Table 2–23 lists the Cyclone V PLL specifications when operating in the commercial

(0° to 85°C), industrial (–40° to 100°C), and automotive (–40° to 125°C) junction

temperature ranges.

Table 2–23. PLL Specifications for Cyclone V Devices—Preliminary ⁽¹⁾(Part 1 of 3)

Symbol

Parameter

Min

5

Typ

—

50

—

Max

670 ⁽²⁾

622 ⁽²⁾

500 ⁽²⁾

325

TBD ⁽¹⁾

1600

1400

1300

60

550 ⁽³⁾

460 ⁽³⁾

667 ⁽³⁾

533 ⁽³⁾

55

Unit

MHz

%

C6 speed grade

f_IN

Input clock frequency

C7, I7 speed grades

C8, A7 speed grades

5

f_INPFD

Integer input clock frequency to the PFD

Fractional input clock frequency to the PFD

5

f_FINPFD

50

600

40

—

45

—

C6 speed grade

f_VCO

PLL VCO operating range

C7, I7 speed grades

C8, A7 speed grades

t_EINDUTY

Input clock or external feedback clock input duty cycle

C6 speed grade

Output frequency for internal global

MHz

%

f_OUT

C7, I7 speed grades

or regional clock

C8, A7 speed grades

C6 speed grade

Output frequency for external clock

C7, I7 speed grades

output

f_{OUT_EXT}

C8, A7 speed grades

Duty cycle for external clock output (when set to 50%)

External feedback clock compensation time

Time required to reconfigure phase shift

t_OUTDUTY

t_FCOMP

10

TBD ⁽¹⁾

ns

t_CONFIGPHASE

t_DYCONFIGCLK

—

Dynamic configuration clock

100

MHz

Time required to lock from end-of-device configuration or

deassertion of areset

t_LOCK

—

1

ms

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–19

Switching Characteristics

Table 2–23. PLL Specifications for Cyclone V Devices—Preliminary ⁽¹⁾(Part 2 of 3)

Symbol

t_DLOCK

Parameter

Min

Typ

Max

Unit

Time required to lock dynamically (after switchover or

reconfiguring any non-post-scale counters/delays)

—

1

ms

PLL closed-loop low bandwidth

—

10

—

0.3

1.5

4

—

MHz

ps

f_CLBW

PLL closed-loop medium bandwidth

(8)

PLL closed-loop high bandwidth

—

t_{PLL_PSERR}

t_ARESET

Accuracy of PLL phase shift

—

50

Minimum pulse width on the aresetsignal

Input clock cycle-to-cycle jitter (F_REF≥ 100 MHz)

Input clock cycle-to-cycle jitter (F_REF< 100 MHz)

Period jitter for dedicated clock output (F_OUT≥ 100 MHz)

Period jitter for dedicated clock output (F_OUT< 100 MHz)

—

ns

0.15

750

UI (p-p)

ps (p-p)

mUI (p-p)

(4), (5)

t_INCCJ

(1)

TBD

(6)

t_{OUTPJ_DC}

(1)

Cycle-to-cycle jitter for dedicated clock output

(F_OUT≥ 100 MHz)

—

TBD

ps (p-p)

mUI (p-p)

ps (p-p)

(6)

t_{OUTCCJ_DC}

Cycle-to-cycle jitter for dedicated clock output

(F_OUT< 100 MHz)

(1)

Period jitter for clock output on regular I/O

(F_OUT≥ 100 MHz)

(6), (9)

t_{OUTPJ_IO}

Period jitter for clock output on regular I/O

(F_OUT< 100 MHz)

mUI (p-p)

ps (p-p)

Cycle-to-cycle jitter for clock output on regular I/O

(F_OUT≥ 100 MHz)

(6), (9)

t_{OUTCCJ_IO}

Cycle-to-cycle jitter for clock output on regular I/O

(F_OUT< 100 MHz)

—

mUI (p-p)

t_{OUTPJ_DC_F}

t_{OUTCCJ_DC_F}

Period jitter for dedicated clock output in fractional mode

TBD ⁽¹⁾

—

Cycle-to-cycle jitter for dedicated clock output in fractional

mode

Period jitter for clock output on regular I/O in fractional

mode

t_{OUTPJ_IO_F}

—

TBD ⁽¹⁾

—

Cycle-to-cycle jitter for clock output on regular I/O in

fractional mode

t_{OUTCCJ_IO_F}

Period jitter for dedicated clock output in cascaded PLLs

(F_OUT≥ 100 MHz)

(1)

TBD

ps (p-p)

mUI (p-p)

t_{CASC_OUTPJ_DC}

(6), (7)

Period jitter for dedicated clock output in cascaded PLLs

(F_OUT< 100 MHz)

(1)

TBD

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–20

Chapter 2: Device Datasheet for Cyclone V Devices

Switching Characteristics

Table 2–23. PLL Specifications for Cyclone V Devices—Preliminary ⁽¹⁾(Part 3 of 3)

Symbol

t_DRIFT

Parameter

Min

—

Typ

—

Max

10

Unit

Frequency drift after PFDENA is disabled for a duration of

100 µs

%

dK_BIT

Bit number of Delta Sigma Modulator (DSM)

Numerator of Fraction

—

24

—

Bits

—

k_VALUE

TBD ⁽¹⁾8388608 TBD ⁽¹⁾

f_RES

Resolution of VCO frequency (f_INPFD=100 MHz)

—

5.96

—

Hz

Notes to Table 2–23:

(1) Pending silicon characterization.

(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O

standard.

(3) This specification is limited by the lower of the two: I/O f_MAXor F_OUTof the PLL.

(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.

(5) F_REFis f_IN/Nwhen N = 1.

(6) Peak-to-peak jitter with a probability level of 10^–12(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies

to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a

different measurement method and are available in Table 2–28 on page 2–24.

(7) The cascaded PLL specification is only applicable with the following condition:

a. Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz

b. Downstream PLL: Downstream PLL BW > 2 MHz

(8) High bandwidth PLL settings are not supported in external feedback mode.

(9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 2–28 on page 2–24.

DSP Block Specifications

Table 2–24 lists the Cyclone V DSP block performance specifications.

Table 2–24. DSP Block Performance Specifications for Cyclone V Devices—Preliminary

Performance

Mode

Unit

C6

C7, I7

Speed Grade

C8, A7

Speed Grade

Modes using One DSP Block

Independent 9 x 9 Multiplication

Independent 18 x 19 Multiplication

Independent 18 x 18 Multiplication

Independent 27 x 27 Multiplication

Independent 18 x 25 Multiplication

Independent 20 x 24 Multiplication

Two 18 x 19 Multiplier Adder Mode

18 x 18 Multiplier Added Summed with 36-bit Input

Modes using Two DSP Blocks

340

287

250

310

300

250

200

250

260

200

160

200

MHz

Complex 18 x 19 multiplication

Two 27 x 27 Multiplier Adder

310

250

310

250

200

250

200

160

200

MHz

Four 18 x 19 Multiplier Adder

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–21

Switching Characteristics

Memory Block Specifications

Table 2–25 lists the Cyclone V memory block specifications.

Table 2–25. Memory Block Performance Specifications for Cyclone V Devices—Preliminary ^{(1), (2)}

Resources Used

Performance

Memory

Mode

Unit

C6

C7, I7

C8, A7

ALUTs

Memory

Speed Grade Speed Grade Speed Grade

Single port, all supported widths

0

1

450

380

330

MHz

Simple dual-port, all supported

widths

450

380

330

MLAB

Simple dual-port with read and

write at the same address

0

1

350

300

250

MHz

ROM, all supported width

0

1

450

315

380

275

330

240

MHz

Single-port, all supported widths

Simple dual-port, all supported

widths

0

1

315

275

315

275

240

275

240

180

240

MHz

Simple dual-port with the

read-during-write option set to

Old Data, all supported widths

M10K

Block

True dual port, all supported

widths

ROM, all supported widths

0

1

315

275

240

MHz

ps

Min Pulse Width (clock high time)

Min Pulse Width (clock low time)

—

1,450

1,000

1,550

1,200

1,650

1,350

ps

Notes to Table 2–25:

(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL

set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.

(2) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in f_MAX

.

Periphery Performance

This section describes periphery performance and the high-speed I/O and external

memory interface.

I/O performance supports several system interfaces, such as the LVDS high-speed

I/O interface, external memory interface, and the PCI/PCI-X bus interface.

General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-V LVTTL/LVCMOS

are capable of a typical 167 MHz and 1.2 LVCMOS at 100 MHz interfacing frequency

with 10 pF load.

1

Actual achievable frequency depends on design- and system-specific factors. You

must perform HSPICE/IBIS simulations based on your specific design and system

setup to determine the maximum achievable frequency in your system.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–22

Chapter 2: Device Datasheet for Cyclone V Devices

Switching Characteristics

High-Speed I/O Specification

Table 2–26 lists high-speed I/O timing for Cyclone V devices.

Table 2–26. High-Speed I/O Specifications for Cyclone V Devices—Preliminary ^{(2), (3)}(Part 1 of 2)

C6

C7, I7

Speed Grade

C8, A7

Speed Grade

Symbol

Conditions

Unit

Min Typ

Max Min Typ

Max

Min Typ

Max

f

_{HSCLK_in}(input

clock frequency)

True Differential I/O

Standards

Clock boost factor W = 1

5

—

437.5

5

—

420

5

—

320

MHz

(4)

to 40

f_{HSCLK_in}(input

clock frequency)

Single Ended I/O

Standards

Clock boost factor W = 1

5

—

320

420

5

—

320

370

5

—

275

320

MHz

(4)

to 40

f_{HSCLK_OUT}(output

clock frequency)

—

Transmitter

(5)

SERDES factor J = 4 to 10

—

840

—

740

—

640 Mbps

True Differential I/O

Standards - f_HSDR

(data rate)

SERDES factor J = 1 to 2,

Uses DDR Registers

(7)

Mbps

Emulated

Differential I/O

Standards with

Three External

Output Resistor

Networks - f_HSDR

(5)

SERDES factor J = 4 to 10

—

640

170

—

640

170

—

550 Mbps

(6)

(data rate)

Emulated

Differential I/O

Standards with One

External Output

Resistor Network -

(5)

170 Mbps

(6)

f_HSDR(data rate)

Total Jitter for Data Rate,

600 Mbps - 840 Mbps

—

160

0.1

—

160

0.1

—

160

0.1

ps

UI

t_{x Jitter}- True

Differential I/O

Standards

Total Jitter for Data Rate,

< 600 Mbps

t_{x Jitter}- Emulated

Differential I/O

Standards with

Three External

Output Resistor

Networks

Total Jitter for Data Rate

< 640 Mbps

—

TBD ⁽¹⁾

—

TBD ⁽¹⁾

—

TBD ⁽¹⁾

UI

t_{x Jitter}- Emulated

Differential I/O

Standards with One

External Output

Resistor Network

Total Jitter for Data Rate

< 640 Mbps

TBD ⁽¹⁾

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

Switching Characteristics

2–23

Unit

Table 2–26. High-Speed I/O Specifications for Cyclone V Devices—Preliminary ^{(2), (3)}(Part 2 of 2)

C6

C7, I7

Speed Grade

C8, A7

Speed Grade

Symbol

Conditions

Min Typ

Max Min Typ

Max

Min Typ

Max

TX output clock duty

cycle for both True and

Emulated Differential I/O

Standards

t_DUTY

45

—

50

—

55

45

—

50

—

55

45

—

50

—

55

%

ps

True Differential I/O

Standards

200

250

200

250

200

300

Emulated Differential I/O

Standards with Three

External Output Resistor

Networks

t_{RISE &}t_FALL

Emulated Differential I/O

Standards with One

External Output Resistor

Network

—

300

200

300

—

300

250

300

—

300

250

300

ps

True Differential I/O

Standards

Emulated Differential I/O

Standards with Three

External Output Resistor

Networks

TCCS

Emulated Differential I/O

Standards with One

External Output Resistor

Network

—

300

—

300

—

300

ps

Receiver

(5)

SERDES factor J = 4 to 10

—

875 ⁽⁶⁾

—

840 ⁽⁶⁾

—

640 ⁽⁶⁾Mbps

f_HSDR(data rate)

SERDES factor J = 1 to 2,

Uses DDR Registers

(7)

Mbps

Sampling Window

—

350

—

350

—

350

ps

Notes to Table 2–26:

(1) Pending silicon characterization.

(2) When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.

(3) This is achieved by using the LVDS clock network.

(4) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.

(5) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,

or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.

(6) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew

margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

(7) The maximum ideal frequency is the SERDES factor (J) x PLL max output frequency (f_out), provided you can close the design timing and the

signal integrity simulation is clean.You can estimate the achievable maximum data rate by performing link timing closure analysis. You must

consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–24

Chapter 2: Device Datasheet for Cyclone V Devices

Switching Characteristics

DQS Logic Block and Memory Output Clock Jitter Specifications

Table 2–27 lists the DQS phase shift error for Cyclone V devices.

Table 2–27. DQS Phase Shift Error Specification for DLL-Delayed Clock (t_{DQS_PSERR}) for Cyclone V

Devices—Preliminary ^{(1), (2)}

Number of DQS Delay

Buffers

C6

C7, I7

Speed Grade

C8, A7

Speed Grade

Unit

Speed Grade

2

69

70

80

ps

Notes to Table 2–27:

(1) The numbers are preliminary pending silicon characterization.

(2) This error specification is the absolute maximum and minimum error. For example, skew on two DQS delay buffers

in a –7 speed grade is 70 ps or 35 ps.

(3) Delay chain engineering option setting: rb_co[1:0]=“11”.

Table 2–28 lists the memory output clock jitter specifications for Cyclone V devices.

Table 2–28. Memory Output Clock Jitter Specification for Cyclone V Devices—Preliminary ^{(1), (2), (3)}

C6

C7, I7

C8, A7

Clock

Network

Speed Grade

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

Clock period jitter

Regional

t_JIT(per)

t_JIT(cc)

TBD

ps

Cycle-to-cycle period

jitter

TBD

Duty cycle jitter

Regional

Global

t_JIT(duty)

t_JIT(per)

TBD

ps

Clock period jitter

Cycle-to-cycle period

jitter

Global

t_JIT(cc)

TBD

ps

Duty cycle jitter

t_JIT(duty)

Notes to Table 2–28:

(1) Pending silicon characterization.

(2) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.

(3) The clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by

a PLL output routed on a PHY, regional, or global clock network as specified. Altera recommends using PHY clock networks whenever possible.

OCT Calibration Block Specifications

Table 2–29 lists the OCT calibration block specifications for Cyclone V devices.

Table 2–29. OCT Calibration Block Specifications for Cyclone V Devices—Preliminary (Part 1 of 2)

Symbol

Description

Min

Typ

Max

Unit

OCTUSRCLK

Clock required by OCT calibration blocks

—

20

MHz

Number of OCTUSRCLK clock cycles required for

R_SOCT /R_TOCT calibration

T_OCTCAL

—

1000

—

Cycles

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–25

Switching Characteristics

Table 2–29. OCT Calibration Block Specifications for Cyclone V Devices—Preliminary (Part 2 of 2)

Symbol

T_OCTSHIFT

Description

Min

Typ

Max

Unit

Number of OCTUSRCLK clock cycles required for OCT code

to shift out

—

32

—

Cycles

Time required between the dyn_term_ctrland oesignal

transitions in a bidirectional I/O buffer to dynamically switch

between R_SOCT and R_TOCT

T_{RS_RT}

—

2.5

—

ns

Figure 2–1 shows the timing diagram for the oeand dyn_term_ctrlsignals.

Figure 2–1. Timing Diagram for the oe and dyn_term_ctrl Signals

Tristate

RX

TX

RX

oe

dyn_term_ctrl

T_{RS_RT}

[

Duty Cycle Distortion (DCD) Specifications

Table 2–30 lists the worst-case DCD for Cyclone V devices.

Table 2–30. Worst-Case DCD on I/O Pins for Cyclone V Devices—Preliminary

C6

C7, I7

Speed Grade

C8, A7

Speed Grade

Symbol

Unit

Min

45

Max

Min

45

Max

Min

45

Max

Output Duty Cycle

55

%

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–26

Chapter 2: Device Datasheet for Cyclone V Devices

Configuration Specification

This section provides configuration specifications and timing for Cyclone V devices.

These characteristics can be designated as preliminary or final.

■

Preliminary characteristics are obtained using simulation results, process data,

and other known parameters. The title of these tables show the designation as

“Preliminary.”

Final numbers are based on actual silicon characterization and testing. The

numbers reflect the actual performance of the device under worst-case silicon

process, voltage, and junction temperature conditions. There are no designations

on finalized tables.

POR Specifications

Table 2–31 lists the specifications for fast and standard POR delay for Cyclone V

devices.

Table 2–31. Fast and Standard POR Delay Specification for Cyclone V Devices

POR Delay

Fast ⁽¹⁾

PORSEL Pin Setting

Minimum (ms)

Maximum (ms)

High

GND

4

12

Standard

100

300

Note to Table 2–31:

(1) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize

after the POR trip.

JTAG Configuration Timing

Table 2–32 lists the JTAG timing parameters and values for Cyclone V devices.

Table 2–32. JTAG Timing Parameters and Values for Cyclone V Devices—Preliminary

Symbol

Description

TCK clock period

Min

30

14

1

Max

—

Unit

ns

t_JCP

t_JCH

t_JCL

TCK clock high time

—

TCK clock low time

—

t_{JPSU (TDI)}

t_{JPSU (TMS)}

t_JPH

TDI JTAG port setup time

TMS JTAG port setup time

JTAG port hold time

—

3

—

5

—

(1)

t_JPCO

JTAG port clock to output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

—

11

14

(1)

t_JPZX

t_JPXZ

Note to Table 2–32:

(1) A 1 ns adder is required for each V_CCIOvoltage step down from 3.0 V. For example, t_JPCO= 12 ns if V_CCIOof the TDO

I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Cyclone V Devices

2–27

Configuration Specification

FPP Configuration Timing

This section describes the fast passive parallel (FPP) configuration timing parameters

for Cyclone V devices.

DCLK-to-DATA[] Ratio (r) for FPP Configuration

FPP configuration requires a different DCLK-to-DATA[]ratio when you turn on

encryption or the compression feature.

Table 2–33 lists the DCLK-to-DATA[]ratio for each combination.

Table 2–33. DCLK-to-DATA[] Ratio for Cyclone V Devices—Preliminary ⁽¹⁾

Configuration Scheme

Encryption

Compression

DCLK-to-DATA[] ratio (r)

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

1

2

1

2

4

FPP (8-bit wide)

FPP (16-bit wide)

Note to Table 2–33:

(1) Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r times the DATA[]

rate in byte per second (Bps) or word per second (Wps). For example, in FPP x16 where the r is 2, the DCLK

frequency must be 2 times the DATA[]rate in Wps.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–28

Chapter 2: Device Datasheet for Cyclone V Devices

Configuration Specification

FPP Configuration Timing when DCLK to DATA[] = 1

Figure 2–2 shows the timing waveform for an FPP configuration when using a

MAX^®II device as an external host. This waveform shows timing when the

DCLK-to-DATA[]ratio is 1.

1

When you enable decompression or the design security feature, the DCLK-to-DATA[]

ratio varies for FPP x8 and FPP x16. For the respective DCLK-to-DATA[]ratio, refer to

Table 2–33 on page 2–27.

Figure 2–2. DCLK-to-DATA[] FPP Configuration Timing Waveform for Cyclone V Devices When the Ratio is 1 ⁽¹⁾

t_CF2ST1

t_CFG

t_CF2CK

nCONFIG

nSTATUS (2)

t_STATUS

(6)

t_CF2ST0

t_CLK

CONF_DONE (3)

t

_CHt_CL

t_CF2CD

t_ST2CK

(4)

DCLK

t_DH

Word 0 Word 1 Word 2 Word 3

Word n

Word n-2 Word n-1

DATA[15..0](5)

User Mode

t_DSU

High-Z

User I/O

(7)

INIT_DONE

t_CD2UM

Notes to Figure 2–2:

(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG

, nSTATUS, and CONF_DONEare at logic-high levels. When

nCONFIGis pulled low, a reconfiguration cycle begins.

(2) After power up, the Cyclone V device holds nSTATUSlow for the time of the POR delay.

(3) After power up, before and during configuration, CONF_DONEis low.

(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.

(5) For FPP x16, use DATA[15..0]. For FPP x8, use DATA[7..0]. DATA[15..0]are available as a user I/O pin after configuration. The state of this

pin depends on the dual-purpose pin settings.

(6) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONEis released high when the Cyclone V

device receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization

and enter user mode.

(7) After the option bit to enable the INIT_DONEpin is configured into the device, INIT_DONE goes low.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–29

Configuration Specification

Table 2–34 lists the timing parameters for Cyclone V devices for an FPP configuration

when the DCLK-to-DATA[]ratio is 1.

(1)

Table 2–34. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices When the Ratio is 1—Preliminary

Symbol

t_CF2CD

t_CF2ST0

t_CFG

Parameter

nCONFIGlow to CONF_DONElow

nCONFIGlow to nSTATUSlow

Minimum

Maximum

600

Unit

ns

—

600

ns

nCONFIGlow pulse width

2

268

—

µs

(2)

nSTATUSlow pulse width

1506

t_STATUS

t_CF2ST1

t_CF2CK

t_ST2CK

t_DSU

(3)

nCONFIGhigh to nSTATUShigh

nCONFIGhigh to first rising edge on DCLK

nSTATUShigh to first rising edge of DCLK

1506

2

—

DATA[]setup time before rising edge on

DCLK

5.5

—

ns

DATA[]hold time after rising edge on DCLK

DCLKhigh time

0

—

ns

t_DH

0.45 x 1/f_MAX

t_CH

DCLKlow time

0.45 x 1/f_MAX

—

ns

t_CL

DCLKperiod

1/f_MAX

—

ns

t_CLK

f_MAX

t_R

DCLKfrequency (FPP x8 and x16)

Input rise time

—

125

40

MHz

ns

—

Input fall time

—

175

40

ns

t_F

(4)

CONF_DONEhigh to user mode

437

—

µs

t_CD2UM

t_CD2CU

t_CD2UMC

CONF_DONEhigh to CLKUSRenabled

4 × maximum DCLKperiod

—

t

_CD2CU+ (T_initx CLKUSR

CONF_DONEhigh to user mode with CLKUSR

option on

—

period)

Number of clock cycles required for device

initialization

T_init

17,408

Cycles

Notes to Table 2–34:

(1) Use these timing parameters when the DCLK-to-DATA[]ratio is 1. To find the DCLK-to-DATA[]ratio for your system, refer to Table 2–33 on

page 2–27.

(2) You can obtain this value if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.

(3) You can obtain this value if you do not delay configuration by externally holding nSTATUSlow.

(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–30

Chapter 2: Device Datasheet for Cyclone V Devices

Configuration Specification

FPP Configuration Timing when DCLK to DATA[] > 1

Figure 2–3 shows the timing waveform for an FPP configuration when using a

MAX II device or microprocessor as an external host. This waveform shows timing

when the DCLK-to-DATA[]ratio is more than 1.

(1), (2)

Figure 2–3. FPP Configuration Timing Waveform for Cyclone V Devices When the DCLK-to-DATA[] Ratio is > 1

t_CF2ST1

t_CFG

t_CF2CK

nCONFIG

nSTATUS (3)

t_STATUS

t_CF2ST0

CONF_DONE (4)

t

CL

t_CF2CD

(8)

t_ST2CK

t

CH

DCLK (6)

DATA[15..0] (8)

User I/O

(7)

(5)

1

2

1

2

r

1

2

r

t

CLK

n

Word 0

Word 1

Word (n-1) Word

User Mode

Word 3

t

t_DSU

DH

High-Z

(9)

INIT_DONE

t_CD2UM

Notes to Figure 2–3:

(1) To find the DCLK-to-DATA[]ratio for your system, refer to Table 2–33 on page 2–27.

(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONEare at logic high levels.

When nCONFIGis pulled low, a reconfiguration cycle begins.

(3) After power up, the Cyclone V device holds nSTATUSlow for the time as specified by the POR delay.

(4) After power up, before and during configuration, CONF_DONEis low.

(5) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.

(6) “r” denotes the DCLK-to-DATA[]ratio. For the DCLK-to-DATA[]ratio based on the decompression and the design security feature enable

settings, refer to Table 2–33 on page 2–27.

(7) If needed, pause DCLKby holding it low. When DCLKrestarts, the external host must provide data on the DATA[15..0]pins prior to sending

the first DCLKrising edge.

(8) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONEis released high after the Cyclone V

device receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin

initialization and enter user mode.

(9) After the option bit to enable the INIT_DONEpin is configured into the device, INIT_DONEgoes low.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–31

Configuration Specification

Table 2–35 lists the timing parameters for Cyclone V devices when the

DCLK-to-DATA[]ratio is more than 1.

Table 2–35. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices when the Ratio is > 1—Preliminary ⁽¹⁾

Symbol

t_CF2CD

t_CF2ST0

t_CFG

Parameter

nCONFIGlow to CONF_DONElow

nCONFIGlow to nSTATUSlow

Minimum

Maximum

600

Unit

—

ns

600

nCONFIGlow pulse width

2

268

—

µs

(2)

nSTATUSlow pulse width

1506

t_STATUS

t_CF2ST1

t_CF2CK

t_ST2CK

t_DSU

(3)

nCONFIGhigh to nSTATUShigh

nCONFIGhigh to first rising edge on DCLK

nSTATUShigh to first rising edge of DCLK

1506

2

—

DATA[]setup time before rising edge on

DCLK

5.5

—

ns

(4)

DATA[]hold time after rising edge on DCLK

DCLKhigh time

N–1/f_DCLK

—

ns

t_DH

0.45 x 1/f_MAX

t_CH

DCLKlow time

0.45 x 1/f_MAX

—

ns

t_CL

DCLKperiod

1/f_MAX

—

ns

t_CLK

f_MAX

t_R

DCLKfrequency (FPP x8 and x16)

Input rise time

—

125

40

MHz

ns

—

Input fall time

—

175

40

ns

t_F

CONF_DONEhigh to user mode ⁽⁵⁾

CONF_DONEhigh to CLKUSRenabled

437

—

µs

t_CD2UM

t_CD2CU

t_CD2UMC

4 × maximum DCLKperiod

—

t

_CD2CU+ (T_initx CLKUSR

CONF_DONEhigh to user mode with CLKUSR

option on

—

period)

Number of clock cycles required for device

initialization

T_init

17,408

Cycles

Notes to Table 2–35:

(1) Use these timing parameters when you use decompression and the design security features.

(2) This value can be obtained if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.

(3) This value can be obtained if you do not delay configuration by externally holding nSTATUSlow.

(4) N is the DCLK-to-DATAratio and f_DCLKis the DCLKfrequency the system is operating.

(5) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–32

Chapter 2: Device Datasheet for Cyclone V Devices

Configuration Specification

AS Configuration Timing

Figure 2–4 shows the timing waveform for the active serial (AS) x1 mode and AS x4

mode configuration timing.

Figure 2–4. AS Configuration Timing for Cyclone V Devices

t

(1)

POR

nCONFIG

nSTATUS

CONF_DONE

nCSO

DCLK

t

CO

t

DH

Read Address

AS_DATA0/ASDO

AS_DATA1 (2)

t

SU

bit 1

bit 0

bit N - 1

bit N

t

(3)

CD2UM

INIT_DONE (4)

User I/O

User Mode

Notes to Figure 2–4:

(1) The AS scheme supports standard and fast POR delay (t_POR). For t_PORdelay information, refer to “POR Delay Specification” in the Configuration,

Design Security, and remote System Upgrades in Cyclone V Devices chapter.

(2) If you are using AS x4 mode, this signal represents the AS_DATA[3..0]and EPCQ sends in 4-bits of data for each DCLKcycle.

(3) The initialization clock can be from the internal oscillator or the CLKUSRpin.

(4) After the option bit to enable the INIT_DONEpin is configured into the device, INIT_DONEgoes low.

Table 2–36 lists the timing parameters for AS x1 and AS x4 configurations in

Cyclone V devices.

(1), (2)

Table 2–36. AS Timing Parameters for AS x1 and x4 Configurations in Cyclone V Devices—Preliminary

Symbol

t_CO

Parameter

Minimum

Maximum

Unit

µs

DCLK falling edge to the AS_DATA0

/

ASDOoutput

—

4

t_SU

Data setup time before the rising edge on DCLK

Data hold time after the rising edge on DCLK

CONF_DONEhigh to user mode

1.5

—

437

—

ns

t_H

0

175

ns

t_CD2UM

t_CD2CU

t_CD2UMC

µs

CONF_DONEhigh to CLKUSRenabled

4 x maximum DCLKperiod

—

t

_CD2CU+ (T_initx CLKUSR

CONF_DONEhigh to user mode with CLKUSR

option on

—

period)

Number of clock cycles required for device

initialization

T_init

17,408

Cycles

Notes to Table 2–36:

(1) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.

(2) The t_CF2CD, t_CF2ST0, t_CFG, t_STATUS, and t_CF2ST1timing parameters are identical to the timing parameters for passive serial (PS) mode listed in

Table 2–38 on page 2–34.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–33

Configuration Specification

Table 2–37 lists the internal clock frequency specification for the AS configuration

scheme.

Table 2–37. DCLK Frequency Specification in the AS Configuration Scheme for Cyclone V

Devices—Preliminary ^{(1), (2)}

Minimum

Typical

7.9

Maximum

12.5

Unit

MHz

5.3

10.6

21.3

15.7

31.4

62.9

25.0

50.0

42.6

100.0

Notes to Table 2–37:

(1) This applies to the DCLKfrequency specification when using the internal oscillator as the configuration clock

source.

(2) The AS multi-device configuration scheme does not support DCLKfrequency of 100 MHz.

PS Configuration Timing

Figure 2–5 shows the timing waveform for a PS configuration when using a MAX II

device or microprocessor as an external host.

Figure 2–5. PS Configuration Timing Waveform for Cyclone V Devices ⁽¹⁾

t_CF2ST1

t_CFG

t_CF2CK

nCONFIG

nSTATUS (2)

t_STATUS

t_CF2ST0

(6)

t_CLK

CONF_DONE (3)

t

_CHt_CL

t_CF2CD

t_ST2CK

(4)

(5)

DCLK

t_DH

Bit 2 Bit 3

Bit n

Bit 0 Bit 1

DATA0

t_DSU

High-Z

User I/O

User Mode

INIT_DONE (7)

t_CD2UM

Notes to Figure 2–5:

(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG

, nSTATUS, and CONF_DONEare at logic high levels. When

nCONFIGis pulled low, a reconfiguration cycle begins.

(2) After power up, the Cyclone V device holds nSTATUSlow for the time of the POR delay.

(3) After power up, before and during configuration, CONF_DONEis low.

(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.

(5) DATA0is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins

Option.

(6) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONEis released high after the Cyclone V

device receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin

initialization and enter user mode.

(7) After the option bit to enable the INIT_DONEpin is configured into the device, INIT_DONEgoes low.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–34

Chapter 2: Device Datasheet for Cyclone V Devices

Configuration Specification

Table 2–38 lists the PS timing parameter for Cyclone V devices.

Table 2–38. PS Timing Parameters for Cyclone V Devices—Preliminary

Symbol

t_CF2CD

Parameter

nCONFIGlow to CONF_DONElow

nCONFIGlow to nSTATUSlow

Minimum

Maximum

600

Unit

ns

—

t_CF2ST0

600

ns

nCONFIGlow pulse width

2

—

µs

t_CFG

(1)

nSTATUSlow pulse width

268

1506

t_STATUS

t_CF2ST1

t_CF2CK

t_ST2CK

t_DSU

t_DH

(2)

nCONFIGhigh to nSTATUShigh

nCONFIGhigh to first rising edge on DCLK

nSTATUShigh to first rising edge of DCLK

DATA[]setup time before rising edge on DCLK

DATA[]hold time after rising edge on DCLK

DCLKhigh time

—

1506

µs

1506

—

125

40

437

—

µs

2

µs

5.5

ns

0

ns

0.45 x 1/f_MAX

ns

t_CH

DCLKlow time

0.45 x 1/f_MAX

ns

t_CL

DCLKperiod

1/f_MAX

ns

t_CLK

DCLKfrequency

—

MHz

ns

f_MAX

t_R

Input rise time

—

Input fall time

—

175

ns

t_F

CONF_DONEhigh to user mode ⁽³⁾

CONF_DONEhigh to CLKUSRenabled

CONF_DONEhigh to user mode with CLKUSRoption on

Number of clock cycles required for device initialization

µs

t_CD2UM

t_CD2CU

t_CD2UMC

T_init

4 x maximum DCLKperiod

—

t_CD2CU+ (T_init

x

CLKUSRperiod)

—

17,408

Cycles

Notes to Table 2–38:

(1) You can obtain this value if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.

(2) You can obtain this value if you do not delay configuration by externally holding nSTATUSlow.

(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Cyclone V Devices

2–35

I/O Timing

Remote System Upgrades Circuitry Timing Specification

Table 2–39 lists the timing parameter specifications for the remote system upgrade

circuitry.

Table 2–39. Remote System Upgrade Circuitry Timing Specification for Cyclone V Devices—

Preliminary

Parameter

Minimum

Maximum

Unit

(1)

(3)

—

40

MHz

t_{MAX_RU_CLK}

(2)

t_{RU_nCONFIG}

250

—

ns

t_{RU_nRSTIMER}

Notes to Table 2–39:

(1) This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE

megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification.

(2) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the

minimum timing specification. For more information, refer to “Remote System Upgrade State Machine” in the

Device Interfaces and Integration Basics for Cyclone V Devices chapter.

(3) This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE megafunction high for the

minimum timing specification. For more information, refer to “User Watchdog Timer” in the Device Interfaces and

Integration Basics for Cyclone V Devices chapter.

User Watchdog Internal Oscillator Frequency Specification

Table 2–40 lists the frequency specifications for the user watchdog internal oscillator.

Table 2–40. User Watchdog Internal Oscillator Frequency Specifications for Cyclone V

Devices—Preliminary

Minimum

Typical

Maximum

Unit

5.3

7.9

12.5

MHz

I/O Timing

Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the

Quartus II Timing Analyzer.

Excel-based I/O timing provides pin timing performance for each device density and

speed grade. The data is typically used prior to designing the FPGA to get an estimate

of the timing budget as part of the link timing analysis. The Quartus II Timing

Analyzer provides a more accurate and precise I/O timing data based on the specifics

of the design after you complete place-and-route.

1

The Excel-based I/O Timing spreadsheet will be available in the future release of the

Quartus II software.

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–36

Chapter 2: Device Datasheet for Cyclone V Devices

I/O Timing

Programmable IOE Delay

Table 2–41 lists the Cyclone V IOE programmable delay settings.

(1)

Table 2–41. IOE Programmable Delay for Cyclone V Devices

Fast Model

Slow Model

C7, I7

Available Minimum

Parameter

Unit

C6

C8, A7

Settings

Offset

Industrial Commercial

Speed Grade Speed Grade Speed Grade

TBD

ns

Note to Table 2–41:

(1) Pending data extraction from the Quartus II software.

Programmable Output Buffer Delay

Table 2–42 lists the delay chain settings that control the rising and falling edge delays

of the output buffer. The default delay is 0 ps.

(1), (2)

Table 2–42. Programmable Output Buffer Delay for Cyclone V Devices—Preliminary

Symbol

Parameter

Typical

0 (default)

50

Unit

ps

Rising and/or falling edge

delay

D_OUTBUF

100

ps

150

ps

Notes to Table 2–42:

(1) Pending data extraction from the Quartus II software.

(2) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay

Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the

Output Buffer Delay assignment.

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Cyclone V Devices

2–37

Glossary

Table 2–43 lists the glossary for this chapter.

Table 2–43. Glossary Table (Part 1 of 4)

Letter

Subject

Definitions

A

B

C

—

Receiver Input Waveforms

Single-Ended Waveform

Positive Channel (p) = V

IH

V

ID

Negative Channel (n) = V

Ground

IL

V

CM

Differential Waveform

V

ID

p − n = 0 V

V

ID

Differential I/O

Standards

D

Transmitter Output Waveforms

Single-Ended Waveform

Positive Channel (p) = V

OH

V

OD

Negative Channel (n) = V

Ground

OL

V

CM

Differential Waveform

V

OD

p − n = 0 V

V

OD

E

F

—

f_HSCLK

Left/right PLL input clock frequency.

High-speed I/O block—Maximum/minimum LVDS data transfer rate

(f_HSDR= 1/TUI), non-DPA.

f_HSDR

High-speed I/O block—Maximum/minimum LVDS data transfer rate

(f_HSDRDPA= 1/TUI), DPA.

f_HSDRDPA

G

H

I

—

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–38

Chapter 2: Device Datasheet for Cyclone V Devices

Glossary

Table 2–43. Glossary Table (Part 2 of 4)

Letter

Subject

Definitions

J

High-speed I/O block—Deserialization factor (width of parallel data bus).

JTAG Timing Specifications:

TMS

TDI

t_JCP

J

JTAG Timing

Specifications

t_JCH

t _JCL

t_JPH

t_JPSU

TCK

TDO

t_JPXZ

t_JPZX

t_JPCO

K

L

M

N

O

—

(1)

Diagram of PLL Specifications

CLKOUT Pins

f_{OUT_EXT}

Switchover

4

CLK

f_IN

f_INPFD

N

GCLK

RCLK

Counters

C0..C17

f_VCO

VCO

f_OUT

PFD

CP

LF

Core Clock

PLL

Specifications

P

Delta Sigma

Modulator

Key

External Feedback

Reconfigurable in User Mode

Note:

(1) Core Clockcan only be fed by dedicated clock input pins or PLL outputs.

Q

R

—

R_L

Receiver differential input discrete resistor (external to the Cyclone V device).

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Cyclone V Devices

2–39

Glossary

Table 2–43. Glossary Table (Part 3 of 4)

Letter

Subject

Definitions

Timing Diagram—the period of time during which the data must be valid in order to capture

it correctly. The setup and hold times determine the ideal strobe position within the sampling

window, as shown:

Sampling window

(SW)

Bit Time

Sampling Window

(SW)

RSKM

0.5 x TCCS

The JEDEC standard for the SSTl and HSTL I/O defines both the AC and DC input signal

values. The AC values indicate the voltage levels at which the receiver must meet its timing

specifications. The DC values indicate the voltage levels at which the final logic state of the

receiver is unambiguously defined. After the receiver input has crossed the AC value, the

receiver changes to the new logic state.

The new logic state is then maintained as long as the input stays beyond the AC threshold.

This approach is intended to provide predictable receiver timing in the presence of input

waveform ringing, as shown:

S

Single-Ended Voltage Referenced I/O Standard

Single-ended

voltage

V_CCIO

referenced I/O

standard

V_OH

V_IH

(

)

AC

V_IH(DC)

V_REF

V_IL(DC)

V_IL(AC

)

V_OL

V_SS

t_C

High-speed receiver/transmitter input and output clock period.

The timing difference between the fastest and slowest output edges, including the t_CO

variation and clock skew, across channels driven by the same PLL. The clock is included in

the TCCS measurement (refer to the Timing Diagram figure under SW in this table).

TCCS (channel-

to-channel-skew)

High-speed I/O block—Duty cycle on high-speed transmitter output clock.

Timing Unit Interval (TUI)

t_DUTY

The timing budget allowed for skew, propagation delays, and the data sampling window.

T

(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w)

t_FALL

Signal high-to-low transition time (80-20%)

Cycle-to-cycle jitter tolerance on the PLL clock input

Period jitter on the general purpose I/O driven by a PLL

Period jitter on the dedicated clock output driven by a PLL

Signal low-to-high transition time (20–80%)

—

t_INCCJ

t_{OUTPJ_IO}

t_{OUTPJ_DC}

t_RISE

U

—

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–40

Chapter 2: Device Datasheet for Cyclone V Devices

Document Revision History

Table 2–43. Glossary Table (Part 4 of 4)

Letter

Subject

V_CM(DC)

Definitions

DC common mode input voltage.

V_ICM

Input common mode voltage—The common mode of the differential signal at the receiver.

Input differential voltage swing—The difference in voltage between the positive and

complementary conductors of a differential transmission at the receiver.

V_ID

V_DIF(AC)

V_DIF(DC)

AC differential input voltage—Minimum AC input differential voltage required for switching.

DC differential input voltage— Minimum DC input differential voltage required for switching.

Voltage input high—The minimum positive voltage applied to the input which is accepted by

the device as a logic high.

V_IH

V_IH(AC)

V_IH(DC)

High-level AC input voltage

High-level DC input voltage

V

Voltage input low—The maximum positive voltage applied to the input which is accepted by

the device as a logic low.

V_IL

V_IL(AC)

V_IL(DC)

Low-level AC input voltage

Low-level DC input voltage

Output common mode voltage—The common mode of the differential signal at the

transmitter.

V_OCM

V_OD

Output differential voltage swing—The difference in voltage between the positive and

complementary conductors of a differential transmission at the transmitter.

V_SWING

V_X

Differential input voltage

Input differential cross point voltage

Output differential cross point voltage

High-speed I/O block—Clock Boost Factor

V_OX

W

X

Y

Z

—

Document Revision History

Table 2–44 lists the revision history for this chapter.

Table 2–44. Document Revision History

Date

Version

Changes

■ Added automotive speed grade information.

■ Added Figure 2–1.

■ Updated Table 2–3, Table 2–8, Table 2–9, Table 2–20, Table 2–21, Table 2–22,

Table 2–23, Table 2–24, Table 2–25, Table 2–26, Table 2–27, Table 2–28, Table 2–30,

Table 2–35, and Table 2–41.

February 2012

1.2

■ Minor text edits.

■ Added Table 2–5.

November 2011

October 2011

1.1

1.0

■ Updated Table 2–3, Table 2–4, Table 2–11, Table 2–13, Table 2–20, and Table 2–21.

Initial release.

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Cyclone V Devices

2–41

Document Revision History

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

2–42

Chapter 2: Device Datasheet for Cyclone V Devices

Document Revision History

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Additional Information

This chapter provides additional information about the document and Altera.

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the

following table.

Contact ⁽¹⁾

Technical support

Contact Method

Website

Email

Address

www.altera.com/support

www.altera.com/training

custrain@altera.com

Technical training

Product literature

Website

Email

www.altera.com/literature

nacomp@altera.com

Nontechnical support (general)

(software licensing)

Note to Table:

Email

authorization@altera.com

(1) You can also contact your local Altera sales office or sales representative.

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue

Meaning

Indicate command names, dialog box titles, dialog box options, and other GUI

labels. For example, Save As dialog box. For GUI elements, capitalization matches

the GUI.

Bold Type with Initial Capital

Letters

Indicates directory names, project names, disk drive names, file names, file name

extensions, software utility names, and GUI labels. For example, \qdesigns

directory, D: drive, and chiptrip.gdf file.

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

Indicates variables. For example, n + 1.

italic type

Variable names are enclosed in angle brackets (< >). For example, <file name> and

<project name>.pof file.

Indicate keyboard keys and menu names. For example, the Delete key and the

Options menu.

Initial Capital Letters

“Subheading Title”

Quotation marks indicate references to sections in a document and titles of

Quartus II Help topics. For example, “Typographic Conventions.”

February 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

Info–2

Additional Information

Typographic Conventions

Visual Cue

Meaning

Indicates signal, port, register, bit, block, and primitive names. For example, data1

tdi, and input. The suffix denotes an active-low signal. For example, resetn

Indicates command line commands and anything that must be typed exactly as it

appears. For example, c:\qdesigns\tutorial\chiptrip.gdf

,

n

.

Courier type

.

Also indicates sections of an actual file, such as a Report File, references to parts of

files (for example, the AHDL keyword SUBDESIGN), and logic function names (for

example, TRI).

r

An angled arrow instructs you to press the Enter key.

1., 2., 3., and

Numbered steps indicate a list of items when the sequence of the items is important,

such as the steps listed in a procedure.

a., b., c., and so on

■

Bullets indicate a list of items when the sequence of the items is not important.

The hand points to information that requires special attention.

1

h

The question mark directs you to a software help system with related information.

The feet direct you to another document or website with related information.

The multimedia icon directs you to a related multimedia presentation.

f

m

A caution calls attention to a condition or possible situation that can damage or

destroy the product or your work.

c

A warning calls attention to a condition or possible situation that can cause you

injury.

w

The envelope links to the Email Subscription Management Center page of the Altera

website, where you can sign up to receive update notifications for Altera documents.

Cyclone V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet


型号：	5CGTD9
厂家：	ALTERA CORPORATION
描述：	Cyclone V Device Handbook 旋风V器件手册
文件：	总74页 (文件大小：1776K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5CGTD9 [ALTERA]

相关型号：

5CGTFD5B5F23I7

5CGTFD5B5U19C7N

5CGTFD5C5F23C7N

5CGTFD5C5F23I7N

5CGTFD5C5F27C7N

5CGTFD5D5F23C7

5CGTFD7D5F27C7

5CGTFD9A5U19C7

5CGTFD9A5U19I7

5CGTFD9D5F27C6

5CGTFD9D5U19C6

5CGTFD9D5U19I7