AS7C34096A-20JCN [ALSC]
3.3V 512K x 8 CMOS SRAM; 3.3V 512K ×8 CMOS SRAM
| 型号： | AS7C34096A-20JCN |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V 512K x 8 CMOS SRAM |
| 文件： | 总9页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2004
AS7C34096A
®
3.3V 512K × 8 CMOS SRAM
• Equal access and cycle times
Features
• Easy memory expansion with CE
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
,
OE inputs
• Pin compatible to AS7C34096
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW / max @ 10 ns
Pin arrangements
36-pin SOJ (400 mil)
• Low power consumption: STANDBY
- 28.8 mW / max CMOS
A0
A1
A2
A3
A4
CE
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
2
A18
A17
A16
A15
OE
3
4
5
Logic block diagram
6
I/O1
I/O2
VCC
7
I/O8
I/O7
GND
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
8
9
GND
I/O3
I/O4
WE
A5
10
11
12
13
14
15
16
17
18
VCC
GND
Input buffer
A6
A7
A8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A9
I/O1
I/O8
524,288 × 8
Array
(4,194,304)
44-pin TSOP 2
NC
NC
NC
NC
A18
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A0
A1
A2
A3
A4
CE
2
3
4
A17
A16
A15
OE
5
6
7
Column decoder
WE
OE
CE
Control
Circuit
8
I/O1
I/O2
VCC
I/O8
I/O7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
VCC
GND
I/O3
I/O4
WE
A5
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A6
A7
A8
A9
NC
NC
NC
NC
Selection guide
–10
10
4
–12
12
5
–15
15
6
–20
20
7
Unit
ns
Maximum address access time
Maximum outputenable access time
ns
Industrial
180
170
8
160
150
8
140
130
8
110
100
8
mA
mA
mA
Maximum operating current
Commercial
Maximum CMOS standby current
8/17/04, v. 2.1
Alliance Semiconductor
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
AS7C34096A
®
Functional description
The AS7C34096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
524,288 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 4/5/6/7 ns are
AA RC WC
OE
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in
CMOS standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written
on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins
only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage. This device is available as
per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
Absolute maximum ratings
Parameter
Symbol
Min
–0.5
–0.5
–
Max
Unit
V
Voltage on V relative to GND
V
V
+5.0
CC
t1
t2
D
Voltage on any pin relative to GND
Power dissipation
V
+0.5
V
CC
P
T
1.0
W
Storage temperature (plastic)
–65
–55
–
+150
+125
20
°C
°C
mA
stg
Temperature with V applied
T
CC
bias
DC current into output (low)
I
OUT
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
WE
X
OE
X
Data
Mode
Standby (I , I
)
High Z
High Z
SB SB1
Output disable (I
)
H
H
CC
D
Read (I
)
L
H
L
OUT
CC
D
Write (I
)
CC
L
L
X
IN
Key: X = Don’t care, L = Low, H = High
8/17/04, v. 2.1
Alliance Semiconductor
P. 2 of 9
AS7C34096A
®
Recommended operating condition
Parameter
Symbol
Min
3.0
2.0
–0.5
0
Nominal
Max
Unit
Supply voltage
V
(10/12/15/20)
3.3
–
3.6
V
V
CC
**
V
V
+ 0.5
CC
IH
Input voltage
*
V
–
0.8
70
85
V
IL
commercial
industrial
T
–
°C
°C
Ambient operating
temperature
A
T
–40
–
A
*
**
V
IL min = –1.0V for pulse width less than 5ns.
VIH max = VCC + 2.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)1
–10
–12
–15
–20
Parameter
Symbol
Test conditions
Min Max Min Max Min Max Min Max Unit
Input leakage
current
|I |
–
–
1
1
–
–
1
1
–
–
1
1
–
–
1
1
µA
µA
LI
V
= Max, V = GND to V
IN CC
CC
Output leakage
current
V
= Max, CE = V
IH
CC
|I
|
LO
CC
V
= GND to V
OUT
CC
–
-
180
170
60
–
-
160
150
60
–
-
140
130
60
–
-
110 mA
100 mA
60 mA
Industrial
Operating power
supply current
V
= Max, CE ≤ V
Max OUT
I
CC
f = f , I
IL
= 0mA
Commercial
I
–
–
–
–
V
= Max, CE ≥ V f = f
IH, Max
SB
CC
V
= Max,
Standby power
supply current
CC
CE ≥ V – 0.2V,
≤ 0.2V or V ≥ V – 0.2V,
CC
I
–
8
–
8
–
8
–
8
mA
SB1
V
IN
IN CC
f = 0
V
V
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
I
= 8 mA, V = Min
OL
OL
CC
Output voltage
2.4
2.4
2.4
2.4
I
= –4 mA, V = Min
OH
OH
CC
Capacitance (f = 1MHz, T = 25° C, V = NOMINAL)2
a
CC
Parameter
Input capacitance
I/O capacitance
Symbol
Signals
A, CE, WE, OE
I/O
Test conditions
= 0V
Max
Unit
C
V
5
7
pF
pF
IN
IN
C
V
= V
= 0V
OUT
I/O
IN
8/17/04, v. 2.1
Alliance Semiconductor
P. 3 of 9
AS7C34096A
®
Read cycle (over the operating range)3,9
–10
–12
–15
–20
Parameter
Read cycle time
Symbol Min
Max
Min
Max
Min
Max
Min
Max Unit Notes
t
t
10
–
–
–
3
3
–
0
–
0
–
–
12
–
15
–
20
–
20
20
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
10
10
4
–
–
–
3
3
–
0
–
0
–
12
12
5
–
–
–
3
3
–
0
–
0
–
15
15
6
–
–
–
3
3
–
0
–
0
–
3
3
Address access time
AA
t
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE High to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
ACE
t
OE
t
–
–
–
–
5
OH
t
–
–
–
–
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
CLZ
t
5
6
7
9
CHZ
t
–
–
–
–
OLZ
OHZ
t
5
6
7
9
t
–
–
–
–
PU
t
10
12
15
20
Power down time
PD
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
tAA
tOH
DOUT
Data valid
Read waveform 2 (CE, OE controlled)3,6,8,9
tRC1
CE
tOE
OE
tOLZ
tOHZ
tCHZ
tACE
DOUT
Data valid
tCLZ
tPD
50%
ICC
ISB
tPU
Supply
current
50%
8/17/04, v. 2.1
Alliance Semiconductor
P. 4 of 9
AS7C34096A
®
Write cycle (over the operating range)10
–10
–12
–15
–20
Parameter
Write cycle time
Symbol Min
Max
Min
Max
Min
Max
Min
Max Unit Notes
t
t
t
10
7
–
12
–
15
–
20
–
–
–
–
–
–
–
–
–
–
9
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AW
–
–
–
–
–
–
–
–
–
5
–
8
8
–
–
–
–
–
–
–
–
–
6
–
10
10
0
–
–
–
–
–
–
–
–
–
7
–
12
12
0
Chip enable (CE) to write end
Address setup to write end
Address setup time
7
t
0
0
AS
t
t
7
8
10
15
0
12
20
0
Write pulse width (OE = high)
Write pulse width (OE = low
Address hold from end of write
Write recovery time
WP1
WP2
10
0
12
0
t
t
AH
0
0
0
0
WR
DW
t
5
6
7
9
Data valid to write end
t
0
0
0
0
4, 5
4, 5
4, 5
Data hold time
DH
t
t
0
0
0
0
Write enable to output in high Z
Output active from write end
WZ
3
3
3
3
OW
Write waveform 1 (WE controlled)10
tWC
tAW
tWR
tAH
Address
tWP
WE
tAS
tDW
Data valid
tDH
DIN
tWZ
tOW
DOUT
8/17/04, v. 2.1
Alliance Semiconductor
P. 5 of 9
AS7C34096A
®
Write waveform 2 (CE controlled)10
tWC
tWR
tAH
tAW
Address
tAS
tCW
CE
tWP
WE
tWZ
tDW
Data valid
tDH
DIN
DOUT
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figures A and B.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
DOUT
+3.3V
320
Ω
Thevenin equivalent:
168
+3.0V
DOUT
350
90%
10%
90%
10%
Ω
Ω
C11
+1.728V
GND
GND
Figure B: 3.3V Output load
2 ns
Figure A: Input pulse
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
t
CLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 All write cycle timings are referenced from the last valid address to the first transitioning address.
11 C=30pF, except on High Z and Low Z parameters, where C=5pF.
8/17/04, v. 2.1
Alliance Semiconductor
P. 6 of 9
AS7C34096A
®
Package dimensions
c
4443424140393837363534333231302928 2726
252423
44-pin TSOP 2
Min(mm) Max(mm)
A
1.2
E
E1
44-pin TSOP 2
A
0.05
0.95
0.15
1.05
1
A
2
b
c
0.30
0.45
1 2 3 4 5 6 7 8 9 10111213141516171819202122
0.21
0.12
d
18.31
10.06
11.68
18.52
10.26
11.94
d
E1
E
e
L
A2
A
0.80 (typical)
0–5°
A1
L
0.40
0.60
e
b
36-pin SOJ 400
Min(mils) Max(mils)
A
0.128
0.025
0.105
0.015
0.026
0.007
.920
0.148
–
A
1
A
0.115
0.020
0.032
0.013
.930
2
D
e
b
b1
b
1
E1E2
A
36-pin SOJ
c
D
e
A1
Seating
Plane
b
c
0.045
0.055
Pin 1
E
0.370 BSC
A2
E
0.395
0.435
0.405
0.445
1
2
E
E
8/17/04, v. 2.1
Alliance Semiconductor
P. 7 of 9
AS7C34096A
®
Ordering codes
Package Temperature
10 ns
12 ns
15 ns
20 ns
Commercial
SOJ
AS7C34096A-10JC AS7C34096A-12JC AS7C34096A-15JC AS7C34096A-20JC
AS7C34096A-10JI AS7C34096A-12JI AS7C34096A-15JI AS7C34096A-20JI
Industrial
Commercial
TSOP 2
AS7C34096A-10TC AS7C34096A-12TC AS7C34096A-15TC AS7C34096A-20TC
AS7C34096A-10TI AS7C34096A-12TI AS7C34096A-15TI AS7C34096A-20TI
Industrial
Note: Add suffix ‘N’ to the above part number for Lead Free Parts. (Ex: AS7C34096A - 10 TIN)
Part numbering system
AS7C
X
4096A
–XX
J orT
X
X
Packages:
J: SOJ 400 mil
T: TSOP 2
Temperature ranges:
C: Commercial, 0°C to 70°C N=Lead Free Parts
I: Industrial, –40°C to 85°C
Voltage:
SRAM
prefix
Device
number
Access time
3 - 3.3V CMOS
8/17/04, v. 2.1
Alliance Semiconductor
P. 8 of 9
AS7C34096A
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C34096A
Document Version: v. 2.1
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
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