AS7C3256-10TC [ALSC]
Standard SRAM, 32KX8, 10ns, CMOS, PDSO28, 8 X 13.40 MM, TSOP1-28;
| 型号： | AS7C3256-10TC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 32KX8, 10ns, CMOS, PDSO28, 8 X 13.40 MM, TSOP1-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2001
Advance Information
AS7C256
AS7C3256
®
5V/3.3V 32K X 8 CMOS SRAM (Common I/O)
Features
• AS7C256 (5V version)
• AS7C3256 (3.3V version)
- 7.2 mW (AS7C3256) / max CMOS I/O
• 2.0V data retention
• Easy memory expansion with CE and OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
- 300 mil PDIP
- 300 mil SOJ
- 8 × 13.4 TSOP
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• High speed
- 12/15/20 ns address access time
- 5/6/7/9 ns output enable access time
• Very low power consumption: ACTIVE
- 660mW (AS7C256) / max @ 12 ns
- 216mW (AS7C3256) / max @ 12 ns
• Very low power consumption: STANDBY
- 22 mW (AS7C256) / max CMOS I/O
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
Pin arrangement
28-pin TSOP I (8×13.4)
V
28-pin DIP, SOJ (300 mil)
CC
GND
Input buffer
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
OE
A11
A9
1
A10
CE
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(1)
(21) 28
(20) 27
(19) 26
(18) 25
(17) 24
(16) 23
(15) 22
(14) 21
(13) 20
(12) 19
(11) 18
(10) 17
(9) 16
(8) 15
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A0
A1
A8
4
I/O7
I/O0
A13
WE
5
6
A2
A3
256 X 128 X 8
Array
V
7
CC
AS7C256
AS7C3256
8
A14
A12
A7
9
(2)
A4
10
11
12
13
14
(3)
9
(4)
(262,144)
A6
A5
(5)
A5
A0
10
11
12
13
14
A6
(6)
A4
A1
A2
I/O0
I/O1
I/O2
GND
(7)
A3
A14
17
16
15
Note: This part is compatible with both pin numbering
conventions used by various manufacturers.
WE
OE
CE
Column decoder
Control
circuit
A
7
A
8
A
9
A
A
A
A
10 11 12 13
Selection guide
AS7C256-10
AS7C256-12
AS7C256-15
AS7C256-20
AS7C3256-10
AS7C3256-12
AS7C3256-15
AS7C3256-20
Unit
Maximum address access time
10
12
5
15
6
20
7
ns
Maximum output enable access time
ns
AS7C256
AS7C3256
120
60
4
115
55
4
110
50
4
mA
mA
mA
mA
Maximum operating current
AS7C256
Maximum CMOS standby
current
AS7C3256
2
2
2
1/10/2001
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C256
AS7C3256
®
Functional description
The AS7C(3)256 is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized
as 262,144 words × 16 bits. It is designed for memory applications requiring fast data access at low voltage, including
PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V
operation without sacrificing performance or operating margins.
The device enters standby mode when CE is high. CMOS standby mode consumes ≤3.6 mW. Normal operation offers 75% power
reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions
of the AS7C256 offer 2.0V data retention.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 5/6/7/9 ns are
ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank
memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.3 0.3V supply. The
AS7C(3)256A is packaged in high volume industry standard packages.
Absolute maximum ratings
Parameter
Device
Symbol
Vt1
Min
–0.5
–0.5
–0.5
–
Max
Unit
V
AS7C256
AS7C3256
+7.0
+5.0
VCC + 0.5
1.0
Voltage on VCC relative to GND
Vt1
V
Voltage on any pin relative to GND
Power dissipation
Vt2
V
PD
W
oC
oC
mA
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
Tstg
–65
–55
–
+150
+125
20
Tbias
IOUT
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
WE
X
OE
X
Data
Mode
High Z
High Z
DOUT
DIN
Standby (ISB, ISB1)
H
H
L
H
L
Output disable (ICC)
Read (ICC
Write (ICC)
L
)
L
X
Key: X = Don’t care, L = Low, H = High
1/10/2001
Alliance Semiconductor
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AS7C256
AS7C3256
®
Recommended operating conditions
Parameter
Device
Symbol
Min
4.5
3.0
2.2
2.0
-0.5*
0
Typical
Max
5.5
Unit
V
AS7C256 VCC
5.0
3.3
–
Supply voltage
AS7C3256 VCC
AS7C256 VIH
3.6
V
VCC+0.5
VCC+0.5
0.8
V
Input voltage
AS7C3256 VIH
–
V
*
—
VIL
–
V
commercial TA
industrial TA
–
70
oC
oC
Ambient operating temperature
–40
–
85
*
V
min = –2.0V for pulse width less than t /2.
RC
IL
DC operating characteristics (over the operating range)1
-10
-12
-15
-20
Parameter
Sym Test conditions
Device
Min Max Min Max Min Max Min Max Unit
Input leakage
current
V
CC = Max,
|ILI|
|ILO
–
–
1
1
–
–
1
1
–
–
1
1
µA
µA
Vin = GND to VCC
Output leakage
current
VCC = Max,
|
VOUT = GND to VCC
Operating
power supply ICC
current
AS7C256
–
–
120
60
–
–
115
55
–
–
110
50
VCC = Max, CE ≤ VIL
f = fMax, IOUT = 0mA
mA
mA
mA
AS7C3256
AS7C256
AS7C3256
AS7C256
–
–
–
40
20
–
–
–
35
20
–
–
–
30
20
VCC = Max, CE ≤ VIL
f = fMax, IOUT = 0mA
ISB
Standby power
supply current
4.0
4.0
4.0
VCC = Max, CE > VCC–0.2V
ISB1
V
V
IN < GND + 0.2V or
IN > VCC–0.2V, f = 0
AS7C3256
–
2.0
–
2.0
–
2.0
VOL IOL = 8 mA, VCC = Min
VOH IOH = –4 mA, VCC = Min
–
0.4
–
–
0.4
–
–
0.4
–
V
V
Output voltage
2.4
2.4
2.4
Capacitance (f = 1MHz, T = room temperature, V = NOMINAL)2
a
CC
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
I/O capacitance
CIN
Vin = 0V
5
7
pF
pF
A, CE
I/O
, WE, OE
CI/O
Vin = Vout = 0V
1/10/2001
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AS7C256
AS7C3256
®
Read cycle (over the operating range)3,9
-10
-12
-15
-20
Parameter
Symbol Min Max Min Max Min Max Min Max
Unit Notes
ns
Read cycle time
tRC
12
–
–
12
12
5
15
–
–
15
15
6
20
–
–
20
20
7
Address access time
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
tACE
tOE
–
–
–
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE LOW to output in low Z
CE HIGH to output in high Z
OE LOW to output in low Z
OE HIGH to output in high Z
Power up time
–
–
–
tOH
tCLZ
tCHZ
tOLZ
tOHZ
tPU
3
3
–
–
3
3
–
–
3
3
–
–
5
–
–
–
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
3
4
5
0
–
–
0
–
–
0
–
–
3
4
5
0
–
–
0
–
–
0
–
–
Power down time
tPD
12
15
20
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
Read waveform 1 (address controlled)3,6,7,9
t
RC
Address
tAA
t
OH
D
Data valid
out
Read waveform 2 (CE controlled)3,6,8,9
1
t
RC
C E
O E
t
OE
t
t
t
OLZ
OHZ
CHZ
t
ACE
D
out
Data valid
t
CLZ
t
PD
I
I
CC
SB
t
PU
Supply
current
50%
50%
1/10/2001
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AS7C256
AS7C3256
®
Write cycle (over the operating range)11
-10
-12
-15
-20
Parameter
Symbol
tWC
tCW
tAW
tAS
Min Max Min Max Min Max
Unit
Notes
Write cycle time
12
8
8
0
8
0
6
0
–
–
–
–
–
–
–
–
–
5
–
15
10
10
0
–
–
–
–
–
–
–
–
5
–
20
12
12
0
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip enable to write end
Address setup to write end
Address setup time
Write pulse width
tWP
tAH
tDW
tDH
tWZ
tOW
9
12
0
Address hold from end of write
Data valid to write end
Data hold time
0
8
10
0
0
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
Shaded areas contain advance information.
–
–
3
3
3
Write waveform 1 (WE controlled)10,11
t
WC
t
t
t
AW
AH
Address
t
WP
W E
t
AS
t
DW
DH
D
Data valid
in
t
t
WZ
OW
D
out
Write waveform 2 (CE controlled)10,11
t
WC
t
t
AH
AW
Address
t
t
CW
AS
C E
t
WP
W E
t
t
t
WZ
DW
DH
D
Data valid
in
D
out
1/10/2001
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AS7C256
AS7C3256
®
Data retention characteristics (over the operating range)13
Parameter
Symbol
Test conditions
Min
2.0
–
Max
–
Unit
V
VCC for data retention
VDR
VCC = 2.0V
500
–
µA
µA
ns
Data retention current
ICCDR
CE ≥ VCC–0.2V
–
VIN ≥ VCC–0.2V
or
VIN ≤ 0.2V
Chip enable to data retention time tCDR
0
–
Operation recovery time
Input leakage current
tR
tRC
–
–
ns
| ILI |
1
µA
Data retention waveform
Data retention mode
V
VCC
VCC
V
DR ≥ 2.0V
CC
tCDR
t
R
V
DR
V
V
C E
IH
IH
AC test conditions
- Output load: see Figure B or Figure C.
Thevenin equivalent
168
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Ω
D
+1.72V (5V and 3.3V)
out
+3.3V
+5V
320
Ω
480
Ω
D
D
out
out
+3.0V
90%
10%
90%
10%
350
Ω
C(14)
GND
255
Ω
C(14)
GND
2 ns
Figure A: Input pulse
GND
Figure C: Output load
Figure B: Output load
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CE is required to meet I specification.
CC CC SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, C.
These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 2V data retention applies to the commercial operating range only.
14 C=30pF, except on High Z and Low Z parameters, where C=5pF.
1/10/2001
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AS7C256
AS7C3256
®
Typical DC and AC characteristics
Normalized supply current ICC, ISB
vs. supply voltage VCC
1.4
Normalized supply current ICC, ISB
Normalized supply current ISB1
vs. ambient temperature T
vs. ambient temperature Ta
a
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
625
25
ICC
VCC = VCC(NOMINAL)
ICC
1.0
0.8
0.6
5
1
ISB
ISB
0.4
0.2
0.04
0.2
0.0
MIN
NOMINAL
–55
–10
35
80
-55
-10
35
80
MAX
125
125
Supply voltage (V)
Ambient temperature (°C)
Ambient temperature (°C)
Normalized access time tAA
vs. supply voltage VCC
Normalized access time tAA
vs. ambient temperature Ta
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
1.5
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.3
1.2
1.1
1.0
0.9
0.8
Ta = 25°C
VCC = VCC(NOMINAL)
VCC = VCC(NOMINAL)
Ta = 25°C
MIN
NOMINAL
–55
–10
35
80
0
25
50
75
MAX
125
100
Supply voltage (V)
Ambient temperature (°C)
Cycle frequency (MHz)
Output source current IOH
vs. output voltage VOH
Output sink current IOL
vs. output voltage VOL
Typical access time change ∆tAA
vs. output capacitive loading
140
120
100
80
140
120
100
80
35
30
25
20
15
10
5
VCC = VCC(NOMINAL)PL
Ta = 25°C
VCC = VCC(NOMINAL)
VCC = VCC(NOMINAL)
T = 25°C
a
60
60
40
40
20
20
0
0
0
0
0
0
250
500
750
VCC
VCC
1000
Output voltage (V)
Output voltage (V)
Capacitance (pF)
1/10/2001
Alliance Semiconductor
P. 7 of 9
AS7C256
AS7C3256
®
Package diagrams
28-pin PDIP
Min
Max
0.175
-
A
A1
B
-
A
D
0.010
0.058
0.016
0.008
-
B
S
0.064
0.022
0.014
1.400
0.320
0.298
b
c
E
E1
α
c
L
D
E
0.295
0.278
A1
eA
e
b
E1
e
Seating
Plane
0.100 BSC
Pin 1
eA
L
0.330
0.120
0°
0.370
0.140
15°
α
S
-
0.055
D
e
B
b
28-pin SOJ
Min
-
Max
0.140
-
A
A
A1
A2
B
A1
E1 E2
0.025
0.095
Seating
Plane
0.105
Pin 1
0.028 TYP
c
0.018 TYP
0.010 TYP
b
c
A2
E
-
0.730
0.285
0.305
0.347
D
E
E1
E2
e
0.245
0.295
0.327
b
e
0.050 BSC
c
A2
A
A1
L
28-pin
8×13.4
Min
–
Max
1.20
pin 1(22)
pin 1(7)
pin 8(21)
pin 5(8)
D
Hd
A
0.10
0.95
0.15
0.20
1.05
0.25
A1
A2
b
c
D
e
α
0.10
0.20
11.60
11.80
28-pin
0.55 nominal
Note: This part is compatible with both pin numbering
conventions used by various manufacturers.
E
1/10/2001
Alliance Semiconductor
P. 8 of 9
AS7C256
AS7C3256
®
Ordering information
Package / Access time
Volt/Temp
10 ns
12 ns
15 ns
20 ns
5V commercial
3.3V commercial
5V commercial
3.3V commercial
5V industrial
AS7C256-10PC
AS7C3256-10PC
AS7C256-10JC
AS7C3256-10JC
AS7C256-10JI
AS7C3256-10JI
AS7C256-10TC
AS7C3256-10TC
AS7C256-10TI
AS7C3256-10TI
AS7C256-12PC
AS7C3256-12PC
AS7C256-12JC
AS7C3256-12JC
AS7C256-12JI
AS7C256-15PC
AS7C3256-15PC
AS7C256-15JC
AS7C3256-15JC
AS7C256-15JI
AS7C3256-15JI
AS7C256-15TC
AS7C3256-15TC
AS7C256-15TI
AS7C3256-15TI
AS7C256-20PC
Plastic DIP, 300 mil
AS7C3256-20PC
AS7C256-20JC
AS7C3256-20JC
AS7C256-20JI
AS7C3256-20JI
AS7C256-20TC
AS7C3256-20TC
AS7C256-20TI
AS7C3256-20TI
Plastic SOJ, 300 mil
3.3V industrial
5V commercial
3.3V commercial
5V industrial
AS7C3256-12JI
AS7C256-12TC
AS7C3256-12TC
AS7C256-12TI
AS7C3256-12TI
TSOP 8x13.4
3.3V industrial
Part numbering system
AS7C
3
256
–XX
X
C or I
Commercial temperature range:
0 oC to 70 0C
Package: J = SOJ 300 mil
SRAM prefix
3 = 3.3V supply Device number Access time
T
= TSOP 8x13.4
Industrial temperature range:
-40C to 85C
1/10/2001
Alliance Semiconductor
P. 9 of 9
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names
may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors
that may appear in this document. The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without
notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information
for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the
application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a par-
ticular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alli-
ance products are made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works
rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or
failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and
agrees to indemnify Alliance against all claims arising from such use.
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