AS7C32098A-10TI [ALSC]
3.3 V 128K x 16 CMOS SRAM; 3.3 V 128K ×16的CMOS SRAM
| 型号： | AS7C32098A-10TI |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3 V 128K x 16 CMOS SRAM |
| 文件： | 总10页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS7C32098A
February 2005
Preliminary Information
®
3.3 V 128K × 16 CMOS SRAM
Features
• Industrial and commercial temperature
• Organization: 131,072 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
- 28.8 mW /max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Low power consumption: STANDBY
Logic block diagram
Pin arrangement for TSOP 2
A0
A1
A2
A3
A4
CE
I/O1
I/O2
I/O3
I/O4
1
2
3
4
5
6
44
43
42
41
A16
A15
A14
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
A0
A1
A2
V
CC
1024 × 128 × 16
A3
GND
A4
40
39
38
37
36
35
34
33
32
31
30
Array
(2,097,152)
A6
A7
A8
7
A12
A13
8
9
I/O1–I/O8
I/O9–I/O16
I/O
buffer
Control circuit
10
V
11
12
13
14
15
CC
Column decoder
WE
GND
I/O5
I/O6
I/O7
V
CC
I/O12
I/O11
I/O10
UB
OE
LB
CE
I/O8
WE
A5
A6
A7
A8
A9
16
17
18
19
20
21
22
29
I/O9
NC
28
27
26
25
24
23
A13
A12
A11
A10
NC
Selection guide
–10
10
4
–12
–15
15
6
–20
20
7
Unit
Maximum address access time
12
5
ns
ns
Maximum output enable access time
Industrial
180
170
8
160
150
8
140
130
8
110
100
8
mA
mA
mA
Maximum operating current
Commercial
Maximum CMOS standby current
2/24/05, v. 1.0
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C32098A
®
Functional description
The AS7C32098A is a high-performance CMOS 2,097,152-bit Static Random Access Memory (SRAM) device organized as
131,072 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 4/5/6/7 ns are
AA RC WC
OE
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in
CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input
pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C32098A) supply. The device is
available in the JEDEC standard TSOP 2 package.
Absolute maximum ratings
Parameter
Voltage on VCC relative to GND
Voltage on any pin relative to GND
Power dissipation
Symbol
Vt1
Min
–0.50
–0.50
–
Max
+5.0
Unit
V
Vt2
VCC +0.50
1.5
V
PD
W
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
Tstg
–65
–55
–
+150
°C
°C
mA
Tbias
IOUT
+125
±20
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
WE
X
OE
X
LB
X
UB
X
I/O1–I/O8
I/O9–I/O16
Mode
High Z
High Z
Standby (I , I
)
SB SB1
L
H
H
X
X
High Z
High Z
High Z
Output disable (I
)
CC
L
X
X
H
H
L
H
D
OUT
L
L
H
L
L
H
L
High Z
D
D
Read (I
)
CC
OUT
OUT
L
L
D
OUT
L
H
D
High Z
IN
X
H
L
High Z
D
D
IN
IN
L
L
D
Write (I
)
CC
IN
Key: X = Don’t care, L = Low, H = High.
2/24/05,v. 1.0
Alliance Semiconductor
P. 2 of 10
AS7C32098A
®
Recommended operating conditions
Parameter
Symbol
Min Typical
Max
Unit
V
Supply voltage
V
(10/12/15/20)
3.0
2.0
–0.5
0
3.3
–
3.6
CC
**
V
V
+ 0.5
CC
V
IH
Input voltage
*
V
–
0.8
70
85
V
IL
commercial
Ambient operating temperature
industrial
T
–
°C
°C
A
T
–40
–
A
*
**
VIL min = –1.0V for pulse width less than 5ns.
V
IH max = VCC + 2.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)1
–10
–12
–15
–20
Parameter Symbol
Test conditions
= Max
Min Max Min Max Min Max Min Max Unit
Input leakage
V
CC
|I |
–
1
–
1
–
1
–
1
µA
LI
current
V
= GND to V
IN CC
V
= Max
CC
Output leakage
current
CE = V or OE = V
IH IH
|I
|
–
1
–
1
–
1
–
1
µA
LO
or WE = V
IL
V
= GND to V
I/O
CC
Operating
power supply
current
Industrial
Commercial
–
-
180
170
–
-
160
150
–
-
140
130
–
-
110 mA
100 mA
V
= Max
CC
I
CC
CE ≤ V , f = f
I
= 0mA
IL
max OUT
V
= Max
CC
I
–
–
60
8
–
–
60
8
–
–
60
8
–
–
60 mA
SB
CE ≥ V , f = Max
IH
Standby power
supply current
V
= Max
CC
CE ≥ V – 0.2V, V ≥ V – 0.2V or
I
CC
IN
CC
8
mA
SB1
V
≤ 0.2V, f = 0
IN
V
I
= 8 mA, V = Min
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
OL
OL
CC
Output voltage
V
I
= –4 mA, V = Min
2.4
2.4
2.4
2.4
OH
OH
CC
Capacitance (f = 1MHz, T = 25° C, V = NOMINAL)4
a
CC
Signals
Parameter
Input capacitance
I/O capacitance
Symbol
Test conditions
= 0V
Max
Unit
C
A, CE, WE, OE, UB, LB
I/O
V
6
8
pF
pF
IN
IN
C
V
= V
= 0V
OUT
I/O
IN
2/24/05,v. 1.0
Alliance Semiconductor
P. 3 of 10
AS7C32098A
®
Read cycle (over the operating range)2,8
–10
–12
–15
–20
Parameter
Read cycle time
Symbol
Min Max Min Max Min Max Min Max Unit Notes
t
10
–
–
–
3
3
–
0
–
–
0
–
0
–
–
10
10
4
12
–
–
–
3
3
–
0
–
–
0
–
0
–
–
12
12
5
15
–
–
–
3
3
–
0
–
–
0
–
0
–
–
15
15
6
20
–
–
–
3
3
–
0
–
–
0
–
0
–
–
20
20
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
t
Address access time
AA
t
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE High to output in high Z
OE Low to output in low Z
OE High to output in high Z
LB, UB access time
ACE
t
OE
t
–
–
–
–
4
OH
t
–
–
–
–
3,4
3,4
3,4
3,4
CLZ
t
5
6
7
9
CHZ
t
–
–
–
–
OLZ
t
5
6
7
9
OHZ
t
5
6
7
8
BA
t
–
–
–
–
LB, UB Low to output in low Z
LB, UB High to output in high Z
Power up time
BLZ
t
5
6
7
9
BHZ
t
–
–
–
–
4
4
PU
t
10
12
15
20
Power down time
PD
Key to switching waveforms
Rising input
Falling input
tRC
Undefined/don’t care
Read waveform 1 (address controlled)5,6,8
Address
tAA
tOH
Previous data valid
tOH
DataOUT
Data valid
2/24/05,v. 1.0
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AS7C32098A
®
Read waveform 2 (CE, OE, UB, LB controlled)5,7,8
tRC
Address
tAA
OE
tOHZ
tOE
tOH
tOLZ
CE
tACE
tCLZ
tCHZ
LB, UB
tBA
tBHZ
tBLZ
DataOUT
Data valid
Write cycle (over the operating range)9
–10
–12
–15
–20
Parameter
Write cycle time
Symbol Min Max Min Max Min Max Min Max Unit Note
t
t
t
10
7
–
–
–
–
–
–
–
–
–
–
5
–
–
12
8
–
–
–
–
–
–
–
–
15
10
10
0
–
–
–
–
–
–
–
–
–
–
7
–
–
20
12
12
0
–
–
–
–
–
–
–
–
–
–
9
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AW
Chip enable (CE) to write end
Address setup to write end
Address setup time
7
8
t
0
0
AS
t
t
7
8
10
15
0
12
20
0
Write pulse width (OE = High)
Write pulse width (OE = Low)
Write recovery time
WP1
WP2
10
0
12
0
t
WR
t
0
0
0
0
Address hold from end of write
Data valid to write end
AH
t
5
6
7
9
DW
t
0
0
–
6
–
–
0
0
3,4
3,4
3,4
3,4
Data hold time
DH
WZ
t
t
0
0
0
0
Write enable to output in High-Z
Output active from write end
Byte enable Low to write end
3
3
3
3
OW
t
7
8
10
12
BW
2/24/05,v. 1.0
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AS7C32098A
®
Write waveform 1(WE controlled)9
tWC
tAH
tWR
Address
tCW
tBW
tAW
CE
LB, UB
tAS
tWP
WE
tDW
tDH
Data valid
DataIN
tWZ
tOW
DataOUT
Data undefined
High Z
Write waveform 2 (CE controlled)9
tWC
tAH
tWR
Address
tAS
tCW
CE
tAW
tBW
LB, UB
WE
tWP
tDW
tDH
Data valid
High Z
DataIN
DataOUT
tCLZ
High Z
tWZ
Data undefined
tOW
2/24/05,v. 1.0
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AS7C32098A
®
Write waveform 3 9
tWC
tAH
tWR
Address
CE
tAS
tCW
tAW
tBW
LB, UB
WE
tWP
tDW
Data valid
tDH
DataIN
tWZ
Data undefined
DataOUT
High Z
High Z
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+3.3V
320
Ω
+3.0V
DOUT
350
168Ω
90%
10%
90%
10%
Thevenin equivalent:
+1.728V
DOUT
Ω
C10
GND
2 ns
GND
Figure B: 3.3V Output load
Figure A: Input pulse
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
For test conditions, see AC Test Conditions, Figures A and B.
t
CLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
10 C=30pF, except on High Z and Low Z parameters, where C=5pF.
2/24/05,v. 1.0
Alliance Semiconductor
P. 7 of 10
AS7C32098A
®
Package dimensions
c
44 434241403938373635343332313029282726252423
44-pin TSOP 2
Min (mm) Max (mm)
A
1.2
He
e
44-pin TSOP 2
A
0.05
0.95
0.3
0.15
1.05
1
A
2
b
c
0.45
1 2 3 4 5 6 7 8 9 101112131415161718 19202122
d
0.21
0.12
18.31
10.06
11.68
d
e
18.52
10.26
11.94
H
e
l
A2
A
E
l
0.80 (typical)
0–5°
A1
0.40
0.60
b
E
2/24/05,v. 1.0
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P. 8 of 10
AS7C32098A
®
Ordering Codes
Package
Temperature
10 ns
12 ns
15 ns
20 ns
Commercial
Industrial
AS7C32098A-10TC AS7C32098A-12TC AS7C32098A-15TC AS7C32098A-20TC
AS7C32098A-10TI AS7C32098A-12TI AS7C32098A-15TI AS7C32098A-20TI
TSOP 2
Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts. (EX: AS7C32098A - 10TCN)
Part numbering system
AS7C
X
2098A
–XX
T
X
X
Temperature ranges:
C: Commercial, 0°C to 70°C
I: Industrial, –40°C to 85°C
SRAM
prefix
Voltage:
Device Access
Package:
T: TSOP 2
N = Lead Free Parts
3 - 3.3V CMOS number time
2/24/05,v. 1.0
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AS7C32098A
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: AS7C32098A
Document Version: v. 1.0
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
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