UCN5910A [ALLEGRO]
HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS; HIGH- VOLTAGE采用BiMOS III 10位串行输入，锁存驱动程序
| 型号： | UCN5910A |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS |
| 文件： | 总8页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT, LATCHED DRIVERS
The UCN5910x combines a 10-bit CMOS shift register and accompanying
data latches, control circuitry, high-voltage bipolar sourcing outputs with
DMOS active pull-downs. Designed primarily to drive ink-jet and piezoelec-
tric printers, large flat-panel vacuum-fluorescent or ac plasma displays, the
140 V or 150 V and ±50 mA output ratings also allow these devices to be used
in many other peripheral power driver applications. The lower-cost (suffix
“-2”) devices are identical to the basic devices except for output voltage rating.
20
19
18
17
16
15
14
13
OUT
OUT
OUT
1
2
3
OUT
OUT
8
7
6
9
10
LOAD
SUPPLY (6-10)
V
BB
LATCHES
REGISTER
SERIAL
DATA OUT
CLOCK
4
CLK
SUB
LOGIC
GROUND
SERIAL
DATA IN
The CMOS shift register and latches allow direct interfacing with micro-
processor-based systems. With a 5 V logic supply, serial-data input rates are
typically over 5 MHz, with significantly higher speeds obtainable at 12 V.
Use with TTL may require appropriate pull-up resistors to ensure an input logic
high.
5
6
REGISTER
LATCHES
LOGIC
SUPPLY
V
BLANKING
BLNK
DD
LOAD
SUPPLY (1-5)
V
STROBE
7
8
ST
BB
POWER
GROUND
OUT
1
2
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices for up to 60-volt operation are
available in 10, 12, 20, and 32-bit configurations.
12 OUT
11 OUT
OUT
5
9
OUT
10
4
3
Dwg. PP-029-14
The UCN5910A/LW output source drivers are npn Darlingtons capable of
sourcing at least 40 mA. The DMOS active pull-downs are capable of sinking
at least 30 mA. For inter-digit blanking, all of the output drivers can be
disabled and the DMOS sink drivers turned ON by the BLANKING input high.
Note that the dual in-line package (designator
‘A’) and small-outline IC package (designator
‘LW’) are electrically identical and share a
common terminal number assignment.
The UCN5910A and UCN5910A-2 are furnished in a 20-pin dual in-line
plastic package. The surface-mount UCN5910LW and UCN5910LW-2 are
furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing
leads. Copper lead frames, reduced supply current requirements, and lower
output saturation voltages allow all devices to be operated at ±20 mA from all
outputs (50% duty cycle), at ambient temperatures up to +30°C, or at ±15 mA
to +55°C.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ................ 15 V
Driver Supply Voltage, VBB
UCN5910A/LW ......................... 150 V
Suffix “-2” .................................. 140 V
Continuous Output Current Range,
IOUT ....................... -30 mA to +40 mA
Input Voltage Range,
VIN .................... -0.3 V to VDD + 0.3 V
Package Power Dissipation, PD . See Graph
Operating Temperature Range,
FEATURES
■ High-Speed Source Drivers
■ 140 V (suffix “-2”) or 150 V
Minimum Output Breakdown
■ Improved Replacements
for TL4810B
■ Low Output Saturation Voltages
■ Low-Power CMOS Logic and Latches
■ To 3.3 MHz Data Input Rate
■ Active DMOS Pull-Downs
TA ............................... -20°C to +85°C
Storage Temperature Range,
PRELIMINARY INFORMATION
TS .............................. -55°C to +150°C
(Subject to change without notice)
January 18, 2000
Caution: CMOS devices have input static
protectionbutaresusceptibletodamagewhen
exposed to extremely high static electrical
charges.
Always order by complete part number, e.g., UCN5910A-2 .
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
V
DD
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
STROBE
BLANKING
MOS
BIPOLAR
LOAD
SUPPLY
V
BB
GROUND
OUT OUT OUT
OUT
N
Dwg. FP-013-1
1
2
3
TYPICAL INPUT CIRCUIT
V
DD
IN
2.5
2.0
1.5
1.0
0.5
0
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
V BB
OUTN
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. No. A-14,219
Dwg. GS-004A
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1984, 1999, Allegro MicroSystems, Inc.
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 150 V (basic devices) or
140 V (suffix “-2”) unless otherwise noted.
Limits @ VDD
=
5
V
Limits= 12@V
V
DD
Characteristic
Symbol
ICEX
Test Conditions
VOUT = 0 V, TA = +70°C
Basic, IOUT = -40 mA
Suffix “-2”, IOUT = -40 mA
IOUT = 5 mA
Mln. Typ. Max. Min. Typ. Max. Units
Output Leakage Current
Output Voltage
–
-5.0 -15
–
-5.0 -15
µA
V
VOUT(1)
145 148
–
–
145 148
–
–
135
–
–
2.5
5.0
–
135
–
–
2.0
–
V
VOUT(0)
3.2
–
3.2
–
V
IOUT = 10 mA
–
–
V
IOUT = 30 mA
–
–
–
12
–
25
–
V
Output Pull-Down Current
Input Voltage
IOUT(0)
VOUT = 5 V to VBB
VOUT = 20 V to VBB
10
–
14
–
–
–
mA
mA
V
–
25
10.5
-0.3
–
40
–
–
VIN(1)
VIN(0)
IIN(1)
3.5
-0.3
–
–
5.3
+0.8
12.3
+0.8
–
–
V
Input Current
VIN = VDD
0.05 0.5
0.05 1.0
µA
µA
V
IIN(0)
VIN = 0.8 V
-0.3
4.5
–
–
-0.8
–
-0.3
–
-0.8
–
Serial Data Output Voltage VOUT(1)
VOUT(0)
IOUT = -200 µA
IOUT = 200 µA
5.0
11.7 12
200 250
5.0
–
5.0
–
200 250
mV
MHz
µA
µA
Maximum Clock Frequency
Supply Current
fclk
IDD(1)
IDD(0)
IBB(1)
IBB(0)
tPHL
tPLH
tf
3.3
–
–
–
–
All Outputs High
All Outputs Low
320 450
320 450
650 800
650 800
–
–
Outputs
High,
No
Load
–
0.6 1.75
–
0.91.75
mA
Outputs Low
–
10
100
–
10
50%
100
–
µA
Blanking to Output Delay
CL
CL
=
30
pF,
pF,
50%
50%
to
to
0.µ7s 0.9–
=
30
50%
1.5
–
–
–
0.91.3
0.6
– µs0.35 0.6
Output Fall Time
Output Rise Time
CL = 30 pF, 90% to 10%
CL = 30 pF, 10% to 90%
–
1.3
1.2
0.7
1.2
µs
µs
tr
–
1.5
1.0
Negative current is defined as coming out of (sourcing) the specified device terminal.
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
CLOCK
A
D
B
DATA IN
STROBE
BLANKING
OUTN
E
F
C
G
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
Dwg. No. A-12,649A
TIMING CONDITIONS
(TA = +25°C, VDD = 12 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ........................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................... 75 ns
C. Minimum Data Pulse Width ............................................................. 150 ns
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON. The information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
D. Minimum Clock Pulse Width ........................................................... 100 ns
E. Minimum Time Between Clock Activation and Strobe .................... 300 ns
F. Minimum Strobe Pulse Width .......................................................... 100 ns
G. Typical Time Between Strobe Activation and
Output Transition ............................................................................. 750 ns
TRUTH TABLE
Serial
Data Clock
Input Input I
Shift Register Contents
Serial
Data Strobe
Output Input
Latch Contents
Output Contents
... I
I
I
...
I
I
I
I
I
...
I
I
Blanking
I
I
I
I
N-1 N
1
2
3
N-1
N
1
2
3
N-1
N
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
...
...
...
...
...
R
R
R
X
R
R
R
R
X
1
1
2
2
2
3
N-2 N-1
N-1
N-1
N
R
N-2 N-1
X
R
X
R
1
N-1
N-1
N
N
X
L
R
R
R
...
...
...
R
R
1
2
3
N-1
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
L
P
L
P
L
... P
... L
P
L
1
2
3
N
1
2
3
N-1
N
1
2
3
N-1
N
X
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5910A & UCN5910A-2
Dimensions in Inches
(controlling dimensions)
0.014
0.008
20
11
0.430
MAX
0.280
0.240
0.300
BSC
1
10
0.100
0.070
0.045
0.005
BSC
MIN
1.060
0.980
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-20 in
Dimensions in Millimeters
(for reference only)
0.355
0.204
20
11
10.92
MAX
7.11
6.10
7.62
BSC
1
10
2.54
1.77
1.15
0.13
BSC
MIN
26.92
24.89
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-20 mm
NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5910LW & UCN5910LW-2
Dimensions in Inches
(for reference only)
20
11
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
BSC
0° TO 8°
0.5118
0.4961
0.0926
0.1043
Dwg. MA-008-20 in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
20
11
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
13.00
12.60
2.65
2.35
Dwg. MA-008-20 mm
0.10 MIN.
NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
This page intentionally left blank
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
BiMOS II (Series 5800), BiMOS III (Series 5900),
& DABiC IV (Series 6800) INTELLIGENT POWER
INTERFACE DRIVERS
†
Function
Output Ratings*
Part Number
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers)
8-Bit
8-Bit
8-Bit
-120 mA
350 mA
350 mA
350 mA
350 mA
75 mA
50 V‡
50 V
80 V
50 V‡
80 V‡
17 V
5895
5821
5822
5841
5842
6275
8-Bit
8-Bit (constant-current LED driver)
9-Bit
1.6 A
50 V
5829
10-Bit (active pull-downs)
10-Bit (active pull-downs)
10-Bit (active pull-downs)
-25 mA
-40 mA
-40 mA
60 V
140 V
150 V
5810-F and 6809/10
5910-2
5910
12-Bit (active pull-downs)
-25 mA
75 mA
-25 mA
60 V
17 V
60 V
5811 and 6811
6276
16-Bit (constant-current LED driver)
20-Bit (active pull-downs)
5812-F and 6812
32-Bit (active pull-downs)
32-Bit
32-Bit (saturated drivers)
-25 mA
100 mA
100 mA
60 V
30 V
40 V
5818-F and 6818
5833
5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V‡
5800
8-Bit
8-Bit
-25 mA
350 mA
60 V
50 V‡
5815
5801
SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver
Addressable 28-Line Decoder/Driver
1.25 A
450 mA
50 V‡
30 V
5804
6817
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
†
‡
Complete part number includes additional characters to indicate operating temperature range and package style.
Internal transient-suppression diodes included for inductive-load protection.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such
departures from the detail specifications as may be required to permit improvements in
the design of its products.
The information included herein is believed to be accurate and reliable. However,
Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringe-
ments of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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