UCN5810LWF [ALLEGRO]
BiMOS II 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS; 采用BiMOS II 10位串行输入，具有ACTIVE- DMOS下拉功能锁存源极驱动器
| 型号： | UCN5810LWF |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | BiMOS II 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS |
| 文件： | 总8页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5810-F
BiMOS II 10-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
The UCN5810AF, UCN5810EPF, and UCN5810LWF combine a 10-bit
CMOS shift register and accompanying data latches, control circuitry, bipolar
sourcing outputs with DMOS active pull-downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow
these devices to be used in many other peripheral power driver applications.
The UCN5810AF/EPF/LWF feature reduced supply requirements (active
DMOS pull-downs) and lower saturation voltages when compared with the
original UCN5810A.
UCN5810AF
18 OUT
17 OUT
1
2
3
4
OUT
OUT
OUT
9
8
7
6
10
SERIAL
DATA OUT
16
15
14
LATCHES
LOAD
SUPPLY
CLK
V
BB
CLOCK
REGISTER
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V supply, they will operate to at
least 3.3 MHz. At 12 V, higher speeds are possible. Use with TTL may
require appropriate pull-up resistors to ensure an input logic high.
SERIAL
DATA IN
GROUND
5
6
REGISTER
LATCHES
LOGIC
SUPPLY
V
BLNK 13 BLANKING
DD
12 OUT
7
8
ST
STROBE
1
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices are available as the
UCN5811A (12 bits), UCN5812AF/EPF (20 bits), and UCN5818AF/EPF (32
bits).
11 OUT
OUT
5
2
9
10 OUT
OUT
4
3
Dwg. PP-029
The UCN5810AF/EPF/LWF output source drivers are NPN Darlingtons
capable of sourcing up to 40 mA. The DMOS active pull-downs are capable
of sinking up to 15 mA. For inter-digit blanking, all of the output drivers can
be disabled and the DMOS sink drivers turned on by the BLANKING input
high.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD .....................15 V
Driver Supply Voltage, VBB ....................60 V
Continuous Output Current Range,
The UCN5810AF is furnished in an 18-pin dual in-line plastic package.
The UCN5810EPF is furnished in a 20-lead plastic chip carrier. The
UCN5810LWF is furnished in a wide-body, small-outline plastic package
(SOIC) with gull-wing leads. Copper lead frames, reduced supply current
requirements, and lower output saturation voltages allow all devices to source
25 mA from all outputs continuously, over the entire operating temperature
range. All devices are also available for operation between -40°C and +85°C.
To order, change the prefix from ‘UCN’ to ‘UCQ’.
I
OUT .......................... -40 mA to +15 mA
Input Voltage Range,
V
IN ........................ -0.3 V to VDD + 0.3 V
Package Power Dissipation, PD
(UCN5810AF) ........................... 2.27 W*
(UCN5810EPF) ........................ 1.78 W*
(UCN5810LWF) ........................ 1.56 W*
Operating Temperature Range,
TA .................................. -20°C to +85°C
Storage Temperature Range,
TS ................................ -55°C to +150°C
FEATURES
*Derate linearly to 0 W at +150°C.
I High-Speed Source Drivers I Low Output Saturation Voltages
Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
I 60 V Minimum
I Low-Power CMOS Logic
and Latches
Output Breakdown
I Improved Replacements
for TL4810B
I To 3.3 MHz Data Input Rate
I Active DMOS Pull-Downs
Note that the UCN5810AF (dual in-line package)
and UCN5810LWF (small-outline IC package) are
electrically identical and share a common pin
number assignment.
Always order by complete part number, e.g., UCN5810AF .
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5810EPF
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
V
DD
CLOCK
SERIAL
DATA OUT
4
18
17
16
15
14
CLOCK
NC
CLK
SERIAL
DATA IN
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
LATCHES
REGISTER
LOAD
SUPPLY
V
5
6
7
BB
STROBE
NC
GROUND
REGISTER
LATCHES
LOGIC
SUPPLY
SERIAL
DATA IN
V
DD
BLANKING
BLNK
MOS
BLANKING
Dwg. PP-059
8
ST
STROBE
BIPOLAR
LOAD
SUPPLY
V
BB
GROUND
OUT OUT OUT
OUT
N
Dwg. FP-013-1
1
2
3
UCN5810LWF
OUT
8
1
2
3
4
5
6
18
17 OUT
OUT
9
TYPICAL INPUT CIRCUIT
OUT
7
10
SERIAL
DATA OUT
16
15
14
13
12
OUT
6
LATCHES
V
V
LOAD
SUPPLY
DD
CLOCK
CLK
BB
REGISTER
SERIAL
DATA IN
GROUND
REGISTER
LATCHES
LOGIC
SUPPLY
V
BLANKING
BLNK
DD
7
8
ST
OUT
1
STROBE
IN
11 OUT
OUT
5
2
3
9
OUT
10
OUT
4
Dwg. PP-029-1
Dwg. PP-029-1
Dwg. EP-010-4A
2.5
SUFFIX 'EP', R
= 59°C/W
θJA
TYPICAL OUTPUT DRIVER
2.0
1.5
1.0
0.5
0
SUFFIX 'A', R
= 60°C/W
θJA
V BB
OUTN
SUFFIX 'LW', R
75
= 80°C/W
θJA
25
50
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. GP-024B
Dwg. No. A-14,219
Dwg. GP-024A
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1988, 2000 Allegro MicroSystems, Inc.
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
ELECTRICAL CHARACTERISTICS at T = +25°C, V
= 60 V unless otherwise noted.
A
BB
Limits @ V
= 5 V Limits @ V
= 12 V
DD
DD
Characteristic
Symbol
Test Conditions
Mln. Typ. Max.
Min. Typ. Max.
Units
µA
V
Output Leakage Current
Output Voltage
I
V
= 0 V, T = +70°C
—
58
—
-5.0
58.5
1.0
—
-15
—
—
58
-5.0
58.5
—
-15
—
CEX
OUT
OUT
OUT
OUT
A
V
V
I
I
I
= -25 mA
= 1 mA
= 2 mA
OUT(1)
OUT(0)
1.5
—
—
—
V
—
—
1.0
—
1.5
—
V
Output Pull-Down Current
Input Voltage
I
V
= 5 V to V
BB
2.0
—
3.5
—
—
—
mA
mA
V
OUT(0)
OUT
OUT
V
= 20 V to V
—
8.0
10.5
-0.3
—
13
—
BB
V
V
3.5
-0.3
—
—
5.3
+0.8
100
—
12.3
+0.8
240
-1.0
—
IN(1)
IN(0)
IN(1)
IN(0)
—
—
V
Input Current
I
I
V
V
= V
—
—
µA
µA
V
IN
DD
= 0.8 V
—
-0.05 -0.5
—
-0.1
IN
Serial Data Output Voltage
V
V
I
I
= -200 µA
= 200 µA
4.5
—
4.7
200
—
—
250
—
11.7 11.8
OUT(1)
OUT(0)
OUT
OUT
—
—
—
—
—
—
—
—
—
—
100
—
200
—
mV
MHz
µA
µA
mA
µA
ns
Maximum Clock Frequency
Supply Current
f
I
I
I
I
t
t
t
t
3.3*
—
clk
All Outputs High
All Outputs Low
100
100
0.7
300
300
2.0
100
—
200
200
0.7
500
500
2.0
100
—
DD(1)
DD(0)
BB(1)
BB(0)
PHL
PLH
f
—
Outputs High, No Load
Outputs Low
—
—
10
10
Blanking to Output Delay
C = 30 pF, 50% to 50%
—
2000
1000
1450
650
1000
850
650
700
L
C = 30 pF, 50% to 50%
—
—
—
ns
L
Output Fall Time
Output Rise Time
C = 30 pF, 90% to 10%
—
—
—
ns
L
C = 30 pF, 10% to 90%
—
—
—
ns
r
L
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
CLOCK
A
D
B
DATA IN
STROBE
BLANKING
OUTN
E
F
C
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
G
Dwg. No. A-12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time).......................................................................... 75 ns
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON. The information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion ......................................................................... 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Data Clock
Input Input I
Shift Register Contents
Serial
Data Strobe
Output Input
Latch Contents
Output Contents
... I
I
I
...
I
I
I
I
I
...
I
I
Blanklng
I
I
I
I
N-1 N
1
2
3
N-1
N
1
2
3
N-1
N
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
...
...
...
...
...
R
R
R
X
R
R
R
X
R
R
R
X
1
1
2
2
2
3
N-2
N-2
N-1
N-1
N-1
N
N-1
N-1
N
X
R
X
1
L
R
R
R
...
...
...
R
R
1
2
3
N-1
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
L
P
L
P
L
... P
... L
P
L
1
2
3
N-1
N
N
1
2
3
N-1
N
1
2
3
N-1
N
X
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5810AF
Dimensions in Inches
(controlling dimensions)
0.014
0.008
18
10
0.430
MAX
0.280
0.240
0.300
BSC
1
9
0.100
BSC
0.070
0.045
0.005
MIN
0.920
0.880
0.210
MAX
0.015
MIN
0.150
0.115
0.022
0.014
Dwg. MA-001-18A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
18
10
10.92
MAX
7.11
6.10
7.62
BSC
1
9
2.54
BSC
1.77
1.15
0.13
MIN
23.37
22.35
5.33
MAX
0.39
MIN
3.81
2.93
0.558
0.356
Dwg. MA-001-18A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 21 devices.
www.allegromicro.com
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5810EPF
Dimensions in Inches
(controlling dimensions)
13
9
0.021
0.013
8
4
14
0.169
0.141
0.032
0.026
0.395
0.385
INDEX AREA
0.356
0.350
0.050
BSC
0.169
0.141
18
19 20
1
2
3
0.356
0.350
0.020
MIN
0.395
0.385
0.180
0.165
Dwg. MA-005-20A in
Dimensions in Millimeters
(for reference only)
13
9
0.533
0.331
8
14
4.29
3.58
0.812
10.03
0.661
9.78
INDEX AREA
9.042
8.890
1.27
BSC
4.29
3.58
18
4
19 20
1
2
3
9.042
8.890
0.51
MIN
10.03
9.78
4.57
4.20
Dwg. MA-005-20A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 48 devices or add “TR” to part number for tape and reel.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5810LWF
Dimensions in Inches
(for reference only)
18
10
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
BSC
0° TO 8°
0.4625
0.4469
0.0926
0.1043
Dwg. MA-008-18A in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
10
18
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
11.75
11.35
2.65
2.35
Dwg. MA-008-18A mm
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 41 devices or add “TR” to part number for tape and reel.
www.allegromicro.com
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
相关型号：
UCN5810LWF-1
Vacuum Fluorescent Driver, 10-Segment, BIMOS, PDSO18, 0.300 INCH, PLASTIC, MS-013AB, SOIC-18
ALLEGRO
UCN5811A-1
Latch Based Peripheral Driver, 0.025A, BIMOS, PDIP20, 0.300 INCH, PLASTIC, DIP-20
ALLEGRO
UCN5812AF-1
Vacuum Fluorescent Driver, 20-Segment, BIMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
ALLEGRO
UCN5812EPF-1
Vacuum Fluorescent Driver, 20-Segment, BIMOS, PQCC28, 0.050 INCH PITCH, PLASTIC, LCC-28
ALLEGRO
©2020 ICPDF网 联系我们和版权申明