UCN5800L [ALLEGRO]
BiMOS II LATCHED DRIVERS; 采用BiMOS II锁存驱动程序
| 型号： | UCN5800L |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | BiMOS II LATCHED DRIVERS |
| 文件： | 总12页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5800 AND
5801
BiMOS II LATCHED DRIVERS
The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS
ICs merge high-current, high-voltage outputs with CMOS logic. The
CMOS input section consists of 4 or 8 data (‘D’ type) latches with
associated common CLEAR, STROBE, and OUTPUT ENABLE
circuitry. The power outputs are bipolar npn Darlingtons. This merged
technology provides versatile, flexible interface. These BiMOS power
interface ICs greatly benefit the simplification of computer or micropro-
cessor I/O. The UCN5800A and UCN5800L each contain four latched
drivers; the UCN5801A, UCN5801EP, and UCN5801LW contain eight
latched drivers.
UCN5800L
1
14
UCN5800A
OUTPUT
ENABLE
1
2
3
4
14
13
12
11
CLEAR
STROBE
V
SUPPLY
DD
OUT
1
IN
1
The UCN5800A/L and UCN5801A/EP/LW supersede the original
BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These
second-generation devices are capable of much higher data input
rates and will typically operate at better than 5 MHz with a 5 V logic
supply. Circuit operation at 12 V affords substantial improvement over
the 5 MHz figure.
IN
2
OUT
2
5
6
10
9
OUT
3
IN
3
OUT
4
IN
4
7
8
COMMON
GROUND
The CMOS inputs are compatible with standard CMOS and NMOS
circuits. TTL circuits may mandate the addition of input pull-up resis-
tors. The bipolar Darlington outputs are suitable for directly driving
many peripheral/power loads: relays, lamps, solenoids, small dc
motors, etc.
Dwg. PP-014A
Note the UCN5800A (DIP) and the UCN5800L
(SOIC) are electrically identical and share a
common terminal number assignment.
All devices have open-collector outputs and integral diodes for
inductive load transient suppression. The output transistors are
capable of sinking 500 mA and will withstand at least 50 V in the OFF
state. Because of limitations on package power dissipation, the simul-
taneous operation of all drivers at maximum rated current can only be
accomplished by a reduction in duty cycle. Outputs may be paralleled
for higher load current capability.
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, VCE . . . . . . . . . . . . . . 50 V
Supply Voltage, VDD . . . . . . . . . . . . . . 15 V
Input Voltage Range,
VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V
Continuous Collector Current,
lC . . . . . . . . . . . . . . . . . . . . . . 500 mA
Package Power Dissipation,
PD . . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
The UCN5800A is furnished in a standard 14-pin DIP; the
UCN5800L and UCN5801LW in surface-mountable SOICs; the
UCN5801A in a 22-pin DIP with 0.400" (10.16 mm) row centers; the
UCN5801EP in a 28-lead PLCC.
FEATURES
■ Output Transient Protection
■ To 4.4 MHz Data Input Rate ■ Internal Pull-Down Resistors
TA . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature Range,
■ High-Voltage,
■ Low-Power CMOS Latches
■ Automotive Capable
High-Current Outputs
■ CMOS, NMOS,
TTL Compatible Inputs
TS . . . . . . . . . . . . . . . -55°C to +150°C
Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Always order by complete part number, e.g., UCN5801EP .
5800AND 5801
BiMOS II
LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
SUPPLY
COMMON
V
DD
IN
N
OUT
N
STROBE
CLEAR
GROUND
OUTPUT ENABLE
COMMON MOS CONTROL
TYPICAL MOS LATCH
TYPICAL BIPOLAR DRIVE
Dwg. FP-016-1
2.5
2.0
1.5
1.0
0.5
TYPICAL INPUT CIRCUIT
22-PIN DIP, R
28-LEAD PLCC, R
14-PIN DIP, R
= 50°C/W
θJA
= 55°C/W
= 60°C/W
θJA
θJA
V
DD
24-LEAD SOIC, R
= 68°C/W
IN
θJA
Dwg. EP-010-4A
14-LEAD SOIC, R
= 95°C/W
θJA
0
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. GP-023-1
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 1997, Allegro MicroSystems, Inc.
5800AND 5801
BiMOS II
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at T = +25°C, V
= 5 V (unless otherwise noted).
DD
A
Limits
Characteristic
Symbol
Test Conditions
= 50 V, T = +25°C
Min.
—
Typ. Max.
Units
µA
µA
V
Output Leakage Current
I
V
V
—
—
50
100
1.1
1.3
1.6
1.0
—
CEX
CE
A
= 50 V, T = +70°C
—
CE
A
Collector-Emitter
Saturation Voltage
V
I
I
I
= 100 mA
= 200 mA
= 350 mA, V
—
0.9
1.1
1.3
—
CE(SAT)
C
C
C
—
V
= 7.0 V
—
V
DD
Input Voltage
V
V
—
V
IN(0)
V
V
V
V
V
V
V
V
V
V
V
V
V
= 12 V
= 10 V
10.5
8.5
3.5
50
50
50
—
—
V
IN(1)
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
—
—
V
= 5.0 V (See Note)
= 12 V
—
—
V
Input Resistance
Supply Current
r
200
300
600
1.0
0.9
0.7
—
—
kΩ
kΩ
kΩ
mA
mA
mA
µA
µA
µA
µA
V
IN
= 10 V
—
= 5.0 V
—
I
= 12 V, Outputs Open
= 10 V, Outputs Open
= 5.0 V, Outputs Open
= 12 V, Outputs Open, Inputs = 0 V
= 5.0 V, Outputs Open, Inputs = 0 V
2.0
1.7
1.0
200
100
50
DD(ON)
(Each
Stage)
—
—
I
—
DD(OFF)
(Total)
—
50
Clamp Diode
Leakage Current
I
= 50 V, T = +25°C
—
—
R
R
R
A
= 50 V, T = +70°C
—
—
100
2.0
A
Clamp Diode Forward Voltage
V
I = 350 mA
—
1.7
F
F
NOTE: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic “1”.
25
24
23
22
21
OUT
IN
5
6
7
8
1
1
IN
OUT
OUT
OUT
2
3
2
3
IN
UCN5801EP
(additional pinout diagrams
are on next page)
IN
4
4
OUT
OUT
OUT
9
IN
IN
5
6
7
5
6
20
19
10
11
IN
7
Dwg. PP-037
5800AND 5801
BiMOS II
LATCHED DRIVERS
UCN5801A
CLEAR
F
STROBE
OUTPUT
ENABLE
1
2
3
4
22
21
20
19
18
17
16
CLEAR
A
C
G
B
B
C
C
A
B
OUTPUT
ENABLE
STROBE
V
SUPPLY
DD
G
IN
N
OUT
1
IN
1
E
E
D
IN
2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
2
3
4
5
6
7
8
OUT
N
5
6
IN
3
Dwg. No. A-10,895A
TIMING CONDITIONS
IN
4
(Logic Levels are VDD and Ground)
7
8
IN
5
IN
6
15
A. Minimum Data Active Time Before Strobe Enabled
(Data Set-Up Time) ..........................................................50 ns
IN
7
9
14
13
12
10
IN
8
B. Minimum Data Active Time After Strobe Disabled
(Data Hold Time) .............................................................. 50 ns
11
COMMON
Dwg. PP-015
GROUND
C. Minimum Strobe Pulse Width ..................................................125 ns
D. Typical Time Between Strobe Activation and
Output On to Off Transition ............................................500 ns
E. Minimum Time Between Strobe Activation and
Output Off to On Transition ............................................500 ns
UCN5801LW
F. Minimum Clear Pulse Width ....................................................300 ns
G.Minimum Data Pulse Width .....................................................225 ns
OUTPUT
ENABLE
1
2
3
4
24
23
22
21
20
19
18
CLEAR
Information present at an input is transferred to its latch when the
STROBE is high. A high CLEAR input will set all latches to the output
OFF condition regardless of the data or STROBE input levels. A high
OUTPUT ENABLE will set all outputs to the OFF condition, regardless
of any other input conditions. When the OUTPUT ENABLE is low, the
outputs depend on the state of their respective latches.
STROBE
V
SUPPLY
DD
OUT
1
IN
1
IN
2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
2
3
4
5
6
7
8
5
6
IN
3
IN
4
TRUTH TABLE
7
8
IN
5
OUT
N
OUTPUT
ENABLE
IN
6
17
IN
STROBE
CLEAR
t-1
t
N
IN
7
9
16
15
14
0
1
X
X
X
X
1
1
X
X
0
0
0
0
1
X
0
0
0
0
X
1
0
0
X
X
X
X
ON
OFF
OFF
ON
OFF
OFF
ON
10
IN
8
11
12
COMMON
GROUND
NO
NO
NC
13
NC
CONNECTION
CONNECTION
OFF
Dwg. PP-015-1
X = irrelevant.
t-1 = previous output state.
t = present output state.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5800AND 5801
BiMOS II
LATCHED DRIVERS
TYPICAL APPLICATION
UNIPOLAR STEPPER-MOTOR DRIVE
+30 V
OUTPUT ENABLE (ACTIVE LOW)
CLEAR
STROBE
IN 1
14
1
2
3
4
5
6
7
V
V
13
12
11
10
9
DD
DD
OUT 1
µρ
IN 2
IN 3
IN 4
OUT 2
OUT 3
OUT 4
8
UCN-5800A
+30 V
Dwg. No. B-1537
UNIPOLAR WAVE DRIVE
UNIPOLAR 2-PHASE DRIVE
STROBE
IN 1
STROBE
IN 1
IN 2
IN 2
IN 3
IN 3
IN 4
IN 4
OUT 1
OUT 2
OUT 3
OUT 4
OUT 1
OUT 2
OUT 3
OUT 4
Dwg. GP-060
Dwg. GP-060-1
5800AND 5801
BiMOS II
LATCHED DRIVERS
UCN5800A
Dimensions in Inches
(controlling dimensions)
0.014
0.008
14
8
0.430
MAX
0.280
0.240
0.300
BSC
1
7
0.100
0.070
0.045
0.005
BSC
MIN
0.775
0.735
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-14A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
14
8
10.92
MAX
7.11
6.10
7.62
BSC
1
7
2.54
1.77
1.15
0.13
BSC
MIN
19.68
18.67
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-14A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5800AND 5801
BiMOS II
LATCHED DRIVERS
UCN5800L
Dimensions in Inches
(for reference only)
14
8
0.0098
0.0075
0.1574
0.1497
0.2440
0.2284
0.050
0.016
0.020
0.013
1
2
3
0.050
BSC
0° TO 8°
0.3444
0.3367
0.0688
0.0532
Dwg. MA-007-14 in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
14
8
0.25
0.19
4.00
3.80
6.20
5.80
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
8.75
8.55
1.75
1.35
Dwg. MA-007-14A mm
0.10 MIN.
NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
5800AND 5801
BiMOS II
LATCHED DRIVERS
UCN5801A
Dimensions in Inches
(controlling dimensions)
0.015
0.008
22
12
0.500
MAX
0.380
0.330
0.400
BSC
1
2
3
11
0.100
0.070
0.030
0.005
BSC
MIN
1.120
1.050
0.210
MAX
0.015
0.160
0.115
MIN
0.022
0.014
Dwg. MA-002-22 in
Dimensions in Millimeters
(for reference only)
0.381
0.204
22
12
12.70
MAX
9.65
8.39
10.16
BSC
1
2
3
11
2.54
0.070
0.030
0.13
BSC
MIN
28.44
26.67
5.33
MAX
0.39
4.06
2.93
MIN
0.558
0.356
Dwg. MA-002-22 mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5800AND 5801
BiMOS II
LATCHED DRIVERS
UCN5801EP
Dimensions in Inches
(controlling dimensions)
18
12
0.013
0.021
19
11
0.219
0.191
0.026
0.032
0.456
0.450
INDEX AREA
0.495
0.485
0.050
BSC
0.219
0.191
25
5
26
28
1
4
0.020
0.456
0.450
MIN
0.165
0.180
0.495
0.485
Dwg. MA-005-28A in
Dimensions in Millimeters
(for reference only)
18
12
0.331
0.533
19
11
5.56
4.85
0.812
0.661
11.58
11.43
12.57
12.32
INDEX AREA
1.27
BSC
5.56
4.85
25
5
26
28
1
4
0.51
11.582
11.430
MIN
4.57
4.20
12.57
12.32
Dwg. MA-005-28A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
5800AND 5801
BiMOS II
LATCHED DRIVERS
UCN5801LW
Dimensions in Inches
(for reference only)
24
13
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
BSC
0° TO 8°
0.6141
0.5985
0.0926
0.1043
Dwg. MA-008-24A in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
24
13
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
15.60
15.20
2.65
2.35
Dwg. MA-008-24A mm
0.10 MIN.
NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5800AND 5801
BiMOS II
LATCHED DRIVERS
This page intentionally left blank
5800AND 5801
BiMOS II
LATCHED DRIVERS
BiMOS II (Series 5800) & DABiC IV (Series 6800)
INTELLIGENT POWER INTERFACE DRIVERS
SELECTION GUIDE
Function
Output Ratings *
Part Number †
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers)
-120 mA
350 mA
350 mA
350 mA
350 mA
50 V‡
50 V
5895
5821
5822
5841
5842
8-Bit
8-Bit
8-Bit
8-Bit
80 V
50 V‡
80 V‡
9-Bit
1.6 A
-25 mA
-25 mA
-25 mA
50 V
60 V
60 V
60 V
5829
10-Bit (active pull-downs)
12-Bit (active pull-downs)
20-Bit (active pull-downs)
5810-F and 6809/10
5811 and 6811
5812-F and 6812
32-Bit (active pull-downs)
32-Bit
-25 mA
100 mA
100 mA
60 V
30 V
40 V
5818-F and 6818
5833
32-Bit (saturated drivers)
5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V‡
5800
8-Bit
8-Bit
-25 mA
350 mA
60 V
5815
5801
50 V‡
SPECIAL-PURPOSE FUNCTIONS
Unipolar Stepper Motor Translator/Driver
Addressable 28-Line Decoder/Driver
1.25 A
50 V‡
30 V
5804
6817
450 mA
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
†
‡
Complete part number includes additional characters to indicate operating temperature range and package style.
Internal transient-suppression diodes included for inductive-load protection.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from
the detail specifications as may be required to permit improvements in the design of its products.
The information included herein is believed to be accurate and reliable. However, Allegro
MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or
other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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