APS12800LLHALT0L1A [ALLEGRO]
Two-Wire Hall-Effect Latch with Advanced Diagnostics;
| 型号： | APS12800LLHALT0L1A |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Two-Wire Hall-Effect Latch with Advanced Diagnostics |
| 文件： | 总18页 (文件大小：1042K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APS12800
2
-
Two-Wire Hall-Effect Latch with Advanced Diagnostics
FEATURES AND BENEFITS
• Functional safety
DESCRIPTION
The APS12800 is a two-wire planar Hall-effect sensor
integrated circuit (IC) developed in accordance with
ISO 26262:2011. It includes internal diagnostics and a fault
state that support a functional safety level of ASIL B when
integratedandusedinconjunctionwiththeappropriatesystem-
level control. The two-wire interface provides interconnect
open/short diagnostics and a fault state to communicate
diagnostic information while maintaining compatibility
with legacy two-wire systems. The continuous background
diagnostics are transparent to the host system and results in
a reduced fault tolerant time.
▫ Developed in accordance with ISO 26262:2011
(pending assessment)
▫ Designed to meet ASIL B requirements
▫ Integrated background diagnostics for:
◦ Signal path
◦ Regulator
◦ Hall plate and bias
◦ Overtemperature detection
◦ Nonvolatile memory
▫ Defined fault state
• Multiple product options
The APS12800 product options include magnetic switch
points, temperaturecoefficient, magneticandoutputpolarity.
Theswitchpointsareconfiguredforastableorflattemperature
response. Additional temperature response characteristics
for NdFeB or low-cost ferrite magnets may be available by
contacting Allegro MicroSystems. For situations where a
functionally equivalent two-wire switch device is preferred,
refer to the APS11800.
▫ Magnetic polarity, switch points, and hysteresis
▫ Temperature coefficient
▫ Output polarity
• Reduces module bill-of-materials (BOM) and assembly cost
▫ ASIL B sensor can replace redundant sensors
▫ Integrated overvoltage clamp and reverse-battery diode
• Automotive-grade ruggedness and fault tolerance
▫ Extended AEC-Q100 Grade 0 qualification
▫ Operation to 175°C junction temperature
▫ 3 to 30 V operating voltage range
▫ ±8 kV HBM ESD
Continued on next page...
APPLICATIONS
• Automotive and industrial safety systems
• Seat/window motors
• Sun roof/convertible top/liftgate/tailgate actuation
• Brake and clutch by wire actuators
• Engine management actuators
• Electronic power steering
▫ Overtemperature indication
3-Pin SIP
PACKAGES
(Suffix UA)
3-Pin SOT23W
(Suffix LH)
Not to scale
• Transmission shift actuators
VDD
Regulator
Undervoltage Monitor
Internal Oscillator
To All Subcircuits
Schmitt
Trigger
Hall Plate
and Input
Diagnostics
Output
Control
Sample, Hold,&
Averaging
Signal Path
Diagnostics
H
ALL
MP
A
.
Low-Pass
Filter
Programming
Diagnostics
Programming
System Diagnostics
GND
Figure 1: Functional Block Diagram
APS12800-DS
MCO-0000806
March 24, 2020
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
DESCRIPTION (continued)
APS12800 sensors are engineered to operate in the harshest operation directly from an automotive 12 V battery system. These
environmentswithminimalexternalcomponents.Theyarequalified integrated features reduce the end-product bill-of-materials (BOM)
beyond the requirements of AEC-Q100 Grade 0 and will survive and assembly cost.
extended operation at 175°C junction temperature.
Packageoptionsincludeindustry-standardsurface-mountSOT(LH)
These monolithic ICs include on-chip reverse-battery protection, and through-hole SIP (UA) packages. Both packages are RoHS-
overvoltage protection (e.g., 40 V load dump), ESD protection, compliantandlead(Pb)freewith100%matte-tin-platedleadframes
overtemperature detection, and an internal voltage regulator for
RoHS
COMPLIANT
SELECTION GUIDE
ICC(L)
Selection
Magnetic
Temperature
Coefficient
Output Polarity
for B > BOP
Device Latch
Threshold (G)
Part Number [1]
Package
Packing
(mA)
APS12800LLHALT-0H1A
APS12800LLHALX-0H1A
APS12800LUAA-0H1A
3-pin SOT23-W surface mount
3-pin SOT23-W surface mount
3-pin SIP through-hole
7-inch reel, 3000 pieces/reel
13-inch reel, 10000 pieces/reel
Bulk, 500 pieces/bag
BOP: +80 max
BRP: –80 max
Flat
Flat
Flat
ICC(H)
ICC(H)
ICC(H)
5 to 6.9
BOP: +80 max
BRP: –80 max
5 to 6.9
2 to 5
APS12800LUAATN-0H1A
APS12800LUAA-0H2A[2]
APS12800LUAATN-0H2A[2]
3-pin SIP through-hole
13-inch reel, 4000 pieces/reel
Bulk, 500 pieces/bag
3-pin SIP through-hole
BOP: +80 max
BRP: –80 max
3-pin SIP through-hole
13-inch reel, 4000 pieces/reel
[1] Contact Allegro MicroSystems for options not listed in the selection guide.
[2] Contact Allegro MicroSystems for availability.
ꢀoꢁꢂlete Part
ꢃꢄꢁꢅer ꢆorꢁat
Allegro Iden�fier (Device Family)
APS – Digital Posi�on Sensor
Allegro Device Number
12800 – 2-wire Planar Hall-Effect Latch
Configura�on Op�ons
A P S 1 2 8 0 0 L L H A L X 0 L 1 A
-
Temperature Coefficient
A – Flat
ICCLOW Selec�on
1 – 5 to 6.9 mA
2 – 2 to 5 mA
Output Polarity for B > BOP
H – ICC(H)
L – ICC(L)
Device Switch Threshold Magnitude
0 – BOP: +80 G max; BRP: -80 G min
1 – BOP: +40 G max; BRP: -40 G min
Instruc�ons (Packing)
(no op�on code) – Bulk, 500 pieces/bag (UA Only)
LT – 7-in. reel, 3,000 pieces/reel (LH Only)
LX – 13-in. reel, 10,000 pieces/reel (LH Only)
Package Designa�on
LHA – 3-pin SOT23W Surface Mount
UAA – 3-pin SIP Through-Hole
Ambient Opera�ng Temperature Range
L – -40°C to +150°C
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
VCC
Notes
Rating
45
Unit
V
Forward Supply Voltage [1]
Reverse Supply Voltage [1]
VRCC
–30
V
165
°C
Maximum Junction Temperature
Storage Temperature
TJ(MAX)
Tstg
1000 hours
175
–65 to 170
°C
[1] This rating does not apply to extremely short voltage transients such as Load Dump and/or ESD. Those events have individual ratings, specific to
the respective transient voltage event.
ESD PERFORMANCE
Characteristic
Symbol
Notes
Rating
Unit
AEC-Q100 ESD
VESD(HBM)
Human Body Model AEC-Q100-002
±8
kV
TRANSIENT PROTECTION CHARACTERISTICS: Valid for TA = 25°C and CBYP = 0.1 µF (unless otherwise specified)
Characteristics
Symbol
VZ
Test Conditions
ICC(max) + 3 mA
Min.
44
–
Typ.
Max.
–
Unit
Forward Supply Zener Clamp Voltage
Reverse Supply Zener Clamp Voltage
Reverse Supply Current
–
–
–
V
V
VRCC
IRCC
ICC = –1 mA
–30
–5
VRCC = –30 V
–
mA
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
PINOUT DIAGRAMS AND TERMINAL LISTS
3
1
2
1
2
3
Package LH, 3-Pin
SOT23W Pinout
Package UA, 3-Pin
SIP Pinout
Terminal List Table
Pin Number
Symbol
LH
Package
UA
Package
Description
VCC
GND
GND
1
1
2
3
Supply Voltage
2*
3*
Ground
Ground
* Pins 2 and 3 are tied together internally and the device will operate with
either pin 2 or 3 grounded externally; however, grounding both pins
externally is recommended for EMC robustness.
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
OPERATING CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ (max), and
BYP = 0.1 µF, unless otherwise specified
C
Characteristics
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
Supply Voltage
VCC
Operating; min. VCC for magnetically actuated output
3
–
30
V
Voltage threshold at which the device output is set to POS
during power down
Undervoltage Lockout
Shutdown Voltage
VUVLO
VSD
–
2.3
–
V
Sensor output shuts down
ICCLOW Selection = 2
–
2
1.8
–
–
5
V
mA
mA
mA
ICC(L)
ICCLOW Selection = 1
5
–
6.9
17
Supply Current
ICC(H)
IFAULT
12
–
Safe current state; indicates device diagnostics have
detected a fault condition; see Table 1
–
–
1.8
mA
Standard circuit; CBYP = 100 nF, CL [2] = 20 pF, RSENSE = 100 Ω
Min. circuit; CBYP = 10 nF, CL [2] = 20 pF, RSENSE = 100 Ω
–
–
0.4
4
–
–
mA/µs
mA/µs
Output Slew Rate
dI/dt
tPO
On power up only; time starts when supply voltage
exceeds VCC(min)
Power-On Time [3]
Power-On State [4]
–
–
70
µs
Output state during power on; valid only when VCC
VCC(min)
≥
POS
fC
ICC(H)
–
–
–
–
mA
Chopping Frequency
800
kHz
Diagnostic Characteristics
Fault Reaction Time
tDIAG
tDIAGF
TJF
CBYP = 0.1 µF, RSENSE = 100 Ω
–
–
–
–
44
2
–
–
–
–
µs
ms
°C
°C
Diagnostic Fault Retry Time
Overtemperature Shutdown
Overtemperature Hysteresis
Temperature increasing
205
25
THYS
[1] Typical data is at TA = 25°C and VCC = 12 V, unless otherwise noted; for design information only.
[2] CL – measurement probe capacitance.
[3] Measured from VCC ≥ VCC(min) to valid output.
[4] Power-on state is defined only when VCC slew rate > 6 V/ms.
5
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955 Perimeter Road
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APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
MAGNETIC CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max) and
BYP = 0.01 µF, unless otherwise specified
C
Magnetic
Switch Point
Option
Temperature
Coefficient
Characteristics
Symbol
Test Conditions
Min.
Typ. [8]
Max.
Unit [9]
-0
-1
-0
-1
-0
-1
All
A – Flat
A – Flat
A – Flat
A – Flat
A – Flat
A – Flat
All
TA = –40°C to 150°C
TA = –40°C to 150°C
TA = –40°C to 150°C
TA = –40°C to 150°C
TA = –40°C to 150°C
TA = –40°C to 150°C
BOP + BRP
5
–
–
80
40
–5
–5
110
65
30
G
G
G
G
G
G
G
Operate Point
Release Point
BOP
5
–80
–40
40
–
BRP
–
–
Hysteresis
Symmetry
BHYS
BSYM
15
40
–
–30
Switch Point Temperature
Coefficient
All
-1
A – Flat
A – Flat
TA = –40°C to 150°C
–
–
0
–
–
%/°C
%
Jitter [10]
–
0.25
[8] Typical data is at TA = 25°C and VCC = 12 V, unless otherwise noted; for design information only.
[9] Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and a positive value for south-polarity magnetic fields.
[10] Output edge repeatability as a percentage of the period.
6
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955 Perimeter Road
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www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Notes
Rating
Unit
Package LH, 1-layer PCB with copper limited to solder pads
228
°C/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area, each
side connected by thermal vias
Package Thermal Resistance
RθJA
110
165
°C/W
°C/W
Package UA, 1-layer PCB with copper limited to solder pads
Power Derating ꢌꢉrve
ꢀ1
ꢀ0
2ꢅ
28
2ꢄ
2ꢃ
2ꢂ
2ꢁ
2ꢀ
22
21
20
1ꢅ
18
1ꢄ
1ꢃ
1ꢂ
1ꢁ
1ꢀ
12
11
10
ꢅ
ꢋꢌꢌꢍꢈaꢇꢎ
LH Pacꢑage
2-laꢒer Pꢌꢓ
ꢔA Pacꢑage
1-laꢒer Pꢌꢓ
LH Pacꢑage
1-laꢒer Pꢌꢓ
8
ꢄ
ꢃ
ꢂ
ꢋꢌꢌꢍꢈinꢎ
ꢁ
ꢀ
20
ꢁ0
ꢃ0
80
100
120
1ꢁ0
1ꢃ0
180
Teꢈꢏeratꢉre ꢍꢐꢌꢎ
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
FUNCTIONAL DESCRIPTION
cal vibration and electrical noise. Figure 3 shows the output
switching behavior relative to increasing and decreasing magnetic
Operation
The output of these devices switches when a magnetic field
perpendicular to the Hall-effect sensor exceeds the operate point
threshold (BOP). When the magnetic field is reduced below the
release point, BRP, the device output switches to the alternate
state. The output state (polarity) and magnetic field polarity
depends on the selected device options. For unipolar south, an
increasing south field is required; likewise, for unipolar north, an
increasing north field is required to exceed BOP. The output state
is a configuration option.
field. On the horizontal axis, the B+ direction indicates increasing
south polarity magnetic field strength. Figure 2 shows the sensing
orientation of the magnetic field, relative to the device package.
The difference between operate (BOP) and release (BRP) points
is the hysteresis, BHYS. Hysteresis allows clean switching of the
output even in the presence of external mechanical vibration and
electrical noise.
Figure 3 shows the potential unipolar and omnipolar options and
output polarity options the APS12800 can be configured for. The
direction of the applied magnetic field is perpendicular to the
branded face of the APS12800.
The difference in magnetic operate and release points is the hys-
teresis, BHYS, of the device. This built-in hysteresis allows clean
switching of the output even in the presence of external mechani-
Latch
ꢁꢇ
ꢁꢂꢂꢃHꢄ
Standard
ꢀꢁtꢂꢁt
Polaritꢃ
ꢄPꢀL ꢅ Hꢆ
ꢁꢂꢂꢃꢀꢄ
0
0
ꢅꢇ
Y
Y
X
X
ꢅHꢆS
A
B
Z
Z
Latch
ꢁꢇ
ꢇeversed
ꢀꢁtꢂꢁt
ꢁꢂꢂꢃHꢄ
Polaritꢃ
ꢄPꢀL ꢅ Lꢆ
Figure 2: Magnetic Sensing Orientations
LH Package (Panel A), UA Package (Panel B)
ꢁꢂꢂꢃꢀꢄ
0
0
ꢅꢇ
ꢅHꢆS
Figure 3: Hall Latch Output State vs. Magnetic Field
B- indicates increasing north polarity magnetic field strength, and B+
indicates increasing south polarity magnetic field strength.
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
fications are not be guaranteed over temperature and process
corners when VUVLO < VCC < VCC(min). As soon as VCC exceeds
Power-On/Off Behavior
During power up when VCC reaches VCC(min), the output will
enter Power-On State and stay there until tPO expires. The tPO
timer starts as soon as VCC exceeds VCC(min); once tPO expires,
the device output is determined by the BOP/BRP specifications.
(Note the minimum allowed power VCC slew rate is 6 V/ms to
ensure that VCC has reached VCC(min) within tPO).
VCC(min), BOP/BRP limits will be guaranteed over process and
temperature. See Figure 4. If VCC continues to drop below the
UVLO threshold, the device output will be forced to POS (ICC(H)
and will remain there as long as VPD < VCC ≤ VCC(min). Once
)
VCC has dropped below VUVLO, the device will go through
power-up sequence once VCC is restored. If VCC continues to
drop below VPD, the device will power down and the output will
After the device is powered up, if VCC drops below VCC(min), the
output state will continue to function; however, BOP/BRP speci-
not be functional until VCC is restored to be >VCC(min)
.
ꢀ
VCC(min)
UVLO
VPD
ꢂ
tPO
t
POS
ICC(H)
Output Valid
Output Valid
Output Not Valid
BOP/BRP Not Guaranteed
ICC(L)
t
Figure 4: Device power up and subsequent restart after falling below VCC(min) but not below VUVLO
ꢀ
VCC(min)
UVLO
VSD
ꢂ
tPO
tPO
t
t
POS
POS
POS
ICC(H)
Output Valid
ꢀꢁtꢂꢁt ꢃalid
Output Not Valid
Output Not Valid
BOP/BRP Not
Guaranteed
ICC(L)
Figure 5: Device power up and subsequent reset after VCC falls below VUVLO
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
supply current will be in the IFAULT region. Additionally, if the
any of the device internal diagnostics described in Table 1 detect
a fault, the output will go to IFAULT. A supply current greater than
the specified maximum for the high level (ICC > ICC(H)(max)), typi-
cally indicates a short condition. If ICC < IFAULT(min) typically
indicates an open-circuit condition.
Two-Wire Interface
The regulated current output is configured for two-wire appli-
cations, requiring one less wire for operation than latches with
the traditional open-collector output. Additionally, the two-wire
interface provides basic diagnostics to the system by monitoring
the supply current. During normal operation, the supply current
should operate in the specified ranges; see Figure 6. Any current
level not within the specified operating ranges for ICC(H) or ICC(L)
indicates a fault condition.
This unique two-wire interface protocol is backward compatible
with legacy systems using two-wire latches. Additionally, the low
fault mode supply current resulting from an internal fault will
fall outside of the low and high supply current ranges and can be
similarly identified as a sensor fault.
There are a couple specific fault conditions indicated by ICC
IFAULT. If the device junction temperature exceeds TJF, average
=
ꢎmA
ꢀaꢁlt
ꢇꢈꢈꢉHꢊ ꢉmaꢋꢊ
ꢇꢈꢈꢉHꢊ ꢉminꢊ
ꢇꢈꢈꢉHꢊ Range
ꢀaꢁlt
ꢇꢈꢈꢉꢌꢊ ꢉmaꢋꢊ
ꢇꢈꢈꢉꢌꢊꢉminꢊ
ꢇꢈꢈꢉꢌꢊ Range
ꢇꢀAUꢌꢍ Range
ꢀaꢁlt
ꢂꢃertemꢄ or ꢅiagnostic ꢆrror
ꢀaꢁlt
ꢇꢀAUꢌꢍ
Figure 6: Two Wire Interface Output
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
path monitoring system verifies two internal state transitions (BOP
and BRP within limits) under normal operation. In cases when
these output transitions do not occur, or if another internal fault is
detected, the output will go to the safe state.
Functional Safety
The APS12800 was developed in accordance with the interna-
tional standard for automotive functional safety, ISO 26262:2011.
Designed to meet ASIL B requirements when integrated and used
in conjunction with the appropriate system-level control in the
manner prescribed in the APS12800 Safety Manual.
In the event of an internal fault, the device will continuously run
the diagnostics routine every 2 ms (tDIAGF). The periodic recov-
ery attempt sequence allows the device to continually check for
the presence of a fault and return to normal operation if the fault
condition clears.
The APS12800 features a proprietary diagnostics routine to sup-
port ASIL B safety requirements; see Table 1 and Figure 7. This
internal diagnostics routine continuously runs in the background,
monitoring all key subsystems of the IC. The diagnostic scheme
runs at high speed and provides minimal impact on device perfor-
mance.
In the case where the fault is no longer present, the output will
resume normal operation. However, if the fault is persistent, the
device will not exit fault mode and ICC will continue to be IFAULT
.
See Figure 8.
The Hall element biasing circuit and voltage regulator are
checked for valid operation, and the digital and nonvolatile
memory blocks are checked for valid device configuration.
When a system rating higher than ASIL B is required, additional
external safety measures may be employed (e.g., sensor redun-
dancy and rationality checks, etc.). Refer to the device safety
manual for additional details about the diagnostics.
All diagnostics are running in real time in the background, allow-
ing for a fault reaction time of approximately 44 µs. The signal
Table 1: Diagnostics Coverage
Feature
Coverage
1
2
3
4
5
6
Hall plate
Connectivity and biasing of Hall plate
Signal path
Signal path and Schmitt trigger
Voltage regulator
Digital subsystem
Entire system
Output
Regulator voltage for normal operation
Digital subsystem and non-volatile memory
Overtemperature and redundancies for single point failures
Output verified with external monitors
VDD
3
Regulator
5
Undervoltage Monitor
Internal Oscillator
To All Subcircuits
1
2
6
Schmitt
Trigger
Hall Plate
and Input
Diagnostics
Output
Control
Sample, Hold,&
Averaging
Signal Path
Diagnostics
H
ALL
MP
A
.
Low-Pass
Filter
Programming
Diagnostics
Programming
4
System Diagnostics
GND
Figure 7: Device Functional Block Diagram with Diagnostic Features Indicated
11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
ICC
Failure Detected
Device Recovers
ICC(H)
ꢀꢁtꢂꢁt switches
according to eꢃternal
magnetic ꢄield
ꢀꢁtꢂꢁt switches
according to eꢃternal
magnetic ꢄield
Diag Retry*
ꢅinternal diagnostics actiꢆeꢇ
ꢅinternal diagnostics actiꢆeꢇ
ICC(L)
IFAULT
2 ms
2 ms
ꢈ ꢉor a deꢆice with oꢂtion ꢊꢋꢋꢌꢀꢍ Selection ꢎ 1, ꢊꢋꢋ goes to the ꢊꢋꢋꢅꢌꢇ sꢂeiꢄicied ꢏy ꢊꢋꢋꢌꢀꢍ Selection ꢎ ꢐ dꢁring ꢑiagnostics Retry.
Similarly, ꢄor a deꢆice with oꢂtion ꢊꢋꢋꢌꢀꢍ Selection ꢎ ꢐ, ꢊꢋꢋ goes to the ꢊꢋꢋꢅꢌꢇ sꢂeiꢄicied ꢏy ꢊꢋꢋꢌꢀꢍ Selection ꢎ 1 dꢁring ꢑiagnostics Retry.
ꢒhis diꢄꢄerentiates a normal oꢂeration condition ꢄrom a ꢄaꢁlt condition.
t
Figure 8: Diagnostic mode operation and timing during normal operation and during a fault condition
12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
APPLICATIONS INFORMATION
Extensive applications information on magnets and Hall-effect
sensors is available in:
Typical Applications
For the LH and UA, an external bypass capacitor, CBYP, should
be connected as close as possible to the Hall sensor between the
supply and ground to reduce noise. See Figure 9.
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines For Designing Subassemblies
Using Hall-Effect Devices AN27703.1
Temperature Coefficient and Magnet Selection
• Soldering Methods for Allegro’s Products – SMT and Through-
Hole, AN26009
The APS12800 incorporates circuitry to compensate the magnetic
switch points over the operating temperature range. This feature
is referred to as the magnetic switch point temperature coeffi-
cient. The default option is for flat stable response over tempera-
ture. If the application requires compensation for temperature
drifts common with NdFeB and ferrite magnets, contact Allegro
MicroSystems. It is recommended that system designers evalu-
ate their magnetic circuit over the expected operating temperature
range to ensure the magnetic switching requirements are met.
• Functional Safety Challenges to the Automotive Supply Chain
(http://www.allegromicro.com/en/Design-Center/Technical-
Documents/General-Semiconductor-Information/Functional-
Safety-Challenges-Automotive-Supply-Chain.aspx)
All are provided on the Allegro website:
www.allegromicro.com
ECU
V+
VCC
APS12800
RSENS E
VSENS E
V+
CBYP
0.1 µF
VCC
A119x
APS12800
CBYP
0.1 µF
GND
VSENS E
ECU
GND
RSENS E
(A) Low-Side Sensing
(B) High-Side Sensing
Figure 9: Typical Application Circuits
13
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
CHOPPER STABILIZATION
A limiting factor for switch point accuracy when using Hall-
effect technology is the small-signal voltage developed across
the Hall plate. This voltage is proportionally small relative to the
offset that can be produced at the output of the Hall sensor. This
makes it difficult to process the signal and maintain an accurate,
reliable output over the specified temperature and voltage range.
Chopper stabilization is a proven approach used to minimize Hall
offset.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetically induced signal to recover
its original spectrum at baseband while the DC offset becomes
a high-frequency signal. Then, using a low-pass filter, the signal
passes while the modulated DC offset is suppressed.
Allegro’s innovative chopper stabilization technique uses a high-
frequency clock. The high-frequency operation allows a greater
sampling rate that produces higher accuracy, reduced jitter, and
faster signal processing. Additionally, filtering is more effective
and results in a lower noise analog signal at the sensor output.
Devices such as the APS12800 that use this approach have a stable
quiescent Hall output voltage, are immune to thermal stress, and
have precise recoverability after temperature cycling. This tech-
nique is made possible through the use of a BiCMOS process
which allows the use of low-offset and low-noise amplifiers in
combination with high-density logic and sample-and-hold circuits.
The technique, dynamic quadrature offset cancellation, removes
key sources of the output drift induced by temperature and pack-
age stress. This offset reduction technique is based on a signal
modulation-demodulation process. Figure 10: Model of Chopper
Stabilization Circuit (Dynamic Offset Cancellation) illustrates
how it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation.
Regulator
Clock/Logic
Low-Pass
Filter
Hall
Element
Sample and
Hold
Amp.
Figure 10: Model of Chopper Stabilization Circuit (Dynamic Offset Cancellation)
14
Allegro MicroSystems
955 Perimeter Road
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APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
POWER DERATING
The device must be operated below the maximum junction
temperature, TJ (max). Reliable operation may require derating
supplied power and/or improving the heat dissipation properties
of the application.
17 mA, calculate the maximum allowable power level, PD (max).
First, using equation 3:
∆Tꢀ(max)ꢀ=ꢀTJ (max) – TAꢀ=ꢀ165°Cꢀ–ꢀ150°Cꢀ=ꢀ15°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, from equation 2:
Thermal Resistance (junction to ambient), RθJA, is a figure of
merit summarizing the ability of the application and the device to
dissipate heat from the junction (die), through all paths to ambi-
ent air. RθJA is dominated by the Effective Thermal Conductivity,
K, of the printed circuit board which includes adjacent devices
and board layout. Thermal resistance from the die junction to
case, RθJC, is a relatively small component of RθJA. Ambient air
temperature, TA, and air motion are significant external factors in
determining a reliable thermal operating point.
PDꢀ(max)ꢀ=ꢀ∆Tꢀ(max)ꢀ÷ꢀRθJAꢀ=ꢀ15°Cꢀ÷ꢀ165°C/Wꢀ=ꢀ91ꢀmW
Finally, using equation 1, solve for maximum allowable VCC for
the given conditions:
V
CC (est) = PDꢀ(max)ꢀ÷ꢀICCꢀ(max)ꢀ=ꢀ91ꢀmWꢀ÷ꢀ17ꢀmAꢀ=ꢀ5.4ꢀV
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤ VCC (est).
The following three equations can be used to determine operation
points for given power and thermal conditions.
If the application requires VCC > VCC(est) then RθJA must by
improved. This can be accomplished by adjusting the layout,
PCB materials, or by controlling the ambient temperature.
PD = VIN × IIN
∆Tꢀ=ꢀPD × RθJA
TJ = TAꢀ+ꢀ∆Tꢀꢀ
(1)
(2)
(3)
Determining Maximum TA
ꢀ
ꢀ
In cases where the VCC (max) level is known, and the system
designer would like to determine the maximum allowable ambi-
ent temperature TA (max), for example, in a worst-case scenario
with conditions VCC (max) = 24 V, ICC (max) = 17 mA, and RθJA
= 228°C/W for the LH package using equation 1, the largest pos-
sible amount of dissipated power is:
For example, given common conditions: TA = 25°C, VCC = 12 V,
ICC = 17 mA, and RθJA = 110°C/W for the LH package, then:
PD = VCC × ICC = 12 V × 17 mA = 204 mW
ꢀ
∆Tꢀ=ꢀPD × RθJA = 204 mW × 110°C/W = 22.44°C
TJ = TAꢀ+ꢀ∆Tꢀ=ꢀ25°Cꢀ+ꢀ22.44°Cꢀ=ꢀ47.44°C
PD = VIN × IIN
PD = 24 V × 17 mA = 408 mW
Then, by rearranging equation 3 and substituting with equation 2:
Determining Maximum VCC
TA (max) = TJꢀ(max)ꢀ–ꢀΔT
TAꢀ(max)ꢀ=ꢀ165°Cꢀ–ꢀ(408ꢀmWꢀ×ꢀ228°C/W)
TAꢀ(max)ꢀ=ꢀ165°Cꢀ–ꢀ93°Cꢀ=ꢀ72°C
For a given ambient temperature, TA, the maximum allow-
able power dissipation as a function of VCC can be calculated.
PD (max) represents the maximum allowable power level without
exceeding TJ (max) at a selected RθJA and TA.
Example: VCC at TA = 150°C, package UA, using low-K PCB.
Finally, note that the TA (max) rating of the device is 150°C and
performance is not guaranteed above this temperature for any
power level.
Using the worst-case ratings for the device, specifically: RθJA
=
165°C/W, TJ (max) = 165°C, VCC (max) = 24 V, and ICC (max) =
15
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
PACKAGE OUTLINE DRAWINGS
+0.125
–0.75
2.975
3
ꢃ
1.49
4ꢍꢄ4ꢍ
A
+0.020
0.180
–0.053
ꢃ
0.96
ꢃ
+0.10
2.90
+0.19
–0.06
2.40
1.91
–0.20
0.70
0.25 ꢏIN
1.00
2
1
0.55 RꢀF
0.25 BSC
0.95
PCB Laꢆout Reference ꢊieꢋ
Seating Plane
ꢁauge Plane
B
Branꢅeꢅ Face
8ꢎ 10ꢍ ꢄ5ꢍ
1.00 ꢄ0.13
+0.10
XXX
1
0.05
–0.05
C
Stanꢅarꢅ Branꢅing Reference ꢊieꢋ
0.95 BSC
0.40 ꢄ0.10
Line 1 ꢌ Three ꢅigit assigneꢅ branꢅ number
For reference onlꢆꢈ not for tooling use (reference ꢃWꢁ-0000628, Reꢂ. 1).
ꢃimensions in millimeters.
ꢃimensions exclusiꢂe of molꢅ flash, gate burrs, anꢅ ꢅambar protrusions.
ꢀxact case anꢅ leaꢅ configuration at supplier ꢅiscretion ꢋithin limits shoꢋn.
Actiꢂe Area ꢃepth, 0.28 ꢄ0.04 mm
A
B
Reference lanꢅ pattern laꢆout
All paꢅs a minimum of 0.20 mm from all aꢅꢇacent paꢅsꢈ aꢅꢇust as necessarꢆ
to meet application process reꢉuirements anꢅ PCB laꢆout tolerances
C
ꢃ
Branꢅing scale anꢅ appearance at supplier ꢅiscretion
Hall element, not to scale
Figure 11: Package LH, 3-Pin SOT23W
16
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
ꢀor ꢁeference Only ꢂ Not for Tooling ꢃse
(Reference ꢅWꢍ-0000619, Reꢆ. 1)
NOT TO SCALꢈ
ꢅimensions in millimeters
ꢅimensions exclusiꢆe of mold flash, gate burrs, anꢃ ꢃambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.08
4.09
–0.05
45ꢁ
B
C
ꢈ
2.04 NOꢀ
1.52 ꢂ0.05
10ꢁ
1.44 NOꢀ
ꢈ
ꢈ
ꢈꢉector Pin
Flash Protrusion
+0.08
3.02
–0.05
45ꢁ
Branꢃeꢃ
Face
0.79 RꢈF
A
1.02
ꢀAX
NNN
1
1
2
3
Stanꢃarꢃ Branꢃing Reference ꢊieꢋ
ꢅ
ꢌ Supplier emblem
N ꢌ Last three ꢃigits of ꢃeꢆice part number
14.99 ꢂ0.25
+0.03
–0.06
0.41
+0.05
–0.07
0.43
ꢅambar remoꢆal protrusion (6ꢇ)
ꢀolꢃ gate protrusion ꢄone
A
ꢀ
ꢁ
ꢅ
Actiꢆe Area ꢅepth, 0.50 mm ꢂ0.08
Branꢃing scale anꢃ appearance at supplier ꢃiscretion
Hall element (not to scale)
ꢈ
1.27 NOꢀ
Figure 12: Package UA, 3-Pin SIP
17
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12800
Two-Wire Hall-Effect Latch with Advanced Diagnostics
Revision History
Number
Date
March 24, 2020
Description
–
Initial release
Copyright 2020, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
18
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
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