ACS71020KMABTR-030B3-I2C [ALLEGRO]
Power Supply Management Circuit,;
| 型号： | ACS71020KMABTR-030B3-I2C |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Power Supply Management Circuit, 光电二极管 |
| 文件： | 总37页 (文件大小：846K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACS71020
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
DESCRIPTION
FEATURES AND BENEFITS
• Accurate power monitoring for both AC and DC applications
• UL certification for reinforced isolation up to 517 VRMS in
a single package
• Accurate measurements of active, reactive, and apparent
power, as well as power factor
• Separate RMS and instantaneous measurements for both
voltage and current channels
• 0.85 mΩ primary conductor resistance for low power loss
and high inrush current withstand capability
• Dedicated voltage zero crossing pin
• Overcurrent fault output pin
• Hall-effect-based current measurement with common-
mode stray field rejection
• User-programmable undervoltage and overvoltage thresholds
for input voltage as well as overcurrent fault thresholds
• 1 kHz bandwidth
TheAllegroACS71020 power monitoring IC greatly simplifies
the addition of power monitoring to many AC or DC powered
systems.Thesensormaybepoweredfromthesamesupplyasthe
system’sMCU,eliminatingtheneedformultiplepowersupplies
and expensive digital isolation ICs. The device’s construction
includesacopperconductionpaththatgeneratesamagneticfield
proportional to applied current. The magnetic field is sensed
differentiallytorejecterrorsintroducedbycommonmodefields.
Allegro’s Hall-effect-based galvanically isolated current
sensing technology achieves reinforced isolation ratings in a
small PCB footprint. These features enable isolated current
sensing without expensive Rogowski coils, oversized current
transformers, isolated operational amplifiers, or the power loss
of shunt resistors.
The ACS71020 power monitoring IC offers key power
measurement parameters that can easily be accessed through its
SPIorI2Cdigitalprotocolinterfaces.Dedicatedandconfigurable
I/Opinsforvoltagezerocrossing,undervoltageandovervoltage
reporting, and overcurrent fault detection are also available (in
I2C mode). The thresholds for overvoltage, undervoltage, and
overcurrent are all user-programmable via EEPROM.
• Current-sensing range from 0 to 90 A
• Options for I2C or SPI digital interface protocols
• User-programmable EEPROM and integrated charge pump
• 16-bit voltage and current ADCs
PACKAGE
16-pin SOICW (suffix MA)
TheACS71020isprovidedinasmalllow-profilesurfacemount
SOIC16 wide-body package, is lead (Pb) free, and is fully
calibratedpriortoshipmentfromtheAllegrofactory.Customer
calibration can further increase accuracy in application.
Not to scale
REINFORCED
ISOLATION
N (L)
L (N)
1 MΩ 1 MΩ
RSENSE
1 MΩ 1 MΩ
1
16
VINP
VINN
IP+ ACS71020
MCU
TÜV America
2
3
GND
15
14
13
12
11
10
9
Certificate Number:
U8V 14 11 54214 032
CB 14 11 54214 031
IP+
IP+
IP+
IP-
IP-
IP-
IP-
GND
To User
4
5
6
7
8
VCC
VCC
IP
SDA / MISO
SCL / SCLK
DIO_0 / MOSI
DIO_1 / CS
CB Certificate Number:
US-22334-A2-UL
Linear
Regulator
Single Output
Isolated Power
Supply
(Flyꢀack, etc.)
Figure 1: Typical Application
ACS71020-DS, Rev. 1
MCO-0000459
September 19, 2018
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
SELECTION GUIDE
Communication
Part Number
VCC(NOM) (V)
IPR (A)
TA (°C)
Packing [1]
Protocol
ACS71020KMABTR-015B5-SPI
ACS71020KMABTR-030B3-SPI
ACS71020KMABTR-030B3-I2C
ACS71020KMABTR-090B3-I2C
5
±15
±30
±30
±90
SPI
Tape and reel,
1000 pieces per reel,
3000 pieces per box
3.3
3.3
3.3
–40 to 125
I2C
[1] Contact Allegro for additional packing options.
ACS ꢀ10ꢁ0 ꢂ MAꢃ ꢐR
-
015
ꢃ
5 - SPꢒ
Commꢄnication Protocol
Sꢄꢅꢅly ꢆoltageꢇ
5 ꢈ ꢆCC ꢉ 5 ꢆ
3 ꢈ ꢆCC ꢉ 3.3 ꢆ
ꢊꢄtꢅꢄt ꢋirectionalityꢇ
ꢃ ꢈ ꢃidirectional ꢌꢅositiꢍe and negatiꢍe cꢄrrentꢎ
Cꢄrrent Sensing Range ꢌAꢎ
Pacꢏing ꢋesignator
Pacꢏage ꢋesignator
ꢊꢅerating ꢐemꢅeratꢄre Range
5 ꢋigit Part Nꢄmꢑer
Allegro Cꢄrrent Sensor
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
VCC
Notes
Rating
6.5
Units
V
Supply Voltage
Reverse Supply Voltage
Input Voltage
VRCC
–0.5
V
V
INP, VINN
RNP, VRNN
VDIO
VCC + 0.5
–0.5
V
Reverse Input Voltage
Digital I/O Voltage
V
V
6
V
SPI, I2C, and general purpose I/O
Range K
Reverse Digital I/O Voltage
Operating Ambient Temperature
Junction Temperature
VRDIO
–0.5
V
TA
–40 to 125
165
°C
°C
TJ(max)
Storage Temperature
Tstg
–65 to 170
°C
ISOLATION CHARACTERISTICS
Characteristic
Symbol
Notes
Rating
Unit
Agency type-tested for 60 seconds per UL 60950-1
(edition 2). Production tested at 3000 VRMS for 1 second, in
accordance with UL 60950-1 (edition 2).
Dielectric Strength Test Voltage
VISO
4800
VRMS
1480
1047
730
VPK
VRMS or VDC
VPK
Maximum approved working voltage for basic (single) isolation
according to UL 60950-1 (edition 2).
Working Voltage for Basic Isolation
VWVBI
Maximum approved working voltage for reinforced isolation
according to UL 60950-1 (edition 2).
Working Voltage for Reinforced Isolation
VWVRI
517
7.5
VRMS or VDC
mm
Clearance
Creepage
Dcl
Dcr
Minimum distance through air from IP leads to signal leads.
Minimum distance along package body from IP leads to signal
leads
7.5
mm
THERMAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions*
Value Units
Mounted on the Allegro 85-0738 evaluation board with 700 mm2 of 4 oz.
copper on each side, connected to pins 1 and 2, and to pins 3 and 4, with
thermal vias connecting the layers. Performance values include the power
consumed by the PCB.
Package Thermal Resistance
(Junction to Ambient)
RθJA
23
5
°C/W
°C/W
Package Thermal Resistance
(Junction to Lead)
RθJL
Mounted on the Allegro ACS71020 evaluation board.
*Additional thermal information available on the Allegro website. See https://www.allegromicro.com/en/Design-Center/Technical-Documents/Hall-Effect-Sensor-IC-Publica-
tions/DC-and-Transient-Current-Capability-Fuse-Characteristics.aspx.
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
FUNCTIONAL BLOCK DIAGRAM
ꢈCC
ꢀꢁꢂꢁꢃAꢄ SꢅSꢃꢆꢇ
ꢀandgaꢁ
R
Reꢂerence
SꢊA ꢎ MꢆSꢏ
SCL ꢎ SCLꢐ
ꢊꢆꢏꢑ0 ꢎ MꢏSꢆ
ꢅemꢁeratꢄre
Comꢁensation
Logic
ꢍ
ꢆ CꢎSPꢆ
ꢅemꢁeratꢄre
Sensor
ꢅo All
Commꢄnication
Sꢄꢋcircꢄits
ꢌꢌPRꢏM ꢇ
ꢈꢆNP
ꢈꢆNN
Charge Pꢄmꢁ
ꢈ
AꢊC
AꢊC
ꢊꢆꢏꢑ1 ꢎ CS
ꢍR
I
Metrology
ꢌngine
ꢆPꢇ
ꢃaꢄlt Logic
Hall Sensor Array
ꢉNꢊ
ꢆP–
Table of Contents
ADCs ............................................................................ 12
Raw Signal Sensitivity and Offset Trim............................... 12
Phase Compensation ...................................................... 12
Zero Crossing................................................................. 12
Power Calculations............................................................. 13
Digital Communication........................................................ 15
Registers and EEPROM .................................................. 15
EEPROM Error Checking and Correction (ECC)................. 17
Memory Map .................................................................. 18
Volatile Memory Map....................................................... 26
Application Connections...................................................... 34
Recommended PCB Layout ................................................ 35
Package Outline Drawing.................................................... 36
Features and Benefits........................................................... 1
Description.......................................................................... 1
Package ............................................................................. 1
Typical Application................................................................ 1
Selection Guide ................................................................... 2
Absolute Maximum Ratings................................................... 3
Isolation Characteristics........................................................ 3
Thermal Characteristics ........................................................ 3
Functional Block Diagram ..................................................... 4
Pinout Diagram and Terminal List........................................... 5
Digital I/O............................................................................ 5
Electrical Characteristics....................................................... 6
Data Acquisition................................................................. 12
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
PINOUT DIAGRAM AND TERMINAL LIST
Terminal List Table
16 VINP
IP+
IP+
IP+
IP+
IP-
1
2
3
4
5
6
7
8
Description
Number
Name
15 VINN
I2C
SPI
14 GND
1, 2, 3, 4
IP+
IP-
Terminals for current being sensed; fused internally
Terminals for current being sensed; fused internally
13 VCC
5, 6, 7, 8
12 SDA / MISO
11 SCL / SCLK
10 DIO_0 / MOSI
9
DIO_1/CS
DIO_0/MOSI
SCL /SCLK
SDA /MISO
VCC
Digital I/O 1
Digital I/O 0
SCL
Chip Select (CS)
MOSI
IP-
10
11
12
13
14
15
16
IP-
SCLK
IP-
9
DIO_1 / CS
SDA
MISO
Device power supply terminal
Pinout Diagram
GND
Device Power and Signal ground terminal
Negative Input Voltage
VINN
VINP
Positive Input Voltage
DIGITAL I/O
The Digital I/O can be programmed to represent the following
functions (Digital Output pins are low true):
DIO_0:
DIO_1:
0. VZC: Voltage zero crossing
0. OCF: Overcurrent fault
1. OVRMS: The VRMS overvoltage flag
2. UVRMS: The VRMS undervoltage flag
3. The OR of OVRMS and UVRMS (if either flag is triggered,
the DIO_0 pin will be asserted)
1. UVRMS: The VRMS undervoltage flag
2. OVRMS: The VRMS overvoltage flag
3. The OR of OVRMS, UVRMS, and OCF_LAT [Latched
Overcurrent fault] (if any of the three flags are triggered, the
DIO_1 pin will be asserted)
ꢁꢉC
ꢊꢋꢀꢆ0
ꢀꢁꢂꢃS
ꢄꢁꢂꢃS
ꢊꢋꢀꢆ0 ꢌ ꢃꢀSꢋ
ꢃꢀSꢋ
ꢊꢋꢀꢆ0ꢆSꢍꢎꢏ0ꢐꢐ1ꢑ
CꢒꢓꢓꢆSꢍꢎ
ꢀCꢅ
ꢊꢋꢀꢆ1
ꢄꢁꢂꢃS
ꢀꢁꢂꢃS
ꢊꢋꢀꢆ1 ꢌ CS
CS
ꢀCꢅꢆꢇAꢈ
ꢊꢋꢀꢆ1ꢆSꢍꢎꢏ0ꢐꢐ1ꢑ
CꢒꢓꢓꢆSꢍꢎ
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
COMMON ELECTRICAL CHARACTERISTICS [1]: Valid through the full range of TA and VCC = VCC(nom), unless otherwise specified
Characteristic
ELECTRICAL CHARACTERISTICS
Supply Voltage
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VCC
ICC
VCC(nom) × 0.9
VCC(nom)
VCC(nom) × 1.1
V
VCC(min) ≤ VCC ≤ VCC(max), no load
on output pins
Supply Current
–
12
14
mA
VOLTAGE INPUT BUFFER
Differential Input Range
ΔVIN
VINP – VINN
–275
–
–
275
mV
V
2/3 × VCC
– 0.275
2/3 × VCC
+ 0.275
Common Mode Input Voltage
VIN(CM)
VOLTAGE CHANNEL ADC
Sample Frequency
fS
–
–
32
16
–
–
kHz
bits
Number of Bits
NADC(V)
Ratio of change on VCC to change in
ADC internal reference at DC
Voltage ADC Power Supply Rejection
V_PSRR
60
70
–
dB
VOLTAGE CHANNEL
Noise
VN
BW
ELIN
–
–
–
10
1
–
–
–
LSB
kHz
%
Internal Bandwidth
Linearity Error
±0.2
CURRENT CHANNEL ADC
Sample Frequency
Number of Bits
fS
–
–
32
16
–
–
kHz
bits
NADC(I)
Ratio of change on VCC to change in
ADC internal reference at DC
Current Channel ADC Power Supply Rejection
I_PSRR
60
70
–
dB
CURRENT CHANNEL
Internal Bandwidth
BW
RIP
VN
–
–
–
–
1
–
–
–
–
kHz
mΩ
LSB
%
Primary Conductor Resistance
Noise
TA = 25°C
0.85
100
±1.5
Linearity Error
ELIN
OVERCURRENT FAULT CHARACTERISTICS
Time from IP rising above IFAULT until
VFAULT < VFAULT(max) for a current
step from 0 to 1.2 × IFAULT; 10 kΩ and
100 pF from DIO_1 to ground;
fltdly = 0
Fault Response Time
tRF
–
5
–
μs
Internal Bandwidth
BW
–
–
200
0.05 × IPR
–
–
–
kHz
A
Fault Hysteresis [2]
IHYST
IFAULT
Fault Range
Set using FAULT field in EEPROM
0.5 × IPR
1.75 × IPR
A
VOLTAGE ZERO CROSSING
Voltage Zero Crossing Delay
td
700
µs
–
[1] Device may be operated at higher primary current levels, IP, ambient, TA, and internal leadframe temperatures, TA, provided that the Maximum Junction Temperature,
TJ(max), is not exceeded.
[2] After IP goes above IFAULT, tripping the internal fault comparator, IP must go below IFAULT – IHYST, before the internal fault comparator will reset.
Continued on next page...
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
xKMATR-I2C OPERATING CHARACTERISTICS: Valid through the full range of TA, VCC = VCC(nom), REXT = 10 kΩ,
unless otherwise specified
Characteristic
I2C INTERFACE CHARACTERISTICS [1]
Bus Free Time Between Stop and Start
Hold Time Start Condition
Setup Time for Repeated Start Condition
SCL Low Time
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
tBUF
thdSTA
tsuSTA
tLOW
tHIGH
tsuDAT
thdDAT
tsuSTO
VIL
1.3
0.6
0.6
1.3
0.6
100
0
–
–
–
–
–
–
–
–
–
–
–
µs
µs
–
µs
–
µs
SCL High Time
–
µs
Data Setup Time
–
µs
Data Hold Time
900
–
µs
Setup Time for Stop Condition
Logic Input Low Level (SDA, SCL pins)
Logic Input High Level (SDA, SCL pins)
Logic Input Current
0.6
–
µs
30
–
%VCC
%VCC
µA
VIH
70
–1
–
–
–
–
–
IIN
Input voltage on SDA or SCL = 0 V to VCC
SDA sinking = 1.5 mA
1
Output Low Voltage (SDA)
Clock Frequency (SCL pin)
Output Fall Time (SDA pin)
I2C Pull-Up Resistance
VOL
0.36
400
250
–
V
fCLK
–
kHz
ns
tf
REXT = 2.4 kΩ, CB = 100 pF
–
–
REXT
2.4
10
kΩ
Total Capacitive Load for Each of SDA and
SCL Buses
CB
–
–
20
pF
[1] These values are ratiometric to the supply voltage, I2C Interface Characteristics are ensured by design and not factory tested.
tsuDAT
tsuSTA thdSTA
tBUF
thdDAT
tsuSTO
SDA
SCL
tLOW
tHIGH
Figure 2: I2C Interface Timing
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
xKMATR-SPI OPERATING CHARACTERISTICS: Valid through the full range of TA, VCC = VCC(nom), unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
SPI INTERFACE CHARACTERISTICS
MOSI, SCLK, CS pins, VCC (nom) = 3.3 V
MOSI, SCLK, CS pins, VCC (nom) = 5 V
MOSI, SCLK, CS pins
2.8
4
–
–
–
3.63
5.5
V
V
V
Digital Input High Voltage
Digital Input Low Voltage
VIH
VIL
–
0.5
MISO pin, CL = 20 pF, TA = 25°C,
VCC (nom) = 3.3 V
2.8
4
3.3
5
3.8
5.5
V
V
SPI Output High Voltage
VOH
MISO pin, CL = 20 pF, TA = 25°C,
VCC (nom) = 5 V
SPI Output Low Voltage
SPI Clock Frequency
SPI Frame Rate
VOL
fSCLK
tSPI
MISO pin, CL = 20 pF, TA = 25°C
MISO pin, CL = 20 pF
–
0.3
–
0.5
10
V
0.1
5.8
MHz
kHz
–
588
Time from CS going low to SCLK falling
edge
Chip Select to First SCLK Edge
tCS
50
–
–
ns
Data Output Valid Time
MOSI Setup Time
MOSI Hold Time
tDAV
tSU
Data output valid after SCLK falling edge
Input setup time before SCLK rising edge
Input hold time after SCLK rising edge
–
40
–
–
–
–
ns
ns
ns
25
50
tHD
–
Hold SCLK high time before CS rising
edge
SCLK to CS Hold Time
Load Capacitance
tCHD
CL
5
–
–
–
–
ns
Loading on digital output (MISO) pin
20
pF
Figure 3: SPI Timing
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
ACS71020KMA-015B5 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range, TA = –40°C to 125°C,
BYPASS = 0.1 µF, and VCC = 5 V, unless otherwise specified
C
Characteristic
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
GENERAL CHARACTERISTICS
Nominal Supply Voltage
V
CC (nom)
–
5
–
V
NOMINAL PERFORMANCE – CURRENT CHANNEL
Current Sensing Range
Sensitivity
IPR
–15
–
–
15
–
A
Sens(I)
IPR (min) < IP < IPR (max)
2184
LSB/A
ACCURACY PERFORMANCE – CURRENT CHANNEL
Measured at IP = IPR (max), TA = 25°C to 125°C
Measured at IP = IPR (max), TA = –40°C to 25°C
–
–
±2
±3
–
–
%
%
Total Output Error
ETOT(I)
TOTAL OUTPUT ERROR COMPONENTS – CURRENT CHANNEL
Measured at IP = IPR (max), TA = 25°C to 125°C
Measured at IP = IPR (max), TA = –40°C to 25°C
IP = 0 A, TA = 25°C to 125°C
–
–
–
–
±1
–
–
–
–
%
%
Sensitivity Error
Offset Error
ESENS(I)
±1.5
±300
±500
LSB
LSB
EO(I)
IP = 0 A, TA = –40°C to 25°C
NOMINAL PERFORMANCE – VOLTAGE CHANNEL
Sensitivity Sens(V)
VPR (min) < VP < VPR (max)
–
238
–
LSB/mV
ACCURACY PERFORMANCE – VOLTAGE CHANNEL
Measured at VP = VPR (max), TA = 25°C to 125°C
Measured at VP = VPR (max), TA = –40°C to 25°C
–
–
±1.2
±1.3
–
–
%
%
Total Output Error
ETOT(V)
TOTAL OUTPUT ERROR COMPONENTS – VOLTAGE CHANNEL
Measured at VP = VPR (max), TA = 25°C to 125°C
Measured at VP = VPR (max), TA = –40°C to 25°C
VP = 0 mV, TA = 25°C to 125°C
–
–
–
–
±1
±1
–
–
–
–
%
%
Sensitivity Error
Offset Error
ESENS(V)
±100
±150
LSB
LSB
EO(V)
VP = 0 mV, TA = –40°C to 25°C
ACCURACY PERFORMANCE – ACTIVE POWER
Measured at VP = VPR (max), TA = 25°C to 125°C
Measured at VP = VPR (max), TA = –40°C to 25°C
–
–
±2.3
±3.3
–
–
%
%
Total Output Error
ETOT(P)
[1] Typical values are based on mean ±3 sigma.
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
ACS71020KMA-030B3 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range, TA = –40°C to 125°C,
CBYPASS = 0.1 µF, and VCC = 3.3 V, unless otherwise specified
Characteristic
GENERAL CHARACTERISTICS
Nominal Supply Voltage
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
V
CC (nom)
–
3.3
–
V
NOMINAL PERFORMANCE – CURRENT CHANNEL
Current Sensing Range
Sensitivity
IPR
–30
–
–
30
–
A
Sens(I)
IPR (min) < IP < IPR (max)
1092
LSB/A
ACCURACY PERFORMANCE – CURRENT CHANNEL
Measured at IP = IPR (max), TA = 25°C to 125°C
Measured at IP = IPR (max), TA = –40°C to 25°C
–
–
±2
±3
–
–
%
%
Total Output Error
ETOT(I)
TOTAL OUTPUT ERROR COMPONENTS – CURRENT CHANNEL
Measured at IP = IPR (max), TA = 25°C to 125°C
Measured at IP = IPR (max), TA = –40°C to 25°C
IP = 0 A, TA = 25°C to 125°C
–
–
–
–
±1
–
–
–
–
%
%
Sensitivity Error
Offset Error
ESENS(I)
±1.5
±500
±700
LSB
LSB
EO(I)
IP = 0 A, TA = –40°C to 25°C
NOMINAL PERFORMANCE – VOLTAGE CHANNEL
Sensitivity Sens(V)
VPR (min) < VP < VPR (max)
–
238
–
LSB/mV
ACCURACY PERFORMANCE – VOLTAGE CHANNEL
Measured at VP = VPR (max), TA = 25°C to 125°C
Measured at VP = VPR (max), TA = –40°C to 25°C
–
–
±1.2
±1.3
–
–
%
%
Total Output Error
ETOT(V)
TOTAL OUTPUT ERROR COMPONENTS – VOLTAGE CHANNEL
Measured at VP = VPR (max), TA = 25°C to 125°C
Measured at VP = VPR (max), TA = –40°C to 25°C
VP = 0 mV, TA = 25°C to 125°C
–
–
–
–
±1
±1
–
–
–
–
%
%
Sensitivity Error
Offset Error
ESENS(V)
±60
±80
LSB
LSB
EO(V)
VP = 0 mV, TA = –40°C to 25°C
ACCURACY PERFORMANCE – ACTIVE POWER
Measured at VP = VPR (max), TA = 25°C to 125°C
Measured at VP = VPR (max), TA = –40°C to 25°C
–
–
±2.3
±3.3
–
–
%
%
Total Output Error
ETOT(P)
[1] Typical values are based on mean ±3 sigma.
10
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
ACS71020KMA-090B3 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range, TA = –40°C to 125°C,
BYPASS = 0.1 µF, and VCC = 3.3 V, unless otherwise specified
C
Characteristic
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
GENERAL CHARACTERISTICS
Nominal Supply Voltage
V
CC (nom)
–
3.3
–
V
NOMINAL PERFORMANCE – CURRENT CHANNEL
Current Sensing Range
Sensitivity
IPR
–90
–
–
90
–
A
Sens(I)
IPR (min) < IP < IPR (max)
364
LSB/A
ACCURACY PERFORMANCE – CURRENT CHANNEL
Measured at IP = IPR (max), TA = 25°C to 125°C
Measured at IP = IPR (max), TA = –40°C to 25°C
–
–
±2
±3
–
–
%
%
Total Output Error
ETOT(I)
TOTAL OUTPUT ERROR COMPONENTS – CURRENT CHANNEL
Measured at IP = IPR (max), TA = 25°C to 125°C
Measured at IP = IPR (max), TA = –40°C to 25°C
IP = 0 A, TA = 25°C to 125°C
–
–
–
–
±1
–
–
–
–
%
%
Sensitivity Error
Offset Error
ESENS(I)
±1.5
±300
±500
LSB
LSB
EO(I)
IP = 0 A, TA = –40°C to 25°C
NOMINAL PERFORMANCE – VOLTAGE CHANNEL
Sensitivity Sens(V)
VPR (min) < VP < VPR (max)
–
238
–
LSB/mV
ACCURACY PERFORMANCE – VOLTAGE CHANNEL
Measured at VP = VPR (max), TA = 25°C to 125°C
Measured at VP = VPR (max), TA = –40°C to 25°C
–
–
±1.2
±1.3
–
–
%
%
Total Output Error
ETOT(V)
TOTAL OUTPUT ERROR COMPONENTS – VOLTAGE CHANNEL
Measured at VP = VPR (max), TA = 25°C to 125°C
Measured at VP = VPR (max), TA = –40°C to 25°C
VP = 0 mV, TA = 25°C to 125°C
–
–
–
–
±1
±1
–
–
–
–
%
%
Sensitivity Error
Offset Error
ESENS(V)
±100
±150
LSB
LSB
EO(V)
VP = 0 mV, TA = –40°C to 25°C
ACCURACY PERFORMANCE – ACTIVE POWER
Measured at VP = VPR (max), TA = 25°C to 125°C
Measured at VP = VPR (max), TA = –40°C to 25°C
–
–
±2.3
±3.3
–
–
%
%
Total Output Error
ETOT(P)
[1] Typical values are based on mean ±3 sigma.
11
Allegro MicroSystems, LLC
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
DATA ACQUISITION
ADCs
Phase Compensation
Both the Current and Voltage channels are sampled at a high
Phase delay may be introduced on either the voltage or current
frequency and then digitally filtered and decimated to avoid large channels. The range is EEPROM selectable, either 5° of delay
anti-aliasing filters. The final sample rate will be near 32 kHz for
an 8 MHz clock. The digital low-pass filters are EEPROM pro-
grammable and have a cutoff from 1 to 8 kHz. The digital word
from the ADC is 16 bits for both the current and the voltage.
(step size of 0.67°) or 40° of delay (step size of 5.36°).
Zero Crossing
The zero crossings are only detected on the voltage signal. Both
the high-to-low and low-to-high transitions will be detected
with time-based hysteresis that removes the possibility of noise
causing multiple zero crossings to be reported at each true zero
crossing.
Raw Signal Sensitivity and Offset Trim
The gain and offset for both current and voltage channels use a
shared temperature compensation engine which is trimmed in
production. The fine sensitivity and offset are also trimmed in
production at the factory; however, the user has access to the fine
sensitivity field for the current channel should they want to trim
the gain in application.
The zero crossing output can be a square wave that transitions
at each zero crossing or a pulse with a fixed width at each zero
crossing. When in pulse mode, the width of the pulse is tP (see
delaycnt_sel; nominal setting is 32 µs). There will be a fixed
delay, tD, from the time that a true zero crossing has occurred
to the time that it is reported. This delay helps to keep the zero
crossing detection more precise.
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢓC
ꢇꢈꢉꢊꢃ
ꢋꢊꢂꢌꢆ
ꢍꢁꢎꢆ
ꢃꢋ
ꢃꢔ
Sꢏꢊꢄꢐꢆ
ꢑꢄꢒꢆ
ꢍꢁꢎꢆ
Figure 4: Zero Crossing
12
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
POWER CALCULATIONS
Reactive Power
IRMS / VRMS
Cycle by cycle calculation of the root mean square of both the
current and voltage channels:
Imaginary component of power being measured; calculated at the
end of each cycle:
n = N – 1 In
∑
n = N – 1Vn
2
2
2
ꢀ ꢁ ꢂ2 ꢃ ꢄꢅCꢆꢇꢈꢉ
∑
n = 0
n = 0
IRMS
=
VRMS =
N
N
Power Factor
where In (Icodes) and Vn (Vcodes) are the instantaneous mea-
surements of current and voltage, respectively.
The magnitude of the ratio of real power to apparent power;
calculated at the end of each cycle:
Apparent Power
PACTIVE
|PF| =
|S|
The magnitude of the complex power being measured; calculated
at the end of each cycle:
|S| = IRMS × VRMS
Lead/Lag
The voltage leading or lagging the current will be communicated
as a single bit. This bit also represents the sign of the Reactive
Active Power
The real component of power being measured; calculated cycle
by cycle:
Power.
∑
n = N – 1 Pn
n = 0
PACTIVE
=
Pn = In × Vn
N
ꢀ ꢅ ꢃ 2 ꢆ ꢄ 2
Ф
Actiꢁe Power, ꢃ = ꢁꢂ cosФ
Figure 5: Power Triangle
13
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
number, rms_avg_1, is used to determine the number of averages.
There is an additional accumulator that will be used to average
Overcurrent Fault
The overcurrent fault threshold may be set from 50% to 175% of
IP. The user sets the trip point with an 8-bit word. The user also
has the ability to set the trip level digital delay. This allows for up
to a 32 µs delay on the Fault.
the output of the first accumulator. There is a 10-bit number, rms_
avg_2, that will be used to determine the number of averages for
this accumulator. The combination of the two accumulator allows
the user to select how long to average for as well as how often the
values are updated. The exact time this averages over depends on
n (the number of samples per cycle). Averages could be read in
Reg 0x26 to 0x29.
Averaging Over Time
IRMS or VRMS and PACTIVE may be averaged over a program-
mable number of updates. Note that either VMRS and IRMS can
be averaged, not both.
Over/Undervoltage Detection
There are two flags that can be used to detect undervoltage and
overvoltage. These flags have a programmable voltage trip level.
Refer to the Digital I/O section for all possible configurations.
The number of averages is controlled by two different registers.
There is an accumulator that averages the above values. A 7-bit
Ac�ve Power Averaging
pinstant
Averaging Block 1
Averaging Block 2
RMS Calcula�ons
rms_avg_1
rms_avg_2
vcodes
RMS Calcula�on
n
Averaging Block 1
Averaging Block 2
icodes
RMS Calcula�on
VRMS/IRMS Averaging
iavgselen
Figure 6: ACS71020 Trim Diagram
14
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
DIGITAL COMMUNICATION
Communication Interfaces
Registers and EEPROM
The ACS71020 supports communication over 1 MHz I2C and
10 MHz SPI. However, the communication protocol is fixed dur-
ing factory programming. Refer to the Selection Guide for more
information.
WRITE ACCESS
The ACS71020 supports factory and customer EEPROM space as
well as volatile registers. The customer access code must be sent
prior to writing these customer EEPROM spaces. In addition, the
device includes a set of free space EEPROM registers that are
accessible with or without writing the access code.
SPI
The SPI frame consists of:
READ ACCESS
• The Master writes on the MOSI line the 7-bit address of the
register to be read from or written to.
All EEPROM and volatile registers may be read at any time
regardless of the access code.
• The next bit on the MOSI line is the read/write (RW) indicator.
A high state indicates a Read and a low state indicates a Write.
EEPROM
• The device sends a 32-bit response on the MISO line. The
contents correspond to the previous command.
At power up all shadow registers are loaded from EEPROM
including all configuration parameters. The shadow registers can
be written to in order to change the device behavior without hav-
ing to perform an EEPROM write. Any changes made it shadow
memory are volatile and do not persist through a reset event.
• On the MOSI line, if the current command is a write, the 32
bits correspond to the Write data, and in the case of a read, the
data is ignored.
WRITING
The Timing Diagram for an EEPROM write is shown in Figure 7
and Figure 8.
CSN
SCLK
0
1
5
6
0
1
30
31
REGISTER ADDRESS
RW
WRITE DATA OR DC
MOSI
MISO
PREVIOUS CMD DATA
Figure 7: EEPROM Write – SPI Mode
SDA
SA[6:0]
A[6:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
ST
Slave W A 0 Register A Register A Register A Register A Register A SP
address
C
K
address C Data
[7:0]
C
K
Data
[15:8]
C
K
Data
[23:16]
C
K
Data
[31:24]
C
K
K
Figure 8: EEPROM Write – I2C Mode
Blue represents data sent by the master and
orange is the data sent by the slave.
15
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
READING
The timing diagram for an EEPROM read is shown in Figure 9
and Figure 10.
CSN
SCLK
0
1
5
6
0
1
30
31
REGISTER ADDRESS
RW
WRITE DATA OR DC
MOSI
MISO
PREVIOUS CMD DATA
Figure 9: EEPROM Read – SPI Mode
For SPI, the read data will be sent out
during the above command.
SA[6:0]
A[6:0]
SA[6:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
SDA
ST
Slave W A 0 Register A ST
Slave R A Register A Register A Register A Register N SP
address
C
K
address C
address
C
K
Data
[7:0]
C
K
Data
[15:8]
C
K
Data
[23:16]
C
K
Data
[31:24]
A
C
K
K
Figure 10: EEPROM Read – I2C Mode
Blue represents data sent by the master and
orange is the data sent by the slave.
16
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
EEPROM Error Checking and Correction (ECC)
EEPROM ECC Errors
Hamming code methodology is implemented for EEPROM
checking and correction (ECC). ECC is enabled after power-up.
Bits
Name
Description
31:28
–
No meaning
The ACS71020 analyzes message data sent by the controller and
the ECC bits are added. The first 6 bits sent from the device to
the controller are dedicated to ECC. The device always returns 32
bits.
00 = No Error
01 = Error detected and message corrected
10 = Uncorrectable error
11 = No meaning
27:26
25:0
ECC
D[25:0]
EEPROM data
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
MEMORY MAP
EEPROM/Shadow Memory
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x0B
0x0C
ECC
ECC
crs_sns
sns_fine
qvo_fine
n
rms_avg_2
rms_avg_1
pacc_trim
0x0D
ECC
fltdly
fault
0x0E
0x0F
ECC
ECC
undervreg
overvreg
vevent_cycs
i2c_slv_addr
0x1B
0x1C
crs_sns
sns_fine
qvo_fine
n
rms_avg_2
rms_avg_1
0x1D
fltdly
fault
pacc_trim
0x1E
0x1F
undervreg
overvreg
vevent_cycs
i2c_slv_addr
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Device Trim Flow
The trim process for voltage, current, and power channels are
depicted in Figure 11 through Figure 13. Refer to the “Register
Details” Section for more information regarding trim fields.
Gain Trim
Delay
Offset Trim
Satura�on
adc_out_v
Z-x
+
+
vcodes
VchanGainSel
ichan_del_en
vqvo
+
+
Factory
Trim
chan_del_sel
vqvo_tc
Figure 11: Voltage Channel Trim Flow
Delay
Offset Trim
Gain Trim
Satura�on
adc_out_i
Z-x
+
+
icodes
ichan_del_en
qvo_fine
+
+
sns_fine
qvo_tc
chan_del_sel
Factory
Trim
sns_tc
Figure 12: Current Channel Trim Flow
Offset Trim
pac�ve_int
+
+
pac�ve
pacc_trim
Figure 13: Power Channel Trim Flow
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register Details – EEPROM
Register 0x0B/0x1B
Bits
8:0
Name
qvo_fine
sns_fine
crs_sns
iavgselen
unused
ecc
Description
Offset fine trimming on current channel
Fine gain trimming on the current channel
Coarse gain setting
17:9
20:18
21
Current Averaging selection
Unused
25:22
31:26
Error Code Correction
qvo_fine
crs_sns
Offset adjustment for the current channel. This is a signed
9-bit number with an input range of –256 to 255. With a step
size of 64 LSB, this equates to an offset trim range of –16384
to 16320 LSB, which is added to the icodes value. The trim is
implemented as shown in Figure 12. The current channel’s offset
trim should be applied before the gain is trimmed. “qvo_fine” is
further described in Table 1.
Coarse gain adjustment for the current channel. This gain is
implemented in the analog domain before the ADC. This is a
3-bit number that allows for 8 gain selections. Adjustments to
“crs_sns” may impact the device’s performance over temperature.
Datasheet limits apply only to the factory settings for “crs_sns”.
The gain settings map to 1×, 2×, 3×, 3.5×, 4×, 4.5×, 5.5×, and 8×.
“crs_sns” is further described in Table 3.
Table 1: qvo_fine
Table 3: crs_sns
Range
Value
Units
Range
Value
1×
Units
–256 to 255
–16,384 to 16,320
LSB
0
1
2
3
4
5
6
7
–
–
–
–
–
–
–
–
2×
sns_fine
3×
Gain adjustment for the current channel. This is a signed 9-bit
number with an input range of –256 to 255. This gain adjustment
is implemented as a percentage multiplier centered around 1 (i.e.
writing a 0 to this field multiplies the gain by 1, leaving the gain
unaffected). The fine sensitivity parameter ranges from 50% to
150% of IP. The current channel’s offset trim should be applied
before the gain is trimmed. “sns_fine” is further described in
Table 2.
3.5×
4×
4.5×
5.5×
8×
iavgselen
Current Averaging selection enable. 0 will select vrms for averag-
ing. 1 will select irms for averaging. See Figure 6.
Table 2: sns_fine
Range
Value
Units
–256 to 255
50 to 100
%
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register 0x0C/0x1C
Bits
6:0
Name
rms_avg_1
rms_avg_2
n
Description
Average of the rms voltage or current – stage 1
Average of the rms voltage or current – stage 2
Number of samples per half period.
Error Code Correction
16:7
25:17
31:26
ecc
rms_avg_1
n
Number of averages for the first averaging stage (vrmsavgonesec This is the number of samples to be used in all rms calcula-
or irmsavgonesec). The value written into this field directly maps tions if the “bypass n enable” bit (bypass_n_en) is set. is set. If
to the number of averages ranging from 0 to 127. The channel to
be averaged is selected by the “current average select enable” bit
(iavgselen). “rms_avg_1” is further described in Table 4.
bypass_n_en is 0 (Reg 0x0E), then this field is unused. The value
written into this field directly maps to the number of samples
ranging from 0 to 511. “n” is further described in Table 6.
Table 4: rms_avg_1
Table 6: n
Range
Value
Units
Range
Value
Units
0 to 127
0 to 127
number of averages
0 to 511
0 to 511
number of samples
rms_avg_2
Number of averages for the second averaging stage (vrmsavgo-
nemin or irmsavgonemin). This stage averages the outputs of the
first averaging stage. The value written into this field directly maps
to the number of averages ranging from 0 to 1023. The channel to
be averaged is selected by the “current average select enable” bit
(iavgselen). “rms_avg_2” is further described in Table 5.
Table 5: rms_avg_2
Range
Value
Units
0 to 1023
0 to 1023
number of averages
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register 0x0D/0x1D
Bits
6:0
Name
pacc_trim
ichan_del_en
unused
Description
Trims the active power
7
Enable phase delay on voltage or current channel
8
unused
11:9
12
chan_del_sel
unused
Sets phase delay on voltage or current channel
unused
20:13
23:21
24
fault
Sets the overcurrent fault threshold
fltdly
Sets the overcurrent fault delay
halfcycle_en
Outputs pulses at every zero crossing when enabled, and every rising edge when disabled
25
squarewave_en Selects pulse or square wave output for the zero crossing reporting
ecc Error Code Correction
31:26
pacc_trim
fault
Offset trim in the active power calculation, and is implemented
as shown in Figure 13. This is a signed 7-bit number with an
input range of –64 to 63. This equates to a trim range of –384 to
378 LSB, which is added to the “pactive” value. “pacc_trim” is
further described in Table 7.
Overcurrent fault threshold. This is an usigned 8-bit number with
an input range of 0 to 255, which equates to a fault range of 50%
to 175% of IP. The factory setting of this field is 0. “fault” is
further described in Table 10.
Table 10: fault
Table 7: pacc_trim
Range
Value
Units
Range
Value
Units
0 to 255
50 to 175
% of IP
–64 to 63
–384 to 378
LSB
fltdly
ichan_del_en
Fault delay setting of the amount of delay applied before flagging
a fault condition. “fltdly” is further described in Table 11.
Enables delay for either the voltage or current channel. Setting to 1
enables delay for the current channel. This behavior is depicted in Fig-
ure 11 and Figure 12. “ichan_del_en” is further described in Table 8.
Table 11: fltdly
Range
Value
0
Units
µs
Table 8: ichan_del_en
0
1
2
3
4
5
6
7
Range
Value
Units
LSB
0
µs
0
1
0 – voltage channel
1 – current channel
4.75
9.25
13.75
18.5
23.25
27.75
µs
LSB
µs
µs
chan_del_sel
µs
Sets the amount of delay applied to the voltage or current channel (set
by ichan_del_en). The step size of this field is determined by the value
of vadc_rate_sel. “chan_del_sel” is further described in Table 9.
µs
µs
halfcycle_en
Table 9: chan_del_sel
vadc_rate_sel
Range
0 to 7
0 to 7
Value
Units
µs
Setting for the voltage zero-crossing detection. When set to 0,
the voltage zero-crossing will be indicated on every rising edge.
When set to 1, the voltage zero-crossing will be indicated on both
rising and falling edges.
0
1
0 to 219
0 to 875
µs
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
squarewave_en
Setting for the Voltage Zero-Crossing Detection. When set to 0,
the zero-crossing event will be indicated by a pulse on the DIO
pin. When set to 1, the zero-crossing event will be indicated by a
level change on the DIO pin. Note that the device must be config-
ured to report Voltage-Zero-Crossing detection on the DIO pin.
23
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register 0x0E/0x1E
Bits
5:0
6
Name
Description
vevent_cycs
vadc_rate_set
bypass_n_en
Sets the number of qualifying cycles needed to flag overvoltage or undervoltage
Sample Frequency Selection
7
When enabled, the dynamic calibration of n is ignored and
instead uses the programmed n value for computations
13:8
19:14
20
overvreg
undervreg
delaycnt_sel
unused
Sets the overvoltage fault threshold
Sets the undervoltage fault threshold
Sets the width of the voltage zero-crossing output pulse
Unused
25:21
31:26
ecc
Error Code Correction
vevent_cycs
overvreg
Sets the number of cycles required to assert the OVRMS flag
or the UVRMS. This is an unsigned 6-bit number with an input
Sets the threshold of the overvoltage rms flag (ovrms). This is a
6-bit number ranging from 0 to 63. This trip level spans the entire
range of 0 to 63. The value in this field directly maps to the num- range of the vrms register. The flag is set if the rms value is above
ber of cycles. “vevent_cycs” is further described in Table 12.
this threshold for the number of cycles selected in vevent_cycs.
“overvreg” is further described in Table 14.
Table 12: vevent_cycs
Table 14: overvreg
Range
Value
Units
Range
Value
Units
0 to 63
1 to 64
cycles
0 to 63
0 to 32,768
LSB
vadc_rate_set
undervreg
Sets the threshold of the undervoltage rms flag (uvrms). This is
Sets the voltage ADC update rate. Setting this field to a 0 selects
a 32 kHz update. Setting this field to a 1 selects an 8 kHz update,
which will reduce the number of samples used in each rms calcu- a 6-bit number ranging from 0 to 63. This trip level spans one
lation, but will allow for a larger phase delay correction between
channels (see chan_del_sel). “vadc_rate_set” is further described
in Table 13.
entire range of the vrms register. The flag is set if the rms value is
below this threshold for the number of cycles selected in vevent_
cycs. “undervreg” is further described in Table 15.
Table 13: vadc_rate_set
Table 15: undervreg
Range
Value
32
Units
kHz
Range
Value
Units
0
1
0 to 63
0 to 32,768
LSB
8
kHz
delaycnt_sel
bypass_n_en
Selection bit for the width of pulse for a voltage zero-crossing
event. When set to 0, the pulse is 32 µs. When set to 1, the
pulse is 256 µs. When the squarewave_en bit is set, this field is
ignored. “delaycnt_sel” is further described in Table 16.
When enabled, the dynamic calibration of n is ignored and
instead uses the programmed n value for computations.
Table 16: delaycnt_sel
Range
Value
32
Units
µs
0
1
256
µs
24
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register 0x0F/0x1F
Bits
1:0
Name
unused
Description
Unused
8:2
i2c_slv_addr
I2C slave address selection
9
i2c_dis_slv_addr Disable I2C slave address selection circuit
15:10
17:16
19:18
25:20
31:26
unused
dio_0_sel
dio_1_sel
unused
ecc
Unused
Digital output 0 multiplexor selection bits
Digital output 1 multiplexor selection bits
Unused
Error Code Correction
i2c_slv_addr
i2c_dis_slv_addr
Settings for the I2C Slave Address. The Voltage on the DIO pins
are measured at power and are used to set the device’s slave
address.
Enables or disables the analog I2C slave address feature at power
on. When this bit is set, the I2C slave address will map directly to
i2c_slv_addr.
Each DIO pin has 4 voltage “bins” which may be used to set
the I2C slave address. These voltages may be set using resistor
divider circuits from VCC to Ground. “i2c_slv_addr” is further
described in Table 17.
dio_0_sel
Determines which flags are output on the DIO0 pin. Only used
when the device is in I2C programming mode. “dio_0_sel” is
further described in Table 18.
Table 17: i2c_slv_addr
Table 18: dio_0_sel
Slave Address
(decimal)
DIO_1
DIO_0
A6
A5
A4
A3
A2
A1
A0
Value
Selection
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
96
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
97
0
1
2
3
VZC: Voltage zero crossing
OVRMS: The VRMS overvoltage flag
UVRMS: The VRMS undervoltage flag
1
1
0
0
0
1
0
98
1
1
0
0
0
1
1
99
1
1
0
0
1
0
0
100
1
1
0
0
1
0
1
101
The OR of OVRMS and UVRMS (if either flag is
triggered, the DIO_0 pin will be asserted)
1
1
0
0
1
1
0
102
1
1
0
0
1
1
1
103
1
1
0
1
0
0
0
104
1
1
0
1
0
0
1
105
dio_1_sel
1
1
0
1
0
1
0
106
1
1
0
1
0
1
1
107
Determines which flags are output on the DIO1 pin. Only used
when the device is in I2C programming mode. “dio_1_sel” is
further described in Table 19.
1
1
0
1
1
0
0
108
109
1
1
0
1
1
0
1
1
1
0
1
1
1
0
110
EE
EE
EE
EE
EE
EE
EE
EEPROM value
Table 19: dio_1_sel
Value
Selection
0
1
2
3
OCF: Overcurrent fault
UVRMS: The VRMS undervoltage flag
OVRMS: The VRMS overvoltage flag
The OR of OVRMS, UVRMS, and OCF (if any of
the three flags are triggered, the DIO_0 pin will be
asserted).
Ratio of VCC on DIO Pin
25
Allegro MicroSystems, LLC
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Volatile Memory
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
irms
vrms
pactive
papparent
pimag
pfactor
numptsout
irmsavgonesec
irmsavgonemin
vrmsavgonesec
vrmsavgonemin
pactavgonesec
pactavgonemin
vcodes
icodes
pinstant
0x2D
0x2E
0x2F
access_code
0x30
0x31
26
Allegro MicroSystems, LLC
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register Details – Volatile
Register 0x20
Bits
14:0
Name
vrms
irms
Description
Voltage RMS value
Current RMS value
30:16
vrms
irms
RMS voltage output. This field is an unsigned 15-bit fixed point
number with 15 fractional bits. It ranges from 0 to ~1 with a step
RMS current output. This field is an unsigned 15-bit fixed point
number with 14 fractional bits. It ranges from 0 to ~2 with a step
size of 1/215. This number should be multiplied by the overall full size of 1/214. This number should be multiplied by the overall full
scale of the voltage path in order to get to volts. For example, the
device is trimmed to a full scale input of 275 mV, and if a resis-
tor divider network is used to create 275 mV when it has 250 V
across it, then the multiplier should be 250 V. “vrms” is further
described in Table 20.
scale of the current path in order to get to amps. For example, if
the device is trimmed to a full scale input of 30 A, then the multi-
plier should be 30 A. “irms” is further described in Table 21.
Table 21: irms
Range
Value
Units
Table 20: vrms
0 to ~2
[0 to ~2] × IPR(MAX)
A
Range
Value
Units
0 to ~1
[0 to ~1] × ΔVIN(MAX)
V
Register 0x21
Bits
Name
pactive
Description
16:0
Active power
pactive
Active power output. This field is a signed 17-bit fixed point
number with 15 fractional bits. It ranges from -2 to ~2 with a step
size of 1/215. This number should be multiplied by the overall
full-scale power in order to get to watts. For example, if full-scale
voltage is 250 V and IPR is 30 A, the multiplier will be 7500 W.
“pactive” is further described in Table 22.
Table 22: pactive
Range
Value
Units
–2 to ~2
[–2 to ~2] × MaxPow
W
27
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register 0x22
Bits
Name
Description
15:0
papparent
Apparent power
papparent
Apparent power output. This field is an unsigned 16-bit fixed
point number with 15 fractional bits. It ranges from 0 to ~2 with
a step size of 1/215. This number should be multiplied by the
overall full-scale power in order to get to VA. For example, if full
scale voltage is 250 V and IPR is 30 A, then the multiplier will be
7500 VA. “papparent” is further described in Table 23.
Table 23: papparent
Range
Value
Units
0 to ~2
[0 to ~2] × MaxPow
VA
Register 0x23
Bits
Name
pimag
Description
16:0
Reactive power
pimag
Reactive power output. This field is an unsigned 17-bit fixed
point number with 16 fractional bits. It ranges from 0 to ~2 with
a step size of 1/216. This number should be multiplied by the
overall full-scale power in order to get to VAR. For example, if
full-scale voltage is 250 V and IPR is 30 A, then the multiplier
will be 7500 VAR. “pimag” is further described in Table 24.
Table 24: pimag
Range
Value
Units
0 to ~2
[0 to ~2] × MaxPow
VAR
28
Allegro MicroSystems, LLC
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register 0x24
Bits
Name
Description
10:0
pfactor
Power factor
pfactor
Power factor output. This field is an unsigned 9-bit fixed point
number with 9 fractional bits. It ranges from 0 to ~1 with a step
size of 1/29. “pfactor” is further described in Table 25.
Table 25: pfactor
Range
Value
Units
0 to ~1
0 to ~1
–
Register 0x25
Bits
Name
numptsout
Description
8:0
Number of samples of current and voltage used for calculations
numptsout
Number of points used in the rms calculation. If bypass_n_en is
not set, then this will be the dynamic value that is evaluated inter-
nal to the device based on zero crossings of the voltage channel.
If bypass_n_en is set to 1, then this will be the same as the value
in the n field. “numptsout” is further described in Table 26.
Table 26: numptsout
Range
Value
Units
0 to 255
0 to 255
–
29
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register 0x26
Bits
Name
Description
14:0
vrmsavgonesec Averaged voltage RMS value – duration set by rms_avg_1 –
This register will be zero if iavgselen = 1
30:16
irmsavgonesec
Averaged current RMS value – duration set by rms_avg_1 –
This register will be zero if iavgselen = 0
vrmsavgonesec
irmsavgonesec
Voltage RMS value averaged according to rms_avg_1. This regis- Current RMS value averaged according to rms_avg_1. This regis-
ter will be zero if iavgselen = 1.
ter will be zero if iavgselen = 0.
Register 0x27
Bits
Name
Description
14:0
vrmsavgonemin Averaged voltage RMS value – duration set by rms_avg_2 – This register will be zero if
iavgselen = 1
30:16
irmsavgonemin
Averaged current RMS value – duration set by rms_avg_2 – This register will be zero if
iavgselen = 0
vrmsavgonemin
irmsavgonemin
Voltage RMS value averaged according to rms_avg_2. This regis- Current RMS value averaged according to rms_avg_2. This regis-
ter will be zero if iavgselen = 1.
ter will be zero if iavgselen = 0.
Register 0x28
Bits
Name
Description
Active Power value averaged over up to one second — duration set by rms_avg_1
16:0
pactavgs
pactavgs
Active power value averaged according to rms_avg_1.
Register 0x29
Bits
Name
Description
16:0
pactavgm
Active Power value averaged over up to one minute — duration set by rms_avg_2
pactavgm
Active power value averaged according to rms_avg_2.
30
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register 0x2A
Bits
Name
Description
16:0
vcodes
Instantaneous voltage measurement
vcodes
This field contains the instantaneous voltage measurement before
any rms calculations are done. It is a 17-bit signed fixed point
number with 16 fractional bits. It ranges from –1 to ~1 with a step
size of 1/216. This number should be multiplied by the overall full
scale of the voltage path in order to get volts. For example, the
device is trimmed to a full-scale input of 275 mV, and if a resis-
tor divider network is used to create 275 mV, when it has 250 V
across it, then the multiplier should be 250 V. “vcodes” is further
described in Table 27.
Table 27: vcodes
Range
Value
Units
–1 to ~1
[–1 to ~1] × ΔVIN(MAX)
V
Register 0x2B
Bits
Name
icodes
Description
16:0
Instantaneous current measurement
icodes
This field contains the instantaneous current measurement before
any rms calculations are done. This field is a signed 17-bit fixed
point number with 15 fractional bits. It ranges from –2 to ~2
with a step size of 1/215. This number should be multiplied by
the overall full scale of the current path in order to get amps. For
example, the device is trimmed to a full-scale input of 30 A, then
the multiplier should be 30 A. “icodes” is further described in
Table 28.
Table 28: icodes
Range
Value
Units
–2 to ~2
[–2 to ~2] × IPR(MAX)
A
31
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register 0x2C
Bits
Name
Description
31:0
pinstant
Instantaneous power – Multiplication of Vcodes and Icodes
pinstant
This field contains the instantaneous power measurement before
any rms calculations are done. This field is a signed 32-bit fixed
point number with 30 fractional bits. It ranges from –2 to ~2 with
a step size of 1/230. This number should be multiplied by the
overall full-scale power in order to get to watts. For example, if
full scale voltage is 250 V and IPR is 30 A, then the multiplier will
be 7500 W. “pinstant” is further described in Table 29.
Table 29: pinstant
Range
Value
Units
–2 to ~2
[-2 to ~2] × MaxPow
W
Register 0x2D
Bits
0
Name
Description
vzerocrossout
faultout
Voltage zero-crossing output
Current fault output
1
2
faultlatched
overvoltage
undervoltage
posangle
Current fault output latched
Overvoltage flag
3
4
Undervoltage flag
5
Sign of the power angle
Sign of the power factor
6
pospf
vzerocrossout
overvoltage
Flag for the voltage zero-crossing events. Will be present and
active regardless of DIO_0_Sel and DIO_1_Sel. This flag will
still follow the halfcycle_en and squarewave_en settings.
Flag for the overvoltage events. Will be present and active
regardless of DIO_0_Sel and DIO_1_Sel. Will only be set when
fault is present.
faultout
undervoltage
Flag for the overcurrent events. Will be present and active regard- Flag for the undervoltage events. Will be present and active
less of DIO_0_Sel and DIO_1_Sel. Will only be set when fault is regardless of DIO_0_Sel and DIO_1_Sel. Will only be set when
present.
fault is present.
faultlatched
posangle
Flag for the overcurrent events. This bit will latch and will remain Sign bit to represent if the power is being generated (1) or con-
1 as soon as an overcurrent event is detected. This can be reset by sumed (0).
writing a 1 to this field. Will be present and active regardless of
DIO settings.
pospf
Bit to represent leading or lagging. A 0 represents the voltage
leading and a 1 represents the voltage lagging.
32
Allegro MicroSystems, LLC
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Register 0x2F
Bits
Name
Description
31:0
access_code
Access code register:
Customer code: 0x4F70656E
Register 0x30
Bits
Name
Description
0
customer_access Customer write access enabled.
0 = Non Customer mode.
1 = Customer mode.
33
Allegro MicroSystems, LLC
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
APPLICATION CONNECTIONS
The two figures below show possible circuit configurations that
can be used with the voltage channel of this device.
addition of R1 and R2 is required and they will create some offset
on the measured signal. This offset will be ~1.4% of full scale on
a 115 V system.
In Figure 14, an isolated device ground is required for proper
operation.
In both cases, RSENSE should be sized such that the voltage across
RSENSE does not exceed the full-scale value of delta VIN(max)
.
In Figure 15, an isolated device ground is not required but the
ꢀ7
ꢀꢁ
ꢈ
ꢅꢆꢄꢇ
1 MΩ
1 MΩ
ꢀSꢃꢄSꢃ
4.7 kΩ
ꢀꢂ
ꢀ10
ꢄ
ꢅꢆꢄꢄ
1 MΩ
1 MΩ
Figure 14: Isolated Device Ground Required
ꢀ7
ꢀꢁ
ꢈ
ꢅꢆꢄꢇ
1 MΩ
1 MΩ
ꢀSꢃꢄSꢃ
4.7 kΩ
ꢅCC
ꢀ1
1.5 kΩ
ꢅꢆꢄꢄ
ꢀ2
3 kΩ
ꢀꢂ
ꢀ10
ꢄ
1 MΩ
1 MΩ
Figure 15: Isolated Device Ground Not Required
34
Allegro MicroSystems, LLC
955 Perimeter Road
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Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
RECOMMENDED PCB LAYOUT
NOT TO SCALE
All dimensions in millimeters.
15.75
9.54
1.27
0.65
Package Outline
Slot in PCB to maintain >8 mm creepage
once part is on PCB
2.25
7.25
1.27
3.56
17.27
Current
In
Current
Out
Perimeter holes for stitching to the other,
matching current trace design, layers of
the PCB for enhanced thermal capability.
21.51
Figure 16: Recommended PCB Layout
35
Allegro MicroSystems, LLC
955 Perimeter Road
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www.allegromicro.com
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MS-013AA)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
8°
10.30 0.20
E
0°
16
0.33
0.20
D
D1
D2
7.50 0.10
10.30 0.33
A
1.27
0.40
1.40 REF
1
2
0.90
D
Branded Face
0.25 BSC
SEATING PLANE
16×
CC
GAUGE PLANE
2.65 MAX
0.10
C
SEATING
PLANE
0.30
0.10
1.27 BSC
0.51
0.31
1.27
0.65
16
XXXXXXX
Lot Number
2.25
1
B
Standard Branding Reference View
9.50
Lines 1, 2 = 12 characters
Line 1: Part Number
Line 2: First 8 characters of Assembly Lot Number
A
Terminal #1 mark area
B
C
Branding scale and appearance at supplier discretion
1
2
Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C
PCB Layout Reference View
Hall elements (D1, D2), not to scale
D
E
Active Area Depth 0.293 mm
Figure 17: Package MA, 16-Pin SOICW
36
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Single Phase, Isolated, Power Monitoring IC
with Voltage Zero Crossing and Overcurrent Detection
ACS71020
Revision History
Number
Date
Description
–
June 20, 2018
Initial release
Updated Features and Benefits, Description (page 1), Isolation Characteristics, Thermal Characteristics (page
3), Power Calculations section (pages 13-14), Digital Communication (page 15), Register Details (pages 20-33),
Applications Connections (page 34), and Package Outline Drawing (page 36).
September 19,
2018
1
Copyright ©2018, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
37
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