A8902SLBTR [ALLEGRO]
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| 型号： | A8902SLBTR |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | 暂无描述 驱动器 电动机控制 电机 控制器 |
| 文件： | 总12页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8902–A
3-PHASE BRUSHLESS DC MOTOR
CONTROLLER/DRIVER WITH BACK-EMF SENSING
The A8902CLBA is a three-phase brushless dc motor controller/
driver for use in 5 V or 12 V hard-disk drives. The three half-bridge
LOAD
SUPPLY
COMMUTATION
DELAY
1
24
23
C
V
D1
outputs are low on-resistance n-channel DMOS devices capable of
driving up to 1.25 A. The A8902CLBA provides complete, reliable,
self-contained back-EMF sensing motor startup and running algorithms.
A programmable digital frequency-locked loop speed control circuit
together with the linear current control circuitry provides precise motor
speed regulation.
BB
DATA IN
C
2
3
4
D2
22 CLOCK
21
C
WD
C
CHIP SELECT
ST
20 RESET
OUT
5
6
A
A serial port allows the user to program various features and
modes of operation, such as the speed control parameters, startup
current limit, sleep mode, diagnostic modes, and others.
19
18
GROUND
GROUND
GROUND
GROUND
7
8
OUT
B
DATA OUT
OSCILLATOR
MUX
17
16
15
The A8902CLBA is fabricated in Allegro’s BCD (Bipolar CMOS
DMOS) process, an advanced mixed-signal technology that combines
bipolar, analog and digital CMOS, and DMOS power devices. The
A8902CLBA is provided in a 24-lead wide-body SOIC batwing package.
It provides for the smallest possible construction in surface-mount
applications.
9
OUT
C
FLL
V
LOGIC
SUPPLY
CENTERTAP 10
DD
BOOST
CHARGE
PUMP
SECTOR
DATA
14
BRAKE
11
12
C
13 FILTER
RES
Dwg. PP-040B
FEATURES
■ DMOS Outputs
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
■ Low rDS(on)
■ Startup Commutation Circuitry
■ Back-EMF Commutation Circuitry
■ Serial Port Interface
Load Supply Voltage, VBB . . . . . . . . . . 14 V
Output Current, IOUT . . . . . . . . . . . . ±1.25 A
Logic Supply Voltage, VDD . . . . . . . . . 6.0 V
Logic Input Voltage Range,
VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V
Package Power Dissipation, PD See Graph
Operating Temperature Range,
TA . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature, TJ . . . . . . . +150°C†
Storage Temperature Range,
■ Frequency-Locked Loop Speed Control
■ Sector Data Tachometer Signal Input
■ Programmable Start-Up Current
■ Diagnostics Mode
■ Sleep Mode
■ Linear Current Control
TS . . . . . . . . . . . . . . . -55°C to +150°C
■ Internal Current Sensing
■ Dynamic Braking Through Serial Port
■ Power-Down Dynamic Braking
■ System Diagnostics Data Out
■ Data Out Ported in Real Time
■ Internal Thermal Shutdown Circuitry
† Fault conditions that produce excessive junction
temperature will activate device thermal shutdown
circuitry. These conditions can be tolerated, but
should be avoided.
Output current rating may be restricted to a value
determined by system concerns and factors.
These include: system duty cycle and timing,
ambient temperature, and use of any heatsinking
and/or forced cooling. For reliable operation, the
specified maximum junction temperature should
not be exceeded.
Always order by complete part number, e.g., A8902CLBA .
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
C
C
C
C
ST
D1
D2
BRAKE
RES
15
2
24
4
11
12
V
DD
BOOST
CHARGE
PUMP
BRAKE
LOAD
SUPPLY
1
5
8
9
V
BB
OUT
OUT
OUT
FCOM
COMMUTATION
DELAY
A
B
C
OUT
OUT
A
B
START-UP
OSC.
BLANK
OUT
C
10
CENTERTAP
WATCHDOG
C
3
WD
TIMER
SECTOR
DATA
14
CURRENT
CONTROL
FREQUENCY-
LOCKED LOOP
CHARGE
PUMP
OSC 16
R
S
6-7
GROUND
GROUND
23
DATA IN
SERIAL PORT
MUX
TSD
18-19
20
17
22
21
13
FILTER
Dwg. FP-034
2.5
R
= 6°C/W
θJT
2.0
1.5
1.0
0.5
0
R
= 55°C/W
θJA
25
50
75
100
125
150
TEMPERATURE in °C
Dwg. GP-019B
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1992, 1995 Allegro MicroSystems, Inc.
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5.0 V
Limits
Characteristic
Symbol
VDD
Test Conditions
Min.
4.5
—
Typ.
Max.
5.5
10
Units
V
Logic Supply Voltage
Logic Supply Current
Operating
Operating
Sleep Mode
Operating
5.0
7.5
250
—
IDD
mA
µA
V
—
500
14
Load Supply Voltage
Thermal Shutdown
VBB
TJ
4.0
—
165
20
—
°C
Thermal Shutdown Hysteresis
Output Drivers
∆TJ
—
—
°C
Output Leakage Current
IDSX
VBB = 14 V, VOUT = 14 V
BB = 14 V, VOUT = 0 V
—
—
—
1.0
-1.0
1.0
300
-300
1.4
µA
µA
Ω
V
Total Output ON Resistance
(Source + Sink + RS)
rDS(on)
IOUT = 600 mA
Output Sustaining Voltage
Clamp Diode Forward Voltage
Control Logic
VDS(sus)
VF
VBB = 14 V, IOUT = IOUT(MAX), L = 3 mH
IF = 1.0 A
14
—
—
V
V
—
1.25
1.5
Logic Input Voltage
VIN(0)
VIN(1)
IIN(0)
SECTOR DATA, RESET, CLK,
CHIP SELECT, OSC
VIN = 0 V
-0.3
3.5
—
—
—
1.5
5.3
-0.5
1.0
1.5
—
V
V
Logic Input Current
—
µA
µA
V
IIN(1)
VIN = 5.0 V
—
—
DATA Output Voltage
VOUT(0)
VOUT(1)
ICST
IOUT = 500 µA
—
—
IOUT = -500 µA
Charging
3.5
-9.0
—
—
V
CST Current
-10
500
2.5
1.0
-10
10
-11
—
µA
µA
V
Discharging
CST Threshold
VCSTH
VCSTL
IFILTER
2.25
0.85
-9.0
9.0
—
2.75
1.15
-11
11
V
Filter Current
Charging
µA
µA
nA
V
Discharging
Leakage, VFILTER = 2.5 V
—
5.0
2.13
-22
48
Filter Threshold
CD Current
VFILTERTH
ICD
1.57
-18
32
1.85
-20
40
Charging
µA
µA
—
V
(CD1 or CD2
)
Discharging
CD Current Matching
CD Threshold
—
ICD(DISCHRG)/ICD(CHRG)
1.8
2.25
2.0
2.5
2.2
2.75
VCDTH
Continued next page …
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
ELECTRICAL CHARACTERISTICS continued
Limits
Typ.
Characteristic
Symbol
ICWD
VTL
Test Conditions
Min.
-9.0
0.22
2.25
12
Max.
-11
0.28
2.75
—
Units
µA
V
CWD Current
Charging
-10
0.25
2.5
—
CWD Threshold Voltage
VTH
V
Max. FLL Oscillator Frequency
OUT(MAX)
fOSC
—
VDD = 5.0 V, TA = 25°C
D3 = 0, D4 = 0
MHz
A
I
1.0
0.9
0.5
—
1.2
1.0
0.6
250
1.75
20
1.4
1.1
0.7
—
D3 = 0, D4 = 1
A
D3 = 1, D4 = 0
A
D3 = 1, D4 = 1
mA
V
BRAKE Threshold
VBRK
IBRKL
gm
1.5
—
2.0
—
BRAKE Hysteresis Current
Transconductance Gain
Centertap Resistors
VBRK = 750 mV
µA
A/V
kΩ
mV
mV
0.42
5.0
5.0
-5.0
0.50
10
0.58
13
RCT
—
Back-EMF Hysteresis
V
BEMF - VCTAP at
20
37
FCOM Transition
-20
-37
SERIAL PORT TIMING CONDITIONS
CHIP SELECT
E
A
B
D
CLOCK
DATA
C
D
C
Dwg. WP-019
A. Minimum CHIP SELECT setup time before CLOCK rising edge.......... 100 ns
B. Minimum CHIP SELECT hold time after CLOCK rising edge............... 150 ns
C. Minimum DATA setup time before CLOCK rising edge........................ 150 ns
D. Minimum DATA hold time after CLOCK rising edge............................. 150 ns
E. Minimum CLOCK low time before CHIP SELECT.................................. 50 ns
F. Maximum CLOCK frequency .............................................................. 3.3 MHz
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
TERMINAL FUNCTIONS
Term.
Terminal Name
LOAD SUPPLY
CD2
Function
1
2
VBB; the 5 V or 12 V motor supply.
One of two capacitors used to generate the ideal commutation points from the
back-EMF zero crossing points.
3
CWD
Timing capacitor used by the watchdog circuit to disable the back-EMF compara-
tors during commutation transients, and to detect incorrect motor position.
4
5
CST
OUTA
Startup oscillator timing capacitor.
Power amplifier A output to motor.
6-7
8
GROUND
OUTB
Power and logic ground and thermal heat sink.
Power amplifier B output to motor.
9
OUTC
Power amplifier C output to motor.
10
11
CENTERTAP
BRAKE
Motor centertap connection for back-EMF detection circuitry.
Active low turns ON all three sink drivers shorting the motor windings to ground.
External capacitor and resistor at BRAKE provide brake delay. The brake function
can also be controlled via the serial port.
12
13
14
CRES
FILTER
External reservoir capacitor used to hold charge to drive the source drivers’
gates. Also provides power for brake circuit.
Analog voltage input to control motor current. Also, compensation node for
internal speed control loop.
SECTOR DATA
External tachometer input. Can use sector or index pulses from disk to provide
precise motor speed feedback to internal frequency-locked loop.
15
16
17
LOGIC SUPPLY
OSCILLATOR
DATA OUT
VDD; the 5 V logic supply.
Clock input for the speed reference counter. Typical max. frequency is 10 MHz.
Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real
time, controlled by 2-bit multiplexer in serial port.
18-19
20
GROUND
RESET
Power and logic ground and thermal heat sink.
When pulled low forces the chip into sleep mode; clears all serial port bits.
Strobe input (active low) for data word.
21
CHIP SELECT
CLOCK
22
Clock input for serial port.
23
DATA IN
CD1
Sequential data input for the serial port.
24
One of two capacitors used to generate the ideal commutation points from the
back-EMF zero crossing points.
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
FUNCTIONAL DESCRIPTION
Power Outputs. The power outputs of
the A8902CLBA are n-channel DMOS
backward, or remain stationary (if in a null-torque position). If the motor
moves, the back-EMF detection circuit waits for the correct polarity
back-EMF zero crossing (output crossing through centertap). True
back-EMF zero crossings are used by the adaptive commutation delay
circuit to advance the state sequencer (commutate) at the proper time
to synchronously run the motor. Back-EMF zero crossings are indi-
cated by FCOM, an internal signal that toggles at every zero crossing.
FCOM is available at the DATA OUT terminal via the programmable
data out multiplexer.
transistors with a total source plus sink rDS(on)
of typically 1 Ω. Internal charge pump boost
circuitry provides voltage above supply for
driving the high-side DMOS gates. Intrinsic
ground clamp and flyback diodes provide
protection when switching inductive loads and
may be used to rectify motor back-EMF in
power-down conditions. An external Schottky
power diode or pass FET is required in series
with the load supply to allow motor back-EMF
rectification in power down conditions.
V
OUTA
Back-EMF Sensing Motor Startup and
Running Algorithm. The A8902CLBA
provides a complete self-contained back-EMF
sensing startup and running commutation
scheme. The three half-bridge outputs are
controlled by a state machine. There are six
possible combinations. In each state, one
output is high (sourcing current), one low
(sinking current), and one is OFF (high
impedance or ‘Z’). Motor back EMF is sensed
at the OFF output. The truth table for the
output drivers sequencing is:
V
OUTB
SOURCE ON
BACK-EMF VOLTAGE
V
OUTC
V
SINK ON
CTAP
FCOM TOGGLES AT
BACK-EMF ZERO CROSSING
FCOM
Dwg. WP-016-1
Sequencer
State
OUTA
OUTB
OUTC
Startup Oscillator. If the motor does not move at the initial startup
1
2
3
4
5
6
High
Z
Low
Low
Z
Low
Low
Z
High
High
Z
Z
state, then it is in a null-torque position. In this case, the outputs are
commutated automatically by the startup oscillator after a period set by
the external capacitor at CST where
High
High
Z
Low
Low
4(VCSTH - VCSTL) x CST
tCST
=
High
IST(charge) + IST(discharge)
At startup, the outputs are enabled in one
of the sequencer states shown. The back
EMF is examined at the OFF output by
comparing the output voltage to the motor
centertap voltage at CENTERTAP. The
motor will then either step forward, step
In the next state, the motor will move, back EMF will be detected,
and the motor will accelerate synchronously. Once normal synchro-
nous back-EMF commutation occurs, the startup oscillator is defeated
by pulses of pulldown current at CST at each commutation, which
prevents CST from reaching its upper threshold and thus completing a
cycle and commutating.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Adaptive Commutation Delay. The
adaptive commutation delay circuit uses the
back-EMF zero-crossing indicator signal
(FCOM) to determine an optimal commuta-
tion time for efficient synchronous operation.
This circuit commutates the outputs, delayed
from the last zero crossing, using two
Blanking and Watchdog Timing Functions. The blanking and
watchdog timing functions are derived from one timing capacitor, CWD
VTL x CWD
.
where
tBLANK =
ICWD
VTH x CWD
=
ICWD
and
tWD
external timing capacitors, CD1 and CD2,
The CWD capacitor begins charging at each commutation, initiating
the BLANK signal. BLANK is an internal signal that inhibits the back-
EMF comparators during the commutation transients, preventing errors
due to inductive recovery and voltage settling transients.
t
FCOM
FCOM
The watchdog timing function allows time to detect correct motor
position by checking the back-EMF polarity after each commutation. If
the correct polarity is not observed between tBLANK and tWD, then the
watchdog timer commutates the outputs to the next state to synchro-
nize the motor. This function is useful in preventing excessive reverse
rotation, and helps in resynchronizing (or starting) with a moving
spindle.
V
CWD
t
CD1
V
CD1
t
CD2
V
TL
V
CWD
V
CD2
t
BLANK
BLANK
Dwg. WP-016-2
Dwg. WP-022
to measure the time between crossings.
ICD(charge)
NORMAL COMMUTATION
where
tCD = tFCOM x
ICD(discharge)
CD1 charges up with a fixed current from
its 2.5 V reference while FCOM is high.
When FCOM goes low at the next zero
crossing, CD1 is discharged at approximately
twice the charging current. When CD1
reaches the CD threshold, a commutation
occurs. CD2 operates similarly except on the
opposite phase of FCOM . Thus the com-
mutations occur approximately halfway
between zero crossings. The actual delay is
slightly less than halfway to compensate for
electrical delays in the motor, which im-
proves efficiency.
V
TH
V
TL
V
CWD
t
BLANK
BLANK
t
WD
Dwg. WP-021
WATCHDOG-TRIGGERED
COMMUTATION
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Current Control. The A8902CLBA provides linear current control
via the FILTER terminal, an analog voltage input. Maximum current
limit is also provided, and is controlled in four steps via the serial port.
Output current is sensed via an internal sense resistor (RS). The
voltage across the sense resistor is compared to one-tenth the voltage
at the FILTER terminal less the filter threshold voltage, or to the maxi-
mum current limit reference, whichever is lower. This transcon-
ductance function is IOUT = (VFILTER -VFILTERTH) / 10RS, where RS is
nominally 0.2 Ω and VFILTERTH is approximately 1.85 V.
60 x fOSC
desired
total count
=
desired motor speed (rpm)
where the total count (number of oscillator
cycles) is equal to the sum of the selected
(programmed low) count numbers corre-
sponding to bits D5 through D18.
The speed error is detected as the
difference in falling edges of TACH and
REF. The speed error signals control the
error-correcting charge pump on the FILTER
terminal, which drive the external loop com-
pensation components to correct the motor
current.
YANK
POWER UP
SEQUENTIAL
LOGIC
S
R
Q
ERROR FAST
FROM FLL
V
BB
C
RES
SPEED-CONTROL
INITIALIZATION
BOOST
CHARGE
PUMP
V
DD
V
DD
OUT
ERROR SLOW
FROM FLL
+
Sector Mode. An external tachometer
signal, such as sector or index pulses, may
be used to create the TACH signal, rather
than the internally derived once around. To
use this mode, the signal is input to the
SECTOR terminal, and the sector mode must
be enabled via the serial port. When Switch-
ing from the once-around mode to sector
mode, it is important to monitor the SYNC
signal on DATA OUT, and switch modes only
when SYNC is low. This ensures making the
transition without disturbing the speed control
loop. The speed reference counter should be
reprogrammed at the same time.
I
MUX
÷10
c
–
FILTER
+
C
F1
F1
–
x1
–
I
R
d
S
LINEAR
+
CURRENT CONTROL
1.85 V
C
F2
R
FROM
SERIAL PORT
REGISTER
D3 AND D4
CHARGE
PUMP
ERROR FAST
FROM FLL
MAX CURRENT LIMIT
Dwg. EP-046
Speed Control. The A8902CLBA includes a frequency-locked
loop speed control system. This system monitors motor speed via
internal or external digital tachometer signals, generates a precision
speed reference, determines the digital speed error, and corrects the
motor current via an internal charge pump and external filtering compo-
nents on the FILTER terminal.
Speed Loop Initialization (YANK). To
improve the acquire time of the speed control
loop, there is an automatic feature controlled
by an internal YANK signal. The motor is
started at the maximized programmed current
by bypassing the FILTER terminal. The
FILTER terminal is clamped to an internal
reference (the filter threshold voltage),
A once per revolution TACH signal can be generated by counting
cycles of FCOM (the number of motor poles must be selected via the
serial port). TACH is then a jitter-free signal that toggles once per
motor revolution. The rising edge of TACH triggers REF, a precision
speed reference derived by a programmable counter. The duration of
REF is set by programming the counter to count the desired number of
OSC cycles
initializing it near the closed loop operating
point. YANK is enabled at startup and stays
high until the desired speed is reached. Once
the first error-fast occurs, indicating the motor
crossed through the desired speed, YANK
goes low. This releases the clamp on the
FILTER terminal and current control is
returned to FILTER. This feature optimizes
speed acquire and minimizes settling. The
Current Control Block Diagram illustrates the
YANK signal and its effects.
SECTOR
COUNT
÷2
MUX
TACH
FCOM
(3 x MOTOR POLES)
ONCE-AROUND
PULSE
D20 &
D21
D19
REF
TACH
SERIAL PORT
REGISTER
ERROR
SLOW
D5–D18
REF
4-BIT
14-BIT
TACH
OSC
FIXED
COUNTER
PROGRAMMABLE
COUNTER
REF
ERROR
FAST
Dwg. EP-045
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Serial Port. The serial port functions to write various operational
and diagnostic modes to the A8902CLBA. The serial port DATA IN is
enabled/disabled by the CHIP SELECT terminal. When CHIP SE-
LECT is high the serial port is disabled and the chip is not affected by
changes in data at the DATA IN or CLOCK terminals.
Bit Number
Count Number
D5
D6
D7
16
32
64
D8
128
To write data to the serial port, the CLOCK terminal should be low
prior to the CHIP SELECT terminal going low. Once CHIP SELECT
goes low, information on the DATA IN terminal is read into the shift
register on the positive-going transition of the CLOCK. There are 24
bits in the serial input port.
D9
256
512
D10
D11
D12
D13
D14
D15
D16
D17
D18
1 024
2 048
4 096
8 192
16 384
32 768
65 536
131 072
Data written into the serial port is latched and becomes active
upon the low-to-high transition of the CHIP SELECT terminal at the
end of the write cycle. D0 will be the last bit written to the serial port.
SERIAL PORT BIT DEFINITIONS
D0- Sleep/Run Mode; LOW = Sleep, HIGH = Run
D19-Speed-control mode switch;
LOW = internal once-around speed signal,
HIGH = external sector data.
This bit allows the device to be powered down when not in use.
D1- Step Mode; LOW = Normal Operation, HIGH = Step Only
When in the step-only mode the back-EMF commutation circuitry
is disabled and the power outputs are commutated by the start-
up oscillator. This mode is intended for device and system
testing.
D20 and D21-These bits program the number
of motor poles for the once-around FCOM
counter:
D2- Brake; LOW = Run, HIGH = Brake.
D20
D21
Motor Poles
D3 and D4 - These two bits set the output current limit:
0
0
1
1
0
1
0
1
8
–
16
12
D3
D4
Current Limit
0
0
1
1
0
1
0
1
1.2 A
1 A
600 mA
250 mA
D22 and D23-Controls the multiplexer for
DATA OUT:
D22
D23
DATA OUT
D5 thru D18-This 14-bit word (active low) programs the REF time to set
desired motor speed.
0
0
1
1
0
1
0
1
TACH (once around or sector)
Thermal Shutdown
SYNC
FCOM
Reset. The RESET terminal when pulled
low clears all serial port bits, including the D0
latch, which puts the A8902CLBA in the sleep
mode.
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
brake is activated. Once the brake is acti-
vated, due to the inherent capacitive input,
the three sink drivers will remain active until
the device is reset.
V
– V
BRAKE
ACTIVATED
FAULT
D
BRAKE
FAULT
C
B
V
R
BRK
B
t
BRK
VBRK
VFAULT - VD
Dwg. OP-004
tBRK = RBCB 1 – ln
Centertap. The A8902CLBA internally
simulates the centertap voltage of the motor.
To obtain reliable start-up performance from
motor to motor, the motor centertap should be
connected to this terminal.
Braking. A dynamic braking feature of the A8902CLBA shorts the
three motor windings to ground. This is accomplished by turning the
three source drivers OFF and the three sink drivers ON. Activation of
the brake can be implemented through the BRAKE input or through
the D2 bit in the serial port. The supply voltage for the brake circuitry
is the CRES voltage, allowing the brake function to remain active after
power failure. Power-down braking with delay can be implemented by
using an external RC and other components to control the brake
terminal, as shown. Brake delay can be set using the equation below
to ensure that voice-coil head retract occurs before the spindle motor
External Component Selection. Appli-
cations information regarding the selection of
external component values is available from
the factory for external component selection,
frequency-locked loop speed control, and
commutation delay capacitor selection.
TYPICAL APPLICATION
V
BB
BYPASS
COMMUTATION
24
23
22
21
1
2
V
V
C
RET
BB
D1
DELAY
DATA IN
C
D2
3
4
CLOCK
C
WD
CHIP SELECT
C
ST
20
19
18
RESET
5
6
7
8
BYPASS
17
16
15
DATA OUT
MUX
FLL
9
OSC (REF)
V
+5 V
10
DD
C
R
F1
F1
BOOST
CHARGE
PUMP
14
13
SECTOR
DATA
11
12
FAULT
C
B
R
B
C
F2
C
RES
0.22 µF
Dwg. EP-036C
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Dimensions in Inches
(for reference only)
24
13
0.0125
0.0091
0.491
0.394
0.2992
0.2914
0.050
0.016
1
2
3
0.020
0.013
0.050
0.6141
0.5985
0° TO 8°
BSC
NOTE 1
NOTE 3
0.0926
0.1043
Dwg. MA-008-25 in
0.0040MIN
.
Dimensions in Millimeters
(controlling dimensions)
24
13
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
1
2
3
0.51
0.33
1.27
15.60
15.20
0° TO 8°
BSC
NOTE 1
NOTE 3
2.65
2.35
Dwg. MA-008-25A mm
0.10 MIN
.
NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the design of its products.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibil-
ity for its use; nor for any infringements of patents or other rights of third
parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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