A6801SA [ALLEGRO]
DABiC-5 Latched Sink Drivers; DABiC - 5锁存灌电流驱动器
| 型号： | A6801SA |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | DABiC-5 Latched Sink Drivers |
| 文件： | 总12页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A6800/A6801
DABiC-5 Latched Sink Drivers
The A6800 and A6801 latched-input BiMOS ICs merge high-current,
high-voltage outputs with CMOS logic. The CMOS input section con-
sists of 4 or 8 data (‘D’ type) latches with associated common CLEAR,
STROBE, and OUTPUT ENABLE circuitry. The power outputs are
bipolar NPN Darlingtons. This merged technology provides versatile,
flexible interface. These BiMOS power interface ICs greatly benefit the
simplification of computer or microprocessor I/O. The A6800 ICs each
contain four latched drivers. A6801 ICs contain eight latched drivers.
A6800SA
A6800SL
The CMOS inputs are compatible with standard CMOS circuits. TTL
circuits may mandate the addition of input pull-up resistors. The bipolar
Darlington outputs are suitable for directly driving many peripheral/
power loads: relays, lamps, solenoids, small dc motors, etc.
All devices have open-collector outputs and integral diodes for induc-
tive load transient suppression. The output transistors are capable of
sinking 600 mA and will withstand at least 50 V in the OFF state.
Because of limitations on package power dissipation, the simultaneous
operation of all drivers at maximum rated current can only be accom-
plished by a reduction in duty cycle. Outputs may be paralleled for
higher load current capability.
A6801SA
A6801SEP
The A6800SA is furnished in a standard 14-pin DIP; the A6800SL and
A6801SLW in surface-mountable SOICs; the A6801SA in a 22-pin
DIP with 0.400” (10.16 mm) row centers; the A6801SEP in a 28-lead
PLCC. These devices are lead (Pb) free, with 100% matte tin plated
leadframes.
A6801SLW
ABSOLUTE MAXIMUM RATINGS
FEATURES
3.3 V to 5Vlogic supply range
CMOS, TTL compatible inputs
Output transient protection
Internal pull-down resistors
Low-power CMOS latches
Output Voltage, VCE............................................50 V
Supply Voltage, VDD.............................................7 V
Input Voltage Range,VIN ..............–0.3VtoVDD +0.3V
Continuous Collector Current, IC........................ 600 mA
Package Power Dissipation, PD, see Allowable Power
Disspation chart, page 5
To 10 MHz data input rate
High-voltage, high-current outputs
Darlington current-sink outputs, with
improved low-saturation voltages
APPLICATIONS
Operating Temperature Range
Solenoids
Small dc motors
Relays
Lamps
Ambient Temperature, TA............–20°C to +85°C
Storage Temperature, TS ..........–55°C to +150°C
Use the following complete part numbers when ordering:
Part Number
A6800SA-T
A6800SL-T
A6801SA-T
A6801SEP-T
A6801SLW-T
Pins
14
Package
DIP
Caution: CMOS devices have input-static protection,
but are susceptible to damage when exposed to
extremely high static-electrical charges.
14
SOIC
DIP
22
28
PLCC
SOIC
24
A6800/A6801
DABiC-5 Latched Sink Drivers
Functional Block Diagram
COMMON
S UPPLY
V
DD
OUT
N
IN
N
S TR OBE
GR OUND
CLE AR
OUTPUT E NABLE
TYPICAL MOS LATCH
TYPICAL BIPOLAR DR IVE
COMMON MOS CONTR OL
Allowable Power Dissipation
Typical Input Circuit
2.5
V
DD
22-PIN DIP, R
28-LE AD PLCC, R
14-PIN DIP, R
θ
JA = 56°C/W
JA = 68°C/W
JA = 73°C/W
θ
θ
IN
2.0
1.5
1.0
0.5
24-LE AD S OIC, R θJA = 85°C/W
14-LE AD S OIC, R
θJA = 120°C/W
0
25
50
75
100
125
150
AMB IE NT TE MPE R ATUR E (º C)
2
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
DABiC-5 Latched Sink Drivers
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd =3.0Vto5.5V
V
dd = 3.3V
Vdd = 5V
Min. Typ. Max. Min. Typ. Max.
Characteristic
Output Leakage Current
Output Sustaining Voltage
Symbol
Test Conditions
Units
µA
V
ICEX
VOUT = 50 V
–
35
–
–
–
10
–
–
35
–
–
–
10
–
VCE(SUS) IOUT = 350 mA, L = 3 mH
IOUT = 100 mA
0.8
0.9
1.0
–
1.0
1.1
1.3
–
0.8
0.9
1.0
–
1.0
1.1
1.3
–
V
Collector-Emitter Saturation
Voltage
VCE(SAT) IOUT = 200 mA
–
–
V
IOUT = 350 mA (See note 2)
–
–
V
VIN(1)
VIN(0)
RIN
2.2
–
3.3
–
V
Input Voltage
–
1.1
–
–
1.7
–
V
Input Resistance
Logic Supply Current
50
–
–
50
–
–
kΩ
mA
µA
µA
V
IDD(1)
One output on, IOUT = 100 mA
All outputs off
–
1.0
150
50
2.0
–
–
1.0
150
50
2.0
–
IDD(0)
–
130
–
–
130
–
Clamp Diode Leakage Current
Clamp Diode Forward Voltage
Output Fall Time
Ir
Vf
tf
Vr= 50 V
–
–
If = 350 mA
–
–
–
–
VCC = 50V, R1 = 500 Ω, C1≤30pF
VCC = 50V, R1 = 500 Ω, C1≤30pF
–
80
100
–
80
100
ns
ns
Output Rise Time
tr
–
–
–
–
1
2
Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic 1.
Because of limitations on package power dissipation, the simultaneous operation of multiple drivers can only be accomplished by reduction in duty cycle.
Truth Table
OUT
N
OUTPUT
E NAB LE
IN
S TR OB E
C LE AR
t-1
t
N
0
1
X
X
X
X
1
1
X
X
0
0
0
0
1
X
0
0
0
0
X
1
0
0
X
X
OFF
ON
X
OFF
OFF
ON
X
ON
OFF
OFF
X
= irrelevant
t-1 = previous output s tate
= present output state
t
3
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
DABiC-5 Latched Sink Drivers
Timing Requirements and Specifications
(Logic Levels are VDD and Ground)
CLEAR
H
STROBE
A
C
G
B
B
C
C
I
A
B
OUTPUT
ENABLE
IN
N
E
E
D
F
G
OUT
N
Key
A
Description
Time (ns)
25
Minimum data active time before Strobe enabled (Data Set-Up Time)
Minimum data active time after Strobe disabled (Data Hold Time)
Minimum Strobe pulse width
B
25
C
D
E
50
Maximum time between Strobe activation and transition from output on to output off*
Minimum time between Strobe activation and transition from output off to output on*
500
500
500
500
50
F
Maximum time between Output Enable activation and transition from output on to output off*
Minimum time between Output Enable activation and transition from output off to output on*
Minimum Clear pulse width
G
H
I
Minimum data pulse width
100
*Conditions for output transition testing are: VDD = 50 V, VCC = 5 V, R1 = 500 Ω, C1 ≤ 30 pF.
NOTE: Information present at an input is transferred
to its latch when the STROBE is high. A high CLEAR
input will set all latches to the output off condition
regardless of the data or STROBE input levels. A high
OUTPUT ENABLE will set all outputs to the off con-
tdition, regardless of any other input conditions. When
the OUTPUT ENABLE is low, the outputs depend on
the state of their respective latches.
4
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
DABiC-5 Latched Sink Drivers
A6800SL
A6800SA
A6801SA
1
14
OUTPUT
ENABLE
1
2
3
4
22
21
20
19
18
17
16
CLEAR
STROBE
V
SUPPLY
DD
OUTPUT
ENABLE
OUT
1
IN
1
1
2
3
4
14
13
12
11
CLEAR
IN
2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
2
3
4
5
6
7
8
STROBE
V
SUPPLY
DD
5
6
IN
3
OUT
1
IN
1
IN
2
IN
4
OUT
2
5
6
10
9
OUT
3
7
8
IN
3
IN
5
OUT
4
IN
4
IN
6
15
7
8
COMMON
GROUND
IN
7
9
14
13
12
10
IN
8
Dwg. PP-014A
11
COMMON
Dwg. PP-015
GROUND
Note: The A6800SL (SOIC) and the A6800SA
(DIP) are electrically identical and share a com-
mon terminal number assignment.
A6801SEP
A6801SLW
OUTPUT
ENABLE
1
2
3
4
24
23
CLEAR
STROBE
V
DD
SUPPLY
22
21
20
19
18
17
OUT
1
IN
1
25
24
23
22
21
OUT
IN
5
6
7
8
1
1
IN
2
OUT
OUT
OUT
OUT
OUT
2
3
4
5
6
7
8
IN
OUT
OUT
OUT
2
3
2
3
5
6
IN
3
IN
IN
4
IN
4
4
7
8
IN
5
OUT
OUT
OUT
9
IN
IN
5
6
7
5
6
IN
6
20
19
10
11
IN
7
9
16 OUT
IN
7
10
15
14
13
OUT
IN
8
11
12
COMMON
GROUND
NO
NO
NC
NC
CONNECTION
CONNECTION
Dwg. PP-037
Dwg. PP-015-1
5
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
DABiC-5 Latched Sink Drivers
TYPICAL APPLICATION
UNIPOLAR STEPPER-MOTOR DRIVE
+30 V
OUTPUT E NABLE (ACTIVE LOW)
CLE AR
S TR OBE
IN 1
14
1
2
3
4
5
6
7
V
V
13
12
11
10
9
DD
OUT 1
DD
∝
IN 2
IN 3
IN 4
OUT 2
OUT 3
OUT 4
8
A6800S A
+30 V
Dwg. No. B-1537
UNIPOLAR WAVE DRIVE
UNIPOLAR 2-PHASE DRIVE
S TR OBE
IN 1
S TR OBE
IN 1
IN 2
IN 2
IN 3
IN 3
IN 4
IN 4
OUT 1
OUT 2
OUT 3
OUT 4
OUT 1
OUT 2
OUT 3
OUT 4
Dwg. GP-060
Dwg. GP-060-1
6
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
DABiC-5 Latched Sink Drivers
A6800SA
Dimensions in Inches
(controlling dimensions)
0.014
0.008
14
8
0.430
MAX
0.280
0.240
0.300
BSC
1
7
0.100
0.070
0.045
0.005
BSC
MIN
0.775
0.735
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-14A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
14
8
10.92
MAX
7.11
6.10
7.62
BSC
1
7
2.54
1.77
1.15
0.13
BSC
MIN
19.68
18.67
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-14A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
7
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
DABiC-5 Latched Sink Drivers
A6800SL
Dimensions in Inches
(for reference only)
14
8
0.0098
0.0075
0.1574
0.1497
0.2440
0.2284
0.050
0.016
0.020
0.013
1
2
3
0.050
BSC
0° TO 8°
0.3444
0.3367
0.0688
0.0532
Dwg. MA-007-14 in
0.0040 MIN.
14
Dimensions in Millimeters
(controlling dimensions)
8
0.25
0.19
4.00
3.80
6.20
5.80
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
8.75
8.55
1.75
1.35
Dwg. MA-007-14A mm
0.10 MIN.
NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
8
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
DABiC-5 Latched Sink Drivers
A6801SA
Dimensions in Inches
(controlling dimensions)
0.015
0.008
22
12
0.500
MAX
0.380
0.330
0.400
BSC
1
2
3
11
0.100
0.070
0.030
0.005
BSC
MIN
1.120
1.050
0.210
MAX
0.015
0.160
0.115
MIN
0.022
0.014
Dwg. MA-002-22 in
Dimensions in Millimeters
(for reference only)
0.381
0.204
22
12
12.70
MAX
9.65
8.39
10.16
BSC
1
2
3
11
2.54
0.070
0.030
0.13
BSC
MIN
28.44
26.67
5.33
MAX
0.39
4.06
2.93
MIN
0.558
0.356
Dwg. MA-002-22 mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
9
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
DABiC-5 Latched Sink Drivers
A6801SEP
Dimensions in Inches
(controlling dimensions)
18
12
0.013
0.021
19
11
0.219
0.191
0.026
0.032
0.456
0.450
INDEX AREA
0.495
0.485
0.050
BSC
0.219
0.191
25
5
26
28
1
4
0.020
0.456
0.450
MIN
0.165
0.180
0.495
0.485
Dwg. MA-005-28A in
Dimensions in Millimeters
(for reference only)
18
12
0.331
0.533
19
11
5.56
4.85
0.812
0.661
11.58
11.43
INDEX AREA
12.57
1.27
BSC
12.32
5.56
4.85
25
5
26
28
1
4
0.51
MIN
11.582
11.430
4.57
4.20
12.57
12.32
Dwg. MA-005-28A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
10
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
DABiC-5 Latched Sink Drivers
A6801SLW
Dimensions in Inches
(for reference only)
13
24
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
BSC
3
0° TO 8°
0.6141
0.5985
0.0926
0.1043
Dwg. MA-008-24A in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
24
13
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
BSC
3
0° TO 8°
15.60
15.20
2.65
2.35
Dwg. MA-008-24A mm
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
11
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
DABiC-5 Latched Sink Drivers
The products described here are manufactured under one or
more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical compo-
nents in life-support devices or systems without express written
approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringement of patents or other
rights of third parties which may result from its use.
Copyright©2003, 2004, 2005 Allegro Microsystems, Inc.
12
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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