A6276SLWTR [ALLEGRO]
LED Driver, 16-Segment, BICMOS, PDSO24, SOIC-24;
| 型号： | A6276SLWTR |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | LED Driver, 16-Segment, BICMOS, PDSO24, SOIC-24 驱动 信息通信管理 光电二极管 接口集成电路 |
| 文件： | 总13页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A6276
16-Bit Serial Input, Constant-Current
Latched LED Driver
Features and Benefits
▪ Up to 90 mA constant-current outputs
▪ Undervoltage lockout
▪ Low-power CMOS logic and latches
▪ High data input rate
Description
The A6276 is specifically designed for LED-display
applications. Each BiCMOS device includes a 16-bit CMOS
shiftregister,accompanyingdatalatches,and16NPNconstant-
current sink drivers. Except for package style and allowable
package power dissipation, the device options are identical.
▪ Functional replacement for TB62706BN/BF
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 5 V logic supply,
typicalserialdata-inputratesareupto20MHz.TheLEDdrive
current is determined by the user selection of a single resistor.
A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. For inter-digit
blanking, all output drivers can be disabled with an ENABLE
input high. Similar 8-bit devices are available as the A6275.
Packages
24-pin DIP
(A package)
24-pin TSSOP
with exposed thermal pad
(LP package)
Threepackagestylesareprovided:through-holeDIP(suffix A),
surface-mount SOIC (suffix LW), and TSSOP with exposed
thermal pad (suffix LP). In normal applications, the copper
leadframe and low logic-power dissipation of the DIP allow it
tosinkmaximumratedcurrentthroughalloutputscontinuously
over the operating temperature range (90 mA, 0.75 V drop,
85°C). All packages are lead (Pb) free, with 100% matte tin
leadframe plating.
24-pin SOICW
(LW package)
Not to scale
Functional Block Diagram
26185.201H
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
Selection Guide
Part Number
Ambient
Packing
Package
Temperature (°C)
A6276EA-T
24-pin DIP
15 per tube
–40 to 85
–40 to 85
–40 to 85
–20 to 85
A6276ELPTR-T*
A6276ELWTR-T
A6276SLWTR-T*
24-pin TSSOP
24-pin SOICW
24-pin SOICW
4000 per reel
1000 per reel
1000 per reel
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is
obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant
should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer
available. Status date change November 1, 2008. Deadline for receipt of LAST TIME BUY orders is April 25, 2009.
Absolute Maximum Ratings*
Characteristic
Symbol
VDD
Notes
Rating
7.0
Units
V
Supply Voltage
Output Voltage
Input Voltage
VO
–0.5 to 17
–0.4 to VDD + 0.4
90
V
VROUT
IO
V
Output Current
Ground Current
mA
mA
ºC
ºC
ºC
ºC
IGND
1475
Range S
Range E
–20 to 85
–40 to 85
150
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
TJ(max)
T
stg
–55 to 150
*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high
static electrical charges.
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
Value Units
Package A, 1-layer PCB based on JEDEC standard
50
32
85
ºC/W
ºC/W
ºC/W
2
Package Thermal Resistance
RθJA
Package LP, 2-layer PCB with 3.8 in. copper area each side
Package LW, 1-layer PCB based on JEDEC standard
*Additional thermal information available on the Allegro website
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
24-PIN TSSOP*, RθJA = 32°C/W
24-PIN DIP, RθJA = 50°C/W
24-LEAD SOIC, RθJA = 85°C/W
25
50
75
100
125
150
°
AMBIENT TEMPERATURE IN
C
*Mounted on single-layer, two-sided PCB, with 3.8 in2 copper each side;
additional information on Allegro Web site
Allegro MicroSystems, Inc.
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
Pin-out Diagram
(A, LP, and LW packages)
LOGIC
SUPPLY
V
GROUND
1
2
3
4
24
23
22
21
20
DD
SERIAL
DATA IN
I
O
R
EXT
REGULATOR
SERIAL
DATA OUT
CLOCK
CK
L
LATCH
ENABLE
OUTPUT
ENABLE
OE
REGISTER
LATCHES
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
15
5
6
0
19 OUT
14
1
18
17
OUT
OUT
7
8
2
3
4
5
6
7
13
12
11
10
9
9
16 OUT
15 OUT
14 OUT
13 OUT
10
11
12
8
Terminal Description
Terminal No.
Terminal Name
GND
Function
1
2
Reference terminal for control logic.
SERIAL DATA IN
CLOCK
Serial-data input to the shift-register.
3
Clock input terminal for data shift on rising edge.
Data strobe input terminal; serial data is latched with high-level input.
The 16 current-sinking output terminals.
4
LATCH ENABLE
OUT0-15
5-20
21
OUTPUT ENABLE
When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
22
23
SERIAL DATA OUT
REXT
CMOS serial-data output to the following shift-register.
An external resistor at this terminal establishes the output current for all
sink drivers.
24
SUPPLY
(VDD) The logic supply voltage (typically 5 V).
Allegro MicroSystems, Inc.
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright © 2000, 2003 Allegro MicroSystems, Inc.
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
V
DD
V
DD
IN
IN
Dwg. EP-010-11
Dwg. EP-010-12
OUTPUT ENABLE (active low)
LATCH ENABLE
V
V
DD
DD
OUT
IN
Dwg. EP-063-6
Dwg. EP-010-13
CLOCK and SERIAL DATA IN
SERIAL DATA OUT
TRUTH TABLE
Serial
Data Clock
Input Input I
Shift Register Contents
Serial Latch
Data Enable
Output Input
Latch Contents
Output
Enable
Input
Output Contents
... I
I
I
...
I
I
I
I
I
...
I
I
I
I
I
I
N-1 N
1
2
3
N-1
N
1
2
3
N-1
N
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
...
...
...
...
...
R
R
R
X
R
R
R
X
R
R
R
X
1
1
2
2
2
3
N-2
N-2
N-1
N-1
N-1
N
N-1
N-1
N
X
R
X
1
L
R
R
R
...
...
...
R
R
1
2
3
N-1
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
P
P
... P P
N-1 N
1
2
3
N-1
N
N
1
2
3
N-1
N
1
2
3
X
H
H
H
H
... H
H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
Allegro MicroSystems, Inc.
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ. Max.
Unit
Supply Voltage Range
Under-Voltage Lockout
VDD
VDD(UV)
IO
Operating
4.5
3.4
5.0
–
5.5
4.0
V
VDD = 0 5 V
V
Output Current
VCE = 0.7 V, REXT = 250
VCE = 0.7 V, REXT = 470
64.2
34.1
75.5
40.0
86.8
45.9
mA
mA
(any single output)
Output Current Matching
(difference between any
∆IO
0.4 V VCE(A) = VCE(B) 0.7 V:
REXT = 250
–
–
±1.5
±1.5
±6.0
±6.0
%
%
two outputs at same VCE
)
REXT = 470
Output Leakage Current
Logic Input Voltage
ICEX
VIH
VIL
VOH = 15 V
–
0.7VDD
GND
–
1.0
–
5.0
VDD
0.3VDD
0.4
μA
V
–
V
SERIAL DATA OUT
Voltage
VOL
VOH
RI
IOL = 500 μA
–
V
IOH = -500 μA
4.6
150
100
–
–
–
V
Input Resistance
Supply Current
ENABLE Input, Pull Up
LATCH Input, Pull Down
REXT = open, VOE = 5 V
REXT = 470 Ω, VOE = 5 V
REXT = 250 Ω, VOE = 5 V
REXT = 470 , VOE = 0 V
REXT = 250 , VOE = 0 V
300
200
0.8
6.0
11
13
22
600
400
1.4
k
k
mA
mA
mA
mA
mA
IDD(OFF)
3.5
6.5
7.0
10
8.0
15
IDD(ON)
20
32
Typical Data is at VDD = 5 V and is for design information only.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF.
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ. Max.
Unit
Propagation Delay Time
tpHL
CLOCK-OUTn
–
–
350
350
350
40
1000
1000
1000
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LATCH-OUTn
ENABLE-OUTn
–
CLOCK-SERIAL DATA OUT
CLOCK-OUTn
–
Propagation Delay Time
tpLH
–
300
300
300
40
1000
1000
1000
–
LATCH-OUTn
–
ENABLE-OUTn
–
CLOCK-SERIAL DATA OUT
90% to 10% voltage
10% to 90% voltage
–
Output Fall Time
Output Rise Time
tf
tr
150
150
350
300
1000
600
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Conditions
Min.
Typ. Max.
Unit
Supply Voltage
Output Voltage
Output Current
VDD
VO
IO
4.5
5.0
1.0
–
5.5
4.0
V
V
–
Continuous, any one output
SERIAL DATA OUT
–
90
mA
mA
mA
V
IOH
IOL
VIH
VIL
fCK
–
–
–
-1.0
SERIAL DATA OUT
–
1.0
Logic Input Voltage
Clock Frequency
0.7VDD
-0.3
–
–
VDD + 0.3
0.3VDD
10
–
V
Cascade operation
–
MHz
Allegro MicroSystems, Inc.
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
B
CLOCK
A
SERIAL
DATA IN
DATA
50%
t
p
SERIAL
DATA OUT
50%
DATA
D
E
LATCH
ENABLE
50%
OUTPUT
ENABLE
LOW = ALL OUTPUTS ENABLED
t
p
HIGH = OUTPUT OFF
50%
DATA
OUT
N
A. Data Active Time Before Clock Pulse
LOW = OUTPUT ON
Dwg. WP-029-1
(Data Set-Up Time), tsu(D) ............................. 50 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ................................. 20 ns
C. Clock Pulse Width, tw(CK) .................................. 50 ns
D. Time Between Clock Activation
HIGH = ALL OUTPUTS DISABLED (BLANKED)
and Latch Enable, tsu(L) ............................... 100 ns
E. Latch Enable Pulse Width, tw(L) ...................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................... 4.5 μs
50%
OUTPUT
ENABLE
t
F
pLH
t
t
r
f
90%
NOTE: Timing is representative of a 10 MHz clock. Sig-
nificantly higher speeds are attainable.
50%
10%
OUT
N
DATA
t
pHL
Max. Clock Transition Time, tr or tf ....................... 10 μs
Dwg. WP-030-1A
Serial data present at the input is transferred to the shift
register on the logic 0-to-logic 1 transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data in-
formation towards the SERIAL DATA OUTPUT. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to-
parallel conversion). The latches continue to accept new data as
long as the LATCH ENABLE is held high. Applications where
the latches are bypassed (LATCH ENABLE tied high) will
require that the OUTPUT ENABLE input be high during serial
data entry.
When the OUTPUT ENABLE input is high, the output sink
drivers are disabled (OFF). The information stored in the latches
is not affected by the OUTPUT ENABLE input. With the OUT-
PUT ENABLE input low, the outputs are controlled by the state
of their respective latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE
A6276EA A6276ELW
100
80
60
40
20
100
V
CE = 1 V
V
CE = 0.7 V
VCE = 1 V
80
V
CE = 2 V
V
CE = 3 V
V
CE = 2 V
60
V
CE = 3 V
V
CE = 4 V
VCE = 4 V
40
T
V
A
= +25oC
T
V
A
= +25oC
DD = 5 V
DD = 5 V
20
0
RQJA = 75oC/W
RQJA = 50oC/W
0
0
0
20
40
60
80
100
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-6
Dwg. GP-062-11
100
80
60
40
20
100
V
CE = 1 V
V
CE = 0.7 V
80
60
40
V
CE = 2 V
V
CE = 1 V
VCE = 3 V
V
CE = 2 V
V
CE = 3 V
VCE = 4 V
V
CE = 4 V
T
V
A
= +50oC
T
V
A
= +50oC
DD = 5 V
DD = 5 V
20
0
R
QJA = 50oC/W
R
Q
JA = 75oC/W
0
0
20
40
60
80
100
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-10
Dwg. GP-062-7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A6276EA
A6276ELW
100
100
80
60
40
20
VCE = 0.4 V
V
CE = 0.7 V
VCE = 1 V
80
VCE = 0.7 V
VCE = 1 V
V
CE = 2 V
60
VCE = 2 V
V
CE = 3 V
VCE = 3 V
40
V
CE = 4 V
VCE = 4 V
T
V
A
= +85oC
T
V
A
= +85oC
DD = 5 V
20
0
DD = 5 V
RQJA = 75oC/W
RQJA = 50oC/W
0
0
0
20
40
60
80
100
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-8
Dwg. GP-062-9
TYPICAL CHARACTERISTICS
60
40
20
T = +25oC
A
R
EXT = 500 7
0
0
2.0
0.5
1.0
1.5
VCE IN VOLTS
Dwg. GP-063
Allegro MicroSystems, Inc.
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A6276ELP
100
VCE = 1 V
80
60
40
V
CE = 2 V
VCE = 3 V
VCE = 4 V
T
A
= +25ı°C
V
DD = 5 V
20
0
RˇQJA = 40°ıC/W
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
100
80
VCE = 1 V
VCE = 2 V
VCE = 3 V
60
VCE = 4 V
40
T
A
= +50ı°C
V
DD = 5 V
20
0
RˇQJA = 40ı°C/W
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
Allegro MicroSystems, Inc.
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
Applications Information
The load current per bit (IO) is set by the external resistor
(REXT) as shown in the figure below.
diode (VZ), or a series string of diodes (approximately
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
provide supply voltages as low as 3.3 V.
100
V
CE = 0.7 V
80
For reference, typical LED forward voltages are:
White
Blue
Green
Yellow
Amber
Red
3.5 – 4.0 V
3.0 – 4.0 V
1.8 – 2.2 V
2.0 – 2.1 V
1.9 – 2.65 V
1.6 – 2.25 V
1.2 – 1.5 V
60
40
20
Infrared
Pattern Layout. This device has a common logic-ground
and power-ground terminal. If ground pattern layout
contains large common-mode resistance, and the voltage
between the system ground and the LATCH ENABLE or
CLOCK terminals exceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
0
5 k
2 k
EXT IN OHMS
3 k
100
200
300
500
700
1 k
CURRENT-CONTROL RESISTANCE, R
Dwg. GP-061
Package Power Dissipation (PD). The maximum al-
lowable package power dissipation is determined as
PD(max) = (150 - TA)/RJA
.
The actual package power dissipation is
PD(act) = DC • (VCE • IO • 16) + (VDD • IDD) ,
where DC is the duty cycle.
V
LED
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if PD(act) > PD(max), an external voltage re-
ducer (VDROP) should be used.
V
DROP
V
F
Load Supply Voltage (VLED). These devices are de-
signed to operate with driver voltage drops (VCE) of
0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is recom-
mended to use the lowest possible load supply voltage or
to set any series dropping voltage (VDROP) as
V
CE
Dwg. EP-064
VDROP = VLED - VF - VCE
with VDROP = Io • RDROP for a single driver, or a Zener
Allegro MicroSystems, Inc.
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
Package A, 24-pin DIP
+0.25
–0.64
30.10
24
+0.10
0.38
–0.05
+0.76
–0.25
+0.38
10.92
–0.25
6.35
7.62
A
1
2
For Reference Only
(reference JEDEC MS-001 BE)
Dimensions in millimeters
5.33 MAX
+0.51
3.30
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
–0.38
1.27 MIN
A
2.54
Terminal #1 mark area
+0.25
–0.38
1.52
0.018
0.46 ±0.12
Package A, 24-pin TSSOP
with exposed thermal pad
0.65
7.80 ±0.10
0.45
4° ±4
24
+0.05
0.15
–0.06
B
3.00
6.10
3.00 4.40 ±0.10 6.40 ±0.20
0.60 ±0.15
A
(1.00)
1
2
4.32
0.25
1.65
4.32
PCB Layout Reference View
24X
C
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
C
0.10
C
+0.05
–0.06
0.25
0.65
1.20 MAX
For Reference Only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
0.15 MAX
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Terminal #1 mark area
A
B
C
Exposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
Package LW, 24-pin SOICW
15.40±0.20
4° ±4
0.27
24
24
+0.07
–0.06
2.20
10.30±0.33
7.50±0.10
9.60
A
2
+0.44
–0.43
0.84
1
1
2
0.65
1.27
0.25
PCB Layout Reference View
B
24X
C
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
0.10
C
For Reference Only
(Reference JEDEC MS-013 AD)
0.41 ±0.10
1.27
2.65 MAX
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.20 ±0.10
Terminal #1 mark area
A
B
Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©2000-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
13
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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