A5842SLWTR [ALLEGRO]
Latch Based Peripheral Driver, 0.5A, BIMOS, PDSO20, SOIC-20;
| 型号： | A5842SLWTR |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Latch Based Peripheral Driver, 0.5A, BIMOS, PDSO20, SOIC-20 外围驱动器 驱动程序和接口 接口集成电路 光电二极管 输入元件 |
| 文件： | 总8页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5842 AND
5841
BiMOS II 8-BIT SERIAL-INPUT,
LATCHED DRIVERS
The merging of low-power CMOS logic and bipolar output power
drivers permit the UCN5841/42A, UCN5841/42LW, and A5841/42SLW
integrated circuits to be used in a wide variety of peripheral power
driver applications. Each device has an eight-bit CMOS shift register
and CMOS control circuitry, eight CMOS data latches, and eight bipolar
current-sinking Darlington output drivers. The 500 mA npn Darlington
outputs, with integral transient-suppression diodes, are suitable for use
with relays, solenoids, and other inductive loads. Except for packaging
and the maximum driver output voltage ratings, the UCN5841A,
UCN5841LW, A5841SLW, UCN5842A, UCN5842LW, and A5842SLW
are identical. All package variations of the 5842 offer premium perfor-
mance with a minimum output-breakdown voltage rating of 80 V (50 V
sustaining). All drivers can be operated with a split supply where the
negative supply is up to -20 V.
UCN5841A & UCN5842A
18 OUT
17 OUT
V
1
2
3
4
1
EE
SUB
CLK
CLOCK
2
3
SERIAL
DATA IN
OUT
16
LOGIC
GROUND
15 OUT
14 OUT
13 OUT
4
5
6
7
8
LOGIC
SUPPLY
V
5
6
DD
SERIAL
DATA OUT
OUT
11 OUT
10
ST
12
STROBE
7
8
9
OUTPUT
ENABLE
OE
K
BiMOS II devices have higher data-input rates than the earlier
BiMOS circuits. With a 5 V logic supply, they will typically operate at
better than 5 MHz. With a 12 V supply, significantly higher speeds are
obtained. The CMOS inputs are compatible with standard CMOS and
NMOS logic levels. TTL circuits may require the use of appropriate
pull-up resistors. By using the serial data output, drivers can be
cascaded for interface applications requiring additional drive lines.
V
EE
SUB
Dwg. PP-026-1
Note that the UCN584xA (dual in-line package) and
UCN584xLW (small-outline IC package) are electrically
identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at 25°C Free-Air Temperature
The UCN584xA devices are furnished in a standard 18-pin plastic
DIP; the UCN584xLW devices are in an 18-lead surface-mountable
wide-body SOIC package; the A584xSLW devices are provided in a 20-
lead wide-body SOIC package with improved thermal characteristics.
Output Voltage, V
CE
(5841). . . . . . . . . . . . . . . . . . . . . . 50 V
(5842). . . . . . . . . . . . . . . . . . . . . . 80 V
Output Voltage, V
CE(sus)
(5841). . . . . . . . . . . . . . . . . . . . . 35 V†
(5842). . . . . . . . . . . . . . . . . . . . . 50 V†
Logic Supply Voltage Range,
The A5841SLW and UCN5841LW drivers are also available for
operation to a temperature of -40°C. To order, change the suffix from
‘SLW’ to ‘ELW’, or change the prefix from ‘UCN’ to ‘UCQ’.
V
V
. . . . . . . . . . . . . . . . 4.5 V to 15 V
DD
DD
FEATURES
with Reference to V
. . . . . 25 V
EE
Emitter Supply Voltage, V . . . . . . . -20 V
EE
ꢀ To 3.3 MHz Data-Input Rate
ꢀ CMOS, NMOS, TTL Compatible Inputs
ꢀ Internal Pull-Up/Pull-Down Resistors
ꢀ Low-Power CMOS Logic and Latches,
ꢀ High-Voltage Current-Sink Outputs
ꢀ Output Transient-Protection Diodes
ꢀ Single or Split Supply Operation
ꢀ DIP or SOIC Packaging
Input Voltage Range,
V
. . . . . . . . . . . -0.3 V to V
+ 0.3 V
IN
DD
Continuous Output Current,
I
. . . . . . . . . . . . . . . . . . . . 500 mA
OUT
Package Power Dissipation,
P
. . . . . . . . . . . . . . . . . . . See Graph
D
Operating Temperature Range,
T . . . . . . . . . . . . . . . . -20°C to +85°C
A
Storage Temperature Range,
T . . . . . . . . . . . . . . . -55°C to +150°C
S
†For inductive load applications.
ꢀ Automotive Capable
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
Always order by complete part number, e.g., A5841SLW .
5841 AND 5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
(‘A’ Package Shown)
LOGIC
SUPPLY
V
5
DD
CLOCK
2
SERIAL
DATA IN
SERIAL
DATA OUT
3
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
6
7
LOGIC
GROUND
STROBE
4
OUTPUT ENABLE
(ACTIVE LOW)
8
MOS
BIPOLAR
1
9
POWER
GROUND
14
18
17
16
15
13
12
11
10
OUT OUT
OUT OUT OUT
OUT OUT OUT
K
1
2
3
4
5
6
7
8
SUB
Dwg. FP-013-2
2.5
2.0
1.5
1.0
0.5
0
A5841SLW
& A5842SLW
18-PIN DIP, RθJA = 60°C/W
POWER
GROUND
OUT
OUT
1
2
3
4
20
19
1
2
20-LEAD SOIC, RθJA = 70°C/W
18-LEAD SOIC, RθJA = 80°C/W
SUB
CLK
CLOCK
SERIAL
DATA IN
18 OUT
17 OUT
3
4
5
6
7
GROUND
16
OUT
V
5
6
LOGIC SUPPLY
DD
SERIAL
DATA OUT
15 OUT
ST
14
13
OUT
OUT
STROBE
7
8
OUTPUT
ENABLE
OE
8
POWER
GROUND
9
12
K
SUB
NO
CONNECT.
NO
CONNECT.
10 NC
NC 11
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. PP-029-3
Dwg. GP-022-4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2000 Allegro MicroSystems, Inc.
5841 AND 5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, VEE = 0 V
(unless otherwise specified).
Applicable
Devices
Limits
Max.
Characteristic
Symbol
Test Conditions
VOUT = 50 V
Min.
Unit
Output Leakage Current
ICEX
5841*
5842*
All
—
—
50
100
50
µA
µA
µA
µA
V
VOUT = 50 V, TA = +70°C
VOUT = 80 V
—
VOUT = 80 V, TA = +70°C
IOUT = 100 mA
—
100
1.1
1.3
1.6
—
Collector-Emitter
Saturation Voltage
VCE(SAT)
—
IOUT = 200 mA
—
V
IOUT = 350 mA, VDD = 7.0 V
IOUT = 350 mA, L = 2 mH
IOUT = 350 mA, L = 2 mH
—
V
Collector-Emitter
Sustaining Voltage
VCE(sus)
5841*
5842*
All
35
50
—
V
—
V
Input Voltage
VIN(0)
VIN(1)
0.8
—
V
All
VDD = 12 V
10.5
8.5
3.5
50
50
50
—
V
VDD = 10 V
—
V
VDD = 5.0 V
—
V
Input Resistance
Supply Current
RIN
All
All
All
VDD = 12 V
—
kΩ
kΩ
kΩ
mA
mA
mA
mA
mA
mA
µA
µA
V
VDD = 10 V
—
VDD = 5.0 V
—
IDD(ON)
All Drivers ON, VDD = 12 V
All Drivers ON, VDD = 10 V
All Drivers ON, VDD = 5.0 V
All Drivers OFF, VDD = 12 V
All Drivers OFF, VDD = 10 V
All Drivers OFF, VDD = 5.0 V
VR = 50 V
16
—
14
—
8.0
2.9
2.5
1.6
50
IDD(OFF)
—
—
—
Clamp Diode
Leakage Current
IR
5841*
5842*
All
—
VR = 80 V
—
50
Clamp Diode
VF
IF = 350 mA
—
2.0
Forward Voltage
* Complete part number includes a prefix (A or UCN) and a suffix (A, LW, or SLW) as follows:
UCN5841A, UCN5841LW, or A5841SLW,
UCN5842A, UCN5842LW, or A5842SLW.
www.allegromicro.com
5841 AND 5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
CLOCK
TYPICAL INPUT CIRCUITS
D
A
B
V
DD
DATA IN
STROBE
F
E
C
STROBE
OUTPUT
ENABLE
OUTPUT
ENABLE
G
OUT
N
Dwg. No. A-12,627
Dwg. EP-010-3
V
TIMING CONDITIONS
DD
(TA = +25°C, VDD = 5.0 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
CLOCK
SERIAL
DATA IN
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
Output Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 µs
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
Serial Data present at the input is transferred to the shift register
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
K
Information present at any register is transferred to its respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is held
high. Applications where the latches are bypassed (STROBE tied high)
will require that the ENABLE input be high during serial data entry.
OUT
V
EE
When the ENABLE input is high, all of the output buffers are
disabled (OFF) without affecting the information stored in the latches or
shift register. With the ENABLE input low, the outputs are controlled by
the state of the latches.
SUB
Dwg. EP-021-8
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5841 AND 5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TRUTH TABLE
Serial
Data Clock
Input Input I
Shift Register Contents
Serial
Data Strobe
Output Input
Latch Contents
.............. I
Output Contents
Output
I
I
.............. I
I
I
I
Enable
I
I
I
..............
I
8
1
2
3
8
1
2
3
8
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
.............. R
.............. R
.............. R
.............. X
R
R
R
X
1
1
2
2
2
3
7
7
8
7
7
8
X
R
1
X
L
R
R
R
.............. R
1
2
3
8
P
P
P
.............. P
P
H
P
X
P
X
P
X
.............. P
.............. X
L
P
P
P
..............
P
8
1
2
3
8
8
1
2
3
8
1
2
3
H
H H H .............. H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
TYPICAL APPLICATION
RELAY/SOLENOID DRIVER
Using Split Supply
UCN5842A
The products described here are manufactured
under one or more U.S. patents or U.S. patents
pending.
Allegro MicroSystems, Inc. reserves the right to
make, from time to time, such departures from the detail
specifications as may be required to permit improve-
ments in the performance, reliability, or
manufacturability of its products. Before placing an
order, the user is cautioned to verify that the informa-
tion being relied upon is current.
Allegro products are not authorized for use as
critical components in life-support devices or systems
without express written approval.
The information included herein is believed to be
accurate and reliable. However, Allegro
MicroSystems, Inc. assumes no responsibility for its
use; nor for any infringement of patents or other rights
of third parties which may result from its use.
Dwg. No. A-12,547
www.allegromicro.com
5841 AND 5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5841A and UCN5842A
Dimensions in Inches
(controlling dimensions)
0.014
0.008
18
10
0.430
MAX
0.280
0.240
0.300
BSC
1
9
0.100
0.070
0.045
0.005
BSC
MIN
0.920
0.880
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-18A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
18
10
10.92
MAX
7.11
6.10
7.62
BSC
1
9
2.54
1.77
1.15
0.13
BSC
MIN
23.37
22.35
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-18A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5841 AND 5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5841LW and UCN5842LW
Dimensions in Inches
(for reference only)
10
18
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
BSC
0° TO 8°
0.4625
0.4469
0.0926
0.1043
Dwg. MA-008-18A in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
18
10
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
11.75
11.35
2.65
2.35
Dwg. MA-008-18A mm
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
5841 AND 5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
A5841SLW and A5842SLW
Dimensions in Inches
(for reference only)
20
11
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
BSC
0° TO 8°
0.5118
0.4961
0.0926
0.1043
Dwg. MA-008-20 in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
20
11
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
13.00
12.60
2.65
2.35
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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