A3972SB [ALLEGRO]
DUAL DMOS FULL-BRIDGE MICROSTEPPING PWM MOTOR DRIVER; 双DMOS全桥PWM微电机驱动器
| 型号： | A3972SB |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | DUAL DMOS FULL-BRIDGE MICROSTEPPING PWM MOTOR DRIVER |
| 文件： | 总12页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3972
DUAL DMOS FULL-BRIDGE MICRO-
STEPPING PWM MOTOR DRIVER
Designed for pulse-width modulated (PWM) current control of
bipolar microstepping stepper motors, the A3972SB is capable of
continuous output currents to 1.5 A and operating voltages to 50 V.
Internal fixed off-time PWM current-control timing circuitry can be
programmed via a serial interface to operate in slow, fast, and mixed
current-decay modes.
VCP
CP1
CP2
OSC
23 SLEEP
24
1
2
3
4
VREG
22
OUT1B
LOAD
21 OUT2B
The desired load-current level is set via the serial port with two 6-bit
linear DACs in conjunction with a reference voltage. The six bits of
control allow maximum flexibility in torque control for a variety of step
methods, from microstepping to full-step drive. Load current is set in
1.56% increments of the maximum value.
LOAD
SUPPLY
20
5
6
7
8
SUPPLY
1
V
BB1
V
BB2
2
19
18
GROUND
GROUND
GROUND
GROUND
SENSE
1
SENSE
2
Synchronous rectification circuitry allows the load current to flow
through the low rDS(on) of the DMOS output driver during the current
decay. This feature will eliminate the need for external clamp diodes in
most applications, saving cost and external component count, while
minimizing power dissipation.
17
16
9
OUT2A
LOGIC
OUT1A
STROBE
VDD
15
14
13
10
11
SUPPLY
MUX
CLOCK
Internal circuit protection includes thermal shutdown with hyster-
esis, transient-suppression diodes, and crossover-current protection.
Special power-up sequencing is not required.
REF
DATA 12
Dwg. PP-069-3
The A3972SB is supplied in a 24-lead plastic DIP with a copper
batwing power tab (suffix ‘B’). The power tab is at ground potential and
needs no electrical isolation.
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB ................ 50 V
Output Current, IOUT ...................... 1.5 A
Logic Supply Voltage, VDD .............. 7.0 V
Logic Input Voltage Range,
VIN ................ -0.3 V to VDD + 0.3 V
Reference Voltage, VREF ..................... 3 V
Sense Voltage (dc), VS ................ 500 mV
Package Power Dissipation,
PD .......................................... 3.1 W
Operating Temperature Range,
TA .......................... -20°C to +85°C
Junction Temperature, TJ ............. +150°C
Storage Temperature Range,
FEATURES
I
1.5 A, 50 V Continuous Output Rating
I Low rDS(on) DMOS Output Drivers
I Optimized Microstepping via 6-Bit Linear DACs
I Programmable Mixed, Fast, and Slow Current-Decay Modes
I 4 MHz Internal Oscillator for Digital Timing
I Serial-Interface Controls Chip Functions
I Synchronous Rectification for Low Power Dissipation
I Internal UVLO and Thermal Shutdown Circuitry
I Crossover-Current Protection
TS ......................... -55°C to +150°C
I Precision 2 V Reference
Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the
specified current rating or a junction tempera-
ture of 150°C.
I Inputs Compatible with 3.3 V or 5 V Control Signals
I Sleep and Idle Modes
Always order by complete part number: A3972SB .
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
0.22 µF
0.22 µF
V
CP2
CP1
REG
22
3
2
LOGIC
SUPPLY
LOAD
SUPPLY
2 V
V
V
CP
UVLO AND
FAULT
DETECT
REGULATOR
BANDGAP
1
5
CHARGE PUMP
DMOS H-BRIDGE
15
14
V
DD
0.22 µF
BB1
MUX
6-BIT
LINEAR
DAC
SENSE
1
V
CP
+
-
OUT
1A
6
9
4
PROGRAMMABLE
PWM TIMER
OUT
1B
OSCILATOR
OSC
FIXED-OFF
BLANK
MIXED DECAY
OSC SELECT/
DIVIDER
24
SENSE
1
8
11
12
10
CLOCK
DATA
CONTROL
LOGIC
SERIAL
PORT
GATE
DRIVE
0.1 µF
DMOS H-BRIDGE
20
PHASE 1/2
SYNC. RECT. MODE
SYNC. RECT. DISABLE
MODE 1/2
V
STROBE
BB2
23
SLEEP
OUT
2A
16
21
PROGRAMMABLE
PWM TIMER
OUT
2B
2 V
FIXED-OFF
BLANK
MIXED DECAY
6
BUFFER
REF
13
+
-
SENSE
6-BIT
LINEAR
DAC
2
17
0.1 µF
6
7
18 19
GROUND
Dwg. FP-050-1
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
2
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VS = 0.5 V,
fPWM < 50 kHz (unless otherwise noted).
Limits
Characteristic
Symbol
Test Conditions
Operating
Min.
15
0
Typ. Max.
Units
V
Load Supply Voltage Range
VBB
—
—
5.0
—
—
—
—
—
—
—
50
50
During sleep mode
Operating
V
Logic Supply Voltage Range
Load Supply Current
VDD
IBB
4.5
—
—
—
—
—
—
—
5.5
8.0
6.0
20
V
fPWM < 50 kHz
mA
mA
µA
mA
mA
mA
µA
Operating, outputs disabled
Sleep or idle mode
fPWM < 50 kHz
Logic Supply Current
IDD
12
Outputs off
10
Idle mode (D0 = 1, D18 = 0)
Sleep mode
1.5
100
Output Drivers
Output Leakage Current
IDSS
rDS(on)
VF
VOUT = VBB
—
—
—
—
—
—
<1.0
<-1.0
0.5
50
-50
µA
µA
Ω
VOUT = 0 V
Output On Resistance
Source driver, IOUT = –1.5 A
Sink driver, IOUT = 1.5 A
Source diode, IF = 1.5 A
Sink diode, IF = 1.5 A
0.55
0.315 0.35
Ω
Body Diode Forward Voltage
—
—
1.2
1.2
V
V
Control Logic
Logic Input Voltage
VIN(1)
VIN(0)
IIN(1)
2.0
—
—
—
—
0.8
20
V
V
Logic Input Current
VIN = 2.0 V
—
<1.0
µA
IIN(0)
fOSC
VIN = 0.8 V
—
<-2.0
—
-20
6.0
µA
OSC Input Frequency Range
Divide by one
2.5
MHz
(D0 =1, D13 = 0, D14 = 1)
OSC Input Duty Cycle
Input Hysterisis
—
40
—
—
60
%
V
∆VIN
0.20
0.40
continued next page ...
www.allegromicro.com
3
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VS = 0.5 V,
fPWM < 50 kHz (unless otherwise noted).
Limits
Characteristics
Symbol
fOSC
Test Conditions
Min.
Typ. Max.
Units
Control Logic (continued)
Internal Oscillator
OSC shorted to ground
ROSC = 51 kΩ
3.0
3.4
—
4.0
4.0
1/2
5.0
4.6
—
MHz
MHz
LSB
DAC Accuracy (total error)
ET
Relative to DAC reference buffer
output, D0 = 0, D17 = 0
Reference Input Voltage Range
Reference Buffer Offset
VREF(EXT)
VOS
0.5
—
—
10
2.6
—
V
mV
—
—
µA
V
Reference Divider Ratio
VREF/VS
D0 = 0, D18 = 0
D0 = 0, D18 = 1
VREF = 2.0 V
—
8.0
4.0
—
—
—
—
Reference Input Current
Internal Reference Voltage
Gain (Gm) Error (note 3)
IREF
VREF(INT)
EG
—
0.5
2.06
1.94
2.0
D0 = 0, D17 = 0,
D18 = 0, DAC = 63
D18 = 0, DAC = 31
D18 = 1, DAC = 63
—
—
—
0
0
0
6
9
6
%
%
%
D18 = 1, DAC = 15
VREF = 0 V
—
—
0
10
—
%
Comparator Input Offset Voltage
Propagation Delay Times
VIO
tpd
5.0
mV
50% to 90%:
PWM change to source on
PWM change to source off
PWM change to sink on
500
50
800
150
800
1200
350
ns
ns
ns
500
1200
PWM change to sink off
50
300
—
150
700
165
15
350
900
—
ns
ns
°C
°C
V
Crossover Dead Time
tdt
TJ
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
∆TJ
—
—
VUVLO
∆VUVLO
Increasing VDD
3.9
0.05
4.2
4.45
—
0.10
V
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. EG = [(VREF/Range) – VS]/(VREF/Range).
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
Serial Interface. The A3972SB is controlled via a 3-wire
(clock, data, strobe) serial port. The programmable functions
allow maximum flexibility in configuring the PWM to the
motor drive requirements. The serial data is written as two
19-bit words: 1 bit to select the word and 18 bits of data. The
serial data is clocked in starting with D18.
D13 Bridge 1 Phase. This bit controls the direction of
output current for Load 1.
D13
OUT1A
OUT1B
0
1
L
H
H
L
D14 Bridge 2 Phase. This bit controls the direction of
output current for Load 2.
Word 0 Bit Assignments
Bit
Function
D14
OUT2A
OUT2B
D0
Word select = 0
0
1
L
H
H
L
D1
D2
D3
D4
D5
D6
D7
D8
Bridge 1, DAC, LSB
Bridge 1, DAC, bit 2
Bridge 1, DAC, bit 3
Bridge 1, DAC, bit 4
Bridge 1, DAC, bit 5
Bridge 1, DAC, MSB
Bridge 2, DAC, LSB
Bridge 2, DAC, bit 2
Bridge 2, DAC, bit 3
Bridge 2, DAC, bit 4
Bridge 2, DAC, bit 5
Bridge 2, DAC, MSB
Bridge 1 phase
D15 Bridge 1 Mode.
D15
Mode
0
1
Mixed-decay
Slow-decay
D16 Bridge 2 Mode.
D16
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
Mode
0
1
Mixed-decay
Slow-decay
Bridge 2 phase
Bridge 1 mode
Bridge 2 mode
REF select
D17 REF Select. This bit determines the reference input for
the 6-bit linear DACs.
D17
Reference Voltage
0
1
Internal 2 V
External (3 V max)
Range select
D1 – D6 Bridge 1 Linear DAC. Six-bit word sets desired
current level for Bridge 1. Setting all six bits to zero disables
Bridge 1, with all drivers off (See current regulation section of
functional description).
D18 Gm Range Select. This bit determines the scaling factor
(4 or 8) used.
D18
Divider
Load Current
0
1
1/
1/
8
4
TRIP = VDIAC/8RS
TRIP = VDIAC/4RS
D7 – D12 Bridge 2 Linear DAC. Six-bit word sets desired
current level for Bridge 2. Setting all six bits to zero disables
Bridge 2, with all drivers off (See current regulation section of
functional description).
continued next page ...
www.allegromicro.com
5
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
Word 1 Bit Assignments
For example, with a master oscillator frequency of 4 MHz, the
fast-decay time will be adjustable from 1.75 µs to 63.75 µs in
increments of 2 µs.
Bit
Function
D0
D1
D2
D3
Word select = 1
Blank-time LSB
Blank-time MSB
Off-time LSB
D8 – D11 Fast Decay Time. These four bits set the fast-
decay portion of fixed off-time for the internal PWM control
circuitry. The fast-decay portion is defined by:
D4
Off-time bit 1
tfd = [(1 + N) x 8/fOSC] - 1/fOSC
D5
D6
Off-time bit 2
Off-time bit 3
where N = 0….15
For example, with an oscillator frequency of 4 MHz, the fast-
decay time will be adjustable from 1.75 µs to 31.75 µs in
increments of 2 µs. For tfd > toff , the device will effectively
operate in fast-decay mode.
D7
D8
D9
Off-time MSB
Fast-decay time LSB
Fast-decay time bit 1
Fast-decay time bit 2
Fast-decay time MSB
C0 oscillator control
C1 oscillator control
SR control bit 1
SR control bit 2
Reserved for testing
Reserved for testing
Idle mode
D10
D11
D12
D13
D14
D15
D16
D17
D18
D12 – D13 Oscillator Control. A 4 MHz internal oscillator
is used for the timing functions and charge-pump clock. If
more precise control is required, an external oscillator can be
input to the OSC terminal. To accommodate a wider range of
system clocks, an internal divider is provided to generate the
desired MO frequency according to the following table:
D13
D12
OSC
0
0
1
1
0
1
0
1
4 MHz internal clock
External clock
External clock/2
External clock/4
D1 – D2 Blank Time. These two bits set the blank time for
the current-sense comparator. When a source driver turns on, a
current spike occurs due to the reverse-recovery currents of the
clamp diodes and/or switching transients related to distributed
capacitance in the load. To prevent this current spike from
erroneously resetting the source-enable latch, the sense com-
parator is blanked. The blank timer runs after the off-time
counter to provide the programmable blanking function. The
blank timer is reset when PHASE is changed.
D14 – D15 Synchronous Rectification.
D15
D14
Synchronous Rectifier
0
0
1
1
0
1
0
1
Active
Disabled
Passive
Low side only
D2
D1
Time
The different modes of operation are in the synchronous
rectification section of the functional description.
0
0
1
0
1
0
4/fOSC
6/fOSC
8/fOSC
D16, D17. These bits are reserved for testing and should be
1
1
12/fOSC
programmed to zero during normal operation.
D18 Idle Mode. The device can be placed in a low power
“idle” mode by writing a “0” to D18. The outputs will be
disabled, the charge pump will be turned off, and the device
will draw a lower load supply currrent. The undervoltage
monitor circuit will remain active. D18 should be programmed
high for 1 ms before attempting to enable any output driver.
D3 – D7 Fixed Off Time. These five bits set the fixed off-
time for the internal PWM control circuitry. Fixed off-time is
defined by:
toff = [(1 + N) x 8/fOSC] - 1/fOSC
where N = 0….31
continued next page ...
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
VREG. This internally generated supply voltage is used to run
the sink-side DMOS outputs. VREG is internally monitored and
in the case of a fault condition, the outputs of the device are
disabled. The VREG pin should be decoupled with a 0.22 µF
capacitor to ground.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VREG, the outputs of the
device are disabled until the fault condition is removed. At
power up, or in the event of low VDD, the UVLO circuit
disables the drivers and resets the data in the serial port to zeros.
Current Regulation. The reference voltage can be set by
analog input to the REF terminal, or via the internal 2 V
precision reference. The choice of reference voltage and sense
resistor set the maximum trip current.
Synchronous Rectification. When a PWM off-cycle is
triggered, either by a bridge disable command or internal fixed
off-time cycle, the load current will recirculate according to the
decay mode selected by the control logic. The A3972SB
synchronous rectification feature will turn on the appropriate
MOSFET(s) during the current decay and effectively short out
the body diodes with the low rDS(on) driver. This will lower
power dissipation significantly and can eliminate the need for
external Schottky diodes for most applications.
I
TRIPMAX = VREF/(Range x RS)
Microstepping current levels are set according to the following
equations:
ITRIP = VDAC/(Range x RS)
VDAC = [(1 + DAC) x VREF]/64
Four distinct modes of operation can be configured with the two
serial port control bits:
where DAC input code equals 1 to 63 and Range is 4 or 8 as
selected by Word 0, D18. Programming the DAC input code to
zero disables the bridge, and results in minimum load current.
1. Active Mode. Prevents reversal of load current by
turning off synchronous rectification when a zero current
level is detected.
PWM Timer Function. The PWM timer is programmable via
the serial port to provide fixed off-time PWM signals to the
control block. In mixed-decay mode, the first portion of the off
time operates in fast decay, until the fast-decay time count is
reached, followed by slow decay for the rest of the fixed off-
time period. If the fast-decay time is set longer than the off-
time, the device effectively operates in fast-decay mode.
2. Passive Mode. Allows reversal of current but will turn
off the synchronous rectifier circuit if the load current
inversion ramps up to the current limit.
3. Disabled. MOSFET switching will not occur during load
recirculation. This setting would only be used with four
external clamp diodes per bridge.
Oscillator. The PWM timer is based on an oscillator input,
typically 4 MHz. The A3972SB can be configured to select
either a 4 MHz internal oscillator or, if more precision is
required, an external clock can be connected to the OSC
terminal. If an external clock is used, three internal divider
choices are selectable via the serial port to allow flexibility in
choosing fOSC, based on available system clocks. If the internal
oscillator option is used, the absolute accuracy is dependent on
the process variation of resistance and capacitance. A precision
resistor can be connected from the OSC terminal to VDD to
further improve the tolerance. The frequency will be:
4. Low Side Only. The low-side MOSFETs will switch on
during the off time to short out the current path through the
MOSFET body diode. With this setting, the high-side
MOSFETs will not synchronously rectify so four external
diodes from output to supply are recommended. This mode
is intended for use with high-power applications where it is
desired to save the expense of two external diodes per
bridge. In this mode, the sink-side MOSFETs are chopped
during the PWM off time. In all other cases, the source-
side MOSFETs are chopped in response to a PWM off
command.
fOSC = 204 x 109/ROSC
If the internal oscillator is used without the external resistor, the
OSC terminal should be connected to ground.
Sleep Mode. The input terminal SLEEP is dedicated to
putting the device into a minimum current draw mode. When
pulled low, the serial port will be reset to all zeros and all
circuits will be disabled.
continued next page ...
7
www.allegromicro.com
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
APPLICATIONS INFORMATION
Current Sensing. To minimize inaccuracies in sensing the
IPEAK current level caused by ground-trace IR drops, the sense
resistor should have an independent ground return to the ground
terminal of the device. For low-value sense resistors, the IR
drops in the sense resistor’s PCB traces can be significant and
should be taken into account. The use of sockets should be
avoided as they can introduce variation in RS due to their
contact resistance.
Layout. The printed wiring board should use a heavy ground
plane. For optimum electrical and thermal performance, the
driver should be soldered directly onto the board. The ground
side of RS should have an individual path to the ground pin(s) of
the driver. This path should be as short as physically possible
and should not have any other components connected to it. The
load supply pin, VBB, should be decoupled with an electrolytic
capacitor (>47 µF is recommended) placed as close to the driver
as is possible.
Thermal Protection. Circuitry turns off all drivers when the
junction temperature reaches 165°C typically. It is intended
only to protect the device from failures due to excessive
junction temperature and should not imply that output short
circuits are permitted. Thermal shutdown has a hysteresis of
approximately 15°C.
Serial Port Write Timing Operation. Data is clocked into a
shift register on the rising edge of CLOCK signal. Normally,
STROBE will be held high, and only will be brought low to
initiate a write cycle. The data is written MSB first, followed
by the word-select bit. Refer to serial port diagram for timing
requirements.
SLEEP
H
STROBE
E
C
D
F
G
CLOCK
DATA
A
B
D18
D17
D0
Dwg. WP-038-1
A. Minimum Data Setup Time ..................................... 15 ns
B. Minimum Data Hold Time ...................................... 10 ns
C. Minimum Setup Strobe to Clock Rising Edge...... 150 ns
D. Minimum Clock High Pulse Width......................... 40 ns
E. Minimum Clock Low Pulse Width ......................... 40 ns
F. Minimum Setup Clock Rising Edge to Strobe ........ 50 ns
G. Minimum Strobe Pulse Width............................... 150 ns
H. Minimum Setup Sleep to Strobe Falling................. 50 µs
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
Dimensions in Inches
(controlling dimesnions)
0.014
0.008
NOTE 1
24
13
0.430
MAX
0.300
BSC
0.280
0.240
1
6
7
12
0.100
BSC
0.070
0.045
0.005
MIN
1.280
1.230
0.210
MAX
0.015
MIN
0.150
0.115
0.022
0.014
Dwg. MA-001-25A in
NOTES:1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
4. Supplied in standard sticks/tubes of 15 devices.
www.allegromicro.com
9
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
Dimensions in Millimeters
(for reference only)
0.355
0.204
NOTE 1
24
13
10.92
MAX
7.11
6.10
7.62
BSC
1
6
7
12
2.54
BSC
1.77
1.15
0.13
MIN
32.51
31.24
5.33
MAX
0.39
MIN
3.81
2.93
0.558
0.356
Dwg. MA-001-25A mm
NOTES:1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
4. Supplied in standard sticks/tubes of 15 devices.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
11
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
MOTOR DRIVERS
Function
Output Ratings*
Part Number†
INTEGRATED CIRCUITS FOR BRUSHLESS DC MOTORS
3-Phase Power MOSFET Controller
3-Phase Power MOSFET Controller
3-Phase Power MOSFET Controller
2-Phase Hall-Effect Sensor/Driver
Bidirectional 3-Phase Back-EMF Controller/Driver
2-Phase Hall-Effect Sensor/Driver
3-Phase Back-EMF Controller/Driver
3-Phase Controller/Drivers
—
—
—
28 V
50 V
50 V
26 V
14 V
14 V
14 V
45 V
3933
3932
7600
3626
8906
3625
8902–A
2936 & 2936-120
400 mA
600 mA
900 mA
900 mA
2.0 A
INTEGRATED BRIDGE DRIVERS FOR DC AND BIPOLAR STEPPER MOTORS
Dual Full Bridge with Protection & Diagnostics
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Dual DMOS Full Bridge
PWM Current-Controlled Full Bridge
PWM Current-Controlled Dual Full Bridge
PWM Current-Controlled Microstepping Full Bridge
PWM Current-Controlled Microstepping Full Bridge
PWM Current-Controlled Dual DMOS Full Bridge
Dual Full-Bridge Driver
500 mA
650 mA
650 mA
750 mA
750 mA
750 mA
800 mA
1.0 A
1.3 A
1.5 A
1.5 A
1.5 A
30 V
30 V
30 V
45 V
45 V
45 V
33 V
35 V
50 V
45 V
50 V
50 V
50 V
50 V
50 V
50 V
50 V
3976
3966
3968
2916
2919
6219
3964
3973
3953
2917
3955
3957
3972
2998
3952
3958
3971
1.5 A
2.0 A
2.0 A
2.0 A
PWM Current-Controlled Full Bridge
DMOS Full Bridge PWM Driver
Dual DMOS Full Bridge
2.5 A
UNIPOLAR STEPPER MOTOR & OTHER DRIVERS
Voice-Coil Motor Driver
Voice-Coil Motor Driver
500 mA
800 mA
1 A
1.2 A
1.25 A
1.8 A
1.8 A
3 A
6 V
16 V
46 V
46 V
50 V
50 V
50 V
46 V
46 V
8932–A
8958
7024 & 7029
7042
5804
2540
Unipolar Stepper-Motor Quad Drivers
Unipolar Microstepper-Motor Quad Driver
Unipolar Stepper-Motor Translator/Driver
Unipolar Stepper-Motor Quad Driver
Unipolar Stepper-Motor Quad Driver
Unipolar Stepper-Motor Quad Driver
Unipolar Microstepper-Motor Quad Driver
2544
7026
3 A
7044
* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits
or over-current protection voltage limits. Negative current is defined as coming out of (sourcing) the output.
† Complete part number includes additional characters to indicate operating temperature range and package style.
Also, see 3175, 3177, 3235, and 3275 Hall-effect sensors for use with brushless dc motors.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
12
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