A3946 [ALLEGRO]
Half-Bridge Power MOSFET Controller; 半桥式功率MOSFET控制器
| 型号： | A3946 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Half-Bridge Power MOSFET Controller |
| 文件： | 总14页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A3946
Half-Bridge Power MOSFET Controller
Features and Benefits
Description
▪ On-chip charge pump for 7 V minimum input
supply voltage
TheA3946isdesignedspecificallyforapplicationsthatrequire
high power unidirectional DC motors, three-phase brushless DC
motors, or other inductive loads. The A3946 provides two
high-current gate drive outputs that are capable of driving a
wide range of power N-channel MOSFETs. The high-side gate
driver switches an N-channel MOSFET that controls current to
the load, while the low-side gate driver switches an N-channel
MOSFET as a synchronous rectifier.
▪ High-current gate drive for driving a wide range of
N-channel MOSFETs
▪ Bootstrapped gate drive with top-off charge pump
for 100% duty cycle
▪ Overtemperature protection
▪ Undervoltage protection
▪ –40ºC to 135ºC ambient operation
Abootstrapcapacitorprovidestheabove-batterysupplyvoltage
required for N-channel MOSFETs. An internal top-off charge
pump for the high side allows DC (100% duty cycle) operation
of the half-bridge.
Package: 16-pin TSSOP with exposed
thermal pad (Suffix LP)
The A3946 is available in a power package: a 16-lead TSSOP
with exposed thermal pad (suffix LP). It is lead (Pb) free, with
100% matte tin plated leadframe (suffix -T).
Approximate Scale 1:1
Typical Application
VBAT
VBB
BOOT
GH
~FAULT
ECU
IN1
S
A3946
IN2
PAD
GL
RESET
CP1
M
CP2
VREG
PGND
DT
VREF
LGND
29319.150i
Half-Bridge Power MOSFET Controller
A3946
Selection Guide
Part Number
Packing
Package
A3946KLPTR-T
4000 pieces/reel 16-pin TSSOP with exposed thermal pad
Absolute Maximum Ratings
Characteristic
Symbol
VBB
Notes
Rating
60
Units
V
Load Supply Voltage
Logic Inputs Voltage
VIN
–0.3 to 6.5
–4 to 60
–4 to 75
–0.6 to 75
VREF
V
Pin S Voltage
VS
V
Pin GH Voltage
VGH
V
Pin BOOT Voltage
VBOOT
VDT
V
Pin DT Voltage
V
Pin VREG Voltage
VREG
TA
–0.6 to 15
–40 to 135
150
V
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
Range K
ºC
ºC
ºC
V
TJ(max)
T
–55 to 150
2000
stg
ESD Rating, Human Body Model
ESD Rating, Charged Device Model
AEC-Q100-002, all pins
AEC-Q100-011, all pins
1050
V
THERMAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions*
Value Units
Mounted on a 2-layer PCB with 3.8 in2. 2-oz copper both sides
43
34
ºC/W
ºC/W
RθJA
Package Thermal Resistance
Mounted on a 4-layer PCB based on JEDEC standard
*Additional thermal information available on Allegro Web site.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
Functional Block Diagram
+VBAT
C1
C2
0.47 uF, X7R
V rated to VBAT
0.47 uF, X7R
V rated to VBAT
P
VBB
CP2
CP1
VREF
VREG
BOOT
Charge
Pump
+5 Vref
L
CREG
0.1 uF
X7R
10 V
ILIM
10
k7
P
L
P
Top-Off
Charge Pump
~FAULT
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
CBOOT
L
VREF
RGATE
GH
High Side
Driver
P
DT
Turn-On
Delay
RDEAD
IN1
Control
Logic
S
L
VREG
L
L
RGATE
IN2
GL
Low Side
Driver
PGND
LGND
L
P
RESET
L
P
PAD
Control Logic Table
IN1
X
0
IN2
X
0
DT Pin
X
RESET
GH
Z
GL
Z
Function
0
1
1
1
1
1
1
1
1
Sleep mode
R
DEAD - LGND
L
H
L
Low-side FET ON following dead time
0
1
RDEAD - LGND
RDEAD - LGND
RDEAD - LGND
VREF
L
All OFF
All OFF
1
0
L
L
1
1
H
L
L
High-side FET ON following dead time
All OFF
0
0
L
0
1
VREF
L
H
L
Low-side FET ON
1
0
VREF
H
H
High-side FET ON
1
1
VREF
H
CAUTION: High-side and low-side FETs ON
Allegro MicroSystems, Inc.
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)
Limits
Typ.
Characteristics
Symbol
IVBB
Test Conditions
Min.
Max.
6
Units
mA
μA
V
RESET = High, Outputs Low
3
–
VBB Quiescent Current
VREG Output Voltage
RESET = Low
10
–
12.0
–
13
VBB > 7.75 V, Ireg = 0 mA to 15 mA
VBB = 7 V to 7.75 V, Ireg = 0 mA to 15 mA
13.5
13.5
VREG
11.0
V
–
Charge Pump Frequency
VREF Output Voltage
FCP
CP1, CP2
62.5
kHz
V
–
–
VREF
IREF ≤ 4 mA, CREF = 0.1 ꢀF
4.5
5.5
–
–
Top-Off Charge Pump
Current
ITO
VBOOT – VS = 8.5 V
20
ꢀA
–
Gate Output Drive
Turn On Time
trise
tfall
CLOAD = 3300 pF, 20% to 80%
CLOAD = 3300 pF, 80% to 20%
Tj = 25C
60
40
4
100
80
ns
ns
V
–
Turn Off Time
–
–
–
Pullup On Resistance
RDSUP
Tj = 135C
6
8
–
–
Tj = 25C
2
–
Pulldown On Resistance
RDSDOWN
Tj = 135C
3
4
–
GH Output Voltage
GL Output Voltage
Timing
VGH
VGL
tpw < 10 ꢀs, Bootstrap Capacitor fully charged
VREG – 1.5
–
–
–
–
VREG – 0.2
V
–
Rdead = 5 kΩ
200
5
350
6
500
7
ns
Dead Time (Delay from
Turn Off to Turn On)
tDEAD
tPD
Rdead = 100 kΩ
ꢀs
Propagation Delay
Logic input to unloaded GH, GL. DT = VREF
150
ns
–
–
Allegro MicroSystems, Inc.
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)
Limits
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Protection
VREGOFF
VREGON
VBSOFF
VBSON
VREG decreasing
7.8
8.6
7.25
8
8.3
9.1
8.8
9.6
8.3
9.5
V
V
V
V
VREG Undervoltage
BOOT Undervoltage
VREG increasing
VBOOT decreasing
VBOOT increasing
7.8
8.75
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Logic
TJTSD
Temperature increasing
170
15
°C
°C
–
–
–
–
TJ
Recovery = TJTSD – TJ
Input Current
IIN(1)
IIN(0)
IN1 VIN / IN2 VIN = 2.0 V
IN1 VIN / IN2 VIN = 0.8 V
RESET pin only
IN1 / IN2 logic high
RESET logic high
Logic low
40
16
100
40
1
ꢀA
ꢀA
ꢀA
V
–
–
–
2.0
–
–
–
–
–
–
–
Logic Input Voltage
VIN(1)
–
–
0.8
300
400
1
2.2
V
VIN(0)
V
–
100
Logic Input Hysteresis
Fault Output
All digital inputs
mV
mV
ꢀA
–
Vol
Voh
I = 1 mA, fault asserted
V = 5 V
–
–
Allegro MicroSystems, Inc.
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
Functional Description
possible UVBOOT), FAULT = 0; also the fault latch is cleared
immediately, and remains cleared. If the power is restored
VREG. A 13 V output from the on-chip charge pump, used
to power the low-side gate drive circuit directly, provides the
current to charge the bootstrap capacitors for the high-side gate (no UVREG or UVREF), and if no OVERTEMP fault exists,
drive.
then the latched fault remains cleared when the RESET line
returns to high. However, FAULT = 1 may still occur because a
UVBOOT fault condition may still exist.
The VREG capacitor, CREG, must supply the instantaneous cur-
rent to the gate of the low-side MOSFET. A 10 μF, 25 V capaci-
tor should be adequate. This capacitor can be either electrolytic
or ceramic (X7R).
Charge Pump. The A3946 is designed to accommodate a
wide range of power supply voltages. The charge pump output,
VREG, is regulated to 13 V nominal.
Diagnostics and Protection. The fault output pin,
~FAULT, goes low (i.e., FAULT = 1) when the RESET line is
high and any of the following conditions are present:
In all modes, this regulator is current-limited. When VBB < 8 V,
the charge pump operates as a voltage doubler. When 8V <
VBB< 15V, the charge pump operates as a voltage doubler/
PWM, current-controlled, voltage regulator. When VBB>15V,
the charge pump operates as a PWM, current-controlled, volt-
age regulator. Efficiency shifts, from 80% at VBB= 7 V, to 20%
at VBB = 50 V.
• Undervoltage on VREG (UVREG). Note that the outputs
become active as soon as VREG comes out of undervoltage,
even though the ~FAULT pin is latched until reset.
• Undervoltage on VREF (UVREF). Note that this condition
does NOT latch a fault.
• A junction temperature > 170°C (OVERTEMP). This condi-
tion sets a latched fault.
• An undervoltage on the stored charge of the BOOT capacitor
(UVBOOT). This condition does NOT set a latched fault.
CAUTION. Although simple paralleling of VREG supplies
from several A3946s may appear to work correctly, such a
configuration is NOT recommended. There is no assurance that
one of the regulators will not dominate, taking on all of the load
and back-biasing the other regulators. (For example, this could
occur if a particular regulator has an internal reference voltage
that is higher that those of the other regulators, which would
force it to regulate at the highest voltage.)
An overtemperature event signals a latched fault, but does not
disable any output drivers, regulators, or logic inputs. The user
must turn off the A3946 (e.g., force the RESET line low) to
prevent damage.
The power FETs are protected from inadequate gate drive
voltage by undervoltage detectors. Either of the regulator
undervoltage faults (UVREG or UVREF) disable both output
drivers until both voltages have been restored. The high-side
driver is also disabled during a UVBOOT fault condition.
Sleep Mode/Power Up. In Sleep Mode, all circuits are
disabled in order to draw minimum current from VBB. When
powering up and leaving Sleep Mode (the RESET line is high),
the gate drive outputs stay disabled and a fault remains asserted
until VREF and VREG pass their undervoltage thresholds.
When powering up, before starting the first bootstrap charge
cycle, wait until t = CREG ⁄ 4 (where CREG is in μF, and t is in ns)
to allow the charge pump to stabilize.
Under many operating conditions, both the high-side (GH)
and low-side (GL) drivers may be off, allowing the BOOT
capacitor to discharge (or never become charged) and create a
UVBOOT fault condition, which in turn inhibits the high-side
driver and creates a FAULT = 1. This fault is NOT latched. To
remove this fault, momentarily turn on GL to charge the BOOT
capacitor.
When powered-up (not in Sleep Mode), if the RESET line is
low for > 10 μs, the A3946 may start to enter Sleep Mode (VREF
< 4 V). In that case, ~FAULT = 1 as long as the RESET line
remains low.
If the RESET line is open, the A3946 should go into Sleep
Mode. However, to ensure that this occurs, the RESET line
must be grounded.
Latched faults may be cleared by a low pulse, 1 to 10 μs
wide, on the RESET line. Throughout that pulse (despite a
Allegro MicroSystems, Inc.
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
The dead time circuit can be disabled by tying the DT pin
to VREF. This disables the turn-on delay and allows direct
control of each MOSFET gate via two control lines. This is
shown in the Control Logic table, on page 2.
Dead Time. The analog input pin DT sets the delay to turn
on the high- or low-side gate outputs. When instructed to
turn off, the gate outputs change after an short internal propa-
gation delay (90 ns typical). The dead time controls the time
between this turn-off and the turn-on of the appropriate gate.
The duration, tDEAD, can be adjusted within the range 350 ns
to 6000 ns using the following formula:
Top-Off Charge Pump. An internal charge pump allows
100% duty cycle operation of the high-side MOSFET. This is
a low-current trickle charge pump, and is only operated after
a high-side has been signaled to turn on. A small amount of
bias current is drawn from the BOOT pin to operate the float-
ing high-side circuit. The top-off charge pump simply pro-
vides enough drive to ensure that the gate voltage does not
droop due to this bias supply current. The charge required for
initial turn-on of the high-side gate must be supplied by boot-
strap capacitor charge cycles. This is described in the section
Application Information.
tDEAD = 50 + (RDEAD ⁄ 16.7)
where tDEAD is in ns, and RDEAD is in Ω, and should be in the
range 5 kΩ < RDEAD < 100 kΩ.
Do not ground the DT pin. If the DT pin is left open, dead
time defaults to 12 μs.
Control Logic. Two different methods of control are
possible with the A3946. When a resistor is connected from
DT to ground, a single-pin PWM scheme is utilized by short-
ing IN1 with IN2. If a very slow turn-on is required (greater
than 6 μs), the two input pins can be hooked-up individually
to allow the dead times to be as long as needed.
VREF. VREF is used for the internal logic circuitry and
is not intended as an external power supply. However,
the VREF pin can source up to 4 mA of current. A 0.1 μF
capacitor is needed for decoupling.
Fault Response Table
Fault Mode
RESET
~FAULT
VREG
ON
VREF
ON
GH1
(IL)
0
GL1
(IL)
(IL)
0
No Fault
1
1
1
1
1
0
1
0
0
0
0
1
BOOT Capacitor Undervoltage2
VREG Undervoltage3
VREF Undervoltage4
Thermal Shutdown3
Sleep5
ON
ON
ON
ON
0
OFF
ON
ON
0
0
ON
(IL)
High Z
(IL)
High Z
OFF
OFF
1(IL) indicates that the state is determined by the input logic.
2This fault occurs whenever there is an undervoltage on the BOOT capacitor. This fault is not latched.
3These faults are latched. Clear by pulsing RESET = 0. Note that outputs become active as soon as VREG comes out of undervoltage, even
though ~FAULT = 0.
4Unspecified VREF undervoltage threshold < 4 V.
5During power supply undervoltage conditions, GH and GL are instructed to be 0 (low). However, with VREG < 4 V, the outputs start to be-
come high impedance (High Z). Refer to the section Sleep Mode/Power Up.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
Application Information
At power-up and when the drivers have been disabled for
a long time, the bootstrap capacitor can be completely
discharged. In this case, Delta_v can be considered to be the
full high-side drive voltage, 12 V. Otherwise, Delta_v is the
Bootstrap Capacitor Selection. CBOOT must be cor-
rectly selected to ensure proper operation of the device. If
too large, time is wasted charging the capacitor, with the
result being a limit on the maximum duty cycle and PWM
frequency. If the capacitor is too small, the voltage drop can
be too large at the time the charge is transferred from the
CBOOT to the MOSFET gate.
amount of voltage dropped during the charge transfer, which
should be 400 mV or less. The capacitor is charged whenever
the S pin is pulled low, via a GL PWM cycle, and current
flows from VREG through the internal bootstrap diode
To keep the voltage drop small:
QBOOT >> QGATE
circuit to CBOOT
.
Power Dissipation. For high ambient temperature
applications, there may be little margin for on-chip power
consumption. Careful attention should be paid to ensure that
the operating conditions allow the A3946 to remain in a safe
range of junction temperature.
where a factor in the range of 10 to 20 is reasonable. Using
20 as the factor:
QBOOT = CBOOT
VBOOT = QGATE 20
×
×
and
CBOOT = QGATE 20 / V
×
BOOT
The power consumed by the A3946 can be estimated as:
P_total = Pd_bias + Pd_cpump + Pd_switching_loss
where:
The voltage drop on the BOOT pin, as the MOSFET is being
turned on, can be approximated by:
Delta_v = QGATE / CBOOT
Pd_bias = VBB
IVBB , typically 3 mA,
×
For example, given a gate charge, QGATE, of 160 nC, and the
typical BOOT pin voltage of 12 V, the value of the Boot
capacitor, CBOOT, can be determined by:
and
Pd_cpump = (2VBB – VREG) IAVE, for VBB < 15 V, or
Pd_cpump = (VBB – VREG) IAVE, for VBB > 15 V,
CBOOT = (160 nC 20) / 12 V ≈ 0.266 μF
×
Therefore, a 0.22 μF ceramic (X7R) capacitor can be chosen
for the Boot capacitor.
in either case, where
In that case, the voltage drop on the BOOT pin, when the
high-side MOSFET is turned on, is:
IAVE = Q
2
f
PWM
GATE × ×
and
Pd_switching_loss = QGATE
V
2
fPWM Ratio,
×
REG × ×
Delta_v = 160 nC / 0.22 μF = 0.73 V
where
Bootstrap Charging. It is good practice to ensure that the
high-side bootstrap capacitor is completely charged before a
high-side PWM cycle is requested.
Ratio = 10 ꢀ / (RGATE + 10 ꢀ).
The time required to charge the capacitor can be approxi-
mated by:
tCHARGE = CBOOT (Delta_v / 100 mA)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
Application Block Diagrams
+VBAT
C1
0.47 μF
C2
10 μF
P
VBB
CP2
CP1
VREF
VREF
0.1 uF
VREG
BOOT
Charge
Pump
+5 Vref
CREG
ILIM
10
k7
10 μF
L
L
P
P
Top-Off
Charge Pump
~FAULT
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
CBOOT
0.47 μF
IRF2807
L
RGATE
GH
High Side
Driver
P
DT
Turn-On
Delay
33 7
470
k7
RDEAD
15.8 k7
IN1
Control
Logic
S
L
VREG
IN
Forward
IRF2807
L
L
RGATE
IN
IN2
GL
Low Side
Driver
Brake
33 7
PGND
LGND
DC
Motor
M
External
+5 V
RESET
P
L
L
P
Diagram A. Dependent drivers. Unidirectional motor control with braking and dead time. TDEAD = 1 ꢀs; QTOTAL = 160 nC.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
+VBAT
C1
0.47 μF
C2
10 μF
P
VBB
CP2
CP1
VREF
VREF
0.1 uF
VREG
BOOT
Charge
Pump
+5 Vref
P
CREG
ILIM
10
k7
10 μF
L
L
P
P
Top-Off
Charge Pump
~FAULT
M
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
CBOOT
DC Motor #2
0.47 μF
IRF2807
L
RGATE
GH
High Side
Driver
VREF
DT
Turn-On
Delay
33 7
470
DC Motor #1
Forward
k7
IN1
Control
Logic
S
Slow
Decay
VREG
DC Motor #2
L
L
IRF2807
RGATE
Forward
IN2
GL
Slow
Decay
Low Side
Driver
33 7
470
k7
PGND
LGND
External
+5 V
M
RESET
P
DC Motor #1
L
P
L
Diagram B. Independent drivers. One high-side drive and one low-side drive.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
+VBAT
C1
0.47 ꢀF
C2
10 ꢀF
P
P
VBB
CP2
CP1
VREF
VREF
0.1 uF
VREG
BOOT
Charge
Pump
+5 Vref
CREG
ILIM
10
k7
10 ꢀF
L
L
P
P
Top-Off
Charge Pump
M
M
~FAULT
Protection
DC Motor
#1
DC Motor
#2
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
IRF2807
L
RGATE
GH
High Side
Driver
VREF
DT
Turn-On
Delay
33 7
470
DC Motor #1
Forward
k7
IN1
Control
Logic
S
Slow
Decay
P
VREG
IRF2807
DC Motor #2
L
L
RGATE
Forward
IN2
GL
Low Side
Driver
Slow
Decay
33 7
470
k7
PGND
LGND
External
+5 V
P
RESET
L
L
P
Diagram C. Independent drivers. Two low-side drives.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
Pin-out Diagram
LP package
VREG
CP2
CP1
PGND
GL
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VBB
VREF
DT
PAD
LGND
RESET
IN2
S
GH
IN1
BOOT
~FAULT
Terminal List Table
Name
Number
Description
VREG
1
Gate drive supply.
CP2
CP1
2
3
4
Charge pump capacitor, positive side. When not using the charge pump, leave this pin open.
Charge pump capacitor, negative side. When not using the charge pump, leave this pin open.
External ground. Internally connected to the power ground.
PGND*
Low-side gate drive output for external MOSFET driver. External series gate resistor can be used to control
slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
GL
S
5
6
7
Directly connected to the load terminal. The pin is also connected to the negative side of the bootstrap
capacitor and negative supply connection for the floating high-side drive.
High-side gate drive output for N-channel MOSFET driver. External series gate resistor can be used to
control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
GH
BOOT
~FAULT
IN1
8
High-side connection for bootstrap capacitor, positive supply for the high-side gate drive.
Diagnostic output, open drain. Low during a fault condition.
Logic control.
9
10
11
12
13
IN2
Logic control.
RESET
LGND*
Logic control input. When RESET = 0, the chip is in a very low power sleep mode.
External ground. Internally connected to the logic ground.
Dead Time. Connecting a resistor to GND sets the turn-on delay to prevent shoot-through. Forcing this
input high disables the dead time circuit and changes the logic truth table.
DT
14
VREF
VBB
15
16
5 V internal reference decoupling terminal.
Supply Input.
Exposed thermal pad. Not connected to any pin, but should be externally connected to ground, to reduce
noise pickup by the pad.
PAD
–
The PGND pin (4) and LGND pin (13) grounds are NOT internally connected, and both must be connected to ground externally.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
LP Package TSSOP with Exposed Thermal Pad
0.45
5.00 ±0.10
0.65
16
4° ±4
0.15
16
+0.05
–0.06
1.70
B
4.40 ±0.10 6.40 ±0.20
3.00
0.60 ±0.15
(1.00)
6.10
3.00
A
1
2
3.00
0.25
1
2
C
16X
SEATING PLANE
GAUGE PLANE
3.00
PCB Layout Reference View
SEATING
PLANE
0.10
C
C
+0.05
–0.06
1.20 MAX
0.65
0.25
0.15 MAX
For Reference Only
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Terminal #1 mark area
A
B
C
Exposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
13
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Half-Bridge Power MOSFET Controller
A3946
Copyright ©2003-2010 Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
14
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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