A1262LLHLX-X-T [ALLEGRO]
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch;
| 型号： | A1262LLHLX-X-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | 2D, Dual-Channel, Ultrasensitive Hall-Effect Latch |
| 文件： | 总17页 (文件大小：2083K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
FEATURES AND BENEFITS
DESCRIPTION
• 2D magnetic sensing via planar and vertical Hall elements
• Phase separation between the two channels is inherently 90°
• Dual-channel output allows independent use of Z-axis
planar Hall in conjunction with vertical Hall:
□ Y-axis (default option)
□ X-axis (with -X option)
• High sensitivity, BOP typically 17 G
• Automotive grade
The A1262 integrated circuit is an ultrasensitive Hall-effect
latch.Itfeaturesoperationwithtraditionalplanarmagneticfield
direction as well as vertical. The dual operation of the planar
and vertical Hall elements allows the end user to achieve 90°
of phase separation that is inherently independent of magnetic
pole spacing. The quadrature outputs of the A1262 allow
rotation direction to be determined, such as when sensing a
rotating ring-magnet target.
□ AEC-Q100 qualified for use in automotive applications
□ Output short-circuit protection
□ Resistant to physical stress
□ Reverse-battery protection
□ Solid-state reliability
The A1262 is available in two options that allow flexibility in
end-systemmagneticdesign.BothoptionsfeatureaplanarHall
plate that is sensitive to magnetic fields perpendicular to the
face of the package (Z). The primary option features a vertical
Hall plate that is sensitive to magnetic fields parallel with the
face of the package across the leaded edges of the package (Y).
The -X option features a vertical Hall plate that is sensitive to
magnetic fields parallel with the face of the package across
the leadless edges of the package (X), resulting in lower total
effective air gap.
□ Superior temperature stability
□ Supply voltage Zener clamp
• Small size
PACKAGES:
Onasinglesiliconchip,thedeviceincludes:twoHallplates(one
planarandonevertical),amultiplexer,asmall-signalamplifier,
chopper stabilization, a Schmitt trigger, and two short-circuit
protected NMOS output transistors to sink up to 20 mA. The
A1262 features circuitry that provides automotive ruggedness
and allows operation from 4 to 24 V over a temperature range
5-Pin SOT23W (Suffix LH)
Continued on the next page…
Not to scale
VDD
To All
Regulator
Subcircuits
OUTPUTA
Current
Limit
Low-Pass
Filter
X/Y Hall
Sample, Hold
& Averaging
Amp
OUTPUTB
Z Hall
Current
Limit
GND
Functional Block Diagram
A1262-DS, Rev. 1
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
Description (continued)
of –40°C to 85°C (E temperature range option) or –40°C to 150°C TheA1262 is available in a 5-pin SOT23Wsurface-mount package,
(K temperature range option).
magnetically optimized for a variety of orientations. The package is
RoHS compliant and lead (Pb) free, with 100% matte-tin leadframe
plating.
The small geometries of the BiCMOS process allow these devices
to be offered in an ultrasmall package suitable for most applications.
SPECIFICATIONS
RoHS
COMPLIANT
Selection Guide
Part Number
A1262ELHLT-T
A1262ELHLX-T
A1262LLHLT-T
A1262LLHLX-T
A1262ELHLT-X-T*
Packing
7-in. reel, 3000 pieces/reel
13-in. reel, 10000 pieces/reel 5-pin SOT-23W surface mount
7-in. reel, 3000 pieces/reel 5-pin SOT-23W surface mount
13-in. reel, 10000 pieces/reel 5-pin SOT-23W surface mount
7-in. reel, 3000 pieces/reel 5-pin SOT-23W surface mount
Package
5-pin SOT-23W surface mount
Temperature Range, TA (°C)
Description
–40 to 85
2 Outputs of Y and Z
2 Outputs of X and Z
–40 to 150
–40 to 85
–40 to 150
A1262ELHLX-X-T* 13-in. reel, 10000 pieces/reel 5-pin SOT-23W surface mount
A1262LLHLT-X-T* 7-in. reel, 3000 pieces/reel 5-pin SOT-23W surface mount
A1262LLHLX-X-T* 13-in. reel, 10000 pieces/reel 5-pin SOT-23W surface mount
* Contact Allegro regarding availability.
Terminal List Table
Number
Symbol
VDD
OUTPUTA Output of Z magnetic field direction1
Description
VDD
1
5
4
3
GND
1
2
Connects power supply to chip
GND
Default option: Output of Y magnetic field direction
3
OUTPUTB
With -X option: Output of X magnetic field direction
OUTPUTA
2
OUTPUTB
4
5
GND
GND
Ground
Ground
1 Z-axis recommended for use as the speed channel in a speed and direction application,
due to better repeatability.
Package LH, 5-Pin SOT23W Pinout
Δ
Z
Δ
Y
1
X
Δ
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
Absolute Maximum Ratings
Characteristic
Symbol
VDD
Notes
Rating
26.5
Unit
V
Forward Supply Voltage
Reverse Supply Voltage
Magnetic Flux Density
Output Off Voltage
VRDD
B
–16
V
Unlimited
26.5
G
VOUT
IOUT(Sink)
V
Output Sink Current
Internally Limited
–40 to 85
–40 to 150
165
mA
°C
°C
°C
°C
Range E
Range L
Operating Ambient Temperature
TA
Maximum Junction Temperature2
TJ(MAX)
Tstg
Storage Temperature
–65 to 170
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Notes
Rating
Unit
Package Thermal Resistance
RθJA
Package LH-5 4-layer board based on the JEDEC standard
124
°C/W
* Additional thermal information available on the Allegro website.
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
20
40
60
80
100 120 140 160 180
Temperature (°C)
Maximum Power Dissipation versus Ambient Temperature
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
ELECTRICAL CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges, unless otherwise specified.
Characteristics
Supply Voltage
Symbol
VDD
Test Conditions
Operating, TJ < 165°C
Min.
4
Typ.1
Max.
24
10
500
7.5
–5
–
Unit
V
–
Output Leakage Current
Output On Voltage
IOUTOFF
VOUT(SAT)
IDD
B < BRP
–
–
µA
mV
mA
mA
V
IOUT = 20 mA, B > BOP
–
180
3
Supply Current
–
Reverse-Battery Current
Supply Zener Clamp Voltage
Output Sink Current
Output Sink Current, Continuous
Output Sink Current, Peak
Chopping Frequency
Output Rise Time 2,3
Output Fall Time 2,3
IRDD
VRDD = –16 V
–
–
VZ
ICC = 5 mA; TA = 25°C
28
–
34
–
IOUTPUT(SINK)
20
60
110
–
mA
mA
mA
kHz
µs
IOUTPUT(SINK)C TJ < TJ(max), VOUT = 12 V
30
–
–
IOUTPUT(SINK)P t < 3 seconds
fC
–
–
800
0.2
0.1
32
Low
tr
tf
RL = 820 Ω, CS = 20 pF
RL = 820 Ω, CS = 20 pF
Both channels
–
–
–
–
µs
Power-On Time 2
tON
POS
–
48
µs
Power-On State
1 Typical data are at TA = 25°C and VDD = 4 V, and are for initial design estimations only.
2 Power-on time, rise time, and fall time are guaranteed through device characterization.
3 CS = oscilloscope probe capacitance.
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
MAGNETIC CHARACTERISTICS: Valid over full operating voltage and temperature ranges, unless otherwise specified.
Characteristics
Operate Point 5
Symbol
BOP
Test Conditions
Min.
1
Typ.
17
Max.
40
Unit 4
G
Release Point 5
BRP
–40
15
–17
34
–1
G
Hysteresis
BHYS
BOP – BRP
68
G
Symmetry: Channel A, Channel B,
BSYM(A)
BSYM(B)
,
–35
–
35
G
B
OP(A) + BRP(A), BOP(B) + BRP(B)
Operate Symmetry: BOP(A) – BOP(B)
Release Symmetry: BRP(A) – BRP(B)
BSYM(AB,OP)
BSYM(AB,RP)
–25
–25
–
–
25
25
G
G
4 1 G (gauss) = 0.1 mT (millitesla)
5 Applicable to all directions (X/Y and Z).
N
S
N
N
S
S
X
Y
Z
The A1262 output is turned on when presented with a south polarity magnetic field beyond BOP in the orientations illustrated above.
The X-axis field response is only applicable to the -X option; the Y-axis field response is only applicable to the default option.
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
CHARACTERISTIC DATA
Average Supply Current vs. Ambient Temperature
Average Supply Current vs. Supply Voltage
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
-40°C
25°C
4 V
150°C
24 V
-60 -40 -20
0
20 40 60 80 100 120 140 160
2
6
10
14
18
22
26
Ambient Temperature, TA (°C)
Supply Voltage, VDD (V)
Avg. Output Leakage Current vs. Ambient
Temperature
Avg. Output On Voltage vs. Ambient Temperature
500
10
8
450
400
350
300
250
200
150
100
50
IOUT(OFF)-A
IOUT(OFF)-B
6
4
VOUT(SAT)-A
VOUT(SAT)-B
2
0
0
-60 -40 -20
0
20 40 60 80 100 120 140 160
-60 -40 -20
0
20 40 60 80 100 120 140 160
Ambient Temperature, TA (°C)
Ambient Temperature, TA (°C)
Avg. OUTPUTA Operate Point vs. Ambient
Temperature
Avg. OUTPUTA Operate Point vs. Supply Voltage
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
-40°C
25°C
150°C
4 V
24 V
0
0
-60 -40 -20
0
20 40 60 80 100 120 140 160
2
6
10
14
18
22
26
Ambient Temperature, TA (°C)
Supply Voltage, VDD (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
CHARACTERISTIC DATA (continued)
Avg. OUTPUTB Operate Point vs. Ambient
Temperature
Avg. OUTPUTB Operate Point vs. Supply Voltage
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
-40°C
25°C
150°C
4 V
24 V
0
0
-60 -40 -20
0
20 40 60 80 100 120 140 160
2
6
10
14
18
22
26
Ambient Temperature, TA (°C)
Supply Voltage, VDD (V)
Avg. OUTPUTA Release Point vs. Ambient
Temperature
Avg. OUTPUTA Release Point vs. Supply Voltage
0
0
-5
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
-40°C
4 V
25°C
24 V
150°C
-60 -40 -20
0
20 40 60 80 100 120 140 160
2
6
10
14
18
22
26
Ambient Temperature, TA (°C)
Supply Voltage, VDD (V)
Avg. OUTPUTB Release Point vs. Ambient
Temperature
Avg. OUTPUTB Release Point vs. Supply Voltage
0
-5
0
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
-40°C
4 V
25°C
24 V
150°C
-60 -40 -20
0
20 40 60 80 100 120 140 160
2
6
10
14
18
22
26
Ambient Temperature, TA (°C)
Supply Voltage, VDD (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
CHARACTERISTIC DATA (continued)
Avg. OUTPUTA Hysteresis vs. Ambient
Temperature
Avg. OUTPUTA Hysteresis vs. Supply Voltage
70
60
50
40
30
20
10
70
60
50
40
30
20
10
-40°C
25°C
4 V
150°C
24 V
-60 -40 -20
0
20 40 60 80 100 120 140 160
2
6
10
14
18
22
26
Ambient Temperature, TA (°C)
Supply Voltage, VDD (V)
Avg. OUTPUTB Hysteresis vs. Ambient
Temperature
Avg. OUTPUTB Hysteresis vs. Supply Voltage
70
70
60
50
40
30
20
10
-40°C
60
50
40
30
20
10
25°C
4 V
150°C
24 V
-60 -40 -20
0
20 40 60 80 100 120 140 160
2
6
10
14
18
22
26
Ambient Temperature, TA (°C)
Supply Voltage, VDD (V)
Avg. BOP(A)+BRP(A) Symmetry vs. Ambient
Temperature
Avg. BOP(B)+BRP(B) Symmetry vs. Ambient
Temperature
15
10
5
15
10
5
4 V
4 V
24 V
24 V
0
0
-5
-5
-10
-15
-10
-15
-60 -40 -20
0
20 40 60 80 100 120 140 160
-60 -40 -20
0
20 40 60 80 100 120 140 160
Ambient Temperature, TA (°C)
Ambient Temperature, TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
CHARACTERISTIC DATA (continued)
Avg. BOP(A)–BOP(B) Symmetry vs. Ambient
Temperature
Avg. BRP(A)–BRP(B) Symmetry vs. Ambient
Temperature
15
10
5
15
10
5
4 V
4 V
24 V
24 V
0
0
-5
-5
-10
-15
-10
-15
-60 -40 -20
0
20 40 60 80 100 120 140 160
-60 -40 -20
0
20 40 60 80 100 120 140 160
Ambient Temperature, TA (°C)
Ambient Temperature, TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
FUNCTIONAL DESCRIPTION
V+
Operation
VOUT(OFF)
The outputs of the A1262 switch low (turn on) when the cor-
responding Hall element is presented with a perpendicular south
magnetic field of sufficient strength. OUTPUTA switches low if
the Z-axis direction exceeds the operate point (BOP), and OUT-
PUTB switches low if the Y-axis direction (A1262 with default
option) or X-axis direction (A1262 with -X option) exceeds BOP.
After turn-on, the output voltage is VOUT(SAT). The device outputs
switch high (turn off) when the strength of a perpendicular north
magnetic field exceeds the release point (BRP). The difference in
VOUT(ON)
0
B+
B-
BHYS
the magnetic operate and release points is the hysteresis (BHYS
of the device. See Figure 1.
)
Figure 1: Switching Behavior of Latches
Removal of the magnetic field will leave the device output
latched on if the last crossed switchpoint is BOP, or latched off if
the last crossed switchpoint is BRP.
On the horizontal axis, the B+ direction indicates increasing
south polarity magnetic field strength, and the B– direction
indicates decreasing south polarity field strength (including
the case of increasing north polarity
This built-in hysteresis allows clean switching of the output even
in the presence of external mechanical vibration and electrical
noise. The device will power-on in the low output state, even
when powering-on in the hysteresis region, between BOP and BRP.
With dual-planar Hall sensors, the ring magnet must be properly
designed and optimized for the physical Hall spacing (distance)
in order to have the outputs of the two latches to be in quadra-
ture, or 90 degrees out of phase. With the A1262, which uses one
planar and one vertical Hall-effect sensing element, no target
optimization is required. When the face of the IC is facing the
ring magnet, the planar Hall senses the magnet poles and the
vertical Hall senses the transition between poles, therefore the
Unlike dual-planar Hall-effect sensors, which have two planar
Hall-effect sensing elements spaced apart across the width of the
package, both the vertical and planar sensing elements on the
A1262 are located in essentially the same location on the IC.
Dual-Planar
Sensor
A1262
Figure 2: Ring magnet optimized for a dual-planar Hall-effect sensor resulting in output
quadrature also results in quadrature for the A1262.
Allegro MicroSystems, LLC
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
two channels will inherently be in quadrature, irrespective of the
ring-magnet pole spacing.
the E1-to-E2 spacing, the dual-planar sensor exhibits diminished
phase separation, making signal processing the outputs into speed
and direction less robust. Using a different ring-magnet geom-
etry has no effect on the A1262, and the two channels remain in
quadrature (see Figure 3 below).
Figure 2 above shows a ring magnet optimized for the E1-to-E2
spacing of a dual-planar sensor, resulting in quadrature, or 90
degrees phase separation between channels. This same target
also results in quadrature for the 2D sensing A1262. However
when a different ring magnet is used which is not optimized for
The relationship of the various signals and the typical system tim-
ing is shown in Figure 4.
Dual-Planar
Sensor
A1262
Figure 3: Ring magnet not optimized for a dual-planar Hall-effect sensor resulting in signifi-
cantly reduced output phase separation, however still results in quadrature for the A1262.
Figure 4: Typical System Timing
The Planar (P) and Vertical (V) signals represent the magnetic input signal, which is converted to the device outputs,
OUTPUTA and OUTPUTB, respectively. While the A1262 does not process the signals into Speed and Direction, these
could be determined by the user based on the individual output signals.
Allegro MicroSystems, LLC
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
A1262 Sensor and Relationship to Target
Power-On Sequence and Timing
The A1262 is available in two sensing options: with Z-axis planar The states of OUTPUTA and OUTPUT B are only valid when the
Hall and the Y-axis vertical Hall active (default option), or with
the Z-axis planar Hall and the X-axis vertical Hall active (-X
option). This offers incredible flexibility for positioning the IC
within various applications.
supply voltage is within the specified operating range (VDD(MIN)
≤ VDD ≤ VDD(MAX)) and the power-on time has elapsed (t > tON).
Refer to Figure 7: Power-On Sequence and Timing for an illustra-
tion of the power-on sequence.
The Z-Y option supports the traditional configuration with the
face of the package facing the ring magnet (Figure 5a), with the
axis of rotation going cross the leads, or with the either of the
leaded sides of the package facing the ring magnet (Figure 5b).
V
VOUT(OFF)
Output Responds According
Planar
(Z)
Output Undefined for
to Magnetic Field Input
VDD <VDD(MIN)
B > BOP or B < BRP
t > tON(MAX)
VOUT(ON)
0
time
POS
V
VOUT(OFF)
Output Responds According
to Magnetic Field Input
B > BOP or B < BRP
t > tON(MAX)
Vertical
(X/Y)
Output Undefined for
DD <VDD(MIN)
V
VOUT(ON)
0
time
POS
V
VDD(MIN)
VDD
Figure 5a
Figure 5b
The Z-X option supports having the IC positioned with the face
of the package facing the ring magnet, and the axis of rotation
(Figure 6a) lengthwise along the package body, or with either of
the non-leaded sides of the package facing the ring magnet (Fig-
ure 6b). This latter configuration has the advantage of being able
to be mounted extremely close to the ring magnet, since there are
no leads or solder pads to accommodate for in that dimension.
0
time
tON
Figure 7: Power-On Sequence and Timing
Once the supply voltage is within the operational range, the
outputs will be in the low state (power-on state), irrespective of
the magnetic field. The outputs will remain low until the sensor
is fully powered on (t > tON), at which point, both outputs will
respond to the corresponding magnetic field presented to the sen-
sor (the vertical Hall channel typically responds before the planar
Hall channel).
Figure 6a
Figure 6b
Allegro MicroSystems, LLC
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
Applications
It is strongly recommended that an external capacitor be con-
nected (in close proximity to the Hall sensor) between the supply
and ground of the device to reduce both external noise and noise
generated by the chopper stabilization technique. As shown in
Figure 8, a 0.1 µF capacitor is typical.
VS
VDD
RLOAD
RLOAD
A1262
CBYP
0.1 µF
OUTPUTA
OUTPUTB
Sensor
Outputs
GND
GND
Figure 8: Typical Application Circuit
Extensive applications information on magnets and Hall-effect
sensors is available in:
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines for Designing Subassemblies
Using Hall-Effect Devices AN27703.1
• Soldering Methods for Allegro’s Products – SMD and
Through-Hole, AN26009
All are provided on the Allegro website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
13
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for switch-
point accuracy is the small signal voltage developed across the
Hall element. This voltage is disproportionally small relative to
the offset that can be produced at the output of the Hall sensor.
This makes it difficult to process the signal while maintaining an
accurate, reliable output over the specified operating temperature
and voltage ranges.
The chopper stabilization technique uses a 400 kHz high-
frequency clock. For demodulation process, a sample, hold, and
averaging technique is used, where the sampling is performed
at twice the chopper frequency (800 kHz). This high-frequency
operation allows a greater sampling rate, which results in higher
accuracy and faster signal-processing capability. This approach
desensitizes the chip to the effects of thermal and mechani-
cal stresses, and produces devices that have extremely stable
quiescent Hall output voltages and precise recoverability after
temperature cycling. This technique is made possible through the
use of a BiCMOS process, which allows the use of low-offset,
low-noise amplifiers in combination with high-density logic and
sample-and-hold circuits.
Chopper stabilization is a proven approach used to minimize
Hall offset on the chip. The patented Allegro technique, namely
Dynamic Quadrature Offset Cancellation, removes key sources
of output drift induced by thermal and mechanical stresses. This
technique is based on a signal modulation-demodulation process.
The undesired offset signal is separated from the magnetic field-
induced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field induced signal to recover
its original spectrum at baseband, while the dc offset becomes a
The repeatability of magnetic field-induced switching is affected
slightly by a chopper technique. However, the Allegro high-
frequency chopping approach minimizes the effect of jitter and
makes it imperceptible in most applications. Applications that are
high-frequency signal. The magnetic sourced signal then can pass more likely to be sensitive to such degradation are those requir-
through a low-pass filter, while the modulated DC offset is sup-
pressed. This configuration is illustrated in Figure 3.
ing precise sensing of alternating magnetic fields—for example,
speed sensing of ring-magnet targets. For such applications,
Allegro recommends its digital sensor families with lower sen-
sitivity to jitter. For more information on those devices, contact
your Allegro sales representative.
VDD
Low-Pass
Filter
Sample, Hold &
Amp.
Averaging
Figure 9: Model of Chopper Stabilization Technique
Allegro MicroSystems, LLC
115 Northeast Cutoff
14
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
POWER DERATING
The device must be operated below the maximum junction
temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems website.)
A worst-case estimate (PD(max)) represents the maximum allow-
able power level (VDD(max), IDD(max)), without exceeding TJ(max)
at a selected RθJA and TA.
,
Example: Reliability for VDD at TA = 150°C, package LH5, using
low-K PCB.
Observe the worst-case ratings for the device, specifically:
RθJA = 124°C/W, TJ(max) = 165°C, VDD(max) = 24 V, and
IDD(max) = 7.5 mA.
The Package Thermal Resistance (RθJA) is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Calculate the maximum allowable power level (PD(max)). First,
Its primary component is the Effective Thermal Conductivity (K) invert equation 3:
of the printed circuit board, including adjacent devices and traces.
∆Tmax = TJ(max) – TA = 165°C – 150°C = 15°C
Radiation from the die through the device case (RθJC) is relatively
small component of RθJA. Ambient air temperature (TA) and air
motion are significant external factors, damped by overmolding.
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ at PD.
P
D(max)ꢀ=ꢀ∆Tmax ÷ RθJA = 15°C ÷ 124°C/W = 121 mW
Finally, invert equation 1 with respect to voltage:
V
DD(est) = PD(max) ÷ IDD(max)
PD = VIN × IIN
∆Tꢀ=ꢀPD × RθJA
TJ = TAꢀ+ꢀ∆Tꢀꢀ
(1)
(2)
(3)
VDD(est) = 121 mW ÷ 7.5 mA
ꢀ
ꢀ
VDD(est) = 16.1 V
The result indicates that, at TA, the application and device can
For example, given common conditions such as: TA = 25°C,
VDD = 12 V, IDD = 3 mA, and RθJA = 124°C/W for the LH5 pack-
age, then:
dissipate adequate amounts of heat at voltages ≤ VDD(est)
.
Compare VDD(est) to VDD(max). If VDD(est) ≤ VDD(max), then reli-
able operation between VDD(est) and VDD(max) requires enhanced
RθJA. If VDD(est) ≥ VDD(max), then operation between VDD(est) and
VDD(max) is reliable under these conditions.
PD = VDD × IDD = 12 V × 3.0 mA = 36.0 mW
∆Tꢀ=ꢀPD × RθJA = 36.0 mW × 124°C/W = 4.5°C
TJ = TAꢀ+ꢀ∆Tꢀ=ꢀ25°Cꢀ+ꢀ4.5°Cꢀ=ꢀ29.5°C
Allegro MicroSystems, LLC
115 Northeast Cutoff
15
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference DWG-9069)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.12
2.98
–0.08
4° 4°
0.180
A
5
+0.020
–0.053
D
D1
D
0.11
REF
D1
D3
D
+0.19
–0.06
+0.10
–0.20
1.91
2.90
D
D2
D
D D2
0.25 MIN
D D3
1
2
0.55
REF
0.17
REF
D
0.25 BSC
D3
D
Branded Face
SEATING PLANE
GAUGE PLANE
8X 12°
REF
1.00 0.13
D D2
+0.10
–0.05
0.05
0.40 0.10
0.95
BSC
D1
D
0.20 MIN
NNN
2.ꢀ0
Standard Branding Reference View
C
1.00
A
B
Active Area Depth, 0.28 0.0ꢀ
Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads;
adjust as necessary to meet application process requirements and PCB layout tolerances
0.70
0.95
C
D
Branding Scale and appearance at supplier discretion
PCB Reference Layout View
B
Hall Elements (D1, D2, and D3), not to scale; D2 and D3 are active in the A1262LLH-T;
D1 and D3 are active in the A1262LLH-X-T
Figure 10: Package LH, 5-Pin SOT23-W
Allegro MicroSystems, LLC
115 Northeast Cutoff
16
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1262
2D, Dual-Channel, Ultrasensitive Hall-Effect Latch
Revision History
Number
Date
Description
–
1
September 21, 2015 Initial release
February 10, 2016
Added E temperature range option and magnetic switchpoint symmetry specifications
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
17
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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