HCPL0710 [AGILENT]
40 ns Prop. Delay, SO-8 Optocoupler; 40 ns的支柱，延迟， SO- 8光耦
| 型号： | HCPL0710 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | 40 ns Prop. Delay, SO-8 Optocoupler |
| 文件： | 总2页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
H
40 ns Prop. Delay,
SO-8 Optocoupler
Preliminary Technical Data
HCPL-0710
Functional Diagram
Features
Description
• +5 V CMOS Compatibility
• 8 ns Pulse Width Distortion
• High Speed: 12 Mbd
• 10 kV/µs Minimum Common
Mode Rejection
• Industrial Temperature
Range: 0°C to 85°C
• Safety and Regulatory
Approvals
Available in the SO-8 package
style, the HCPL-0710 optocoupler
utilizes the latest CMOS IC
technology to achieve outstanding
performance with very low power
consumption. The HCPL-0710
requires only two bypass
V
1
2
8
7
V
V
DD1
DD2
V
I
3
4
6
5
*
O
capacitors for complete CMOS
compatibility.
GND
GND
2
1
SHIELD
UL Recognized 2500 V rms for
1 min. per UL 1577
CSA Component Acceptance
Notice #5
Basic building blocks of the
HCPL-0710 are a CMOS LED
driver IC and a CMOS detector
IC. A CMOS logic input signal
controls the LED driver IC which
supplies current to the LED.
The detector IC incorporates an
integrated photodiode, a high-
speed transimpedance amplifier,
and a voltage comparator with an
output driver.
TRUTH TABLE
V , INPUT V , OUTPUT
I
I
H
L
H
L
Applications
• Digital Fieldbus Isolation:
DeviceNet, SDS, PROFIBUS
• Multiplexed Data
Transmission
• Computer Peripheral
Interface
• Microprocessor System
Interface
*Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally. External connections to pin 7 are not recommended.
**A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8.
CAUTION:Itisadvisedthatnormalstaticprecautionsbetakeninhandlingandassemblyofthiscomponent
to prevent damage and/or degradation which may be induced by ESD.
This data sheet represents the latest information at the time of publication of this catalog. All specifications
subject to change. Samples available Fall 1996.
1-416
Electrical Specifications
Unless otherwise noted, all specifications are guaranteed across recommended operating conditions. All
Typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V. Test conditions that are not specified can be
anywhere within the recommended operating range.
Parameter
DC Specifications
Symbol
Min.
Typ. Max. Units
Test Conditions
Logic Low Input Supply Current
Logic High Input Supply Current
Input Supply Current
Output Supply Current
Input Current
IDDIL
IDDIH
IDDI
IDD2
II
1.5
6.0
3.0
10.0
13.0
10.0
10
mA
mA
mA
mA
µA
V
VDD1 = 5.5 V, VI = 0 V
VDD1 = 5.5 V, VI = VDDI
VDD1 = 5.5 V
5.5
VDD2 = 5.5 V
-10
Logic High Output Voltage
VOH
VDD2 - 0.1 VDD2
IO = -20 µA, VI = VIH
IO = -4 mA, VI = VIH
IO = 20 µA, VI = VIL
IO = 4 mA, VI = VIL
0.8 *VDD2
4.5
0
0.2
Logic Low Output Voltage
VOL
0.1
0.8
V
Switching Specifications
Propagation Delay Time to
Logic Low Output
Propagation Delay Time to
Logic High Output
tPHL
tPLH
PW
20
23
40
40
ns
CL = 15 pF
CMOS Signal Levels
Pulse Width
80
Data Rate
12.5 MBd
Pulse Width Distortion
PWD
3
8
ns
CL = 15 pF
|tPHL - tPLH
|
CMOS Signal Levels
Propagation Delay Skew
Output Rise Time
(10 - 90%)
Output Fall Time
(90 - 10%)
tPSK
tR
20
13
5
CL = 15 pF
CMOS Signal Levels
tF
Common Mode Transient
Immunity at Logic High Output
Common Mode Transient
Immunity at Logic Low Output
Input Dynamic Power
Dissipation Capacitance
Output Dynamic Power
Dissipation Capacitance
|CMH|
|CML|
CPD1
10
10
20
20
60
10
kV/µs VI = VDDI, VO >
0.8 VDDI, VCM = 1000 V
VI = 0 V, VO > 0.8 V,
VCM = 1000 V
pF
CPD2
1-417
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ONSEMI
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