5962-8767905KUA [AGILENT]
Logic IC Output Optocoupler, 2-Element, 1500V Isolation, 0.4MBps, HERMETIC SEALED, DIP-16;
| 型号： | 5962-8767905KUA |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | Logic IC Output Optocoupler, 2-Element, 1500V Isolation, 0.4MBps, HERMETIC SEALED, DIP-16 输出元件 光电 |
| 文件： | 总14页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hermetically Sealed, Transistor
Output Optocouplers for Analog and
Digital Applications
Technical Data
Agilent 4N55*, 5962-87679, HCPL-553X, HCPL-653X,
HCPL-257K, HCPL-655X, 5962-90854, HCPL-550X
*See matrix for available extensions.
Features
• Dual Marked with Device Part
Number and DSCC Drawing
Number
Description
Applications
• Manufactured and Tested on a
These units are single, dual
and quad channel, hermetically
sealed optocouplers. The
• Military and Space
• High Reliability Systems
MIL-PRF-38534 Certified Line
• QML-38534, Class H and K
• Vehicle Command, Control, Life
• Five Hermetically Sealed Package
products are capable of
Critical Systems
Configurations
operation and storage over the
full military temperature range
and can be purchased as
either standard product or
with full MIL-PRF-38534 Class
Level H or K testing or from
the appropriate DSCC Drawing.
All devices are manufactured
and tested on a MIL-PRF-
38534 certified line and are
• Line Receivers
• Switching Power Supply
• Voltage Level Shifting
• Performance Guaranteed, Over
-55°C to +125°C
• High Speed: Typically 400 kBit/s
• 9 MHz Bandwidth
• Open Collector Output
• 2-18 Volt V Range
• 1500 Vdc Withstand Test Voltage
• High Radiation Immunity
• Analog Signal Ground Isolation
(see Figures 7, 8, and 13)
• Isolated Input Line Receiver
• Isolated Output Line Driver
CC
included in the DSCC Qualified • Logic Ground Isolation
Manufacturers List QML-38534
for Hybrid Microcircuits.
• Harsh Industrial Environments
• 6N135, 6N136, HCPL-2530/2531,
Function Compatibility
• Isolation for Test Equipment
Systems
• Reliability Data
The connection of a 0.1 µF bypass capacitor between V and GND is recommended.
CC
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Each channel contains a
GaAsP light emitting diode
which is optically coupled to
an integrated photon detector.
Separate connections for the
photodiodes and output
transistor collectors improve
the speed up to a hundred
times that of a conventional
phototransistor optocoupler by
reducing the base-collector
capacitance.
These products are also
available with the transistor
base node not connected to
improve common mode noise
immunity and ESD
susceptibility. In addition,
higher CTR minimums are
available by special request.
characteristics shown in the
figures are identical for all
parts. Occasional exceptions
exist due to package variations
and limitations and are as
noted. Additionally, the same
package assembly processes
and materials are used in all
devices. These similarities give
justification for the use of data
obtained from one part to
represent other part’s
Package styles for these parts
are 8 and 16 pin DIP through
hole (case outlines P and E
respectively), 16 pin DIP flat
pack (case outline F), and
leadless ceramic chip carrier
(case outline 2). Devices may
performance for die related
reliability and certain limited
radiation test results.
These devices are suitable for
wide bandwidth analog
applications, as well as for
interfacing TTL to LSTTL or
CMOS. Current Transfer Ratio
be purchased with a variety of Truth Table
lead bend and plating options,
(Positive Logic)
(CTR) is 9% minimum at I
=
see Selection Guide Table for
details. Standard Microcircuit
Drawing (SMD) parts are
available for each package and
lead style.
F
16 mA. The 18 V V
Input
On (H)
Off (L)
Output
CC
capability will enable the
designer to interface any TTL
family to CMOS. The
L
H
availability of the base lead
allows optimized gain/
bandwidth adjustment in
analog applications. The
shallow depth of the IC
photodiode provides better
radiation immunity than
conventional phototransistor
couplers.
Because the same functional
die (emitters and detectors)
are used for each channel of
each device listed in this data
sheet, absolute maximum
ratings, recommended
operating conditions, electrical
specifications, and performance
Functional Diagram
Multiple Channel Devices
Available
V
CC
V
V
B
O
GND
2
Selection Guide–Package Styles and Lead Configuration Options
16 Pin DIP
8 Pin DIP
8 Pin DIP
16 Pin Flat
Pack
20 Pad LCCC
Package
Lead Style
Through Hole
Through Hole
Through Hole Unformed Leads Surface Mount
Channels
2
1
2
4
2
Common Channel Wiring
Agilent Part No. and Options
Commercial
None
None
VCC GND
VCC GND
None
4N55(1)
HCPL-5500
HCPL-5501
HCPL-550K
Gold Plate
Option 200
Option 100
Option 300
HCPL-5530
HCPL-5531
HCPL-553K
Gold Plate
Option 200
Option 100
Option 300
HCPL-6550
HCPL-6551
HCPL-655K
Gold Plate
HCPL-6530
HCPL-6531
HCPL-653K
Solder Pads
MIL-PRF-38534 Class H
MIL-PRF-38534 Class K
Standard Lead Finish
Solder Dipped*
4N55/883B
HCPL-257K
Gold Plate
Option 200
Option 100
Option 300
Butt Joint/Gold Plate
Gull Wing/Soldered*
Class H SMD Part #
Prescript for all below
5962-
5962-
5962-
5962-
5962-
Either Gold or Soldered
Gold Plate
8767901EX
8767901EC
8767901EA
8767901UC
8767901UA
8767901TA
9085401HPX
9085401HPC
9085401HPA
9085401HYC
9085401HYA
9085401HXA
8767902PX
8767902PC
8767902PA
8767902YC
8767902YA
8767902XA
8767904FX
8767904FC
87679032X
Solder Dipped*
87679032A
Butt Joint/Gold Plate
Butt Joint/Soldered*
Gull Wing/Soldered*
Class K SMD Part #
Prescript for all below
Either Gold or Soldered
Gold Plate
5962-
5962-
5962-
5962-
5962-
8767905KEX
8767905KEC
8767905KEA
8767905KUC
8767905KUA
8767905KTA
9085401KPX
9085401KPC
9085401KPA
9085401KYC
9085401KYA
9085401KXA
8767906KPX
8767906KPC
8767906KPA
8767906KYC
8767906KYA
8767906KXA
8767908KFX
8767908KFC
8767907K2X
Solder Dipped*
8767907K2A
Butt Joint/Gold Plate
Butt Joint/Soldered*
Gull Wing/Soldered*
1. JEDEC registered part.
* Solder contains lead
3
8 Pin Ceramic DIP Single Channel Schematic
I
I
I
CC
8
7
6
I
F
2
V
V
V
CC
B
ANODE
+
B
V
F
O
-
O
CATHODE
3
5
GND
Note, base is pin 7.
Functional Diagrams
16 Pin DIP
Through Hole
2 Channels
8 Pin DIP
Through Hole
1 Channel
8 Pin DIP
Through Hole
2 Channels
16 Pin Flat Pack
Unformed Leads
4 Channels
20 Pad LCCC
Surface Mount
2 Channels
15 14
1
V
16
1
16
B1
V
V
CC2
B2
O2
1
V
8
1
V
V
8
CC
V
CC
O1
19
20
13
12
2
3
4
V
15
14
13
2
3
4
V
V
V
V
V
15
14
13
V
CC1
CC
O1
O2
O3
O4
2
3
4
7
6
5
2
3
4
7
6
5
B
GND
2
V
O1
V
V
OUT
O2
V
CC1
2
3
10
9
V
7
O1
GND
V
B1
GND
1
GND
GND
5
12
5
12
V
B2
8
V
6
7
8
11
10
9
6
7
8
11
10
9
CC2
GND
GND
V
O2
Note: 8 pin DIP and flat pack devices have common V and ground. 16 pin DIP and LCCC (leadless ceramic chip carrier) packages have isolated
CC
channels with separate V and ground connections.
CC
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4
Leaded Device Marking
Leadless Device Marking
Agilent DESIGNATOR
Agilent P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
XXXX
XXXXXX
XXX 50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
Agilent CAGE CODE*
Agilent DESIGNATOR
Agilent P/N
A QYYWWZ
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
XXXXXX
XXXXXXX
XXX XXX
50434
DSCC SMD*
DSCC SMD*
PIN ONE/
COUNTRY OF MFR.
Agilent CAGE CODE*
ESD IDENT
* QUALIFIED PARTS ONLY
* QUALIFIED PARTS ONLY
Outline Drawings
16 Pin Flat Pack, 4 Channels
7.24 (0.285)
6.99 (0.275)
2.29 (0.090)
MAX.
1.27 (0.050)
REF.
11.13 (0.438)
10.72 (0.422)
0.46 (0.018)
0.36 (0.014)
8.13 (0.320)
MAX.
2.85 (0.112)
MAX.
0.88 (0.0345)
MIN.
0.31 (0.012)
0.23 (0.009)
0.89 (0.035)
0.69 (0.027)
5.23
(0.206)
MAX.
9.02 (0.355)
8.76 (0.345)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
20 Terminal LCCC Surface Mount, 2 Channels
8 Pin DIP Through Hole, 1 and 2 Channel
8.70 (0.342)
9.10 (0.358)
9.40 (0.370)
9.91 (0.390)
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
4.95 (0.195)
5.21 (0.205)
7.16 (0.282)
7.57 (0.298)
1.78 (0.070)
2.03 (0.080)
1.02 (0.040) (3 PLCS)
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
0.51 (0.020)
3.81 (0.150)
MIN.
MIN.
0.20 (0.008)
0.33 (0.013)
METALIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
1.52 (0.060)
2.03 (0.080)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
5
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is
available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details).
4.32 (0.170)
MAX.
0.51 (0.020)
1.14 (0.045)
1.40 (0.055)
MIN.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel
product in 8 and 16 pin DIP. DSCC drawing part numbers contain provisions for lead finish. All
leadless chip carrier devices are delivered with solder dipped terminals as a standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option
is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details).
This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
1.40 (0.055)
1.65 (0.065)
MIN.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5˚ MAX.
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
6
Absolute Maximum Ratings
No derating required up to +125° C.
Symbol
Min.
-65°
-55°
Max.
Units
Parameter
Storage Temperature Range
TS
TA
TJ
TC
+150°
+125°
+175°
+170°
260° for 10 s
20
C
C
Operating Ambient Temperature
Junction Temperature
C
Case Temperature
C
Lead Solder Temperature (1.6 mm below seating plane)
Average Input Forward Current
Peak Forward Input Current (each channel, ≤ 1 ms duration)
Reverse Input Voltage
C
IF AVG
IFPK
BVR
IO
mA
mA
40
See Electrical Characteristics
Average Output Current, each channel
Peak Output Current, each channel
Supply Voltage
8
16
20
20
36
50
200
mA
IO
mA
V
VCC
VO
-0.5
-0.5
Output Voltage
V
Input Power Dissipation, each channel
Output Power Dissipation, each channel
Package Power Dissipation, each channel
mW
mW
mW
PD
Single Channel 8 Pin, Dual Channel 16 Pin, and LCCC Only
Emitter Base Reverse Voltage
VEBO
IB
3
5
V
Base Current, each channel
mA
ESD Classification
(MIL-STD-883, Method 3015)
4N55, 4N55/883B, HCPL-257K, HCPL-5500/01/0K, and HCPL-6530/31/3K
HCPL-5530/31/3K, HCPL-6550/51/5K
(∆), Class 1
(Dot), Class 3
Recommended Operating Conditions
Symbol
Min.
Max.
Units
Parameter
Input Current, Low Level
IFL
250
µA
mA
V
Input Current, High Level
Supply Voltage, Output
IFH
12
2
20
18
VCC
7
Electrical Characteristics
T = -55° C to +125° C, unless otherwise specified. See Note 12.
A
Parameter
Symbol
Group A,
Sub-
group
Test Conditions
Limits
Units
Fig.
Notes
Min. Typ.* Max.
Current Transfer Ratio
CTR
IOH
1, 2, 3
1, 2, 3
VO = 0.4V, IF = 16 mA, VCC = 4.5V
9
20
5
%
2, 3
4
1, 2, 10
1
Logic High Output Current
IF = 0,
100
250
1.0
µA
IF (other channels) = 20 mA
VO = VCC = 18 V
Output Leakage Current
IOLeak
1, 2, 3
IF = 250 µA,
IF (other channels) = 20 mA,
VO = VCC = 18 V
30
4
1
µA
µA
Input-Output Insulation Leakage
Current
II-O
1
VI-O = 1500 Vdc,
RH ≤ 65%,
TA = 25°C, t = 5 s
3, 9
Input Forward Voltage
VF
1, 2, 3
1, 2, 3
1, 2, 3
IF = 20 mA
1.55 1.8
1.9
V
V
1
1, 14
1, 13
1, 14
1, 13
1
Reverse Breakdown Voltage
BVR
ICCH
IR = 10 µA
5
3
Logic High Supply
Current
Single
Channel
VCC = 18 V, IF = 0 mA
VCC = 18 V, IF = 0 mA (all channels)
VCC = 18 V, IF = 0 mA (all channels)
VCC = 18 V, IF = 20 mA
0.1
0.2
0.4
35
10
20
µA
Dual
Channel
1,4
1
Quad
Channel
40
Logic Low Supply
Current
Single
Channel
ICCL
1, 2, 3
200
400
1
µA
µs
Dual
Channel
VCC = 18 V, IF1 = IF2 = 20 mA
70
1, 4
1
Quad
Channel
VCC = 18 V, IF1 = IF2 = IF3 = IF4 = 20
mA
140 800
Propagation Delay Time to Logic
High at Output
tPLH
tPHL
9, 10, 11
RL = 8.2 kΩ,
CL = 50 pF,
IF = 16 mA,
VCC = 5 V
1.0
0.4
6.0
2.0
6, 9
1, 6
Propagation Delay Time to Logic
Low at Output
*All typical values are at V = 5 V, T = 25°C.
CC
A
8
Typical Characteristics
All typical values are at T = 25°C, V = 5 V, unless otherwise specified.
A
CC
Symbol
CIN
Test Conditions
VF = 0 V, f = 1 MHz
IF = 20 mA
Typ.
60
Units
pF
Fig.
Notes
Parameter
Input Capacitance
1
1
Input Diode Temperature Coefficient
Resistance (Input-Output)
-1.5
mV/°C
∆VF/∆TA
RI-O
VI-O = 500 V
1012
3
Ω
pF
-
Capacitance (Input-Output)
CI-O
hFE
f = 1 MHz
1.0
250
21
1, 11
Transistor DC Current Gain
VO = 5 V, IO = 3 mA
VCC = 5 V, VO = 2 V
1
1
Small Signal Current Transfer Ratio
%
7
∆IO/∆IF
|CMH|
Common Mode Transient Immunity
at Logic High Level Output
IF = 0 mA, RL = 8.2 kΩ,
VO (min) = 2.0 V,
VCM = 10 VP-P
1000
-1000
9
V/µs
V/µs
MHz
10
1, 7
1, 7
8
Common Mode Transient Immunity
at Logic Low Level Output
|CML|
BW
IF = 16 mA, RL = 8.2 kΩ,
VO (max) = 0.8 V,
VCM = 10 VP-P
10
8
Bandwidth
Multi-Channel Product Only
Parameter
Symbol
II-I
Test Conditions
Typ.
1
1012
Units
pA
Notes
5, 9
5
Input-Input Insulation Leakage Current
Resistance (Input-Input)
RH ≤ 65%, VI-I = 500 V, t = 5 s
RI-I
VI-I = 500 V
Ω
Capacitance (Input-Input)
CI-I
f=1 MHz
0.8
pF
5
Notes:
6.
t
propagation delay is measured from the
PHL
1. Each channel of a multi-channel device.
2. Current Transfer Ratio is defined as the ratio
10. Higher CTR minimums are available to
support special applications.
11. Measured between each input pair shorted
together and all output connections for that
channel shorted together.
12. Standard parts receive 100% testing at 25°C
(Subgroups 1 and 9). SMD and 883B parts
receive 100% testing at 25, 125, and -55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11,
respectively).
13. Not required for 4N55, 4N55/883B, HCPL-
257K, 5962-8767901, and5962-8767905
types.
50% point on the leading edge of the input
pulse to the 1.5 V point on the leading edge
of the output pulse. The t propagation
delay is measured from the 50% point on the
trailing edge of the input pulse to the 1.5 V
point on the trailing edge of the output
pulse.
of output collector current, I , to the
O
forward LED input current, I , times 100%.
PLH
F
CTR is known to degrade slightly over the
unit’s lifetime as a function of input current,
temperature, signal duty cycle, and system
on time. Refer to Application Note 1002 for
more detail. ln short, it is recommended that
designers allow at least 20-25% guardband
for CTR degradation.
7. CM is the maximum rate of rise of the
L
common mode voltage that can be
sustained with the output voltage in the
logic low state (V < 0.8 V). CM is the
maximum rate of fall of the common mode
voltage that can be sustained with the
3. All devices are considered two-terminal
devices; measured between all input leads
or terminals shorted together and all output
leads or terminals shorted together.
4. The 4N55, 4N55/883B, HCPL-257K, HCPL-
6530, HCPL-6531, and HCPL-653K dual
channel parts function as two independent
single channel units. Use the single channel
O
H
14. Required for 4N55, 4N55/883B, HCPL-257K,
5962-8767901, and 5962-8767905 types only.
output voltage in the logic high state (V
2.0 V).
>
O
8. Bandwidth is the frequency at which the ac
output voltage is 3 dB below the low
frequency asymptote. For the HCPL-5530
the typical bandwidth is 2 MHz.
parameter limits. I = 0 mA for channel
F
9. This is a momentary withstand test, not an
operating condition.
under test and I = 20 mA for other
channels.
F
5. Measured between adjacent input pairs
shorted together for each multichannel
device.
9
Figure 1. Input Diode Forward Current vs.
Forward Voltage.
Figure 2. DC and Pulsed Transfer
Characteristic.
Figure 3. Normalized Current Transfer Ratio
vs. Input Diode Forward Current.
100
I
I
= 250 µA,
(OTHER CHANNELS) = 20 mA
F
F
I
I
= 0 µA,
10
1
F
F
(OTHER CHANNELS) = 20 mA
I
= I (OTHER CHANNELS)
F
= 0 mA
F
0.1
V
= V = 18 V
O
CC
0.01
0.001
-60 -40 -20
0
20 40 60 80 100 120 140
TA - TEMPERATURE - ˚C
Figure 4. Logic High Output Current vs.
Temperature.
Figure 5. Logic Low Supply Current vs. Input
Diode Forward Current.
Figure 6. Propagation Delay vs. Temperature.
Figure 7. Normalized Small Signal Current
Transfer Ratio vs. Quiescent Input Current.
10
+12 V
D.U.T.
+12 V
1.2 k Ω
9.1 k Ω
V
CC
0.01 µF
0.01 µF
2.1 k Ω
100 Ω
Q
3
0.1 µF
0.1 µF
V
V
O
B
47 µF
Q
V
O
2
Q
1
(1 MΩ, 12 pF
V
IN
TEST INPUT)
15 k Ω
470
Ω
100 Ω
R
F
51 Ω
1 k Ω
GND
SINGLE CHANNEL TESTING,
INDEPENDENT V DEVICES
22 Ω
CC
1N4150
TRIM FOR UNITY GAIN
, Q , Q : 2N3904
Q
TYPICAL LINEARITY = +3 % AT V = 1 V
IN P-P
TYPICAL SNR = 50 dB
1
2
3
TYPICAL R = 375 Ω
F
TYPICAL V dc = 3.8 V
O
TYPICAL I = 9 mA
F
D.U.T.
+5 V
+15
+10
+15 V
V
T
= 25 ˚C
A
CC
100 Ω
SET I
20 k Ω
F
V
O
INDEPENDENT
DEVICES
+5
0
2N3053
1.6 Vdc
0.25 V
AC INPUT
V
CC
0.1 µF
ac
P-P
560 Ω
100 Ω
GND
COMMON
-5
COMMON V
DEVICES
CC
-10
V
DEVICES
CC
-15
-20
0.1
1.0
10
100
f - FREQUENCY - MHz
Figure 8. Frequency Response.
PULSE GEN.
Z
t
= 50 Ω
= 5 ns
O
r
D.U.T.
I
+5 V
F
V
CC
R
L
V
O
I
MONITOR
F
100 Ω
C
* = 50 pF
L
GND
SINGLE CHANNEL
OR COMMON V DEVICES
CC
10 % DUTY CYCLE
1/f < 100 µs
NOTES:
* C INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
L
BASE LEAD NOT CONNECTED.
Figure 9. Switching Test Circuit.*
*JEDEC Registered Data.
11
IF
B
A
D.U.T.
+5 V
VCC
R
L
RM
V
O
V
FF
GND
SINGLE CHANNEL OR
COMMON VCC DEVICES
V
CM
+
-
PULSE GEN.
NOTE: BASE LEAD NOT CONNECTED.
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.
V
5 V
CC
220 Ω
LSTTL
CMOS
Logic Family
Device No.
VCC
R
L
D.U.T.
54LS14
5 V
CD40106BM
V
CC
5 V
8.2 kΩ
15 V
TTL
RL 5% Tolerance
18 kΩ *
22 kΩ
LOGIC GATE
0.01 µF
*The equivalent output load resistance is affected by the LSTTL input current and is
approximately 8.2 kΩ. This is a worst case design which takes into account 25%
degradation of CTR. See App. Note 1002 to assess actual degradation and lifetime.
GND
EACH CHANNEL
Figure 11. Recommended Logic Interface.
VCC
VOC
D.U.T.*
VCC
(EACH INPUT)
0.1 µF
+
-
VO
VIN
(EACH OUTPUT)
GND
NOMINAL CONDITIONS
PER CHANNEL: IF = 20 mA
IO = 4 mA
ICC = 30 µA
NOTE: BASE LEAD NOT CONNECTED.
T
= +125 ˚C
A
Figure 12. Operating Circuit for Burn-In and
Steady State Life Tests. All Channels Tested
Simultaneously.
12
OFFSET ADJUST
R
3
2
1
2
HCPL-5530
5 k Ω
I
F
-
1
220
-
U
+
Ω
U
8
7
6
5
1
2
3
4
1
+
+
I
I
C
C
3
V
I
F
IN
2
2
R
1 kΩ
4
-
U
5 k Ω GAIN ADJUST
2
-
+
50 k Ω
R
5
-15 V
-
R
R
2
2.7 k Ω
1
U
+
V
OUT
4
2.7 k Ω
U
I
, U , U , U , LM307
1
2
3
4
2
n
1
I
I
F
F
1
I
= K
C
1
2
6 mA
CC
1
1
´
n
2
I
I
F
F
´
2
I
= K
-15 V
C
2
2
Figure 13. Isolation Amplifier Application Circuit.
Description
Performance of Circuit
MIL-PRF-38534 Class H, Class K, and
DSCC SMD Test Program
The schematic uses a
• 1% linearity for 10 V peak-
to-peak dynamic range
dualchannel, high-speed
optocoupler (HCPL-5530) to
function as a servo type dc
isolation amplifier. This circuit
operates on the principle that
two optocouplers will track
each other if their gain
changes by the same amount
over a specific operating
region.
Agilent’s Hi-Rel Optocouplers
are in compliance with MIL-
PRF-38534 Classes H and K.
Class H and Class K devices
are also in compliance with
DSCC drawings 5962-87679,
and 5962-90854. Testing
consists of 100% screening and
quality conformance inspection
to MIL-PRF-38534.
• Gain drift: -0.03%/°C
• Offset Drift: 1 mV/°C
• 25 kHz bandwidth (limited
by Op-Amps U1, U2)
13
www.agilent.com/
semiconductors
For product information and a complete list
of distributors, please go to our web site.
For technical assistance call:
Americas/Canada: +1 (800) 235-0312
or (408) 654-8675
Europe: +49 (0) 6441 92460
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Hong Kong: (+65) 6756 2394
India, Australia, New Zealand: (+65) 6755 1939
Japan: (+81 3) 3335-8152(Domestic/Inter-
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Taiwan: (+65) 6755 1843
Data subject to change.
Copyright © 2004 Agilent Technologies, Inc.
December 10, 2004
5989-1659EN
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