T7633_技术文档

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

■ Alarm reporting and performance monitoring per

Features

AT&T ^®, ANSI^®, and ITU-T standards.

■ Programmable, independent transmit and receive

system interfaces at a 2.048 MHz, 4.096 MHz, or

8.192 MHz data rate.

The T7633 Dual T1/E1 Terminator consists of two

independent, highly integrated, software-config-

urable, full-featured short-haul transceiver/framers.

The T7633 provides glueless interconnection from a

T1/E1 line to a digital PCM system. Minimal external

clocks are needed. Only a system clock/frame sync

and a phase-locked line rate clock are required. Sys-

tem diagnostic and performance monitoring capabil-

ity with integrated programmable test pattern

■ System interface master mode for generation of

system frame sync from the line source.

■ Internal phase-locked loop (with external VCXO)

for generation of system clock from the line source.

Facility Data Link Features

generator/detector and loopback modes is provided.

■ HDLC or transparent modes.

Power Requirements and Package

■ Automatic transmission and detection of ANSI

T1.403 FDL performance report message and bit-

oriented codes.

■ Single 3.3 V ± 5% supply.

■ Low power: 375 mW per channel maximum.

■ 144-pin TQFP package.

■ 64-byte FIFO in both transmit and receive direc-

tions.

■ Operating temperature range: –40 °C to +85 °C.

Microprocessor Interface

T1/E1 Line Interface Features

■ 33 MHz, 8-bit data interface, no wait-states.

■ Intel^®or Motorola^®interface modes with multi-

■ Full T1/E1 pulse template compliance.

plexed or demultiplexed buses.

■ Receiver provides equalization for up to 11 dB of

loss.

■ Directly addressable control registers.

■ Digital clock and data recovery.

■ Line coding: B8ZS, HDB3, ZCS, and AMI.

Applications

■ Line interface coupling and matching networks for

T1 and E1 (120 Ω and 75 Ω).

■ Customer Premises Equipment—CSU/DSU,

routers, digital PBX, channel banks (CB), base

transceiver stations (BTS-picocell), small switches,

and digital subscriber loop access multiplexers

(DSLAM).

T1/E1 Framer Features

■ Supports T1 framing modes ESF, D4, SLC^®-96,

T1DM DDS.

■ Loop/Access—DLC/IDLC, DCS, BTS (microcell/

macrocell), DSLAMs, and multiplexers (terminal,

synchronous/asynchronous, add drop).

■ Supports G.704 basic and CRC-4 multiframe for-

mat E1 framing and procedures consistent with

G.706.

■ Central Office—Digital switches, DCS, CB,

access concentrators, remote switch modules

(RSM), and DSLAMs.

■ Supports unframed transmission format.

■ T1 signaling modes: transparent; ESF 2-state,

4-state, and 16-state; D4 2-state and 4-state; SLC-

96 2-state, 4-state, 9-state, and 16-state. E1 sig-

naling modes: transparent, CAS, CCS, and IRMS.

■ Test Equipment—Transmission/BERT tester.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Table of Contents

Contents

Page

Features ................................................................................................................................................................... 1

Power Requirements and Package.................................................................................................................... 1

T1/E1 Line Interface Features............................................................................................................................ 1

T1/E1 Framer Features...................................................................................................................................... 1

Facility Data Link Features................................................................................................................................. 1

Microprocessor Interface.................................................................................................................................... 1

Applications........................................................................................................................................................ 1

Feature Descriptions .............................................................................................................................................. 13

T1/E1 Line Interface Features.......................................................................................................................... 13

T1/E1 Framer Features.................................................................................................................................... 13

Facility Data Link Features............................................................................................................................... 14

User-Programmable Microprocessor Interface ................................................................................................ 14

Functional Description............................................................................................................................................ 15

Pin Information ....................................................................................................................................................... 19

Line Interface Unit: Block Diagram......................................................................................................................... 26

Line Interface Unit: Receive ................................................................................................................................... 26

Data Recovery.................................................................................................................................................. 26

Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator........................................................... 27

Receive Line Interface Configuration Modes ................................................................................................... 27

T1/DS1 LIU Receiver Specifications ................................................................................................................ 30

CEPT LIU Receiver Specifications................................................................................................................... 31

Line Interface Unit: Transmit .................................................................................................................................. 34

Output Pulse Generation.................................................................................................................................. 34

LIU Transmitter Configuration Modes .............................................................................................................. 35

LIU Transmitter Alarms .................................................................................................................................... 35

DSX-1 Transmitter Pulse Template and Specifications ................................................................................... 37

CEPT Transmitter Pulse Template and Specifications .................................................................................... 38

Line Interface Unit: Jitter Attenuator....................................................................................................................... 40

Generated (Intrinsic) Jitter................................................................................................................................ 40

Jitter Transfer Function .................................................................................................................................... 40

Jitter Accommodation....................................................................................................................................... 41

Jitter Attenuator Enable (Transmit or Receive Path)........................................................................................ 41

Line Interface Unit: Loopbacks............................................................................................................................... 44

Full Local Loopback (FLLOOP)........................................................................................................................ 44

Remote Loopback (RLOOP) ............................................................................................................................ 44

Digital Local Loopback (DLLOOP) ................................................................................................................... 44

Line Interface Unit: Other Features ........................................................................................................................ 45

LIU Powerdown (PWRDN)............................................................................................................................... 45

Loss of Framer Receive Line Clock (LOFRMRLCK Pin).................................................................................. 45

In-Circuit Testing and Driver High-Impedance State (3-STATE)...................................................................... 45

LIU Delay Values.............................................................................................................................................. 45

SYSCK Reference Clock........................................................................................................................................ 46

Line Interface Unit: Line Interface Networks........................................................................................................... 48

LIU-Framer Interface .............................................................................................................................................. 50

LIU-Framer Physical Interface.......................................................................................................................... 50

Interface Mode and Line Encoding................................................................................................................... 52

DS1: Zero Code Suppression (ZCS)................................................................................................................ 53

CEPT: High-Density Bipolar of Order 3 (HDB3)............................................................................................... 54

2

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Table of Contents (continued)

Contents

Page

Frame Formats........................................................................................................................................................55

T1 Framing Structures ......................................................................................................................................55

T1 Loss of Frame Alignment (LFA)...................................................................................................................62

T1 Frame Recovery Alignment Algorithms .......................................................................................................63

T1 Robbed-Bit Signaling ...................................................................................................................................64

CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures.................66

CEPT 2.048 Basic Frame Structure..................................................................................................................67

CEPT Loss of Basic Frame Alignment (LFA)....................................................................................................69

CEPT Loss of Frame Alignment Recovery Algorithm .......................................................................................69

CEPT Time Slot 0 CRC-4 Multiframe Structure................................................................................................70

CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA)..................................................................................71

CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms...................................................................72

CEPT Time Slot 16 Multiframe Structure..........................................................................................................76

CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA) ......................................................................78

CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm............................................................78

CEPT Time Slot 0 FAS/NOT FAS Control Bits .......................................................................................................79

FAS/NOT FAS Si- and E-Bit Source.................................................................................................................79

NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources ...................................................................................80

NOT FAS Sa-Bit Sources..................................................................................................................................80

Sa Facility Data Link Access.............................................................................................................................81

NOT FAS Sa Stack Source and Destination.....................................................................................................82

CEPT Time Slot 16 X0—X2 Control Bits ..........................................................................................................84

Signaling Access.....................................................................................................................................................85

Transparent Signaling.......................................................................................................................................85

DS1: Robbed-Bit Signaling ...............................................................................................................................85

CEPT: Time Slot 16 Signaling...........................................................................................................................86

Auxiliary Framer I/O Timing ....................................................................................................................................87

Alarms and Performance Monitoring.......................................................................................................................91

Interrupt Generation..........................................................................................................................................91

Alarm Definition.................................................................................................................................................91

Event Counters Definition .................................................................................................................................97

Loopback and Transmission Modes .................................................................................................................99

Line Test Patterns...........................................................................................................................................102

Automatic and On-Demand Commands .........................................................................................................106

Facility Data Link (FDL).........................................................................................................................................108

Receive Facility Data Link Interface................................................................................................................108

Transmit Facility Data Link Interface...............................................................................................................114

HDLC Operation..............................................................................................................................................115

Transparent Mode...........................................................................................................................................118

Diagnostic Modes............................................................................................................................................120

Phase-Lock Loop Circuit.......................................................................................................................................122

Framer-System (CHI) Interface.............................................................................................................................124

DS1 Modes .....................................................................................................................................................124

CEPT Modes...................................................................................................................................................124

Receive Elastic Store......................................................................................................................................124

Transmit Elastic Store.....................................................................................................................................124

Concentration Highway Interface (CHI) ................................................................................................................125

CHI Parameters ..............................................................................................................................................126

CHI Frame Timing...........................................................................................................................................129

CHI Offset Programming.................................................................................................................................132

Agere Systems Inc.

3

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Table of Contents (continued)

Contents

Page

JTAG Boundary-Scan Specification ..................................................................................................................... 135

Principle of the Boundary Scan...................................................................................................................... 135

Test Access Port Controller............................................................................................................................ 136

Instruction Register ........................................................................................................................................ 138

Boundary-Scan Register ................................................................................................................................ 139

BYPASS Register........................................................................................................................................... 139

IDCODE Register........................................................................................................................................... 139

3-State Procedures ........................................................................................................................................ 139

Microprocessor Interface...................................................................................................................................... 140

Overview ........................................................................................................................................................ 140

Microprocessor Configuration Modes............................................................................................................. 140

Microprocessor Interface Pinout Definitions................................................................................................... 141

Microprocessor Clock (MPCLK) Specifications.............................................................................................. 142

Microprocessor Interface Register Address Map ........................................................................................... 142

I/O Timing....................................................................................................................................................... 142

Reset .................................................................................................................................................................... 149

Hardware Reset (Pin 43/139)......................................................................................................................... 149

Software Reset/Software Restart................................................................................................................... 149

Interrupt Generation ............................................................................................................................................. 149

Register Architecture............................................................................................................................................ 150

Global Register Architecture................................................................................................................................. 154

Global Register Structure ..................................................................................................................................... 155

Primary Block Interrupt Status Register (GREG0) ......................................................................................... 155

Primary Block Interrupt Enable Register (GREG1) ........................................................................................ 155

Global Loopback Control Register (GREG2) ................................................................................................. 156

Global Loopback Control Register (GREG3) ................................................................................................. 156

Global Control Register (GREG4).................................................................................................................. 157

Device ID and Version Registers (GREG5—GREG7) ................................................................................... 157

Line Interface Unit (LIU) Register Architecture..................................................................................................... 158

Line Interface Alarm Register............................................................................................................................... 159

Alarm Status Register (LIU_REG0)................................................................................................................ 159

Line Interface Alarm Interrupt Enable Register .................................................................................................... 159

Alarm Interrupt Enable Register (LIU_REG1) ................................................................................................ 159

Line Interface Control Registers........................................................................................................................... 160

LIU Control Register (LIU_REG2).................................................................................................................. 160

LIU Control Register (LIU_REG3).................................................................................................................. 161

LIU Control Register (LIU_REG4).................................................................................................................. 162

LIU Configuration Register (LIU_REG5) ........................................................................................................ 162

LIU Configuration Register (LIU_REG6) ........................................................................................................ 163

Framer Register Architecture ............................................................................................................................... 164

Framer Status/Counter Registers................................................................................................................... 165

Framer Parameter/Control Registers ............................................................................................................. 180

FDL Register Architecture .................................................................................................................................... 211

FDL Parameter/Control Registers (800—80E; E00—E0E).................................................................................. 212

Register Maps ...................................................................................................................................................... 219

Global Registers............................................................................................................................................. 219

Line Interface Unit Parameter/Control and Status Registers ......................................................................... 219

Framer Parameter/Control Registers (READ-WRITE)................................................................................... 220

Receive Framer Signaling Registers (READ-ONLY) ..................................................................................... 222

Framer Unit Parameter Register Map ............................................................................................................ 223

Transmit Signaling Registers (READ/WRITE) ............................................................................................... 226

Facility Data Link Parameter/Control and Status Registers (READ-WRITE)................................................. 227

4

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Table of Contents (continued)

Contents

Page

Absolute Maximum Ratings ..................................................................................................................................228

Operating Conditions ............................................................................................................................................228

Handling Precautions............................................................................................................................................228

Electrical Characteristics.......................................................................................................................................229

Logic Interface Characteristics........................................................................................................................229

Power Supply Bypassing ......................................................................................................................................229

Outline Diagram ....................................................................................................................................................230

144-Pin TQFP .................................................................................................................................................230

Ordering Information .............................................................................................................................................231

Index .....................................................................................................................................................................232

Agere Systems Inc.

5

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

List of Figures

Figure

Page

Figure 1. T7633 Block Diagram (One of Two Channels)........................................................................................ 15

Figure 2. T7633 Block Diagram: Receive Section (One of Two Channels)............................................................ 17

Figure 3. T7633 Block Diagram: Transmit Section (One of Two Channels)........................................................... 18

Figure 4. Pin Assignment ....................................................................................................................................... 19

Figure 5. Block Diagram of Line Interface Unit: Single Channel ............................................................................ 26

Figure 6. T1/DS1 Receiver Jitter Accommodation Without Jitter Attenuator.......................................................... 32

Figure 7. T1/DS1 Receiver Jitter Transfer Without Jitter Attenuator ...................................................................... 32

Figure 8. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator....................................................... 33

Figure 9. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator ................................................................... 33

Figure 10. DSX-1 Isolated Pulse Template ............................................................................................................ 37

Figure 11. ITU-T G.703 Pulse Template ................................................................................................................ 38

Figure 12. T1/DS1 Receiver Jitter Accommodation with Jitter Attenuator.............................................................. 42

Figure 13. T1/DS1 Jitter Transfer of the Jitter Attenuator....................................................................................... 42

Figure 14. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator........................................................... 43

Figure 15. CEPT/E1 Jitter Transfer of the Jitter Attenuator.................................................................................... 43

Figure 16. Line Termination Circuitry ..................................................................................................................... 48

Figure 17. T7633 Line Interface Unit Approximate Equivalent Analog I/O Circuits................................................ 49

Figure 18. Block Diagram of Framer Line Interface................................................................................................ 50

Figure 19. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing...................... 51

Figure 20. T1 Frame Structure ............................................................................................................................... 55

Figure 21. T1 Transparent Frame Structure........................................................................................................... 56

Figure 22. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections...................... 58

Figure 23. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe

Structures............................................................................................................................................... 66

Figure 24. CEPT Transparent Frame Structure ..................................................................................................... 68

Figure 25. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer................................... 73

Figure 26. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment

Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991)...................................... 75

Figure 27. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT Mode... 81

Figure 28. Transmit and Receive Sa Stack Accessing Protocol ............................................................................ 83

Figure 29. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode............................................. 87

Figure 30. Timing Specification for TFS, TLCK, and TPD in DS1 Mode................................................................ 87

Figure 31. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode.......................................... 88

Figure 32. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode............................ 88

Figure 33. Timing Specification for RCRCMFS in CEPT Mode.............................................................................. 89

Figure 34. Timing Specification for TFS, TLCK, and TPD in CEPT Mode ............................................................. 89

Figure 35. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode................................................ 90

Figure 36. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode.......................................... 90

Figure 37. Relation Between RLCK1 and Interrupt (Pin 99)................................................................................... 91

Figure 38. Timing for Generation of LOPLLCK (Pin 39/143).................................................................................. 93

Figure 39. The T and V Reference Points for a Typical CEPT E1 Application....................................................... 96

Figure 40. Loopback and Test Transmission Modes............................................................................................ 101

Figure 41. 20-Stage Shift Register Used to Generate the Quasi-Random Signal................................................ 102

Figure 42. 15-Stage Shift Register Used to Generate the Pseudorandom Signal ............................................... 103

Figure 43. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections.................... 108

Figure 44. Block Diagram for the Receive Facility Data Link Interface ................................................................ 109

Figure 45. Block Diagram for the Transmit Facility Data Link Interface ............................................................... 114

Figure 46. Local Loopback Mode ......................................................................................................................... 120

Figure 47. Remote Loopback Mode ..................................................................................................................... 121

Figure 48. T7633 Phase Detector Circuitry .......................................................................................................... 123

Figure 49. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0—bit 2 = 100 (Binary))......... 129

Figure 50. CHIDTS Mode Concentration Highway Interface Timing.................................................................... 130

6

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

List of Figures (continued)

Figure

Page

Figure 51. Associated Signaling Mode Concentration Highway Interface Timing.................................................131

Figure 52. CHI Timing with ASM and CHIDTS Enabled .......................................................................................131

Figure 53. TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 0 (CEX = 3 and CER = 4,

Respectively) .......................................................................................................................................133

Figure 54. CHI TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 1 (CEX = 3 and CER = 6,

Respectively) .......................................................................................................................................133

Figure 55. Receive CHI (RCHIDATA) Timing .......................................................................................................134

Figure 56. Transmit CHI (TCHIDATA) Timing .......................................................................................................134

Figure 57. Block Diagram of the T7633’s Boundary-Scan Test Logic...................................................................135

Figure 58. BS TAP Controller State Diagram........................................................................................................136

Figure 59. Mode 1—Read Cycle Timing (MPMODE = 0, MPMUX = 0)................................................................145

Figure 60. Mode 1—Write Cycle Timing (MPMODE = 0, MPMUX = 0)................................................................145

Figure 61. Mode 2—Read Cycle Timing (MPMODE = 0, MPMUX = 1)................................................................146

Figure 62. Mode 2—Write Cycle Timing (MPMODE = 0, MPMUX = 1)................................................................146

Figure 63. Mode 3—Read Cycle Timing (MPMODE = 1, MPMUX = 0)................................................................147

Figure 64. Mode 3—Write Cycle Timing (MPMODE = 1, MPMUX = 0)................................................................147

Figure 65. Mode 4—Read Cycle Timing (MPMODE = 1, MPMUX = 1)................................................................148

Figure 66. Mode 4—Write Cycle Timing (MPMODE = 1, MPMUX = 1)................................................................148

Agere Systems Inc.

7

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

List of Tables

Table

Page

Table 1. Pin Descriptions........................................................................................................................................ 20

Table 2. Digital Loss of Signal Standard Select ..................................................................................................... 28

Table 3. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) ................................. 29

Table 4. DS1 LIU Receiver Specifications.............................................................................................................. 30

Table 5. CEPT LIU Receiver Specifications........................................................................................................... 31

Table 6. Transmit Line Interface Short-Haul Equalizer/Rate Control ..................................................................... 34

Table 7. DSX-1 Pulse Template Corner Points (from CB119, T1.102) .................................................................. 37

Table 8. DS1 Transmitter Specifications ................................................................................................................ 38

Table 9. CEPT Transmitter Specifications.............................................................................................................. 39

Table 10. Loopback Control ................................................................................................................................... 44

Table 11. SYSCK (16x, CKSEL = 1) Timing Specifications ................................................................................... 46

Table 12. SYSCK (1x, CKSEL = 0) Timing Specifications ..................................................................................... 46

Table 13. Termination Components by Application................................................................................................ 48

Table 14. AMI Encoding ......................................................................................................................................... 52

Table 15. DS1 ZCS Encoding ................................................................................................................................ 53

Table 16. DS1 B8ZS Encoding............................................................................................................................... 53

Table 17. ITU HDB3 Coding................................................................................................................................... 54

Table 18. T-Carrier Hierarchy................................................................................................................................. 55

Table 19. D4 Superframe Format........................................................................................................................... 57

Table 20. DDS Channel-24 Format........................................................................................................................ 58

Table 21. SLC-96 Data Link Block Format............................................................................................................. 59

Table 22. SLC-96 Line Switch Message Codes..................................................................................................... 60

Table 23. Transmit and Receive SLC-96 Stack Structure...................................................................................... 60

Table 24. Extended Superframe (ESF) Structure................................................................................................... 61

Table 25. T1 Loss of Frame Alignment Criteria...................................................................................................... 62

Table 26. T1 Frame Alignment Procedures............................................................................................................ 63

Table 27. Robbed-Bit Signaling Options ................................................................................................................ 64

Table 28. SLC-96 9-State Signaling Format........................................................................................................... 64

Table 29. 16-State Signaling Format...................................................................................................................... 65

Table 30. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame..................................................... 67

Table 31. ITU CRC-4 Multiframe Structure ............................................................................................................ 70

Table 32. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure........................................ 76

Table 33. CEPT IRSM Signaling Multiframe Structure........................................................................................... 77

Table 34. Transmit and Receive Sa Stack Structure.............................................................................................. 82

Table 35. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames .......................................... 86

Table 36. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels................................... 86

Table 37. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT..................................................... 86

Table 38. Red Alarm or Loss of Frame Alignment Conditions ............................................................................... 92

Table 39. Remote Frame Alarm Conditions ........................................................................................................... 92

Table 40. Alarm Indication Signal Conditions......................................................................................................... 93

Table 41. Sa6 Bit Coding Recognized by the Receive Framer .............................................................................. 95

Table 42. Sa6 Bit Coding of NT1 Interface Events Recognized by the Receive Framer ....................................... 96

Table 43. AUXP Synchronization and Clear Sychronization Process.................................................................... 96

Table 44. Event Counters Definition....................................................................................................................... 97

Table 45. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function of

Activating the Primary Loopback Modes.............................................................................................. 100

Table 46. Register FRM_PR69 Test Patterns...................................................................................................... 103

Table 47. Register FRM_PR70 Test Patterns...................................................................................................... 104

Table 48. Automatic Enable Commands.............................................................................................................. 106

Table 49. On-Demand Commands....................................................................................................................... 107

Table 50. Receive ANSI Code.............................................................................................................................. 110

8

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

List of Tables (continued)

Table

Page

Table 51. Performance Report Message Structure...............................................................................................110

Table 52. FDL Performance Report Message Field Definition..............................................................................111

Table 53. Octet Contents and Definition ...............................................................................................................111

Table 54. Receive Status of Frame Byte ..............................................................................................................112

Table 55. HDLC Frame Format.............................................................................................................................115

Table 56. Receiver Operation in Transparent Mode .............................................................................................119

Table 57. Summary of the T7633’s Concentration Highway Interface Parameters ..............................................126

Table 58. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0.....................................................132

Table 59. Programming Values for TOFF[2:0] when CMS = 1 .............................................................................132

Table 60. Programming Values for ROFF[2:0] when CMS = 1.............................................................................132

Table 61. TAP Controller States in the Data Register Branch ..............................................................................137

Table 62. TAP Controller States in the Instruction Register Branch .....................................................................137

Table 63. T7633’s Boundary-Scan Instructions ....................................................................................................138

Table 64. IDCODE Register..................................................................................................................................139

Table 65. Microprocessor Configuration Modes ...................................................................................................140

Table 66. Mode [1—4] Microprocessor Pin Definitions.........................................................................................141

Table 67. Microprocessor Input Clock Specifications ...........................................................................................142

Table 68. T7633 Register Address Map ...............................................................................................................142

Table 69. Microprocessor Interface I/O Timing Specifications..............................................................................143

Table 70. Status Register and Corresponding Interrupt Enable Register for Functional Blocks...........................149

Table 71. Asserted Value and Deasserted State for GREG4 Bit 4 and Bit 6 Logic Combinations .......................149

Table 72. Register Summary ................................................................................................................................150

Table 73. Global Register Set (0x000—0x008) ....................................................................................................154

Table 74. Primary Block Interrupt Status Register (GREG0) (000).......................................................................155

Table 75. Primary Block Interrupt Enable Register (GREG1) (001)......................................................................155

Table 76. Global Loopback Control Register (GREG2) (002)...............................................................................156

Table 77. Global Loopback Control Register (GREG3) (003)...............................................................................156

Table 78. Global Control Register (GREG4) (004) ...............................................................................................157

Table 79. Device ID and Version Registers (GREG5—GREG7) (005—007) .......................................................157

Table 80. Line Interface Units Register Set ((400—40F); (A00—A0F))................................................................158

Table 81. LIU Alarm Status Register (LIU_REG0) (400, A00)..............................................................................159

Table 82. LIU Alarm Interrupt Enable Register (LIU_REG1) (401, A01)...............................................................159

Table 83. LIU Control Register (LIU_REG2) (402, A02).......................................................................................160

Table 84. LIU Control Register (LIU_REG3) (403, A03).......................................................................................161

Table 85. LIU Register (LIU_REG4) (404, A04)....................................................................................................162

Table 86. LIU Configuration Register (LIU_REG5) (405, A05) .............................................................................162

Table 87. LIU Configuration Register (LIU_REG6) (406, A06) .............................................................................163

Table 88. Framer Status and Control Blocks Address Range (Hexadecimal) ......................................................164

Table 89. Interrupt Status Register (FRM_SR0) (600; C00).................................................................................165

Table 90. Facility Alarm Condition Register (FRM_SR1) (601; C01)....................................................................166

Table 91. Remote End Alarm Register (FRM_SR2) (602; C02) ...........................................................................167

Table 92. Facility Errored Event Register-1 (FRM_SR3) (603; C03)....................................................................168

Table 93. Facility Event Register-2 (FRM_SR4) (604; C04).................................................................................169

Table 94. Exchange Termination and Exchange Termination Remote End Interface

Status Register (FRM_SR5) (605; C05) ...............................................................................................171

Table 95. Network Termination and Network Termination Remote End Interface

Status Register (FRM_SR6) (606; C06) ...............................................................................................172

Table 96. Facility Event Register (FRM_SR7) (607; C07) ....................................................................................173

Table 97. Bipolar Violation Counter Registers (FRM_SR8—FRM_SR9) ((608—609); (C08—C09)) ...................173

Table 98. Framing Bit Error Counter Registers (FRM_SR10—FRM_SR11) ((60A—60B); (C0A—C0B)) ............173

Table 99. CRC Error Counter Registers (FRM_SR12—FRM_SR13) ((60C—60D); (C0C—C0D))......................174

Table 100. E-Bit Counter Registers (FRM_SR14—FRM_SR15) ((60E—60F); (C0E—C0F)) ..............................174

Agere Systems Inc.

9

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

List of Tables (continued)

Table

Page

Table 101. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16—FRM_SR17)

((610—611); (C10—C11)) ................................................................................................................ 174

Table 102. E Bit at NT1 from NT2 Counter (FRM_SR18—FRM_SR19) ((612—613); (C12—C13)) ................... 174

Table 103. ET Errored Seconds Counter (FRM_SR20—FRM_SR21) ((614—615); (C14—C15))...................... 175

Table 104. ET Bursty Errored Seconds Counter (FRM_SR22—FRM_SR23) ((616—617); (C16—C17))........... 175

Table 105. ET Severely Errored Seconds Counter (FRM_SR24—FRM_SR25) ((618—619); (C18—C19))....... 175

Table 106. ET Unavailable Seconds Counter (FRM_SR26—FRM_SR27) ((61A—61B); (C1A—C1B)).............. 175

Table 107. ET-RE Errored Seconds Counter (FRM_SR28—FRM_SR29) ((61C—61D); (C1C—C1D)) ............. 175

Table 108. ET-RE Bursty Errored Seconds Counter (FRM_SR30—FRM_SR31) ((61E—61F); (C1E—C1F)) ... 175

Table 109. ET-RE Severely Errored Seconds Counter (FRM_SR32—FRM_SR33)

((620—621); (C20—C21)).................................................................................................................. 175

Table 110. ET-RE Unavailable Seconds Counter (FRM_SR34—FRM_SR35) ((622—623); (C22—C23))......... 176

Table 111. NT1 Errored Seconds Counter (FRM_SR36—FRM_SR37) ((624—625); (C24—C25)).................... 176

Table 112. NT1 Bursty Errored Seconds Counter (FRM_SR38—FRM_SR39) ((626—627); (C26—C27))......... 176

Table 113. NT1 Severely Errored Seconds Counter (FRM_SR40—FRM_SR41) ((628—629); (C28—C29))..... 176

Table 114. NT1 Unavailable Seconds Counter (FRM_SR42—FRM_SR43) ((62A—62B); (C2A—C2B)) ........... 176

Table 115. NT1-RE Errored Seconds Counter (FRM_SR44—FRM_SR45) ((62C—62D); (C2C—C2D)) ........... 176

Table 116. NT1-RE Bursty Errored Seconds Counter (FRM_SR46—FRM_SR47)

((62E—62F); (C2E—C2F))................................................................................................................. 177

Table 117. NT1-RE Severely Errored Seconds Counter (FRM_SR48—FRM_SR49)

((630—631); (C30—C31)).................................................................................................................. 177

Table 118. NT1-RE Unavailable Seconds Counter (FRM_SR50—FRM_SR51) ((632—633); (C32—C33))....... 177

Table 119. Receive NOT-FAS TS0 Register (FRM_SR52) (634; C34)................................................................ 177

Table 120. Receive Sa Register (FRM_SR53) (635; C35)................................................................................... 177

Table 121. SLC-96 FDL Receive Stack (FRM_SR54—FRM_SR63) ((636—63F); (C36—C3F))........................ 178

Table 122. CEPT Sa Receive Stack (FRM_SR54—FRM_SR63) ((636—63F); (C36—C3F))............................. 178

Table 123. Transmit Framer ANSI Performance Report Message Status Register Structure ............................. 179

Table 124. Received Signaling Registers: DS1 Format (FRM_RSR0—FRM_RSR23)

((640—658); (C40—C58)).................................................................................................................. 179

Table 125. Receive Signaling Registers: CEPT Format (FRM_RSR0—FRM_RSR31)

((640—65F); (C40—C5F)) ................................................................................................................. 179

Table 126. Summary of Interrupt Group Enable Registers (FRM_PR0—FRM_PR7)

((660—667); (C60—C67)).................................................................................................................. 180

Table 127. Primary Interrupt Group Enable Register (FRM_PR0) (660; C60)..................................................... 181

Table 128. Interrupt Enable Register (FRM_PR1) (661; C61) ............................................................................. 182

Table 129. Interrupt Enable Register (FRM_PR2) (662; C62) ............................................................................. 182

Table 130. Interrupt Enable Register (FRM_PR3) (663; C63) ............................................................................. 182

Table 131. Interrupt Enable Register (FRM_PR4) (664; C64) ............................................................................. 182

Table 132. Interrupt Enable Register (FRM_PR5) (665; C65) ............................................................................. 182

Table 133. Interrupt Enable Register (FRM_PR6) (666; C66) ............................................................................. 182

Table 134. Interrupt Enable Register (FRM_PR7) (667; C67) ............................................................................. 182

Table 135. Framer Mode Bits Decoding (FRM_PR8) (668; C68)......................................................................... 183

Table 136. Line Code Option Bits Decoding (FRM_PR8) (668; C68) .................................................................. 183

Table 137. CRC Option Bits Decoding (FRM_PR9) (669, C69)........................................................................... 184

Table 138. Alarm Filter Register (FRM_PR10) (66A; C6A).................................................................................. 185

Table 139. Errored Event Threshold Definition .................................................................................................... 185

Table 140. Errored Second Threshold Register (FRM_PR11) (66B; C6B).......................................................... 186

Table 141. Severely Errored Second Threshold Registers (FRM_PR12—FRM_PR13)

((66C—66D; C6C—C6D)).................................................................................................................. 186

Table 142. ET1 Errored Event Enable Register (FRM_PR14) (66E; C6E) .......................................................... 186

Table 143. ET1 Remote End Errored Event Enable Register (FRM_PR15) (66F; C6F)...................................... 187

Table 144. NT1 Errored Event Enable Register (FRM_PR16) (670; C70)........................................................... 187

10

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

List of Tables (continued)

Table

Page

Table 145. NT1 Remote End Errored Event Enable Registers (FRM_PR17—FRM_PR18)

((671—672); (C71—C72)) ..................................................................................................................187

Table 146. Automatic AIS to the System and Automatic Loopback Enable Register

(FRM_PR19) (673; C73).....................................................................................................................188

Table 147. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (674; C74).....................................188

Table 148. Framer FDL Control Command Register (FRM_PR21) (675; C75) ....................................................189

Table 149. Framer Transmit Line Idle Code Register (FRM_PR22) (676; C76)...................................................189

Table 150. Framer System Stuffed Time Slot Code Register (FRM_PR23) (677; C77).......................................189

Table 151. Primary Time-Slot Loopback Address Register (FRM_PR24) (678; C78) ..........................................190

Table 152. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7—5 ..........................................................190

Table 153. Secondary Time-Slot Loopback Address Register (FRM_PR25) (679; C79) .....................................191

Table 154. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6—5 ..........................................................191

Table 155. Framer Reset and Transparent Mode Control Register (FRM_PR26) (67A, C7A).............................192

Table 156. Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A Bit = 1

Control Register (FRM_PR27) (67B, C7B).........................................................................................193

Table 157. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (67C; C7C) ....................194

Table 158. Sa4—Sa8 Source Register (FRM_PR29) (67D; C7D)........................................................................195

Table 159. Sa Bits Source Control for Bit 5—Bit 7 in FRM_PR29 ........................................................................195

Table 160. Sa4—Sa8 Control Register (FRM_PR30) (67E; C7E)........................................................................196

Table 161. Sa Transmit Stack (FRM_PR31—FRM_PR40) ((67F—688); (C7F—C88)) .......................................197

Table 162. SLC-96 Transmit Stack (FRM_PR31—FRM_PR40) ((67F—688); (C7F—C88))................................197

Table 163. Transmit SLC-96 FDL Format.............................................................................................................197

Table 164. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register

(FRM_PR41) (689; C89).....................................................................................................................198

Table 165. Framer Exercise Register (FRM_PR42) (68A; C8A) ..........................................................................198

Table 166. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (68A; C8A) .....................................................................199

Table 167. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (68B; C8B)...201

Table 168. Signaling Mode Register (FRM_PR44) (68C; C8C)............................................................................202

Table 169. CHI Common Control Register (FRM_PR45) (68D; C8D) ..................................................................203

Table 170. CHI Common Control Register (FRM_PR46) (68E; C8E) ..................................................................204

Table 171. CHI Transmit Control Register (FRM_PR47) (68F; C8F) ...................................................................205

Table 172. CHI Receive Control Register (FRM_PR48) (690; C90).....................................................................205

Table 173. CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52) ((691—694); (C91—C94)) ...206

Table 174. CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56) ((695—698); (C95—C98))....206

Table 175. CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60) ((699—69C); (C99—C9C)).....206

Table 176. CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64) ((69D—6A0); (C9D—CA0)).....207

Table 177. CHI Transmit Control Register (FRM_PR65) (6A1; CA1) ...................................................................207

Table 178. CHI Receive Control Register (FRM_PR66) (6A2; CA2)....................................................................207

Table 179. Auxiliary Pattern Generator Control Register (FRM_PR69) (6A5; CA5).............................................208

Table 180. Pattern Detector Control Register (FRM_PR70) (6A6; CA6)..............................................................209

Table 181. Transmit Signaling Registers: DS1 Format (FRM_TSR0—FRM_TSR23)

((6E0—6F7); (CE0—CF7)) .................................................................................................................210

Table 182. Transmit Signaling Registers: CEPT Format (FRM_TSR0—FRM_TSR31)

((6E0—6FF); (CE0—CFF)).................................................................................................................210

Table 183. FDL Register Set (800—80E); (E00—E0E)........................................................................................211

Table 184. FDL Configuration Control Register (FDL_PR0) (800; E00)...............................................................212

Table 185. FDL Control Register (FDL_PR1) (801; E01) .....................................................................................212

Table 186. FDL Interrupt Mask Control Register (FDL_PR2) (802; E02) .............................................................213

Table 187. FDL Transmitter Configuration Control Register (FDL_PR3) (803; E03)............................................214

Table 188. FDL Transmitter FIFO Register (FDL_PR4) (804; E04)......................................................................214

Table 189. FDL Transmitter Mask Register (FDL_PR5) (805; E05) .....................................................................214

Table 190. FDL Receiver Interrupt Level Control Register (FDL_PR6) (806; E06) ..............................................215

Agere Systems Inc.

11

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

List of Tables (continued)

Table

Page

Table 191. FDL Register FDL_PR7...................................................................................................................... 215

Table 192. FDL Receiver Match Character Register (FDL_PR8) (808; E08)....................................................... 215

Table 193. FDL Transparent Control Register (FDL_PR9) (809; E09) ................................................................ 216

Table 194. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (80A; E0A)............................................................ 216

Table 195. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (80B; E0B) ............................................ 217

Table 196. FDL Transmitter Status Register (FDL_SR1) (80C; E0C).................................................................. 218

Table 197. FDL Receiver Status Register (FDL_SR2) (80D; E0D)...................................................................... 218

Table 198. Receive ANSI FDL Status Register (FDL_SR3) (80E; E0E).............................................................. 218

Table 199. FDL Receiver FIFO Register (FDL_SR4) (807; E07)......................................................................... 218

Table 200. Global Register Set ............................................................................................................................ 219

Table 201. Line Interface Unit Register Set.......................................................................................................... 219

Table 202. Framer Unit Status Register Map....................................................................................................... 220

Table 203. Receive Signaling Registers Map....................................................................................................... 222

Table 204. Framer Unit Parameter Register Map ................................................................................................ 223

Table 205. Transmit Signaling Registers Map...................................................................................................... 226

Table 206. Facility Data Link Register Map.......................................................................................................... 227

Table 207. ESD Threshold Voltage...................................................................................................................... 228

Table 208. Logic Interface Characteristics (TA = –40 °C to 85 °C, VDD = 3.3 V ± 5%, VSS = 0).......................... 229

12

Agere Systems Inc.

Advance Data Sheet

May 2002

70 W, 1 GTH7z6,3238 VD,uNa-Cl hTa1n/Ene1l,3L.a3teVraSllyh-Doirftf-uHseadu,lETnehramncinemateonrt

T1/E1 Framer Features

Feature Descriptions

■ Framing formats:

■ Two independent T1/E1 channels each consisting of

a T1/E1 short-haul line interface and a T1/E1 framer

with HDLC formatting on the facility data link inter-

face.

— Compliant with T1 standards ANSI T1.231 (1997),

AT&T TR54016, AT&T TR62411 (1998).

— Unframed, transparent transmission in T1 and E1

formats.

— DS1 extended superframe (ESF).

— DS1 superframe (SF): D4; SLC-96; T1DM DDS;

T1DM DDS with FDL access.

■ Memory-mapped read and write registers.

■ Maskable interrupt events.

■ Hardware and software resets.

■ Onboard software-selectable pseudorandom test

pattern generator and detector for line performance

monitoring.

— DS1 independent transmit and receive framing

modes when using the ESF and D4 formats.

— Compliant with ITU CEPT framing recommenda-

tion:

■ 3-state outputs.

1. G.704 and G.706 basic frame format.

2. G.704 Section 2.3.3.4 and G.706 Section 4.2:

CRC-4 multiframe search algorithm.

3. G.706 Annex B: CRC-4 multiframe search

algorithm with 400 ms timer for interworking of

CRC-4 and non-CRC-4 equipment.

4. G.706 Section 4.3.2 Note 2: monitoring of 915

CRC-4 checksum errors for loss of frame

state.

■ Single 3 V ± 5% supply.

■ 5 V tolerant TTL inputs.

■ Low power consumption: 650 mW max.

T1/E1 Line Interface Features

■ Transmitter includes transmit encoder (B8ZS or

HDB3), pulse shaping, and line driver.

■ Framer line codes:

■ Five pulse equalization settings for template compli-

ance at DSX cross connect.

— DS1: alternate mark inversion (AMI); binary eight

zero code suppression (B8ZS); per-channel zero

code suppression; decoding bipolar violation mon-

itor; monitoring of eight or fifteen bit intervals with-

out positive or negative pulses error indication.

— DS1 independent transmit and receive path line

code formats when using AMI/ZCS and B8ZS cod-

ing.

— ITU-CEPT: AMI; high-density bipolar 3 (HDB3) en-

coding and decoding bipolar violation monitoring,

monitoring of four bit intervals without positive or

negative pulses error indication.

■ Receive includes equalization, digital clock and data

recovery (immune to false lock), and receive

decoder.

■ CEPT/E1 interference immunity as required by

G.703.

■ Transmit jitter <0.02 UI.

■ Receive generated jitter <0.05 UI.

■ Jitter attenuator selectable for use in transmit or

receive path. Jitter attenuation characteristics are

data pattern independent.

— Single-rail option.

■ For use with 100 Ω DS1 twisted-pair, 120 Ω E1

twisted-pair, and 75 Ω E1 coaxial cable.

■ Common transformer for transmit/receive.

■ Analog LOS alarm for signals less than –18 dB for

greater than 1 ms or 10-bit to 255-bit symbol periods

(selectable).

■ Digital LOS alarm for 100 zeros (DS1) or 255 zeros

(E1).

■ Diagnostic loopback modes.

■ Compliant with AT&T CB119(10/79);

ITU G.703(88), G.732(88), G.735-9(88),

G.823-4(3/93), I.431(3/93); ANSI T1.102(93), T1.

408(90); ETSI ETS-300-011(4/92),

ETS-300-166(8/93), ETS-300-233(5/94, 3/95),

TBR12(12/93, 1/96), TBR13(1/96); Telcordia Tech-

nologies^®TR-TSY-000009(5/86), TSY-000170(1/

93), GR-253-CORE(12/95), GR-499-CORE(12/95),

GR-820-CORE(11/94), GR-1244-CORE(6/95).

Agere Systems Inc.

13

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

— Independent transmit and receive frame synchro-

nization input signals.

— Independent transmit and receive system inter-

face clock.

Feature Descriptions (continued)

T1/E1 Framer Features (continued)

— 2.048 Mbits/s, 2.048 MHz concentration highway

■ Signaling:

interface (CHI) default mode.

— Optional 4.096 Mbits/s and 8.192 Mbits/s data

rates.

— Optional 4.096 MHz, 8.192 MHz, and 16.384 MHz

frequency system clock.

— Programmable clock edge for latching frame syn-

chronization signals.

— Programmable clock edge for latching transmit

and receive data.

— Programmable bit and byte offset.

— Programmable CHI master mode for the genera-

tion of the transmit CHI FS from internal logic with

timing derived from the receive line clock signal.

— DS1: extended superframe 2-state, 4-state, and

16-state per-channel robbed bit.

— DS1: D4 superframe 2-state and 4-state per-

channel robbed bit.

— DS1: SLC-96 superframe 2-state, 4-state, 9-state,

and 16-state per-channel robbed bit.

— DS1: channel-24 message-oriented signaling.

— ITU CEPT: channel associated signaling (CAS)

and T7230A mode common channel signaling

(CCS).

— ITU CEPT: international remote switching module

(IRMS).

— Transparent (all data channels).

■ Digital phase comparator for clock generation in the

receive and transmit paths.

■ Alarm reporting, performance monitoring, and main-

tenance:

— ANSI T1.403-1995, AT&T TR 54016, and ITU

G.826 standard error checking.

— Error and status counters:

Facility Data Link Features

1. Bipolar violations.

■ HDLC or transparent mode.

2. Errored frame alignment signals.

3. Errored CRC checksum block.

4. CEPT: received E bit = 0.

■ Automatic transmission of the ESF performance

report messages (PRM).

5. Errored, severely errored, and unavailable

seconds.

— Selectable errored event monitoring for errored

and severely errored seconds processing with

programmable thresholds for errored and severely

errored second monitoring.

■ Detection of the ESF PRM.

■ Detection of the ANSI ESF FDL bit-oriented codes.

■ 64-byte FIFO in both transmit and receive directions.

■ Programmable FIFO full- and empty-level interrupt.

■ SLC-96: FDL transmit and receive register access of

D bits.

— CEPT: Selectable automatic transmission of E bit

to the line.

— CEPT: Sa6 coded remote end CRC-4 error E bit =

0 events.

— Programmable automatic and on-demand alarm

transmission:

User-Programmable Microprocessor Inter-

face

1. Automatic transmission of remote frame alarm

to the line while in loss of frame alignment

state.

2. Automatic transmission of alarm indication

signal (AIS) to the system while in loss of

frame alignment state.

■ 33 MHz read and write access with no wait-states.

■ 12-bit address, 8-bit data interface.

■ Programmable Intel or Motorola interface modes.

■ Demultiplexed or multiplexed address and data bus.

■ Directly addressable internal registers.

■ No clock required.

— Multiple loopback modes.

— Optional automatic line and payload loopback ac-

tivate and deactivate modes.

— CEPT nailed-up connect loopback and CEPT

nailed-up broadcast transmission TS-X in TS-0

transmit mode.

— Selectable test patterns for line transmission.

— Detection of framed and unframed pseudorandom

and quasi-random test patterns.

— Programmable squelch and idle codes.

■ System interface:

— Autonomous transmit and receive system interfac-

es.

14

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Functional Description

RECEIVE

CHANNEL [1—2]

TCHICK[1—2]

TRANSMIT

CONCENTRATION

TCHIFS[1—2]

RTIP_RPD[1—2]

RECEIVE LINE

RECEIVE

HIGHWAY

RECEIVE

FRAMER

UNIT

TCHIDATA[1—2]

TCHIDATAB[1—2]

ELASTIC STORE

(2 FRAMES)

INTERFACE

UNIT

(RLIU)

(TCHI)

RRING_RND[1—2]

RFRMCK[1—2], RFRMDATA[1—2],

RFS[1—2], RSSFS[1—2],

RCRCMFS[1—2]

SYSCK[1—2]

RLCK[1—2]

RFDL[1—2], RFDLCK[1—2]

TCHICK

RECEIVE

RECEIVE FACILITY

DATA LINK MONITOR

(HDLC OR

TRANSPARENT

FRAMING)

RECEIVE

CHANNEL DIGITAL

PHASE DETECTOR

SIGNALING UNIT

(DS1: ROBBED-BIT

OR

RLCK

DIV-RLCK[1—2], DIV-TCHICK[1—2],

TCHICK-EPLL[1—2]

CEPT: TS16)

TRANSMIT

CHANNEL [1—2]

PLLCK[1—2]

TRANSMIT FACILITY

DATA LINK MONITOR

(HDLC OR

TRANSPARENT

FRAMING)

TRANSMIT

SIGNALING UNIT

(DS1: ROBBED-BIT

OR

TRANSMIT

CHANNEL DIGITAL

PHASE DETECTOR

RCHICK

DIV-PLLCK[1—2], DIV-RCHICK[1—2],

PLLCK-EPLL[1—2]

CEPT: TS16)

TFDL[1—2], TFDLCK[1—2]

XMIT FRAMER

TCLK

TRANSMIT

ELASTIC STORE

(2 FRAMES)

TTIP[1—2]

TRANSMIT LINE

INTERFACE

RECEIVE

CONCENTRATION

HIGHWAY

RCHICK[1—2]

RCHIFS[1—2]

RCHIDATA[1—2]

RCHDATAB[1—2]

UNIT

(XLIU)

TRANSMIT

FRAMER

UNIT

INTERFACE

TRING[1—2]

(RCHI)

TND[1—2],

TPD[1—2],

TLCK[1—2]

TFS[1—2], TSSFS[1—2],

TCRCMFS[1—2]

MPMODE

MPMUX

MICROPROCESSOR INTERFACE

A[11:0]

AD[7:0]

CS

ALE_AS

RD_R/W

WR_DS

RDY_DTACK INTERRUPT

MPCK

5-4512(F).cr.2

Figure 1. T7633 Block Diagram (One of Two Channels)

Agere Systems Inc.

15

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Functional Description (continued)

The Agere Systems Inc. T7633 Dual T1/E1 Terminator provides two complete T1/E1 interfaces each consisting of

a fully integrated, full-featured, short-haul line interface transceiver and a full-featured primary rate framer with an

HDLC formatter for facility data link access. The T7633 provides glueless interconnection from a T1 or E1 analog

line interface to devices interfacing to its concentration highway interface (CHI); for example, the T7270 Time Slot

Interchanger or T7115A Synchronous Protocol Data Formatter.

The line interface receiver performs clock and data recovery using a digital phase-locked loop, thereby avoiding

false lock conditions that are common when recovering sparse data patterns with an analog implementation. The

receiver’s equalization circuit guarantees a high level of interference immunity. The receive line unit monitors the

amplitude at the receive input for analog loss of signal detection and the pulse density of the receive signal for dig-

ital loss of signal detection. The receive line unit may be programmed to detect bipolar violations. The line interface

unit may be optionally bypassed.

The line interface unit’s transmit equalization is done with low-impedance output drivers that provide shaped wave-

forms to the transformer, guaranteeing template conformance. The transmitter will interface to the digital cross con-

nect (DSX) at lengths up to 655 feet for DS1 operation, and line impedances of 75 W or 120 W for CEPT-E1

operation. The transmit line unit monitors nonfunctional links due to faults at the primary of the transmit transformer

and periods of no data transmission.The line codes supported in the framer unit include AMI, T1 B8ZS, per-chan-

nel T1 zero code suppression and ITU-CEPT HDB3.

The T7633 supports T1 D4, T1DM, and SLC-96 superframes; extended superframe (ESF); ITU-CEPT-E1 basic

frame; ITU-CEPT-E1 time slot 0 multiframe; and time slot 16 multiframe formats.

The receive framer monitors the following alarms: loss of receive clock, loss of frame, alarm indication signal (AIS),

remote frame alarms, and remote multiframe alarms. These alarms are detected as defined by the appropriate

ANSI, AT&T, and ITU standards.

Performance monitoring as specified by AT&T, ANSI, and ITU is provided through counters monitoring bipolar vio-

lation, frame bit errors, CRC errors, CEPT E bit = 0 conditions, CEPT Sa6 codes, errored events, errored seconds,

bursty errored seconds, severely errored seconds, and unavailable seconds.

In-band loopback activation and deactivation codes can be transmitted to the line via the payload or the facility data

link. In-band loopback activation and deactivation codes in the payload or the facility data link are detected.

System, payload, and line loopbacks are programmable.

The default system interface is a 2.048 Mbits/s data and 2.048 MHz clock concentration highway interface (CHI)

serial bus. This CHI interface consists of independent transmit and receive paths. The CHI interface can be recon-

figured into several modes: a 2.048 Mbits/s data interface and 4.096 MHz clock interface, a 4.096 Mbits/s data

interface and 4.096 MHz clock interface, a 4.096 Mbits/s data interface and 8.192 MHz clock interface, a

8.192 Mbits/s data interface and 8.192 MHz clock interface, and 8.192 Mbits/s data interface and 16.384 MHz

clock interface.

The signaling formats supported are T1 per-channel robbed-bit signaling (RBS), channel-24 message-oriented sig-

naling (MOS), ITU-CEPT-E1 channel-associated signaling (CAS), common channel signaling (CCS) (Agere

T7230A mode), and international remote switching module (IRMS). In the T1, RBS mode voice and data channels

are programmable. The entire payload can be programmed into a data-only (no signaling channels) mode, i.e.,

transparent mode. Signaling access can be through the on-chip signaling registers or the system CHI port in the

associated signaling mode. Data and its associated signaling information can be accessed through the CHI in

either DS1 or CEPT-E1 modes.

Extraction and insertion of the facility data link in ESF, T1DM, SLC-96, or CEPT-E1 modes are provided through a

four-port serial interface or through a microprocessor-accessed, 64-byte FIFO either with HDLC formatting or

transparently. In the T7633’s SLC-96 or CEPT-E1 frame formats, a facility data link (FDL) is provided for FDL

access. The bit-oriented ESF data-link messages defined in ANSI T1.403-1995 are monitored by the receive

framer’s facility data link unit and are transmitted by the transmit framer FDL

The receive framer includes a two-frame elastic store buffer for jitter attenuations that performs control slips and

provides indication of slip directions.

16

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Functional Description (continued)

Accessing internal registers is done via the demultiplexed/multiplexed address and data bus microprocessor inter-

face using either the Intel 80188 (or 80X88) interface protocol with independent read and write signals or the

Motorola MC680X0 or M68360 interface protocol with address and data strobe signals.

The T7633 is manufactured using low-power CMOS technology and is packaged in an 144-pin thin quad flat pack

(TQFP) with 20 mils lead pitch.

RLCK

FRAMER

RPDE, RNDE, RLCKE

RPD, RND, RLCK

RTIP_RPD

JITTER

DIGITAL

CLOCK AND

DATA

RECOVERY

ATTENUATION

(OPTIONAL:

RECEIVE

ANALOG

FRONT END

BPV DECODER

AND MONITOR

RPD-LIU, RND-LIU,

RLCK-LIU

OR TRANSMIT)

RRING_RND

LINE INTERFACE UNIT BYPASS

RECEIVE T1/E1 FRAME ALIGNMENT MONITOR,

RE-ALIGNER, AND SYNC GENERATOR:

– SF: D4, SLC-96, DDS

– ESF

– CEPT: BASIC FRAME, CRC-4 MULTIFRAME,

& SIGNALING MULTIFRAME

RECEIVE PERFORMANCE MONITOR:

– BIPOLAR VIOLATION ERRORS

– T1/E1 CRC ERRORS

– ERRORED EVENTS

– ERRORED SECONDS

TCHIFS

TRANSMIT

CONCENTRATION

HIGHWAY

INTERFACE

(RATE ADAPTER)

RECEIVE

ELASTIC

STORE

– BURSTY ERRORED SECONDS

– SEVERELY ERRORED SECONDS

– UNAVAILABLE SECONDS

TCHIDATA

BUFFER

TCHIDATAB

(2 FRAMES)

RECEIVE ALARM MONITOR:

– ANALOG LOSS OF SIGNAL

– DIGITAL LOSS OF SIGNAL

– REMOTE FRAME ALARM

– CEPT REMOTE MULTIFRAME ALARM

– ALARM INDICATION SIGNAL (AIS)

– SLIPS

RECEIVE PATTERN MONITOR:

20

– QUASI-RANDOM: 2 – 1

TCHICK

RFRMCK

INTERNAL

SYSTEM CLOCK

RECEIVE SLIP

MONITOR

15

– PSEUDORANDOM: 2 – 1

– ANSI T1.403 BIT-ORIENTED AND ESF-FDL ACTIVATE

AND DEACTIVATE LINE LOOPBACK CODES

– CEPT AUXILIARY PATTERN (CEPT = 01)

– CEPT ACTIVATE AND DEACTIVATE LOOPBACK

CODES

RECEIVE SIGNALING EXTRACTER:

– DS1 ROBBED-BIT SIGNALING (RBS)

– CEPT CHANNEL ASSOCIATED AND

COMMON CHANNEL SIGNALING

– CONCENTRATION HIGHWAY ACCESS

– MICROPROCESSOR ACCESS

– CEPT Sa6 CODES

TEST PATTERN DETECTOR

– MARK (ALL1s)

20

– QRSS (QUASI-RANDOM: 2 – 1)

RECEIVE FDL HDLC EXTRACTER:

– 64-byte RECEIVE FIFO

– TRANSPARENT MODE (NO HDLC FRAMING)

– MICROPROCESSOR ACCESS

5

– 2 – 1

6

– 2 – 1 (53)

9

– 2 – 1 (511)

11

– 2 – 1 (2047)

15

– 2 – 1 (PSEUDORANDOM)

20

– 2 – 1

23

– 2 – 1

– 1:1 (ALTERNATING 10)

RECEIVE FACILITY DATA LINK EXTRACTER

AND MONITOR:

RFDLCK

RFDL

– SLC-96 FORMAT

– DDS ACCESS

– ANSI T1.403-1989 ESF FORMAT:

• BIT-ORIENTED MESSAGES

• MESSAGE-ORIENTED MESSAGES

5-4513(F).cr.2

Figure 2. T7633 Block Diagram: Receive Section (One of Two Channels)

Agere Systems Inc.

17

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Functional Description (continued)

TLCK, TND, TPD

÷ 16

SYSCK

LOSS

OF

TLCK

TRANSMIT DATA

MONITOR

ALL 1s SIGNAL

(AIS)

PULSE

JITTER

TTIP

EQUALIZER

AND

BPV

ENCODER

(OPTIONAL)

ATTENUATION

(OPTIONAL:

TRANSMIT OR

RECEIVE)

LINE FORMAT ENCODER

(AMI; B8ZS; HDB3)

WIDTH

CONTROLLER

TLCK, TND, TPD

TRING

PLLCK

TRANSMIT FACILITY DATA LINK

INSERTER:

TFDL

– SLC-96 FORMAT

TRANSMIT T1/E1 FRAME FORMATTER,

AND FRAME SYNC GENERATOR:

– DDS ACCESS

– ANSI T1.403-1989 ESF FORMAT:

• BIT-ORIENTED MESSAGES

• MESSAGE-ORIENTED MESSAGES

TRANSMIT CRC GENERATOR:

TFDLCK

– SF: D4, SLC-96, DDS; SIGNALING

SUPERFRAME

– ESF

– CEPT

TRANSMIT FDL HDLC INSERTER:

– CEPT: BASIC FRAME, CRC-4

MULTIFRAME, & SIGNALING MULTIFRAME

– TRANSPARENT FRAMING

– 64-byte TRANSMIT FIFO

– TRANSPARENT MODE

(NO HDLC FRAMING)

TRANSMIT ALARM MONITOR:

– LOSS OF SYSTEM BIFRAME ALIGNMENT

– SYSTEM ALARM INDICATION SIGNAL (AIS)

– MICROPROCESSOR ACCESS

TRANSMIT SIGNALING INSERTER:

AUTOMATIC AND ON-DEMAND COMMANDS:

– DS1 ROBBED-BIT SIGNALING (RBS)

– CEPT CHANNEL ASSOCIATED AND

COMMON-CHANNEL SIGNALING

– CONCENTRATION HIGHWAY ACCESS

– MICROPROCESSOR ACCESS

– AIS (LINE, SYSTEM, FDL)

– LOOPBACKS

– REMOTE FRAME ALARMS (RFA)

– CEPT E BIT = 0

– CEPT TS16 AIS

– CEPT TS16 RPA

RCHICK

RECEIVE CONCENTRATION

TEST PATTERN GENERATOR

RCHIFS

RCHIDATA

RCHIDATAB

TRANSMIT ELASTIC

STORE BUFFER

(2 FRAMES)

HIGHWAY INTERFACE

(RATE ADAPTER)

– MARK (ALL1s)

– QRSS

5

– 2 – 1

6

– 2 – 1 (53)

9

– 2 – 1 (511)

11

– 2 – 1 (2047)

15

– 2 – 1

20

– 2 – 1

23

– 2 – 1

– 1:1 (ALTERNATING 10)

5-4514(F).dr.2

Figure 3. T7633 Block Diagram: Transmit Section (One of Two Channels)

18

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Pin Information

The package type and pin assignment for the T7633 (Terminator-II) is illustrated in Figure 4.

1

108

107

106

105

104

103

102

101

100

99

VDD

GRND

LOFRMRLCK1

SYSCK1

2

WR_DS

JTAGTRST

JTAGTMS

JTAGTCK

JTAGTDI

JTAGTDO

MPCK

RDY_DTACK

INTERRUPT

A11

3

PLLCK-EPLL1

DIV-RCHICK1

DIV-PLLCK1

PLLCK1

4

5

6

7

8

GRNDA1

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

RRING_RND1

RTIP_RPD1

NC

98

97

A10

96

A9

VDDA1

95

A8

GRNDX1

TRING1

VDDX1

94

A7

93

A6

92

TTIP1

A5

91

GRNDX1

NC

A4

90

A3

89

GRNDX2

TTIP2

A2

88

A1

87

VDDX2

A0

86

TRING2

GRNDX2

VDDA2

AD7

85

AD6

84

AD5

83

NC

AD4

82

RTIP_RPD2

RRING_RND2

NC

AD3

81

AD2

80

AD1

79

GRNDA2

PLLCK2

DIV-PLLCK2

DIV-RCHICK2

PLLCK-EPLL2

SYSCK2

AD0

78

ALE_AS

CS

77

76

MPMUX

RD_R/W

MPMODE

GRND

75

74

73

GRND

5-4712(F).cr.2

Figure 4. Pin Assignment

Agere Systems Inc.

19

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Pin Information (continued)

Table 1 shows the list of T7633 pins and a functional description for each.

Table 1. Pin Descriptions

Symbol

Type*

Description

C1

C2

1, 36, 73, 109

GRND

P

Digital Ground Reference.

2

38

LOFRMRLCK

O

Loss of Framer Receive Line Clock. This pin is asserted high (1)

when the framer internal receive line clock does not toggle for a 250 µs

interval. Once asserted, this signal is deasserted on the first edge of the

framer internal receive line clock.

Terminator Mode: (FRAMER, pin 41/141 = 1) LOFRMRLCK is

asserted high when SYSCK clock, pin 3/35, is absent.

Framer Mode: (FRAMER, pin 41/141 = 0) LOFRMRLCK is asserted

high when RLCK clock, pin 47/135, is absent.

3

35

SYSCK

I^u

LIU System Clock. The clock signal used for clock and data recovery

and jitter attenuation. This clock must be ungapped and free of jitter.

For CKSEL = 1: a 16x clock (for DS1, SYSCK = 24.704 MHz ± 100

ppm and for CEPT, SYSCK = 32.768 MHz ± 100 ppm). For CKSEL = 0:

a 1x clock (for DS1, SYSCK = 1.544 MHz ± 100 ppm and for CEPT,

SYSCK = 2.048 MHz ± 100 ppm).

4

34

PLLCK-EPLL

O

Error Phase-Lock Loop Signal. The error signal proportional to the

phase difference between DIV-PLLCK and DIV-RCHICK as detected by

the internal PLL circuitry (refer to the Phase-Lock Loop Circuit section

on page 122).

5

6

7

33

32

31

DIV-RCHICK

DIV-PLLCK

PLLCK

O

I

Divided-Down RCHI Clock. 32 kHz or 8 kHz clock signal derived from

the RCHICK input signal.

Divided-Down PLLCK Clock. 32 kHz or 8 kHz clock signal derived

from the PLLCK input signal.

Transmit Framer Phase-Locked Line Interface Clock. Clock signal

used to time the transmit framer. This signal must be phase-locked to

RCHICK clock signal and be ungapped and free of jitter. For

FRM_PR45, bit 0 (HFLF) = 0, in DS1 PLLCK = 1.544 MHz and in CEPT

PLLCK = 2.048 MHz. For FRM_PR45, bit 0 (HFLF) = 1 in DS1 PLLCK =

6.176 MHz and in CEPT PLLCK = 8.192 MHz.

8

30

GRNDA

P

Analog Ground Reference.

No Connect.

9, 12, 19,

26, 29

NC

—

U

* I indicates an internal pull-up.

20

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Symbol

Type*

Description

C1

C2

10

28

RRING_RND

I

Receive Bipolar Ring. Negative bipolar input data from the receive

analog line isolation transformer.

Receive Negative Rail Data. Valid when the FRAMER pin is

strapped to 0 V. Nonreturn-to-zero (NRZ) serial data latched by the

rising edge of RLCK. Data rates: DS1-1.544 Mbits/s; CEPT-

2.048 Mbits/s. In the single-rail mode, when RND = 1 the receive

bipolar violation counter increments once for each rising edge of

RLCK.

11

13

27

25

RTIP_RPD

I

Receive Bipolar Tip. Positive bipolar input data from the receive

analog line isolation transformer.

Receive Positive Rail Data. Valid when the FRAMER pin is

strapped to 0 V. NRZ serial data latched by the rising edge of RLCK.

Data rates: DS1-1.544 Mbits/s; CEPT-2.048 Mbits/s. Optional

single-rail NRZ receive data latched by the rising edge of RLCK.

VDDA

GRNDX

TRING

P

O

Analog 3.3 V Power Supply. 3.3 V ± 5%.

14, 18 20, 24

Transmit Line Driver Ground Reference.

15

23

Transmit Bipolar Ring. Negative bipolar output data to the transmit

analog isolation transformer.

16

17

22

21

VDDX

P

Transmit Line Driver 3.3 V Power Supply. 3.3 V ± 5%.

TTIP

O

Transmit Bipolar Tip. Positive bipolar output data to the transmit

analog isolation transformer.

37, 72,

108, 144

VDD

P

3.3 V Power Supply. 3.3 V ± 5%.

143

39

LOPLLCK

O

Loss of PLLCK Clock. This pin is asserted high when the PLLCK

clock does not toggle for a 250 µs interval. This pin is deasserted

250 µs after PLLCK clock restarts toggling.

142

141

40

41

DS1/CEPT

FRAMER

I^u

DS1/CEPT. Strap to VDD to enable defaults for DS1 operation. Strap

to VSS to enable defaults for CEPT operation.

Framer Mode. Strap to VDD to enable integrated LIU and framer

operation. Strap to VSS to bypass the LIU section; the receive framer

is sourced directly from the RPD, RND, and RLCK pins while the

TPD, TND, and TLCK pins are driven by the transmit framer.

140

139

138

42

43

44

3-STATE

RESET^†

TPD

I^u

O

3-State (Active-Low). Asserting this pin low forces the channel

outputs into a high-impedance state. Asserting both 3-state pins low

forces all outputs into a high-impedance state.

Reset (Active-Low). Asserting this pin low resets the channel.

Asserting both RESET pins low resets the entire device including

the global registers.

Transmit Line Interface Positive-Rail Data. This signal is the

transmit framer positive NRZ output data. Data changes on the

rising edge of TLCK. In the single-rail mode, TPD = transmit framer

data.

U

*

I

indicates an internal pull-up.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

Agere Systems Inc.

21

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Symbol

Type*

Description

C1 C2

137 45

TND

O

Transmit Line Interface Negative-Rail Data. This signal is the

transmit framer negative NRZ output data. Data changes on the rising

edge of TLCK. In the single-rail mode, TND = 0.

136 46

135 47

134 49

133 48

132 50

TLCK

RLCK

O

I

Transmit Framer Line Interface Clock. Optional 1.544 MHz DS1 or

2.048 MHz output signal from the transmit framer. TND and TPD data

changes on the rising edge of TLCK.

Receive Framer Line Interface Clock. Valid when the FRAMER pin is

strapped to 0 V. This is the 1.544 MHz DS1 or 2.048 MHz input clock

signal used by the receive framer to latch RPD and RND data.

RFRMCK

CKSEL

O

I^u

O

Receive Framer Clock. Output receive framer clock signal used to

clock out the receive framer output signals. In normal operation, this is

the recovered receive line clock signal.

LIU System Clock Mode. This pin selects either a 16x rate clock for

SYSCK (CKSEL = 1) or a primary line rate clock for SYSCK

(CKSEL = 0).

RFRMDATA

Receive Framer Data. This signal is the decoded data input to the

receive elastic store. During loss of frame alignment, this signal is

forced to 1.

131 51

130 52

RFS

O

Receive Frame Sync. This active-high signal is the 8 kHz frame

synchronization pulse generated by the receive framer.

RSSFS

Receive Framer Signaling Superframe Sync. This active-high signal

is the CEPT signaling superframe (multiframe) synchronization pulse

in the receive framer.

129 53

128 54

127 55

RCRCMFS

RFDLCK

RFDL

O

Receive Framer CRC-4 Multiframe Sync. This active-high signal is

the CEPT CRC-4 multiframe synchronization pulse in the receive

framer.

Receive Facility Data Link Clock. In DS1-DDS with data link access,

this is an 8 kHz clock signal. Otherwise, this is a 4 kHz clock signal.

The receive data link bit changes on the falling edge of RFDLCK.

Receive Facility Data Link. Serial output facility data link bit stream

extracted from the receive line data stream by the receive framer. In

DS1-DDS with data link access, this is an 8 kbits/s signal; otherwise,

4 kbits/s. In the CEPT frame format, RFDL can be programmed to one

of the Sa bits of the NOT FAS frame TS0. During loss of frame

alignment, this signal is 1.

126 56

125 57

TCHICK

TCHIFS

I

Transmit Concentration Highway Interface (CHI) Clock.

2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz. This clock must

be free of jitter.

I/O

Transmit CHI Frame Sync. Transmit CHI 8 kHz input frame

synchronization pulse phase-locked to TCHICK. In the CHI master

mode, the transmit CHI generates the 8 kHz frame sync to control the

CHI.

U

*

I

indicates an internal pull-up.

22

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Symbol

Type*

Description

C1 C2

124 58

TCHIDATA

O

Transmit CHI Data. Serial output system data at 2.048 Mbits/s,

4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high-

impedance state for all inactive time slots.

123 59

122 60

TCHIDATAB

DIV-RLCK

O

Transmit CHI Data B. Serial output system data at 2.048 Mbits/s,

4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high-

impedance state for all inactive time slots.

Divided-Down Receive Line Clock. 8 kHz clock signal derived from

the recovered receive line interface unit clock or the RLCK input

signal.

121 61

120 62

DIV-TCHICK

O

Divided-Down CHI Clock. 8 kHz clock signal derived from the

transmit CHI CLOCK input signal.

TCHICK-EPLL

Error Phase-Lock Loop Signal. The error signal proportional to the

phase difference between DIV-TCHICK and DIV-RLCK as detected

from the internal PLL circuitry (refer to the Phase-Lock Loop Circuit

section on page 122).

119 63

118 64

TFS

O

Transmit Framer Frame Sync. This signal is the 8 kHz frame

synchronization pulse in the transmit framer. This signal is active-high.

TSSFS

Transmit Framer Signaling Superframe Sync. This signal is the

CEPT signaling superframe (multiframe) synchronization pulse in the

transmit framer. This signal is active-high.

117 65

116 66

115 67

TCRCMFS

TFDLCK

TFDL

O

I

Transmit Framer CRC-4 Multiframe Sync. This signal is the CEPT

CRC-4 submultiframe synchronization pulse in the transmit framer.

This signal is active-high.

Transmit Facility Data Link Clock. In DS1-DDS with data link

access, this is an 8 kHz clock signal; otherwise, 4 kHz. The transmit

frame latches data link bits on the falling edge of TFDLCK.

Transmit Facility Data Link. Optional serial input facility data link bit

stream inserted into the transmit line data stream by the transmit

framer. In DS1-DDS with data link access, this is an 8 kbits/s signal;

otherwise, 4 kbits/s. In the CEPT frame format, TFDL can be

programmed to one of the Sa bits of the NOT-FAS frame time slot 0.

114 68

RCHICK

I

Receive Concentration Highway Interface (CHI) Clock. 2.048 MHz,

4.096 MHz, 8.192 MHz, or 16.384 MHz. This clock must be free of

jitter.

113 69

112 70

RCHIFS

RCHIDATA

RCHIDATAB

I

Receive CHI Frame Sync. Receive CHI 8 kHz frame synchronization

pulse phase-locked to RCHICK.

Receive CHI Data. Serial input system data at 2.048 Mbits/s,

4.096 Mbits/s, or 8.192 Mbits/s.

111 71

Receive CHI Data B. Serial input system data at 2.048 Mbits/s,

4.096 Mbits/s, or 8.192 Mbits/s.

U

*

I

indicates an internal pull-up.

Agere Systems Inc.

23

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Symbol

Type*

Description

74

MPMODE

I^u

MPMODE. Strap to ground to enable the Motorola 68360

microprocessor protocol (MODE1 or MODE2). Strapped to VDD to

enable the Intel 80X86/88 microprocessor protocol (MODE3 or

MODE4).

75

RD_R/W

I

Read (Active-Low). In the Intel interface mode, the T7633 drives

the data bus with the contents of the addressed register while RD

is low.

Read/Write. In the Motorola interface mode, this signal is asserted

high for read accesses; this pin is asserted low for write accesses.

76

77

MPMUX

CS^‡

I^u

MPMUX. Strap to VSS to enable the demultiplexed address and

data bus mode. Strap to VDD to enable the multiplexed address

and data bus mode.

I

Chip Select (Active-Low). In the Intel interface mode, this pin

must be asserted low to initiate a read or write access and kept low

for the duration of the access; asserting CS low forces RDY out of

its high-impedance state into a 0 state.

78

ALE_AS

I

Address Latch Enable/Address Strobe. In the address/data bus

multiplex mode of the microprocessor, when this signal transitions

from high to low, the state of the address bus is latched into

internal address registers. In the demultiplexed address mode, the

address is transparent through the T7633 and is latched on the

rising edge of the ALE_AS signal. Alternatively, in the demultiplex

mode, this pin may be connected to ground to make the address

transparent through the T7633.

79—86

AD0—AD7

I/O

Microprocessor Address_Data Bus. Multiplexed address and

bidirectional data bus used for read and write accesses. High-

impedance output.

87—98

99

A0—A11

I

Microprocessor Address Bus. Address bus used to access the

internal registers.

INTERRUPT

O

Interrupt. INTERRUPT is asserted indicating an internal interrupt

condition/event has been generated. This pin is deasserted after

the generating register is read. As a default, interrupt assertion is a

logic one. Interrupt events/conditions are maskable through the

control registers. Interrupt assertion may be inverted (active-low)

or programmed for wired OR or AND operation by setting register

GREG 4 bit 4 and bit 6.

U

*

I

indicates an internal pull-up.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

‡ Asserting this pin low will initially force RDY to a low state.

24

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Symbol

Type*

Description

100

RDY_DTACK

O

Ready. In the Intel interface mode, this pin is asserted high to

indicate the completion of a read or write access; this pin is forced

into a high-impedance state while CS is high.

Data Transfer Acknowledge (Active-Low). In the Motorola

interface mode, DTACK is asserted low to indicate the completion

of a read or write access; DTACK is 1 otherwise.

101

102

103

104

105

MPCK

I^u

O

I^u

Microprocessor Clock. Microprocessor clock used in the Intel

mode to generate the READY signal.

JTAGTDO

JTAGTDI

JTAGTCK

JTAGTMS

JTAG Data Output. Serial output data sampled on the falling edge

of TCK from the boundary-scan test circuitry.

JTAG Data Input. Serial input data sampled on the rising edge of

TCK for the boundary-scan test circuitry.

JTAG Clock Input. TCK provides the clock for the boundary-scan

test logic.

JTAG Mode Select (Active-Low). The signal values received at

TMS are sampled on the rising edge of TCK and decoded by the

boundary-scan TAP controller to control boundary-scan test opera-

tions.

106

107

JTAGTRST

WR_DS

I^d

I

JTAG Reset Input (Active-Low). Assert this pin low to asynchro-

nously initialize/reset the boundary-scan test logic.

Write (Active-Low). In the Intel mode, the value present on the

data bus is latched into the addressed register on the positive edge

of the signal applied to WR.

Data Strobe (Active-Low). In the Motorola mode, when AS is low

and R/W is low (write), the value present on the data bus is latched

into the addressed register on the positive edge of the signal

applied to DS; when AS is low and R/W is high (read), the T7633

drives the data bus with the contents of the addressed register

while DS is low.

110

SECOND

O

Second Pulse. A one second timer with an active-high pulse. The

duration of the pulse is one RLCK cycle. The receive line clock of

FRAMER1 (RLCK1) is the default clock source for the internal sec-

ond pulse timer. When LOFRMCLK1 is active, the receive line

clock of FRAMER2 is used as the clock signal source for the inter-

nal second pulse timer. The second pulse is used for performance

monitoring.

U

d

* I indicates an internal pull-up; I indicates an internal pull-down.

Agere Systems Inc.

25

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Block Diagram

The T7633 LIU diagram is shown in Figure 5. Only a single transceiver is shown here for illustration purposes.

RDLOS

RALOS

RND_BPV

DECODER

JITTER

ATTENUATOR

RPD

CLOCK AND

DATA

RECOVERY

RTIP

EQUALIZER

SLICERS

TO RECEIVE

FRAMER

RRING

(RECEIVE PATH)

RLCK

FLLOOP

(DURING LIU AIS)

INTSYSCK*

FLLOOP

(NO LIU AIS)

TDM

DLLOOP

RLOOP

(CLOCK)

LOTC

PULSE-

WIDTH

CONTROLLER

TLCK-LIU

TND-LIU

JITTER

TTIP

ATTENUATOR

TRANSMIT

DRIVER

PULSE

EQUALIZER

(TRANSMIT PATH)

(DATA)

ENCODER

FROM TRANSMIT

TRING

TPD-LIU

FRAMER

ALARM

INDICATION

SIGNAL (AIS)

LOSS

OF

TLCK

16x

CLOCK

MULTIPLIER

DIVIDE BY 16

INTSYSCK*

LOSS OF

SYSCK

MONITOR

SYSCK

CKSEL

5-4556(F).cr.4

* INTSYSCK always runs at 16 times the primary line rate. If CKSEL = 1, INTSYSCK is equal to SYSCK. If CKSEL = 0, INTSYSCK is sourced

from the internal 16x clock multiplier.

Figure 5. Block Diagram of Line Interface Unit: Single Channel

Line Interface Unit: Receive

Data Recovery

The receive line-interface unit (RLIU) transmission format is bipolar alternate mark inversion (AMI). The RLIU

accepts input data with a data rate tolerance of ±130 ppm (DS1) or ±80 ppm (E1). The RLIU first restores the

incoming data and detects analog loss of signal. Subsequent processing is optional and depends on the program-

mable LIU configuration established within the microprocessor interface registers. The RLIU utilizes an equalizer to

operate on line length with typically up to 15 dB of loss at 772 kHz (DS1) or 13 dB loss at 1.024 MHz (E1). The sig-

nal is then peak-detected and sliced to produce digital representations of the data. Selectable digital loss of signal,

jitter attenuation, and data decoding are performed.

The clock is recovered by a digital phase-locked loop that uses SYSCK as a reference to lock to the data rate com-

ponent. Because the reference clock is a multiple of the received data rate, the internal RLCK (RLCK-LIU) output

will always be a valid DS1/CEPT clock that eliminates false lock conditions. During periods with no receive input

signal from the line, the free-run frequency of RLCK-LIU is defined to be either SYSCK/16 or SYSCK depending on

the state of CKSEL. RLCK-LIU is always active with a duty cycle centered at 50%, deviating by no more than ±5%.

Valid data is recovered within the first few bit periods after the application of SYSCK.

26

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Receive (continued)

Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator

The RLIU is designed to accommodate large amounts of input jitter. The RLIU’s jitter performance exceeds the

requirements shown in the RLIU Specification Table 4 and Table 5. Typical receiver performance without the jitter

attenuator in the path is shown in Figures 6—9. Typical receiver performance with the jitter attenuator is given in

Figures 12—15. Jitter transfer is independent of input ones density on the line interface.

Receive Line Interface Configuration Modes

Zero Substitution Decoding (CODE)

When single-rail operation is selected with DUAL = 0 (register LIU_REG3, bit 3), the LIU B8ZS/HDB3 zero substi-

tution decoding can be selected via the CODE bit (register LIU_REG3, bit 2). If CODE = 1, the B8ZS/HDB3 decod-

ing function is enabled in the receive path. Decoded receive data appears at the internal LIU-to-framer RPD

interface (RPD-LIU). Code violations, including BPVs, appear at the internal LIU-to-framer RND_BPV interface

(RND-LIU). If CODE = 0, the receive data is passed unaltered to RPD-LIU, and all bipolar violations (such as two

consecutive 1s if the same polarity) appear at RND-LIU. The default configuration is single-rail, DUAL = 0, with the

decoding active, CODE = 1.

If DUAL = 0, the receive framer must be programmed to the single-rail mode and the receive framer’s interval LIU-

to-framer RPD input will be the receive data port. If DUAL = 0, then the receive framer’s bipolar violation count will

increment by 1 whenever the internal LIU-to-framer RND_BPV signal is one. The bipolar violation count is incre-

mented on the rising edge of the receive framer’s RLCK clock signal.

Agere Systems Inc.

27

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Receive (continued)

Receive Line Interface Configuration Modes (continued)

Receive Line Interface Unit (RLIU) Alarms

Analog Loss of Signal (ALOS) Alarm. An analog signal detector monitors the receive signal amplitude and

reports its status in the analog loss of signal alarm bit ALOS (register LIU_REG0, bit 0). Analog loss of signal is

indicated (ALOS = 1) if the amplitude at the RRING and RTIP inputs drops below a voltage approximately 18 dB

below the nominal signal amplitude. The ALOS alarm condition will clear when the receive signal amplitude returns

to a level greater than 14 dB below normal. The ALOS alarm status bit will latch the alarm and remain set until

being cleared by a read (clear on read). Upon the transition from ALOS = 0 to ALOS = 1, a microprocessor inter-

rupt will be generated if the ALOS interrupt enable bit ALOSIE (register LIU_REG1, bit 0) is set. The reset default is

ALOSIE = 0.

The ALOS circuitry provides 4 dB of hysteresis to prevent alarm chattering. The time required to detect ALOS is

selectable. When ALTIMER = 0 (register LIU_REG4, bit 0), ALOS is declared between 1 ms and 2.6 ms after los-

ing signal as required by I.431(3/93) and ETS-300-233 (5/94). If ALTIMER = 1, ALOS is declared between 10-bit

and 255-bit symbol periods after losing signal as required by G.775 (11/95). The timing is derived from the SYSCK

clock. The detection time is independent of signal amplitude before the loss condition occurs. Normally, ALTIMER

= 1 would be used only in E1 mode since no T1/DS1 standards require this mode. In T1/DS1 mode, this bit should

normally be zero. The reset default is ALTIMER = 0.

The behavior of the receiver RLIU outputs under ALOS conditions is dependent on the loss shutdown (LOSSD)

control bit (register LIU_REG3, bit 4) in conjunction with the receive alarm indication select (RCVAIS) control bit

(register LIU_REG4, bit 1) as described in the Loss Shutdown (LOSSD) and Receiver AIS (RCVAIS) section on

page 29.

Digital Loss of Signal (DLOS) Alarm. A digital loss of signal (DLOS) detector guarantees the received signal

quality as defined in the appropriate ANSI, Telcordia Technologies, and ITU standards. The digital loss of signal

alarm is reported in the RLIU alarm status register (register LIU_REG0, bit 1). For DS1 operation, digital loss of sig-

nal (DLOS = 1) is indicated if 100 or more consecutive 0s occur in the receive data stream. The DLOS condition is

deactivated when the average ones density of at least 12.5% is received in 100 contiguous pulse positions. The

DLOS alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). The

LOSSTD control bit (register LIU_REG2, bit 2) selects the conformance protocols for the DLOS alarm indication

per Table 2. Setting LOSSTD = 1 adds an additional constraint that there are less than 15 consecutive zeros in the

DS1 data stream before DLOS is deactivated. The reset default is LOSSTD = 0.

For E1 operation, DLOS is indicated when 255 or more consecutive 0s occur in the receive data stream. The

DLOS indication is deactivated when the average ones density of at least 12.5% is received in 255 contiguous

pulse positions. LOSSTD has no effect in E1 mode.

Upon the transition from DLOS = 0 to DLOS = 1, a microprocessor interrupt will be generated if the DLOS interrupt

enable bit DLOSIE (register LIU_REG1, bit 1) is set. The reset default is DLOSIE = 0.

The DLOS alarm may occur when FLLOOP is activated (See “Line Interface Unit: Loopbacks” on page 44.) due to

the abrupt change in signal level at the receiver input. Setting the FLLOOP alarm prevention PFLALM = 1 (register

LIU_REG 4, bit 2) prevents the DLOS alarm from occurring when FLLOOP is activated by quickly resetting the

receiver’s internal peak detector. It will not prevent the DLOS alarm during the FLLOOP period but only avoids the

alarm created by the signal amplitude transient. The reset default is PFLALM = 0.

Table 2. Digital Loss of Signal Standard Select

LOSSTD

DS1 Mode

CEPT Mode

0

1

T1M1.3/93-005, ITU-T G.775

TR-TSY-000009

ITU-T G.775

28

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Receive (continued)

Receive Line Interface Configuration Modes (continued)

Loss Shutdown (LOSSD) and Receiver AIS (RCVAIS). The loss shutdown (LOSSD) control bit (register

LIU_REG3, bit 4) acts in conjunction with the receive alarm indication select (RCVAIS) control bit (register

LIU_REG4, bit 1) to place the digital RLIU signals (RPD-LIU, RND-LIU, RLCK-LIU) in a predetermined state when

a digital loss of signal (DLOS) or analog loss of signal (ALOS) alarm occurs.

If LOSSD = 0 and RCVAIS = 0, the RND-LIU, RPD-LIU, and RLCK-LIU signals will be unaffected by the DLOS

alarm condition. However, when an ALOS alarm condition is indicated in the LIU alarm status register (register

LIU_REG0, bit 0), the RPD-LIU and RND-LIU signals are forced to 0 state and the RLCK-LIU free runs (at the

INTSYSCK/16 frequency).

If LOSSD = 1, RCVAIS = 0, and a DLOS alarm condition is indicated in the LIU alarm status register (register

LIU_REG0, bit 1) or an ALOS alarm condition is indicated, the RPD-LIU and RND-LIU signals are forced to the

0 state and the RLCK-LIU free runs (at the INTSYSCK/16 frequency).

If LOSSD = 0, RCVAIS = 1, and a DLOS or an ALOS alarm condition is indicated in the LIU alarm status register

(register LIU_REG0, bits 0 or 1), the RPD-LIU and RND-LIU signals will present an alarm indication signal (AIS, all

ones) based on the free-running INTSYSCK/16 frequency.

If LOSSD = 1, RCVAIS = 1, and a DLOS or an ALOS alarm condition is indicated in LIU alarm status register (reg-

ister LIU_REG0, bits 0 or 1), the RPD-LIU and RND-LIU signals are forced to 0 state and the RLCK-LIU free runs

at the INTSYSCK/16 frequency.

The RND-LIU, RPD-LIU, and RLCK-LIU signals will be remain unaffected if any loopback (FLLOOP, RLOOP,

DLLOOP) is activated independent of LOSSD and RCVAIS settings.

The default reset state is LOSSD = 0 and RCVAIS = 0.

The LOSSD and RCVAIS behavior is summarized in Table 3.

Table 3. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes)

LOSSD

RCVAIS

ALARM

ALOS

DLOS

ALOS

DLOS

ALOS

DLOS

ALOS

DLOS

RPD/RND

RLCK

Free Runs

Recovered Clock

Free Runs

0

1

0

1

0

1

0

Normal Data

0

AIS (all ones)

0

LIU Receiver Bipolar Violation (BPV) Alarm. The receiver LIU bipolar violation (BPV) alarm is used only in the

single-rail mode. When B8ZS(DS1)/HDB3(E1) coding is not used (i.e., CODE = 0), any violations in the receive

data (such as two or more consecutive 1s on a rail) are indicated on the RND-LIU output. When B8ZS(DS1)/

HDB3(E1) coding is used (i.e., CODE = 1), the HDB3/B8ZS code violations, including BPVs, are reflected on the

RND-LIU output.

Agere Systems Inc.

29

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Receive (continued)

T1/DS1 LIU Receiver Specifications

During T1/DS1 operation, the LIU receiver will perform as specified in Table 4.

Table 4. DS1 LIU Receiver Specifications

Parameter

Analog Loss of Signal:

Min

Typ

Max

Unit

Spec

Threshold to Assert

Threshold to Clear

Hysteresis

23

17.5

—

18

14

4

16.5

12.5

—

dB¹

dB

I.431

—

Time to Assert (ALTIMER = 0)

Receiver Sensitivity²

1.0

2.6

ms

I.431

11

15

—

dB

—

Jitter Transfer:

3 dB Bandwidth

Peaking

—

3.84

—

0.1

kHz

dB

Figure 7 on page 32

Figure 13 on page 42

Generated Jitter

—

0.04

0.05

—

UIpk-pk

TR-TSY-000499,

ITU-T G.824

Jitter Accommodation

—

Figure 6 on page 32

Figure 12 on page 42

Return Loss:³

51 kHz to 102 kHz

102 kHz to 1.544 MHz

1.544 MHz to 2.316 MHz

14

20

16

—

dB

—

Digital Loss of Signal:

ITU-T G.775,

T1M1.3/93-005

Flag Asserted When Consecutive Bit

Positions Contain

100

—

zeros

Flag Deasserted when

—

Data Density Is

and

12.5

%ones

Maximum Consecutive Zeros Are

—

15

99

zeros

TR-TRY-000009

ITU-T G.775, T1M1.3/

93-005

1.Below the nominal pulse amplitude of 3.0 V with the line interface circuitry specified in the Line Interface Unit: Line Interface Networks on

page 48.

2.Cable loss at 772 kHz.

3.Using Agere transformer 2795L and components listed in Table 13.

30

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Receive (continued)

CEPT LIU Receiver Specifications

During E1 operation, the LIU receiver will perform as specified in Table 5.

Table 5. CEPT LIU Receiver Specifications

Parameter

Analog Loss of Signal:

Threshold to Assert

Threshold to Clear

Hysteresis

Min

Typ

Max

Unit

Spec

23

17.5

—

18

14

4

16.5

12.5

—

dB¹

dB

I.431, ETSI 300 233

—

Time to Assert (ALTIMER = 0)

Time to Assert (ALTIMER = 1)

1.0

10

—

2.6

255

ms

UI

I.431, ETSI 300 233

G.775

Receiver Sensitivity²

11

9

13.5

12

—

dB

—

Interference Immunity:³

ITU-T G.703

Jitter Transfer:

3 dB Bandwidth, Single-pole Roll Off

Peaking

—

5.1

—

0.5

kHz

dB

Figure 9 on page 33

Figure 15 on page 43

Generated Jitter

—

0.04

—

0.05

—

UIpk-pk

ITU-T G.823, I.431

Jitter Accommodation

—

Figure 8 on page 33

Figure 14 on page 43

Return Loss:⁴

51 kHz to 102 kHz

102 kHz to 2.048 MHz

2.048 MHz to 3.072 MHz

ITU-T G.703

14

20

16

—

dB

Digital Loss of Signal:

—

Flag Asserted When Consecutive Bit

Positions Contain

255

—

zeros

Flag Deasserted When Data Density Is

(LOSSTD = 1)

12.5

%ones

ITU-T G.775

1.Below the nominal pulse amplitude of 3.0 V for 120 Ω and 2.37 V for 75 Ω applications with the line circuitry specified in the Line Interface

Unit: Line Interface Networks on page 48.

2.Cable loss at 1.024 MHz.

3.Amount of cable loss for which the receiver will operate error-free in the presence of a –18 dB interference signal summing with the intended

signal source.

4.Using Agere transformer 2795K or 2795J and components listed in Table 13.

Agere Systems Inc.

31

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Receive (continued)

100 UI

TYPICAL

(SUBJECT TO DEVICE CHARACTERIZATION)

28 UI

T1.408/I.431(DS1)/G.824(DS1)

10 UI

GR-499-CORE

(NON-SONET CAT II INTERFACES)

I.431(DS1), G.824(DS1)

1.0 UI

TR-TSY-000009 (DS1, MUXES)

GR-499/1244-CORE (CAT I INTERFACES)

0.1 UI

100 k

1

10

100

1 k

10 k

FREQUENCY (Hz)

5-5260(F)r.4

Figure 6. T1/DS1 Receiver Jitter Accommodation Without Jitter Attenuator

GR-499-CORE

(NON-SONET CAT II TO CAT II)

0

TYPICAL

(SUBJECT TO DEVICE CHARACTERIZATION)

10

20

30

40

50

60

1

10

100

1k

10 k

100 k

FREQUENCY (Hz)

5-5261(F)

Figure 7. T1/DS1 Receiver Jitter Transfer Without Jitter Attenuator

32

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Receive (continued)

100 UI

G.823

37 UI

I.431(CEPT)/ETS-300-011

20.5 UI

12e-6 Hz

TYPICAL

(SUBJECT TO DEVICE CHARACTERIZATION)

10 UI

G.823,ETSI-300-011A1

I.431(CEPT)/ETS-300-011

1.0 UI

0.1 UI

100 k

1

10

100

1 k

10 k

FREQUENCY (Hz)

5-5262(F)r.3

Figure 8. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator

G.735-9 W/O JITTER REDUCER

0

10

TYPICAL

(SUBJECT TO DEVICE CHARACTERIZATION)

20

30

40

50

60

1

10

100

1 k

10 k

100 k

FREQUENCY (HZ)

5-5263(F)

Figure 9. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator

Agere Systems Inc.

33

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Transmit

Output Pulse Generation

The line interface transmitter accepts a line rate clock and NRZ data in single-rail mode (DUAL = 0) or positive and

negative NRZ data in dual-rail mode (DUAL = 1) from the transmit framer unit or, optionally, the system interface.

The line interface transmitter converts this data to a balanced bipolar signal (AMI format) with optional B8ZS(DS1)/

HDB3(E1) encoding and optional jitter attenuation. Low-impedance output drivers produce the line transmit pulses.

Positive 1s are output as positive pulses on TTIP, and negative 1s are output as positive pulses on TRING. Binary

0s are converted to null pulses.

In DSX-1 applications, transmit pulse shaping is controlled by the on-chip pulse-width controller and pulse equal-

izer. The pulse-width controller produces high-speed timing signals to accurately control the transmit pulse widths.

This eliminates the need for a tightly controlled transmit clock duty cycle that is usually required in discrete imple-

mentations. The pulse equalizer controls the amplitudes and shapes of the pulses. Different pulse equalizations

are selected through settings of EQ2, EQ1, and EQ0 bits (register LIU_REG6, bits 0 to 2) as described in Table 6,

Transmit Line Interface Short-Haul Equalizer/Rate Control, below.

The reset default state of the equalization bits EQ2, EQ1, and EQ0 can be predetermined by setting the

DS1_CEPT pin. The default transmit equalization is EQ2, EQ1, and EQ0 = 000 (0 dB T1/DS1) when DS1_CEPT =

1; EQ2, EQ1, and EQ0 = 110 (CEPT 120 Ω/75 Ω) when DS1_CEPT = 0. This feature aids in transmitting AIS at the

correct rate upon completion of hardware reset; See “LIU Transmitter Alarm Indication Signal Generator (XLAIS)”

on page 35.

Table 6. Transmit Line Interface Short-Haul Equalizer/Rate Control

Short-Haul Applications

EQ2

EQ1

EQ0 Service

Clock Rate

Transmitter Equalization^1,2

Maximum

Cable Loss

to DSX³

Feet

Meters

dB

0

1

0

1

0

1

0

1

0 to 131

0 to 40

40 to 80

0.6

1.2

1.8

2.4

3.0

131 to 262

262 to 393

393 to 524

524 to 655

0

1

0

1

0

1

DSX-1

CEPT⁴

1.544 MHz

2.048 MHz

80 to 120

120 to 160

160 to 200

75 Ω (Option 2)

—

120 Ω or 75 Ω (Option 1)

Not Used

1.In DS1 mode, the distance to the DSX for 22-Gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable

types. In CEPT mode, equalization is specified for coaxial or twisted-pair cable.

2.Reset default state is EQ2, EQ1, and EQ0 = 000 when pin DS1_CEPT = 1 and EQ2, EQ1, and EQ0 = 110 when pin DS1_CEPT = 0.

3.Loss measured at 772 kHz.

4.In 75 Ω applications, Option 1 is recommended over Option 2 for lower LIU power dissipation. Option 2 allows for the use of the same trans-

former as in CEPT 120 Ω applications (see the Line Interface Unit: Line Interface Networks on page 48).

34

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Transmit (continued)

LIU Transmitter Configuration Modes

LIU Transmitter Zero Substitution Encoding (CODE)

LIU transmitter zero substitution (B8ZS/HDB3) encoding can be activated only in the single-rail (DUAL = 0) sys-

tem/framer interface mode. It is activated by setting CODE = 1 (register LIU_REG3, bit 2). Data transmitted from

the framer interface on TPD-LIU will be B8ZS/HDB3 encoded before appearing on TTIP and TRING at the line

interface.

LIU Transmitter Alarm Indication Signal Generator (XLAIS)

When the transmit alarm indication signal control is set (XLAIS = 1) for a given channel (see register LIU_REG5,

bit 1), a continuous stream of bipolar 1s is transmitted to the line interface. The internal LIU to framer TPD interface

(TPD) and internal LIU to framer TND interface (TND) signals are ignored during this mode. The XLAIS control is

ignored when a remote loopback (RLOOP) is selected using loopback control bits LOOPA and LOOPB (register

LIU_REG5, bits 2 to 3). The clock source used for the alarm indication signal is TLCK if present or INTSYSCK if

TLCK is not present. The clock tolerance must meet the nominal transmission specifications of 1.544 MHz ±

32 ppm for DS1 (T1), or 2.048 MHz ± 50 ppm CEPT (E1).

The XLAIS bit is defaulted to 1 on hardware reset allowing the transmitter to send AIS as soon as clocks are avail-

able, without needing to write the LIU registers¹. Because the transmit equalization bits are needed to determine

the correct system rate (DS1/E1), the reset default state of the equalization bits EQ2, EQ1, EQ0 (register

LIU_REG6, bits 0—2) can be predetermined by setting the DS1_CEPT pin (see Table 6 on page 34). The default

transmit equalization is EQ2, EQ1, and EQ0 = 000 (0 dB T1/DS1) when DS1_CEPT = 1, and EQ2, EQ1, and EQ0

= 110 (CEPT 120 Ω/75 Ω) when DS1_CEPT = 0. The transmit equalization bits can be subsequently programmed

to any state by writing the LIU register regardless of the state of the DS1_CEPT pin. The DS1_CEPT pin is only

used to determine the reset default state of the equalization bits.

1. If TLCK from the framer is present, automatic transmission of AIS upon reset will occur only if the CHI common control register FRM_PR45

bit 0 = 0, the default, or low-frequency PLLCK mode. In this case, PLLCK will be equal to the line transmit rate, either 1.544 MHz for DS1 or

2.048 MHz for CEPT.

LIU Transmitter Alarms

Loss of LIU Transmit Clock (LOTC) Alarm

A loss of LIU transmit clock alarm (LOTC = 1, see register LIU_REG0, bit 3) is indicated if any of the clocks used in

the LIU transmitter paths are absent. This includes loss of TLCK-LIU input, loss of RLCK-LIU during remote loop-

back, loss of jitter attenuator output clock (when enabled in transmit path), or the internal loss of clock from the

pulse-width controller. For all of these conditions, the LIU transmitter timing clock is lost and no data can be driven

onto the line. Output drivers TTIP and TRING are placed in a high-impedance state when this alarm is active. The

LOTC alarm asserts between 3 µs and 16 µs after the clock is lost, and deasserts immediately after detecting the

first clock edge. The LOTC alarm status bit will latch the alarm and remain set until being cleared by a read (clear

on read). Upon the transition from LOTC = 0 to LOTC = 1, an interrupt will be generated if the LOTC interrupt

enable bit LOTCIE (register LIU_REG1, bit 3) is set. The reset default is LOTCIE = 0.

An LOTC alarm may occur when RLOOP is activated and deactivated due to the phase transient that occurs as

TLCK-LIU switches its source to and from RLCK-LIU. Setting the RLOOP alarm prevention PRLALM = 1 (register

LIU_REG4, bit 3) prevents the LOTC alarm from occurring at the activation and deactivation of RLOOP but allows

the alarm to operate normally during the RLOOP active period. The reset default is PRLALM = 0.

Agere Systems Inc.

35

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Transmit (continued)

LIU Transmitter Alarms (continued)

LIU Transmitter Driver Monitor (TDM) Alarm

The transmit driver monitor detects two conditions: a nonfunctional link due to faults on the primary of the transmit

line transformer, and periods of no data transmission. The TDM alarm (register LIU_REG0, bit 2) is the OR’d func-

tion of both faults and provides information about the integrity of the LIU transmitter signal path.

The first monitoring function is provided to detect nonfunctional links and protect the LIU transmitter from damage.

The alarm is set (TDM = 1) when one of the LIU transmitter line drivers (TTIP or TRING) is shorted to power supply

or ground, or TTIP and TRING are shorted together. Under these conditions, internal circuitry protects the LIU

transmitter from damage and excessive power supply current consumption by forcing the TTIP and TRING output

drivers into a high-impedance state. The monitor detects faults on the transformer primary side, but the transformer

secondary faults may not be detected. The monitor operates by comparing the line pulses with the transmit inputs.

After 32 transmit clock cycles, the LIU transmitter is powered up in its normal operating mode. The LIU transmitter

drivers attempt to correctly transmit the next data bit. If the error persists, TDM remains active to eliminate alarm

chatter and the transmitter is again internally protected for another 32 transmit clock cycles. This process is

repeated until the error condition is removed, and then the TDM alarm is deactivated. The TDM alarm status bit will

latch the alarm and remain set until being cleared by a read (clear on read).

The second monitoring function is to indicate periods of no data transmission. The alarm is set (TDM = 1) when 33

consecutive zeros have been transmitted. The alarm is cleared (TDM = 0) on the detection of a single pulse. This

alarm condition does not alter the functionality of the signal path.

Upon the transition from TDM = 0 to TDM = 1, a microprocessor interrupt will be generated if the TDM interrupt

enable bit TDMIE (register LIU_REG1, bit 2) is set. The reset default is TDMIE = 0.

A TDM alarm may occur when RLOOP is activated and deactivated. If the PRLALM bit is not set, then RLOOP may

activate an LOTC alarm, which will put the output drivers TTIP and TRING in a high-impedance state as described

in Loss of LIU Transmit Clock (LOTC) Alarm on page 35. The high-impedance state of the drivers may in turn gen-

erate a TDM alarm.

Setting the HIGHZ alarm prevention PHIZALM = 1 (register LIU_REG4, bit 4) prevents the TDM alarm from occur-

ring when the drivers are in a high-impedance state. The reset default is PHIZALM = 0.

36

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Transmit (continued)

DSX-1 Transmitter Pulse Template and Specifications

The DS1 pulse shape template is specified at the DSX (defined by CB119 and ANSI T1.102) and is illustrated in

Figure 10. The LIU transmitter also meets the pulse template specified by ITU-T G.703 (not shown).

1.0

0.5

0

–0.5

0

250

500

750

1000

1250

TIME (ns)

5-1160(C)r.4

Figure 10. DSX-1 Isolated Pulse Template

Table 7. DSX-1 Pulse Template Corner Points (from CB119, T1.102)

Maximum Curve

Minimum Curve

Normalized

Amplitude

Normalized

Amplitude

UI

ns

UI

ns

–0.77

–0.39

–0.27

–0.12

0.0

0.27

0.25

0.93

1.16

0

0.05

0.80

1.15

1.05

–0.07

0.05

–0.77

–0.23

–0.15

0.0

0.15

0.23

0.46

0.66

0.93

1.16

0

–0.05

0.50

0.95

250

325

425

500

675

725

1100

1250

350

400

500

600

650

800

925

1100

1250

0.90

0.50

–0.45

–0.20

–0.05

Agere Systems Inc.

37

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Transmit (continued)

DSX-1 Transmitter Pulse Template and Specifications (continued)

During DS1 operation, the LIU transmitter TTIP and TRING pins will perform as specified in Table 8.

Table 8. DS1 Transmitter Specifications

Parameter

Min

Typ

Max

Unit

Spec

Output Pulse Amplitude at DSX¹

2.5

3.0

3.5

V

AT&T CB119,

ANSI T1.102

Output Pulse Width at Line Side of

Transformer¹

325

350

375

ns

Output Pulse Width at Device Pins

330

350

370

ns

TTIP and TRING¹

Positive/Negative Pulse Imbalance²

Power Levels:^3,4

772 kHz

—

0.1

0.4

dB

12.6

29

—

17.9

—

dBm

dB

1.544 MHz⁵

39

1. With the line circuitry specified in Table 13.

2.Total power difference.

3.Measured in a 2 kHz band around the specified frequency.

4.Using Agere transformer 2795L and components in Table 13.

5.Below the power at 772 kHz.

CEPT Transmitter Pulse Template and Specifications

CEPT pulse shape template is specified at the system output (defined by ITU-T G.703) and is illustrated in Figure

11.

269 ns

(244 + 25)

20%

10%

V = 100%

194 ns

(244 – 50)

10%

NOMINAL PULSE

20%

50%

244 ns

219 ns

(244 – 25)

10%

0%

20%

488 ns

(244 + 244)

5-3145(C)r.3

Figure 11. ITU-T G.703 Pulse Template

38

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Transmit (continued)

CEPT Transmitter Pulse Template and Specifications (continued)

During E1 operation, the LIU transmitter TTIP and TRING pins will perform as specified in Table 9.

Table 9. CEPT Transmitter Specifications

Parameter

Min

Typ

Max

Unit

Spec

Output Pulse Amplitude¹:

ITU-T G.703

75 Ω

120 Ω

2.13

2.7

2.37

3.0

2.61

3.3

V

Output Pulse Width at Line Side of

Transformer¹

219

244

269

ns

Output Pulse Width at Device Pins TTIP

and TRING¹

224

244

264

ns

Positive/Negative Pulse Imbalance:

Pulse Amplitude

Pulse Width

–4

±1.5

±1

4

%

Zero Level (percentage of pulse

amplitude)

–5

0

5

%

Return Loss:²120 Ω

51 kHz to 102 kHz

102 kHz to 2.048 MHz

2.048 MHz to 3.072 MHz

Return Loss:²75 Ω

51 kHz to 102 kHz

CH-PTT

9

15

11

—

dB

ETS 300 166:

1993

7

9

—

dB

102 kHz to 3.072 MHz

1.With the line circuitry specified in Table 13, measured at the transformer secondary.

2.Using Agere transformer 2795K or 2795J and components in Table 13.

Agere Systems Inc.

39

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Jitter Attenuator

A selectable jitter attenuator is provided for narrow-bandwidth jitter transfer function applications. When placed in

the LIU receive path, the jitter attenuator provides narrow-bandwidth jitter filtering for line-synchronization. The jitter

attenuator can also be placed in the LIU transmit path to provide clock smoothing for applications such as synchro-

nous/asynchronous demultiplexers. In these applications, TLCK-LIU will have an instantaneous frequency that is

higher than the data rate and some TLCK-LIU periods are suppressed (gapped) in order to set the average long-

term TLCK-LIU frequency to within the transmit line rate specification. The jitter attenuator will smooth the gapped

clock.

Generated (Intrinsic) Jitter

Generated jitter is the amount of jitter appearing on the output port when the applied input signal has no jitter. The

jitter attenuator outputs a maximum of 0.04 UI peak-to-peak intrinsic jitter.

Jitter Transfer Function

The jitter transfer function describes the amount of jitter that is transferred from the input to the output over a range

of frequencies. The jitter attenuator exhibits a single-pole roll-off (20 dB/decade) jitter transfer characteristic that

has no peaking and a nominal filter corner frequency (3 dB bandwidth) of less than 4 Hz for DS1 operation and

approximately 10 Hz for CEPT operation. Optionally, a lower bandwidth of approximately 1.25 Hz can be selected

in CEPT operation by setting JABW0 = 1 (register LIU_REG4, bit 5) for systems desiring compliance with ETSI-

TBR12 and TBR13 jitter attenuation requirements. The reset default is JABW0 = 0. For a given frequency, different

jitter amplitudes will cause a slight variation in attenuation because of finite quantization effects. Jitter amplitudes of

less than approximately 0.2 UI will have greater attenuation than the single-pole roll-off characteristic. The jitter

transfer curve is independent of data patterns. Typical jitter transfer curves of the jitter attenuator are given in Fig-

ure 13 and Figure 15.

40

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Jitter Attenuator (continued)

Jitter Accommodation

The minimum jitter accommodation of the jitter attenuator occurs when the SYSCK frequency and the input clock’s

long-term average frequency are at their extreme frequency tolerances. When the jitter attenuator is used in the

LIU transmit path, the minimum accommodation is 28 UI peak-to-peak at the highest jitter frequency of

15 kHz. Typical receiver jitter accommodation curves including the jitter attenuator in the LIU receive path are

given in Figure 12 and Figure 14.

When the jitter attenuator is placed in the data path, a difference between the SYSCK/16 frequency and the incom-

ing line rate for receive applications, or the TCLK rate for transmit applications will result in degraded low-

frequency jitter accommodation performance. The peak-to-peak jitter accommodation (JApp) for frequencies from

above the corner frequency of the jitter attenuator (Fc) to approximately 100 Hz is given by the following equation

2( ∆fsysclk – ∆fdata )fdata

-----------------------------------------------------------------

JApp = 64 –

UI

2πfc

where:

fdata = 1.544 MHz for DS1 or 2.048 MHz for E1,

for JABW0 = 0, fc = 3.8 Hz for DS1 or 10 Hz for E1,

and for JABW0 = 1, fc = 1.25 Hz for E1,

ýfsysclk = SYSCK tolerance in ppm,

ýfdata = data tolerance in ppm.

Note that for lower corner frequencies the jitter accommodation is more sensitive to clock tolerance than for higher

corner frequencies. When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on

SYSCK should be tightened to ±20 ppm in order to meet the jitter accommodation requirements of TBR12/13 as

given in G.823 for line data rates of ±50 ppm.

Jitter Attenuator Enable (Transmit or Receive Path)

The jitter attenuator is placed in the LIU receive path by setting JAR = 1 (register LIU_REG3, bit 0). The jitter atten-

uator is selected in the LIU transmit path by setting JAT = 1 (register LIU_REG3, bit 1). When JAR = 1 and JAT = 1

or when JAR = 0 and JAT = 0, the jitter attenuator is disabled. Note that the power consumption increases slightly

on a per-channel basis when the jitter attenuator is active. The reset default case is JAR = JAT = 0.

Agere Systems Inc.

41

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Jitter Attenuator (continued)

100 UI

TYPICAL

28 UI

(SUBJECT TO DEVICE CHARACTERIZATION)

T1.408/I.431(DS1)/G.824(DS1)

10 UI

GR-499-CORE

(NON-SONET CAT II INTERFACES)

I.431(DS1), G.824(DS1)

1.0 UI

TR-TSY-000009 (DS1, MUXES)

GR-499/1244-CORE (CAT I INTERFACES)

0.1 UI

100 k

1

10

100

1 k

10 k

FREQUENCY (Hz)

5-5264(F)r.4

Figure 12. T1/DS1 Receiver Jitter Accommodation with Jitter Attenuator

0

10

20

GR-253-CORE

TR-TSY-000009

30

40

50

60

TYPICAL

(SUBJECT TO DEVICE CHARACTERIZATION)

1

10

100

1 k

10 k

100 k

FREQUENCY (Hz)

5-5265(F)r.1

Figure 13. T1/DS1 Jitter Transfer of the Jitter Attenuator

42

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Jitter Attenuator (continued)

JABW0 = 1

JABW0 = 0

100 UI

G.823

37 UI

I.431(CEPT)/ETS-300-011

TYPICAL

20.5 UI

12e-6 Hz

(SUBJECT TO DEVICE CHARACTERIZATION)

10 UI

G.823,ETSI-300-011A1

I.431(CEPT)/ETS-300-011

1.0 UI

0.1 UI

100 k

1

10

100

1 k

10 k

FREQUENCY (Hz)

5-5266(F)r.2

Figure 14. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator

G.735-9 AT NATIONAL BOUNDARIES

0

10

20

I.431, G.735-9 WITH JITTER REDUCER

ETSI-300-011

ETSI TBR12/13

30

40

50

60

JABW0 = 1

JABW0 = 0

TYPICAL

(SUBJECT TO DEVICE CHARACTERIZATION)

1

10

100

1 k

10 k

100 k

FREQUENCY (Hz)

5-5267(Fr.1

Figure 15. CEPT/E1 Jitter Transfer of the Jitter Attenuator

Agere Systems Inc.

43

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Loopbacks

The LIU has independent loopback paths that are activated using LOOPA and LOOPB control bits (register

LIU_REG5, bits 2 to 3) as shown in Table 10. The locations of these loopbacks are illustrated in Figure 5, Block

Diagram of Line Interface Unit: Single Channel, on page 26.

Full Local Loopback (FLLOOP)

A full local loopback (FLLOOP) connects the LIU transmit driver input to the receive analog front-end circuitry. Valid

transmit output data continues to be sent to the network. If the LIU transmitter AIS signal (all-1s signal) is sent to

the network, by setting the XLAIS bit (register LIU_REG5, bit 1), the looped data is not affected. The ALOS alarm

continues to monitor the receive line interface signal (RTIP and RRING) while the DLOS alarm monitors the looped

data.

See Digital Loss of Signal (DLOS) Alarm section on page 28 regarding the behavior of the DLOS alarm upon acti-

vation of FLLOOP.

Remote Loopback (RLOOP)

A remote loopback (RLOOP) connects the recovered clock and retimed data to the LIU transmitter at the framer

interface and sends the data back to the line. The LIU receiver front end, clock/data recovery, encoder/decoder (if

enabled), jitter attenuator (if enabled), and LIU transmitter driver circuitry are all exercised during this loopback.

The transmit clock, transmit data, and the transmit AIS inputs are ignored. Valid receive output data continues to be

sent to RPD-LIU and RND-LIU. This loopback mode is very helpful in isolating failures between systems.

See Loss of LIU Transmit Clock (LOTC) Alarm section on page 35 and LIU Transmitter Driver Monitor (TDM) Alarm

on page 36 regarding the behavior of the LOTC and TDM alarms upon activation and deactivation of RLOOP.

Digital Local Loopback (DLLOOP)

A digital local loopback (DLLOOP) connects the transmit clock and data through the encoder/decoder pair to the

receive clock and data output pins. This loopback is operational regardless of whether the encoder/decoder pair is

enabled or disabled. The alarm indication signal can be transmitted (XLAIS = 1) without any effect on the looped

signal.

Table 10. Loopback Control

Operation

Normal¹

Symbol

LOOPA

LOOPB

—

0

1

0

1

0

1

Full Local Loopback

Remote Loopback

FLLOOP²

RLOOP³

DLLOOP

Digital Local Loopback

1. The reset default condition is LOOPA = LOOPB = 0 (no loopback).

2. During the transmit AIS condition, the looped data will be the transmitted data from the framer or system interface and not the all 1s signal.

3. Transmit AIS request is ignored.

44

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Other Features

LIU Powerdown (PWRDN)

Each LIU channel has an independent powerdown mode controlled by PWRDN (register LIU_REG5, bit 0). This

provides power savings for systems which use backup channels. If PWRDN = 1, the corresponding LIU channel

will be in a standby mode consuming only a small amount of power. It is recommended that the alarm registers for

the powered down LIU channel be disabled by setting ALOSIE = DLOSIE = TDMIE = LOTCIE = 0 (register

LIU_REG1, bits 0—3). If an LIU channel in powerdown mode needs to be placed back into service, the channel

should be turned on (PWRDN = 0) approximately 5 ms before data is applied.

Loss of Framer Receive Line Clock (LOFRMRLCK Pin)

The LOFRMRLCK (pin 2/38) is set when the internal framer receive line clock is absent. During this alarm condi-

tion, the clock recovery and jitter attenuator functions are automatically disabled. If JAR = 1, the RLCK-LIU, RPD-

LIU, RND-LIU, and DLOS signals will be unknown.

In-Circuit Testing and Driver High-Impedance State (3-STATE)

If 3-STATE (pin 42/140) is activated (3-STATE = 0), the outputs TTIP, TRING, RDY_DTACK, INTERRUPT, and

AD[7:0] are placed in a high-impedance state. The TTIP and TRING outputs have a limiting high-impedance capa-

bility of approximately 8 kΩ.

LIU Delay Values

The transmit coder has 5 UI delay whether it is in the path or not and whether it is B8ZS or HDB3. Its delay is only

removed when in single-rail mode. The remainder of the transmit path has 4.6 UI delay. The receive decoder has

5 UI delay whether it is in the path or not and whether it is B8ZS or HDB3. Its delay is only removed when in single-

rail mode or CDR = 0. The equalizer plus slicer delay is nearly 0 UI delay. The jitter attenuator delay is nominally

33 UI but can be 2 UI—64 UI depending on state. The digital phase-locked loop used for timing recovery has 8 UI

delay.

Agere Systems Inc.

45

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

SYSCK Reference Clock

The LIU requires an externally applied clock, SYSCK pins 3 and 35, for the clock and data recovery function and

the jitter attenuation option. SYSCK must be a continuously active (i.e., ungapped, unjittered, and unswitched) and

an independent reference clock such as from an external system oscillator or system clock for proper operation. It

must not be derived from any recovered line clock (i.e., from RLCK or any synthesized frequency of RLCK).

SYSCK may be supplied in one of two formats. The format is selected for each channel by CKSEL pins 48 and

133. For CKSEL = 1, a clock at 16x the primary line data rate clock (24.704 MHz for DS1 and 32.768 MHz for

CEPT) is applied to SYSCK. For CKSEL = 0, a primary line data rate clock (1.544 MHz for DS1 and 2.048 MHz for

CEPT) is applied to SYSCK.

The CKSEL pin has an internal pull-up resistor allowing the pin to be left open, i.e., a no connect, in applications

using a 16x reference clock and pulled down to ground for applications using a primary line data rate clock.

16x SYSCK Reference Clock

The specifications for SYSCK using a 16x reference clock are defined in Table 11. The 16x reference clock is

selected when CKSEL = 1.

Table 11. SYSCK (16x, CKSEL = 1) Timing Specifications

Value

Parameter

Unit

Min

Typ

Max

Frequency

DS1

CEPT

Range*,^†

—

24.704

32.768

—

MHz

–100

40

—

100

60

ppm

%

Duty Cycle

* When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on SYSCK should be tightened to ±20 ppm in order

to meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm.

† If SYSCK is used as the source for AIS (see LIU Transmitter Alarm Indication Signal Generator (XLAIS) on page 35), it must meet the nomi-

nal transmission specifications of 1.544 MHz ± 32 ppm for DS1 (T1), or 2.048 MHz ± 50 ppm for CEPT (E1).

Primary Line Rate SYSCK Reference Clock and Internal Reference Clock Synthesizer

In some applications, it is more desirable to provide a reference clock at the primary data rate. In such cases, the

LIU can utilize an internal 16x clock synthesizer allowing the SYSCK pin to accept a primary data rate clock. The

specifications for SYSCK using a primary rate reference clock are defined in Table 12.

Table 12. SYSCK (1x, CKSEL = 0) Timing Specifications

Value

Parameter

Unit

Min

Typ

Max

Frequency

DS1

CEPT

Range*,^†

—

1.544

2.048

—

MHz

–100

40

—

100

60

5

ppm

%

Duty Cycle

Rise and Fall Times

(10%—90%)

—

ns

* When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on SYSCK should be tightened to ±20 ppm in order

to meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm.

† If SYSCK is used as the source for AIS (see LIU Transmitter Alarm Indication Signal Generator (XLAIS) on page 35), it must meet the nomi-

nal transmission specifications of 1.544 MHz ± 32 ppm for DS1 (T1), or 2.048 MHz ± 50 ppm for CEPT (E1).

46

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

SYSCK Reference Clock (continued)

The data rate reference clock and the internal clock synthesizer is selected when CKSEL = 0. In this mode, a valid

and stable data rate reference clock must be applied to the SYSCK pin before and during the time a hardware

reset is activated (RESET = 0). The reset must be held active for a minimum of two data rate clock periods to

ensure proper resetting of the clock synthesizer circuit. Upon the deactivation of the reset pin (RESET = 1), the LIU

will extend the reset condition internally for approximately 1/2(2¹²– 1) line clock periods, or 1.3 ms for DS1 and

1 ms for CEPT after the hardware reset pin has become inactive allowing the clock synthesizer additional time to

settle. No activity such as microprocessor read/write should be performed during this period. The device will be

operational 2.7 ms after the deactivation of the hardware reset pin. Issuing an LIU software restart (LIU_REG2 bit

5 (RESTART) = 1) does not impact the clock synthesizer circuit.

Agere Systems Inc.

47

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Line Interface Networks

The transmit and receive tip and ring connections provide a matched interface to the line cable when used with a

proper matching network. The diagram in Figure 16 shows the appropriate external components to interface to the

cable for a single transmit/receive channel. The component values are summarized in Table 13, based on the spe-

cific application.

EQUIPMENT

INTERFACE

RECEIVE DATA

TRANSFORMER

1:N

RR

RTIP

CC

ZEQ

RP

RS

RRING

DEVICE

(1 CHANNEL)

TRANSMIT DATA

RT

TTIP

RL

CP

TRING

N:1

5-3693(C).e

Figure 16. Line Termination Circuitry

Table 13. Termination Components by Application¹

Cable Type

CEPT 75 Ω³Coaxial

Symbol

Name

Unit

DS1²

Twisted

Pair

CEPT 120 Ω⁵

Twisted Pair

Option 1⁴Option 2⁵

CC

CP

Center Tap Capacitor

0.1

—

0.1

150

200

143

147

75

0.1

150

200

261

182

75

0.1

150

200

698

365

120

±4

µF

Line Shunt Capacitor

RP

Receive Primary Impedance

Receive Series Impedance

Receive Secondary Impedance

Equivalent Line Termination

Tolerance

200

332

210

100

±4

Ω

RR

RS

ZEQ

±4

%

RT

RL

N

Transmit Series Impedance

Transmit Load Termination⁶

Transformer Turns Ratio

0

7.5

75

5.36

75

7.5

Ω

100

2.1

120

2.45

1.93

2.45

—

1. Resistor tolerances are ±1%. Transformer turns ratio tolerances are ±2%.

2. Use Agere 2795L transformer.

3. For CEPT 75 Ω applications, Option 1 is recommended over Option 2 for lower device power dissipation. Option 2 increases power dissipa-

tion by 13 mW per channel when driving 50% ones data. Option 2 allows for the use of the same transformer as in CEPT 120 Ω applications.

4. Use Agere 2795K transformer.

5. Use Agere 2795J transformer.

6. A ±5% tolerance is allowed for the transmit load termination.

48

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit: Line Interface Networks (continued)

The transmit and receive tip and ring connections should be provided with a matched and protected interface to

the line (i.e., terminating impedance to match the characteristic impedance of the line cable and secondary line

protection). For the purpose of line protection and matching network design, the equivalent input impedance of the

receiver and the equivalent output circuit of the transmitter can be assumed to be as shown in Figure 17.

20 kΩ

3 pF

2 pF

RECEIVER

INPUT*

47 kΩ

3 pF

20 kΩ

GRNDA

A. Receiver Input Approximate Equivalent Circuit

1 Ω—1.5 Ω

TRANSMITTER

OUTPUT

1 Ω—1.5 Ω

PULSE

VOLTAGE SOURCE

†

B. Transmitter Output Approximate Equivalent Circuit

5-6232(F).b

* Approximately 0.3 V—2.0 V peak.

† Approximate pulse voltage source (peak).

Mode

DS1

Peak

Unit

1.6

V

CEPT:

75 Ω:

Option 1

Option 2

120 Ω

2.3

2.1

2.3

V

Figure 17. T7633 Line Interface Unit Approximate Equivalent Analog I/O Circuits

Agere Systems Inc.

49

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

LIU-Framer Interface

LIU-Framer Physical Interface

The transmit framer-LIU interface for the T7633 consists of the TND, TPD, and TLCK pins. In normal operations,

TND, TPD, and TLCK are directly connected to the transmit line interface and the TPD, TND, and TLCK pins are

driven from the transmit framer. The receive framer-LIU interface for the T7633 consists of the RPD, RND_BPV,

and RLCK internal signals. In normal operations, RND, RPD, and RLCK are directly sourced from the internal

receive line interface unit. In the framer mode, FRAMER = 0, the RPD, RND, and RLCK pins are directly connected

to the receive framer (the internal receive line interface unit is bypassed). Figure 18 illustrates the interfaces of the

transmit and receive framer units.

TRANSMIT

HDLC

FACILITY DATA

LINK

INTERFACE

TLCK

TPD TND

TFDLCK

TFDL

TTIP

RCHIDATA

RCHIFS

TLCK

TND

TPD

RECEIVE

CONCENTRATION

HIGHWAY

TRANSMIT LINE

INTERFACE

UNIT

TRANSMIT

FRAMER

(XFRMR)

INTERFACE

(RCHI)

TRING

(XLIU)

RCHICK

PLLCK

RECEIVE HDLC

FACILITY DATA

SYSTEM INTERFACE

RLCK

LINK INTERFACE

LINE INTERFACE

RFDLCK

RFDL

RND_BPV

RPD

0

1

FRM_RLCK

TCHIDATA

TCHICK

TCHIFS

TRANSMIT

CONCENTRATION

HIGHWAY

RECEIVE

FRAMER

(RFRMR)

FRM_RND

FRM_RPD

LIU_RLCK

LIU_RND/BPV

LIU_RPD

RTIP

INTERFACE

(XCHI)

RECEIVE LINE

INTERFACE

UNIT

(RLIU)

RRING

RFRMCK

FRAMER

5-4557(F).br.2

Figure 18. Block Diagram of Framer Line Interface

50

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

LIU-Framer Interface (continued)

LIU-Framer Physical Interface (continued)

Figure 19 shows the timing requirements for the transmit and receive framer interfaces in the LIU-bypass mode.

FRM_PR45

BIT 0 (HFLF)

t1

HFLF = 0

648 ns

HFLF = 1

162 ns

t1-DS1

PLLCK

t1-CEPT

488 ns

122 ns

t2f-r

t2r-f: t2f-r: PLLCK TO TLCK DELAY = 50 ns

t3-DS1 = 648 ns

t2r-f

t3

t3-CEPT = 488 ns

TLCK

t4

t4 = TLCK TO VALID TPD, TND = 30 ns

TND, TPD

t5-DS1 = 648 ns

t5-CEPT = 488 ns

t5

RLCK

RND, RPD

RFRMCK

t6 = RPD, RND SETUP TO RISING RLCK = 40 ns

t7 = RPD, RND HOLD FROM RISING RLCK = 40 ns

t6

t7

t8r-f: t8f-r: RLCK TO RFRMCK DELAY = 50 ns

t8

5-4558(F).cr.3

Figure 19. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing

Agere Systems Inc.

51

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

LIU-Framer Interface (continued)

Interface Mode and Line Encoding

Single Rail

The default mode for the LIU-framer interface is single-rail, register LIU_REG3 bit 3 (DUAL) = 0 and register

FRM_PR8 bit 7 = 1, bit 6 = 1, and bit 5 = 0.

In the single-rail terminator mode (FRAMER = 1), the LIU bipolar encoder and decoder may be enabled by setting

register LIU_REG3 bit 2 (CODE) to 1. Signals passed on the internal LIU-framer interface are data (LIU_RPD and

TPD), clock (LIU_RLCK and TLCK), and received bipolar violations (LIU_RND/BPV). When LIU_RND/BPV = 1,

the BPV counter increments by one on the rising edge of LIU_RLCK.

In the single-rail framer mode (FRAMER = 0), external signals to and from the framer are data (RTIP_RPD, pin 11/

27 and TPD, pin 44/138), clock (RLCK, pin 47/135, and TLCK, pin 46/136), and received bipolar violations

(RRING_RND, pin 10/28). When RRING_RND = 1, the BPV counter increments by one on the rising edge of

RLCK. In this mode, TND (pin 45/137) is forced to the 0 state.

Dual Rail

Dual-rail LIU-framer interface mode is selected by setting LIU_REG3 bit 3 (DUAL) = 1 and by selecting one of the

dual-rail framer modes of FRM_PR8 bit 5—bit 7.

In the dual-rail terminator mode (FRAMER = 1), the framer bipolar encoder and decoder are enabled. Signals

passed on the internal LIU-framer interface are data (LIU_RPD, LIU_RND, TPD, and TND), and clock (LIU_RLCK

and TLCK). When bipolar violations are detected by the framer, the BPV counter increments by one on the rising

edge of LIU_RLCK.

In the dual-rail framer mode (FRAMER = 0), external signals to and from the framer are data (RTIP_RPD, pin 11/

27, RRING_RND, pin 10/28, TPD, pin 44/138, and TND, pin 45/137) and clock (RLCK, pin 47/135, and TLCK, pin

46/136). When bipolar violations are detected by the framer, the BPV counter increments by one on the rising edge

of RLCK.

DS1: Alternate Mark Inversion (AMI)

The default line code used for T1 is alternate mark inversion (AMI). The coding scheme represents a 1 with a pulse

(mark) on the positive or negative rail and a 0 with no pulse on either rail. This scheme is shown in Table 14.

Table 14. AMI Encoding

Input Bit Stream

AMI Data

1011

–0+–

0000

0111

0+–+

1010

–0+0

The T1 “ones density rule” states that:

In every 24 bits of information to be transmitted, there must be at least three pulses, and no more than 15

zeros may be transmitted consecutively [AT&T TR62411 (1988), ANSI T1.231 (1997)].

Receive ones density is monitored by the receive line interface as per T1M1.3/93-005, ITU G.775, or TR-TSY-

000009.

The receive framer indicates excessive zeros upon detecting any zero string length greater than fifteen contiguous

zeros (no pulses on either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar viola-

tions.

52

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

LIU-Framer Interface (continued)

DS1: Zero Code Suppression (ZCS)

Zero code suppression is a technique known as pulse stuffing in which the seventh bit of each time slot is stuffed

with a one. The line format (shown in Table 15) limits the data rate of each time slot from 64 kbits/s to 56 kbits/s.

The default ZCS format stuffs the seventh bit of those ALL-ZERO time slots programmed for robbed-bit signaling

(as defined in the signaling control registers with the F and G bits).

The receive framer indicates excessive zeros upon detecting any zero string length greater than fifteen contiguous

zeros (no pulses on either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar vio-

lations.

Table 15. DS1 ZCS Encoding

Input Bit Stream

00000000

00000010

01010000

01010010

01010000

00000000

00000010

00000000

00000010

ZCS Data (Framer Mode)

T7633 Default ZCS

00000000

(data time slot remains clear)

DS1: Binary 8 Zero Code Suppression (B8ZS)

Clear channel transmission can be accomplished using Binary 8 Zero Code Suppression (B8ZS). Eight consecu-

tive 0s are replaced with the B8ZS code. This code consists of two bipolar violations in bit positions 4 and 7 and

valid bipolar marks in bit positions 5 and 8. The receiving end recognizes this code and replaces it with the original

string of eight 0s.

The receive framer indicates excessive zeros upon detecting a block of eight (8) or more consecutive 0s (no

pulses on either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar violations.

Table 16 shows the encoding of a string of 0s using B8ZS. B8ZS is recommended when ESF format is used. V

represents a violation of the bipolar rule, and B represents an inserted pulse conforming to the AMI rule.

Table 16. DS1 B8ZS Encoding

Bit Positions

Before B8ZS

1

2

3

4

5

6

7

8

—

1

2

3

4

5

6

7

8

0

1

0

1

0

After B8ZS

V

B

V

B

V

B

V

B

Agere Systems Inc.

53

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

LIU-Framer Interface (continued)

CEPT: High-Density Bipolar of Order 3 (HDB3)

The line code used for CEPT is described in ITU Rec. G.703 Section 6.1 as high-density bipolar of order 3 (HDB3).

HDB3 uses a substitution code that acts on strings of four 0s. The substitute HDB3 codes are 000V and B00V,

where V represents a violation of the bipolar rule and B represents an inserted pulse conforming to the AMI rule

defined in ITU Rec. G.701, item 9004. The choice of the B00V or 000V is made so that the number of B pulses

between consecutive V pulses is odd. In other words, successive V pulses are of alternate polarity so that no direct

current (dc) component is introduced. The substitute codes follow each other if the string of 0s continues. The

choice of the first substitute code is arbitrary. A line code error consists of two pulses of the same polarity that is not

defined as one of the two substitute codes. Excessive zeros consist of any zero string length greater than four con-

tiguous zeros. Both excessive zeros and coding violations are indicated as bipolar violations. An example is shown

in Table 17.

Table 17. ITU HDB3 Coding

Input Bit Stream

1011

–0+–

0000

000V

000–

–000

1-BPV

01

0+

0000

000V

000+

+00+

0000

0000 0000

HDB3-coded Data

B00V B00V B00V

HDB3-coded Levels

HDB3 with 5 Double BPVs

–00–

0–––

+00+ –00–

3-BPV 5-BPV

54

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats

The supported North American T1 framing formats are superframe (D4, SLC-96, and digital data service-DDS) and

extended superframe (ESF). The device can be programmed to support the ITU-CEPT-E1 basic format with and

without CRC-4 multiframe formatting. This section describes these framing formats.

T1 Framing Structures

T1 is a digital transmission system which multiplexes twenty-four 64 kbits/s time slots (DS0) onto a serial link. The

T1 system is the lowest level of hierarchy on the North American T-carrier system, as shown in Figure 20.

Table 18. T-Carrier Hierarchy

T Carrier

DS0 Channels

Bit Rate (Mbits/s)

Digital Signal Level

T1

T1-C

T2

24

48

1.544

3.152

DS1

DS1C

DS2

96

6.312

T3

672

4032

44.736

274.176

DS3

T4

DS4

Frame, Superframe, and Extended Superframe Definitions

Each time slot (DS0) is an assembly of 8 bits sampled every 125 µs. The data rate is 64 kbits/s and the sample

rate is 8 kHz. Time-division multiplexing 24 DS0 time slots together produces a 192-bit (24 DS0s) frame. A framing

bit is added to the beginning of each frame to allow for detection of frame boundaries and the transport of addi-

tional maintenance information. This 193-bit frame, also referred to as a DS1 frame, is repeated every 125 µs to

yield the 1.544 Mbits/s T1 data rate. DS1 frames are bundled together to form superframes or extended super-

frames.

24-FRAME EXTENDED

FRAME 1

FRAME 2

FRAME 3

FRAME 23

FRAME 24

SUPERFRAME

ESF = 3.0 ms

12-FRAME SUPERFRAME

SF = 1.5 ms

FRAME 1

FRAME 2

FRAME 11

FRAME 12

193-bit FRAME

DS1 = 125 µs

F BIT

TIME SLOT 1

TIME SLOT 2

TIME SLOT 24

8-bit TIME SLOT

DS0 = 5.19 µs

1

2

3

4

5

6

7

8

5-4559(F).br.1

Figure 20. T1 Frame Structure

Agere Systems Inc.

55

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

T1 Framing Structures (continued)

Transparent Framing Format

The transmit framer can be programmed to transparently transmit 193 bits of system data to the line. The system

interface must be programmed such that the stuffed time slots are 1, 5, 9, 13, 17, 21, 25, and 29 (FRM_PR43 bits

2—0 must be set to 000) and either transparent framing mode 1 or transparent framing mode 2 is enabled

(FRM_PR26 bit 3 or bit 4 must be set to 1).

In transparent mode 1 or mode 2, the transmit framer extracts from the receive system data bit 8 of time slot 1 and

inserts this bit into the framing bit position of the transmit line data. The other 7 bits of the receive system time slot

1 are ignored by the transmit framer. The receive framer will extract the f-bit (or 193rd bit) of the receive line data

and insert it into bit 8 of time slot 1 of the system data; the other bits of time slot 1 are set to 0.

Frame integrity is maintained in both the transmit and receive framer sections.

TIME SLOT 1 TIME SLOT 2 TIME SLOT 3

TIME SLOT 31 TIME SLOT 32

32 TIME-SLOT CHI FRAME

(STUFF TIME SLOT)

0

F BIT

TRAMSMIT FRAMER’S

193-bit FRAME

F BIT TIME SLOT 1 TIME SLOT 2

TIME SLOT 24

DS1 = 125 µs

5-5989(F).ar.1

Figure 21. T1 Transparent Frame Structure

In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than

bipolar violations and unframed AIS monitoring, there is no processing of the receive line data. The receive framer

will insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data.

In transparent framing mode 2, the receive framer functions normally on receive line data. All normal monitoring of

receive line data is performed and data is passed to the transmit CHI as programmed. The receive framer will

insert the extracted framing bit of the receive line data into bit 8 of time slot 1 of the transmit system data. The

remaining bits in time slot 1 are set to 0.

56

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

T1 Framing Structures (continued)

D4 Frame Format

D4 superframe format consists of 12 DS1 frames. Table 19 shows the structure of the D4 superframe.

Table 19. D4 Superframe Format

Frame

Framing Bits

Bit Used in Each Time Slot

Signaling Options

4-State

Number¹

Bit

Terminal

Signal

Traffic

(All

Remote Signal- None 2-State

Number²Frame FT Frame

FS

Alarm³

ing

4

Channels)

1

2

0

1

—

0

—

0

1—8

1—7

1—8

1—7

2

—

8

—

A

—

A

193

3

386

—

0

4

579

—

1

5

6⁵

772

—

1

965

—

0

7

1158

1351

1544

1737

1930

2123

—

1

—

8

—

A

—

B

8

—

1

9

—

1

10

11

12⁵

—

0

—

0

—

1. Frame 1 is transmitted first.

2. Following ANSI T1.403, the bits are numbered 0—2315. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and

bit 1 of each DS0 is transmitted first.

3. The remote alarm forces bit 2 of each time slot to a 0-state when enabled. The Japanese remote alarm forces framing bit 12 (bit number

2123) to a 1-state when enabled.

4. Signaling option none uses bit 8 for traffic data.

5. Frames 6 and 12 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.

The receive framer uses both the FT and FS framing bits during its frame alignment procedure.

Agere Systems Inc.

57

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

T1 Framing Structures (continued)

Digital Data Service (DDS) Frame Format

The superframe format for DDS is the same as that given for D4. DDS is intended to be used for data-only traffic,

and as such, the system should ensure that the framer is in the nonsignaling mode. DDS uses time slot 24 (FAS

channel) to transmit the remote frame alarm and data link bits. The format for time slot 24 is shown in Table 20. The

facility data link timing is shown in Figure 22 below.

Table 20. DDS Channel-24 Format

Time Slot 24 = 10111YD0

Y = (bit 6)

D = (bit 7)

Remote frame alarm: 1 = no alarm state; 0 = alarm state

Data link bits (8 kbits/s)

t8

t8: TFDLCK CYCLE = 125 µs (DDS)

TFDLCK

250 µs (ALL OTHER

MODES)

t9

t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns

TFDL

t10

t10: RFDLCK CYCLE = 125 µs (DDS)

250 µs (ALL OTHER

MODES)

RFDLCK

RFDL

t11: RFDLCK TO RFDL DELAY = 40 ns

t11

5-3910(F).cr.1

Figure 22. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections

SLC-96 Frame Format

SLC-96 superframe format consists of 12 DS1 frames similar to D4. The FT pattern is exactly the same as D4. The

FS pattern uses that same structure as D4 but also incorporates a 24-bit data link word as shown below.

SLC-96 24-bit DATA LINK WORD

Fs =

. . . 000111000111D1DDDDDDDDDDDDDDDDDDDDDDD24000111000111DDD . . .

FRAME FRAME FRAME FRAME FRAME FRAME

FRAME FRAME FRAME FRAME

N –1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6 N + 7

N + 8

SLC-96 36-FRAME D-bit SUPERFRAME INTERVAL

(72 DS1 FRAMES)

5-6421(F)r.1

58

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

T1 Framing Structures (continued)

External TFDL Source. Data may be inserted and extracted from the SLC-96 data link from either the external

facility data link (TFDL) ports or the SLC-96 data stack. Source selection is controlled by FRM_PR21 bit 6 and

FRM_PR29 bit 5—bit 7.

The transmit framer synchronizes on TFDL = 000111000111 . . . and forces a superframe boundary based on this

pattern. When sourcing an external bit stream, it is the system’s responsibility to ensure that TFDL data contain the

pattern of 000111000111 . . . . The D pattern sequence is shown in Table 21. Table 22 shows the encoding for the

line switch field.

Table 21. SLC-96 Data Link Block Format

Data Link Block

Bit Definition

Bit Value

D1 (leftmost bit)

C1 — concentrator bit

C2 — concentrator bit

C3 — concentrator bit

C4 — concentrator bit

C5 — concentrator bit

C6 — concentrator bit

C7 — concentrator bit

C8 — concentrator bit

C9 — concentrator bit

C10 — concentrator bit

C11 — concentrator bit

Spoiler bit 1

0 or 1

D2

0 or 1

D3

0 or 1

D4

0 or 1

D5

0 or 1

D6

0 or 1

D7

0 or 1

D8

D9

0 or 1

D10

0 or 1

D11

0 or 1

D12

0

D13

Spoiler bit 2

1

D14

Spoiler bit 3

0

0 or 1

D15

M1 — maintenance bit

M2 — maintenance bit

M3 — maintenance bit

A1 — alarm bit

D16

0 or 1

D17

0 or 1

D18

0 or 1

D19

A2 — alarm bit

0 or 1

D20

S1 — line-switch bit

S2 — line-switch bit

S3 — line-switch bit

S4 — line-switch bit

Spoiler bit 4

Defined in Table 22

1

D21

D22

D23

D24 (rightmost bit)

Agere Systems Inc.

59

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

T1 Framing Structures (continued)

Table 22. SLC-96 Line Switch Message Codes

S1

S2

S3

S4

Code Definition

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Idle

Switch line A receive

Switch line B transmit

Switch line C transmit

Switch line D transmit

Switch line B transmit and receive

Internal SLC-96 Stack Source. Optionally, a SLC-96 FDL stack may be used to insert and correspondingly extract

the FDL information in the SLC-96 frame format.

The transmit SLC-96 FDL bits are sourced from the transmit framer SLC-96 FDL stack. The SLC-96 FDL stack

(see FRM_PR31—FRM_PR35) consists of five 8-bit registers that contain the SLC-96 FS and D-bit information as

shown in Table 23. The transmit stack data is transmitted to the line when the stack enable mode is active in the

parameter registers FRM_PR21 bit 6 = 1 and FRM_PR29 bit 5—bit 7 = x10 (binary).

The receive SLC-96 stack data is received when the receive framer is in the superframe alignment state. In the

SLC-96 mode, while in the loss of superframe alignment (LSFA) state, updating of the receive framer SLC-96 stack

is halted and neither the receive stack interrupt nor receive stack flag are asserted.

Table 23. Transmit and Receive SLC-96 Stack Structure

Register

Number

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

1 (LSR)

0

1

2

3

4

5

0

1

C8

C1

C9

M3

C2

C10

A1

C3

C11

A2

C4

C5

C6

C7

M1

S4

SPB1 = 0 SPB2 = 1 SPB3 = 0

S1 S2 S3

M2

SPB4 = 1

Bit 5—bit 0 of the first 2 bytes of the SLC-96 FDL stack in Table 23 are transmitted to the line as the SLC-96 FS

sequence. Bit 7 of the third stack register is transmitted as the C1 bit of the SLC-96 D sequence. The spoiler bits

(SPB1, SPB2, SPB3, and SPB4) are taken directly from the transmit stack. The protocol for accessing the SLC-96

stack information for the transmit and receive framer is described below. The transmit SLC-96 stack must be writ-

ten with valid data when transmitting stack data.

The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 5 (SLC-96

transmit FDL stack ready) high. At this time, the system has about 9 ms to update the stack. Data written to the

stack during this interval will be transmitted during the next SLC-96 superframe D-bit interval. By reading bit 5 in

register SR4, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the trans-

mit stack is not updated, then the content of the stack is retransmitted to the line. The start of the SLC-96 36-frame

FS interval of the transmit framer is a function of the first 2 bytes of the SLC-96 transmit stack registers. These

bytes must be programmed as shown in Table 23. Programming any other state into these two registers disables

the proper transmission of the SLC-96 D bits. Once programmed correctly, the transmit SLC-96 D-bit stack is trans-

mitted synchronous to the transmit SLC-96 superframe structure.

On the receive side, the device indicates that it has received data in the receive FDL stack (registers FRM_SR54—

FRM_SR58) by setting bit 4 in register FRM_SR4 (SLC-96 receive FDL stack ready) high. The system then has

about 9 ms to read the content of the stack before it is updated again (old data lost). By reading bit 4 in register

FRM_SR4, the system clears this bit so that it can indicate the next time the receive stack is ready. As explained

above, the SLC-96 receive stack is not updated when superframe alignment is lost.

60

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

T1 Framing Structures (continued)

Extended Superframe Format

The extended superframe format consists of 24 DS1 frames. The F bits are used for frame alignment, superframe

alignment, error checking, and facility data link transport. Table 24 shows the ESF frame format.

Table 24. Extended Superframe (ESF) Structure

Frame

Bit Use in Each Time

Slot

Signaling Option²

Frame Bit

Number¹

Bit

FE

DL

CRC-6⁴

Traffic

Signaling None⁵2-State

4-State 16-State

Number³

1

2

0

—

0

D

—

D

—

C1

—

C2

—

C3

—

C4

—

C5

—

C6

—

1—8

1—7

1—8

1—7

1—8

1—7

1—8

1—7

—

8

—

A

—

A

—

A

193

3

386

4

579

—

D

5

6⁶

772

—

0

965

—

D

7

1158

1351

1544

1737

1930

2123

2316

2509

2702

2895

3088

3281

3474

3667

3860

4053

4246

4439

—

8

—

A

—

B

—

B

8

—

D

9

—

1

10

11

12⁶

13

14

15

16

17

18⁶

19

20

21

22

23

24⁶

—

D

—

D

—

0

—

8

—

A

—

A

—

C

—

D

—

D

—

1

—

D

—

8

—

A

—

B

—

D

—

D

—

1

—

D

—

1. Frame 1 is transmitted first.

2. The remote alarm is a repeated 1111111100000000 pattern in the DL when enabled.

3. Following ANSI T1.403, the bits are numbered 0—4361. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and

bit 1 of each DS0 is transmitted first.

4. The C1 to C6 bits are the cyclic redundancy check-6 (CRC-6) checksum bits calculated over the previous extended superframe.

5. Signaling option none uses bit 8 for traffic data.

6. Frames 6, 12, 18, and 24 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.

The ESF format allows for in-service error detection and diagnostics on T1 circuits. ESF format consist of 24 fram-

ing bits: 6 for framing synchronization (2 kbits/s); 6 for error detection (2 kbits/s); and 12 for in-service monitoring

and diagnostics (4 kbits/s).

Agere Systems Inc.

61

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

T1 Framing Structures (continued)

Cyclic redundancy checking is performed over the entire ESF data payload (4,608 data bits, with all 24 framing bits

(FE, DL, CRC-6) set to 1 during calculations). The CRC-6 bits transmitted in ESF will be determined as follows:

■ The check bits, c1 through c6, contained in ESF(n + 1) will always be those associated with the contents of

ESF(n), the immediately preceding ESF. When there is no ESF immediately preceding, the check bits may be

assigned any value.

■ For the purpose of CRC-6 calculation only, every F bit in ESF(n) is set to 1. ESF(n) is altered in no other way.

■ The resulting 4632 bits of ESF(n) are used, in order of occurrence, to construct a polynomial in x such that the

first bit of ESF(n) is the coefficient of the term x⁴⁶³¹and the last bit of ESF(n) is the coefficient of the term x⁰.

■ The polynomial is multiplied by the factor x⁶, and the result is divided, modulo 2, by the generator polynomial x⁶

+ x + 1. The coefficients of the remainder polynomial are used, in order of occurrence, as the ordered set of

check bits, c1 through c6, that are transmitted in ESF(n + 1). The ordering is such that the coefficient of the term

x⁵in the remainder polynomial is check bit c1 and the coefficient of the term x⁰in the remainder polynomial is

check bit c6.

The ESF remote frame alarm consists of a repeated eight 1s followed by eight 0s transmitted in the data link posi-

tion of the framing bits.

T1 Loss of Frame Alignment (LFA)

Loss of frame alignment condition for the superframe or the extended superframe formats is caused by the inability

of the receive framer to maintain the proper sequence of frame bits. The number of errored framing bits required to

detect a loss of frame alignment is given is Table 25.

Table 25. T1 Loss of Frame Alignment Criteria

Number of Errored Framing Bits That Will Cause a Loss of Frame Alignment

Format

Condition

D4

2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1.

2 errored FT bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0.

SLC-96

2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1.

2 errored FT bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0.

DDS: Frame

ESF

3 errored frame bits (FT or FS) or channel 24 FAS pattern out of 12 consecutive frame bits.

2 errored FE bits out of 4 consecutive FE bits or optionally 320 or more CRC-6 errored

checksums within a one second interval if loss of frame alignment due to excessive CRC-6

errors is enabled in FRM_PR9.

The receive framer indicates the loss of frame and superframe conditions by setting the LFA and LSFA bits

(FRM_SR1 bit 0 and bit 1), respectively, in the status registers for the duration of the conditions. The local system

may give indication of its LFA state to the remote end by transmitting a remote frame alarm (RFA). In addition, in

the LFA state, the system may transmit an alarm indication signal (AIS) to the system interface.

62

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

T1 Frame Recovery Alignment Algorithms

When in a loss of frame alignment state, the receive framer searches for a new frame alignment and forces its

internal circuitry to this new alignment. The receive framer’s synchronization circuit inhibits realignment in T1 fram-

ing formats when repetitive data patterns emulate the T1 frame alignment patterns. T1 frame synchronization will

not occur until all frame sequence emulating patterns disappear and only one valid pattern exists. The loss of

frame alignment state will always force a loss of superframe alignment state. Superframe alignment is established

only after frame alignment has been determined in the D4 and SLC-96 frame format. Table 26 gives the require-

ments for establishing T1 frame and superframe alignment.

Table 26. T1 Frame Alignment Procedures

Frame Format

D4: Frame

Alignment Procedure

Using the FT frame position as the starting point, frame alignment is established when

24 consecutive FT and FS frame bits, excluding the twelfth FS bit, (48 total frames) are

received error-free. Once frame alignment is established, then superframe alignment is

determined.

D4: Superframe

After frame alignment is determined, two valid superframe bit sequences using the FS

bits must be received error-free to establish superframe alignment.

SLC-96: Frame

Using the FT frame position as the starting point, frame alignment is established when

24 consecutive FT frame bits (48 total frames) are received error-free. Once frame

alignment is established, then superframe alignment is determined.

SLC-96: Superframe

After frame alignment is determined, superframe alignment is established on the first

valid superframe bit sequence 000111000111.

DDS: Frame

Using the FT frame position as the starting point, frame alignment is established when

six consecutive FT/FS frame bits and the DDS FAS in time slot 24 are received error-

free. In the DDS format, there is no search for a superframe structure.

ESF

Frame and superframe alignment is established simultaneously using the FE framing

bit. Alignment is established when 24 consecutive FE bits are received error-free. Once

frame/superframe alignment is established, the CRC-6 receive monitor is enabled.

Agere Systems Inc.

63

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

T1 Robbed-Bit Signaling

To enable signaling, register FRM_PR44 bit 0 (TSIG) must be set to 0.

Robbed-bit signaling, used in either ESF or SF framing formats, “robs” the eighth bit of the voice channels of every

sixth (6th) frame. The signaling bits are designated A, B, C, and D, depending on the signaling format used. The

robbed-bit signaling format used is defined by the state of the F and G bits in the signaling registers (see DS1:

Robbed-Bit Signaling on page 85). The received channel robbed-bit signaling format is defined by the correspond-

ing transmit signaling F and G bits. Table 27 shows the state of the transmitted signaling bits as a function of the F

and G bits.

Table 27. Robbed-Bit Signaling Options

G

F

Robbed-Bit Signaling Format

Frame

6

12

18

24

0

ESF: 16-State

A

B

C

D

SLC*: 9-State, 16-State

0

1

0

1

4-State

Data channel (no signaling)

2-State

A

B

A

B

A

PAYLOAD DATA

A

* See register FRM_PR43 bit 3 and bit 4.

The robbed-bit signaling format for each of the 24 T1 transmit channels is programmed on a per-channel basis by

setting the F and G bits in the transmit signaling direction.

SLC-96 9-State Signaling

SLC-96 9-state signaling state is enabled by setting both the F and G bits in the signaling registers to the 0 state,

setting the SLC-96 signaling control register FRM_PR43 bit 3 to 1, and setting register FRM_PR44 bit 0 to 0.Table

28 shows the state of the transmitted signaling bits to the line as a function of the A, B, C and D bit settings in the

transmit signaling registers. In Table 28 below, X indicates either a 1 or a 0 state, and T indicates a toggle, transi-

tion from either 0 to 1 or 1 to 0, of the transmitted signaling bit.

In the line receive direction, this signaling mode functions identically to the preceding transmit path description.

Table 28. SLC-96 9-State Signaling Format

Transmit Signaling Register Settings

Transmit to the Line Signal Bits

SLC-96 Signaling States

A

B

C

D

A = f(A,C)

B = f(B,D)

State 1

State 2

State 3

State 4

State 5

State 6

State 7

State 8

State 9

0

1

0

1

0

1

0

1

0

1

X

0

1

X

0

1

X

0

1

X

0

T

1

0

T

1

0

T

1

0

T

1

64

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

T1 Robbed-Bit Signaling (continued)

16-State Signaling

The default signaling mode while in SLC-96 framing is 16-state signaling. SLC-96 16-state signaling is enabled by

setting both the F and G bits in the signaling registers to the 0 state, setting the SLC-96 signaling control register

FRM_PR43 bit 3 and bit 4 to 0, and setting register FRM_PR44 bit 0 to 0. Table 29 shows the state of the transmit-

ted signaling bits to the line as a function of the A, B, C, and D bit settings in the transmit signaling registers. In

Table 29 below, under Transmit to the Line Signal Bits, A and B are transmitted into one SLC-96 12-frame signal-

ing superframe, while A’ and B’ are transmitted into the next successive SLC-96 12-frame signaling superframe.

In the line receive direction, this signaling mode functions identically to the preceding transmit path description.

The signaling mapping of this 16-state signaling mode is equivalent to the mapping of the SLC-96 9-state signaling

mode.

Table 29. 16-State Signaling Format

Transmit Signaling Register Settings

Transmit to the Line Signal Bits

SLC-96 Signaling States

A

B

C

D

A

B

A’

B’

State 0

State 1

State 2

State 3

State 4

State 5

State 6

State 7

State 8

State 9

State 10

State 11

State 12

State 13

State 14

State 15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Agere Systems Inc.

65

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Struc-

tures

As defined in ITU Rec. G.704, the CEPT 2.048 frame, CRC-4 multiframe, and channel associated signaling multi-

frame structures are illustrated in Figure 23.

CRC-4 MULTIFRAME IN

0

X⁰YM X1 X2

FRAME 0 TIME

SLOT 16

TIME SLOT 0

A¹B1 C1 D1 A16 B16 C16 D16

A2 B2 C2 D2 A17 B17 C17 D17

A3 B3 C3 D3 A18 B18 C18 D18

A4 B4 C4 D4 A19 B19 C19 D19

A5 B5 C5 D5 A20 B20 C20 D20

A6 B6 C6 D6 A21 B21 C21 D21

A7 B7 C7 D7 A22 B22 C22 D22

A8 B8 C8 D8 A23 B23 C23 D23

A9 B9 C9 D9 A24 B24 C24 D24

A10 B10 C10 D10 A25 B25 C25 D25

A11 B11 C11 D11 A26 B26 C26 D26

A12 B12 C12 D12 A27 B27 C27 D27

A13 B13 C13 D13 A28 B28 C28 D28

A14 B14 C14 D14 A29 B29 C29 D29

A15 B15 C15 D15 A30 B30 C30 D30

MULTIFRAME

FRAME 0 OF CRC-4

MULTIFRAME

C1 0

0 1 A SA4 SA5 SA6 SA7 SA8 TIME SLOT 1

C²0 TIME SLOT 1

0 1 A S^A4SA5 SA6 SA7 SA8 TIME SLOT 1

C3 0 TIME SLOT 1

1 1 A S^A4SA5 SA6 SA7 SA8 TIME SLOT 1

C4 0 TIME SLOT 1

0 1 A S^A4SA5 SA6 SA7 SA8 TIME SLOT 1

C1 0 TIME SLOT 1

1 1 A S^A4SA5 SA6 SA7 SA8 TIME SLOT 1

C2 0 TIME SLOT 1

1 1 A S^A4SA5 SA6 SA7 SA8 TIME SLOT 1

C3 0 TIME SLOT 1

E 1 A S^A4SA5 SA6 SA7 S^A8TIME SLOT 1

C4 0 TIME SLOT 1

E 1 A S^A4SA5 SA6 SA7 S^A8TIME SLOT 1

0

1

0

1

TIME SLOT 1

TIME SLOT 31

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FRAME 15 OF CRC-4

MULTIFRAME

FRAME 15

TIME SLOT 16

MULTIFRAME

CHANNEL ASSOCIATED

SIGNALING MULTIFRAME

IN TIME SLOT 16

CHANNEL NUMBERS REFER TO TELEPHONE

CHANNEL NUMBERS. TIME SLOTS 1 TO 15 AND

17 TO 31 ARE ASSIGNED TO TELEPHONE

CHANNELS NUMBERED FROM 1 TO 30.

FAS FRAME

Si 0

0

1

0

1

TIME SLOT 1

TIME SLOT 31

PRIMARY BASIC FRAME

STRUCTURE

NOT FAS FRAME

Si 1 A SA4 SA5 SA6 SA7 SA8

TIME SLOT 31

256-bit FRAME = 125 µs

TIME SLOT 0

TIME SLOT 1

TIME SLOT 16

TIME SLOT 31

1

2

3

4

5

6

7

8

8-bit TIME SLOT = 3.90625 µs

5-4548(F).cr.1

Figure 23. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe

Structures

66

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT 2.048 Basic Frame Structure

The ITU Rec. G.704 Section 2.3.1 defined frame length is 256 bits, numbered 1 to 256. The frame repetition rate is

8 kHz. The allocation of bits numbered 1 to 8 of the frame is shown in Table 30.

Table 30. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame

Basic Frames

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

(MSB)

(LSB)

Frame Alignment Signal (FAS)

Si

0

1

0

1

0

1

Not Frame Alignment Signal (NOT FAS)

A

Sa4

Sa5

Sa6

Sa7

Sa8

The function of each bit in Table 30 is described below:

1. The Si bits are reserved for international use. A specific use for these bits is described in Table 31, ITU CRC-4

Multiframe Structure on page 70. If no use is realized, these bits should be fixed at 1 on digital paths crossing

an international border.

2. Bit 2 of the NOT FAS frames is fixed to 1 to assist in avoiding simulations of the frame alignment signal.

3. Bit 3 of the NOT FAS is the remote alarm indication (A bit). In undisturbed operation, this bit is set to 0; in alarm

condition, set to 1.

4. Bits 4—8 of the NOT FAS (Sa4—Sa8) may be recommended by ITU for use in specific point-to-point applica-

tions. Bit Sa4 may be used as a message-based data link for operations, maintenance, and performance mon-

itoring. If the data link is accessed at intermediate points with consequent alterations to the Sa4 bit, the CRC-4

bits must be updated to retain the correct end-to-end path termination functions associated with the CRC-4

procedure. The receive framer does not implement the CRC-4 modifying algorithm described in ITU Rec.

G.706 Annex C. Bits Sa4—Sa8, where these are not used, should be set to 1 on links crossing an international

border.

5. MSB = most significant bit and is transmitted first.

6. LSB = least significant bit and is transmitted last.

Agere Systems Inc.

67

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT 2.048 Basic Frame Structure (continued)

Transparent Framing Format

The transmit framer can be programmed to transparently transmit 256 bits of system data to the line. The transmit

framer must be programmed to either transparent framing mode 1 or transparent framing mode 2 (see Framer

Reset and Transparent Mode Control Register (FRM_PR26) on page 192).

In transparent mode 1 or mode 2, the transmit framer transmits all 256 bits of the RCHI payload unmodified to the

line. Time slot 1 of the RCHI, determined by the RCHIFS signal, is inserted into the FAS/NOTFAS time slot of the

transmit line interface.

Frame integrity is maintained in both the transmit and receive framer sections.

TIME SLOT 1 TIME SLOT 2 TIME SLOT 3

TIME SLOT 31 TIME SLOT 32

32 TIME-SLOT CHI FRAME

TIME SLOT 1 TIME SLOT 2 TIME SLOT 3

TIME SLOT 31 TIME SLOT 32

32 TIME-SLOT LINE FRAME

5-5988(F)

Figure 24. CEPT Transparent Frame Structure

In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than

bipolar violations and unframed AIS monitoring, there is no processing of the receive line data. The entire receive

line payload is transmitted unmodified to the CHI.

In transparent framing mode 2, the receive framer functions normally on the receive line data. All normal monitor-

ing of receive line data is performed and data is transmitted to the CHI as programmed.

68

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT Loss of Basic Frame Alignment (LFA)

Frame alignment is assumed to be lost when:

1. As described in ITU Rec. G.706 Section 4.1.1, three consecutive incorrect frame alignment signals have been

received.

2. So as to limit the effect of spurious frame alignment signals, when bit 2 in time slot 0 in NOT FAS frames have

been received with an error on three consecutive occasions.

3. Optionally, as described in ITU Rec. G.706 Section 4.3.2, by exceeding a count of >914 errored CRC-4 blocks

out of 1000, with the understanding that a count of ≥915 errored CRC blocks indicates false frame alignment.

4. On demand via the control registers.

In the LFA state:

1. No additional FAS or NOT FAS errors are processed.

2. The received remote frame alarm (received A bit) is deactivated.

3. All NOT-FAS bit (Si bit, A bit, and Sa4 to Sa8 bits) processing is halted.

4. Receive Sa6 status bits are set to 0.

5. Receive Sa6 code monitoring and counting is halted.

6. All receive Sa stack data updates are halted. The receive Sa stack ready, register FRM_SR4 bit 6 and bit 7, is

set to 0. If enabled, the receive Sa stack interrupt bit is set to 0.

7. Receive data link (RFDL) is set to 1 and RFDCLK maintains previous alignment.

8. Optionally, the remote alarm indication (A = 1) may be automatically transmitted to the line if register

FRM_PR27 bit 0 is set to 1.

9. Optionally, the alarm indication signal (AIS) may be automatically transmitted to the system if register

FRM_PR19 bit 0 is set to 1.

10. If CRC-4 is enabled, loss of CRC-4 multiframe alignment is forced.

11. If CRC-4 is enabled, the monitoring and processing of CRC-4 checksum errors is halted.

12. If CRC-4 is enabled, all monitoring and processing of received E-bit information is halted.

13. If CRC-4 is enabled, the receive continuous E-bit alarm is deactivated.

14. If CRC-4 is enabled, optionally, E bit = 0 is transmitted to the line for the duration of loss of CRC-4 multiframe

alignment if register FRM_PR28 bit 4 is set to 1.

15. If time slot 16 signaling is enabled, loss of the signaling multiframe alignment is forced.

16. If time slot 16 signaling is enabled, updating of the signaling data is halted.

CEPT Loss of Frame Alignment Recovery Algorithm

The receive framer begins the search for basic frame alignment one bit position beyond the position where the LFA

state was detected. As defined in ITU Rec. G.706.4.1.2, frame alignment will be assumed to have been recovered

when the following sequence is detected:

1. For the first time, the presence of the correct frame alignment signal in frame n.

2. The absence of the frame alignment signal in the following frame detected by verifying that bit 2 of the basic

frame is a 1 in frame n + 1.

3. For the second time, the presence of the correct frame alignment in the next frame, n + 2.

Failure to meet 2 or 3 above will initiate a new basic frame search in frame n + 2.

Agere Systems Inc.

69

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT Time Slot 0 CRC-4 Multiframe Structure

The CRC-4 multiframe is in bit 1 of each NOT FAS frame. As described in ITU Rec. G.704 Section 2.3.3.1, where

there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there

is a need for an enhanced error monitoring capability, then bit 1 of each frame may be used for a cyclic redundancy

check-4 (CRC-4) procedure as detailed below. The allocation of bits 1—8 of time slot 0 of every frame is shown in

Table 31 for the complete CRC-4 multiframe.

Table 31. ITU CRC-4 Multiframe Structure

Submultiframe

(SMF)

Frame

Number

Bits

1

C1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

0

4

1

5

6

0

7

1

8

1

I

0

1

A

0

Sa4

1

Sa5

1

Sa6

0

Sa7

1

Sa8

1

2

C2

0

3

A

0

Sa4

1

Sa5

1

Sa6

0

Sa7

1

Sa8

1

4

C3

1

5

A

0

Sa4

1

Sa5

1

Sa6

0

Sa7

1

Sa8

1

6

C4

0

Multiframe

7

A

0

Sa4

1

Sa5

1

Sa6

0

Sa7

1

Sa8

1

II

8

C1

1

9

A

0

Sa4

1

Sa5

1

Sa6

0

Sa7

1

Sa8

1

10

11

12

13

14

15

C2

1

A

0

Sa4

1

Sa5

1

Sa6

0

Sa7

1

Sa8

1

C3

E

A

0

Sa4

1

Sa5

1

Sa6

0

Sa7

1

Sa8

1

C4

E

A

Sa4

Sa5

Sa6

Sa7

Sa8

Notes:

C1 to C4 = cyclic redundancy check-4 (CRC-4) bits.

E = CRC-4 error indication bits.

Sa4 to Sa8 = spare bits.

A = remote frame alarm (RFA) bit (active-high); referred to as the A bit.

The CRC-4 multiframe consists of 16 frames numbered 0 to 15 and is divided into two eight-frame submultiframes

(SMF), designated SMF-I and SMF-II that signifies their respective order of occurrence within the CRC-4 multi-

frame structure. The SMF is the CRC-4 block size (2048 bits). In those frames containing the frame alignment sig-

nal (FAS), bit 1 is used to transmit the CRC-4 bits. There are four CRC-4 bits, designated C1, C2, C3, and C4 in

each SMF. In those frames not containing the frame alignment signal (NOT FAS), bit 1 is used to transmit the 6-bit

CRC-4 multiframe alignment signal and two CRC-4 error indication bits (E). The multiframe alignment signal is

defined in ITU Rec. G.704 Section 2.3.3.4, as 001011. Transmitted E bits should be set to 0 until both basic frame

and CRC-4 multiframe alignment are established. Thereafter, the E bits should be used to indicate received

errored submultiframes by setting the binary state of one E bit from 1 to 0 for each errored submultiframe. The

received E bits will always be taken into account, by the receive E-bit processor¹, even when the SMF that con-

tains them is found to be errored. In the case where there exists equipment that does not use the E bits, the state

of the E bits should be set to a binary 1 state.

1. The receive E-bit processor will halt the monitoring of the received E bit during the loss of CRC-4 multiframe alignment.

70

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT Time Slot 0 CRC-4 Multiframe Structure (continued)

The CRC-4 word, located in submultiframe N, is the remainder after multiplication by x⁴and then division

(modulo 2) by the generator polynomial x⁴+ x + 1, of the polynomial representation of the submultiframe N – 1.

Representing the contents of the submultiframe check block as a polynomial, the first bit in the block, i.e., frame 0,

bit 1 or frame 8, bit 1, is taken as being the most significant bit and the least significant bit in the check block is

frame 7 or frame 15, bit 256. Similarly, C1 is defined to be the most significant bit of the remainder and C4 the least

significant bit of the remainder. The encoding procedure, as described in ITU Rec. G.704 Section 2.3.3.5.2, fol-

lows:

1. The CRC-4 bits in the SMF are replaced by binary 0s.

2. The SMF is then acted upon the multiplication/division process referred to above.

3. The remainder resulting from the multiplication/division process is stored, ready for insertion into the respec-

tive CRC-4 locations of the next SMF.

The decoding procedure, as described in ITU Rec. G.704 Section 2.3.3.5.3, follows:

1. A received SMF is acted upon by the multiplication/division process referred to above, after having its CRC-4

bits extracted and replaced by 0s.

2. The remainder resulting from this division process is then stored and subsequently compared on a bit-by-bit

basis with the CRC bits received in the next SMF.

3. If the remainder calculated in the decoder exactly corresponds to the CRC-4 bits received in the next SMF, it is

assumed that the checked SMF is error-free.

CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA)

Loss of basic frame alignment forces the receive framer into a loss of CRC-4 multiframe alignment state. This state

is reported by way of the status registers FRM_SR1 bit 2. Once basic frame alignment is achieved, a new search

for CRC-4 multiframe alignment is initiated. During a loss of CRC-4 multiframe alignment state:

1. The CRC-4 error counter is halted.

2. The CRC-4 error monitoring circuit for errored seconds and severely errored seconds is halted.

3. The received E-bit counter is halted.

4. The received E-bit monitoring circuit for errored seconds and severely errored seconds at the remote end

interface is halted.

5. Receive continuous E-bit monitoring is halted.

6. All receive Sa6 code monitoring and counting functions are halted.

7. The updating of the receive Sa stack is halted and the receive Sa stack interrupt is deactivated.

8. Optionally, A = 1 may be automatically transmitted to the line if register FRM_PR27 bit 2 is set to 1.

9. Optionally, E = 0 may be automatically transmitted to the line if register FRM_PR28 bit 4 is set to 1.

10. Optionally, if LTS0MFA monitoring in the performance counters is enabled, by setting registers FRM_PR14

through FRM_PR17 bit 1 to 1, then these counts are incremented once per second for the duration of the

LTS0MFA state.

Agere Systems Inc.

71

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms

Several optional algorithms exist in the receive framer. These are selected through programming of register

FRM_PR9.

CRC-4 Multiframe Alignment Algorithm with 8 ms Timer

The default algorithm is as described in ITU Rec. G.706 Section 4.2. The recommendation states that if a condition

of assumed frame alignment has been achieved, CRC-4 multiframe alignment is deemed to have occurred if at

least two valid CRC-4 multiframe alignment signals can be located within 8 ms, the time separating two CRC-4

multiframe signals being 2 ms or a multiple of 2 ms. The search for the CRC-4 multiframe alignment signal is made

only in bit 1 of NOT FAS frames. If multiframe alignment cannot be achieved within 8 ms, it is assumed that frame

alignment is due to a spurious frame alignment signal and a new parallel search for basic frame alignment is initi-

ated. The new search for the basic frame alignment is started at the point just after the location of the assumed

spurious frame alignment signal. During this parallel search for basic frame alignment, there is no indication to the

system of a receive loss of frame alignment (RLFA) state. During the parallel search for basic frame alignment and

while in primary basic frame alignment, data will flow through the receive framer to the system interface as defined

by the current primary frame alignment. The receive framer will continuously search for CRC-4 multiframe align-

ment.

CRC-4 Multiframe Alignment Algorithm with 100 ms Timer

The CRC-4 multiframe alignment with 100 ms timer mode is enabled by setting FRM_PR9 to 0XXXX1X1 (binary).

This CRC-4 multiframe reframe mode starts a 100 ms timer upon detection of basic frame alignment. This is a par-

allel timer to the 8 ms timer. If CRC-4 multiframe alignment cannot be achieved within the time limit of 100 ms due

to the CRC-4 procedure not being implemented at the transmitting side, then an indication is given, and actions are

taken equivalent to those specified for loss of basic frame alignment, namely:

1. Optional automatic transmission of A = 1 to the line if register FRM_PR27 bit 3 is set to 1.

2. Optional automatic transmission of E = 0 to the line if register FRM_PR28 bit 5 is set to 1.

3. Optional automatic transmission of AIS to the system if register FRM_PR19 bit 1 is set to 1.

72

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms (continued)

OUT OF PRIMARY BFA:

• OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM

• OPTIONALLY TRANSMIT A = 1 AND E = 0 TO LINE

• INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING

PRIMARY

NO

BFA SEARCH?

YES

IN PRIMARY BFA:

• ENABLE TRAFFIC TO THE SYSTEM

• TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE

• START 8 ms AND 100 ms TIMERS

• ENABLE PRIMARY BFA LOSS CHECKING PROCESS

YES

CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2 - NOTE 2)

PARALLEL

BFA SEARCH

GOOD?

NO

YES

NO

IS

100 ms

TIMER

ELAPSED?

NO

CAN CRC-4

MFA BE FOUND

IN 8 ms?

NO

YES

INTERNAL

100 ms TRX = 1

?

YES

SET 100 ms TIMER EXPIRATION STATUS BIT TO THE 1 STATE:

SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 1:

• OPTIONALLY TRANSMIT A BIT = 1 TO THE LINE INTERFACE FOR

THE DURATION OF LTS0MFA = 1

ASSUME CRC-4 MULTIFRAME ALIGNMENT:

• CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA

• ADJUST PRIMARY BFA IF NECESSARY

• OPTIONALLY TRANSMIT AIS TO THE SYSTEM INTERFACE FOR THE

DURATION OF LTS0MFA = 1

• OPTIONALLY TRANSMIT E BIT = 0 TO THE LINE INTERFACE FOR

THE DURATION OF LTSOMFA = 1

YES

IS 100 ms TRX = 1

?

SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 0:

• IF TRANSMITTING A BIT = 1 TO THE LINE INTERFACE, TRANSMIT A BIT = 0

• IF TRANSMITTING AIS TO THE SYSTEM INTERFACE, ENABLE DATA

TRANSMISSION TO THE SYSTEM INTERFACE

NO

• IF TRANSMITTING E = 0 TO THE LINE INTERFACE, TRANSMIT E BIT = 1

START CRC-4 PERFORMANCE MONITORING:

• SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4

CRC-4

YES

COUNT > 914

IN 1 SECOND OR

LFA = 1?

NO

CONTINUE CRC-4 PERFORMANCE MONITORING:

• SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4

5-3909(F).er.2

Figure 25. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer

Agere Systems Inc.

73

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms (continued)

CRC-4 Multiframe Alignment Search Algorithm with 400 ms Timer

The CRC-4 multiframe alignment with 400 ms timer mode is enabled by setting FRM_PR9 to 0XXX1XX1 (binary).

This receive CRC-4 multiframe reframe mode is the modified CRC-4 multiframe alignment algorithm described in

ITU Rec. 706 Annex B, where it is referred to as CRC-4-to-Non-CRC-4 equipment interworking. A flow diagram of

this algorithm is illustrated in Figure 26 on page 75. When the interworking algorithm is enabled, it supersedes the

100 ms algorithm described on page 72 and in Figure 25 on page 73. This algorithm assumes that a valid basic

frame alignment signal is consistently present but the CRC-4 multiframe alignment cannot be achieved by the end

of the total CRC-4 multiframe alignment search period of 400 ms, if the distant end is a non-CRC-4 equipment. In

this mode, the following consequent actions are taken:

1. An indication that there is no incoming CRC-4 multiframe alignment signal.

2. All CRC-4 processing on the receive 2.048 Mbits/s signal is inhibited.

3. CRC-4 data is transmitted to the distant end with both E bits set to zero.

This algorithm allows the identification of failure of CRC-4 multiframe alignment generation/detection, but with cor-

rect basic framing, when interworking between each piece of equipment having the modified CRC-4 multiframe

alignment algorithm.

As described in ITU Rec. G.706 Section B.2.3:

1. A 400 ms timer is triggered on the initial recovery of the primary basic frame alignment.

2. The 400 ms timer reset if and only if:

A. The criteria for loss of basic frame alignment as described in ITU Rec. G.706 Section 4.1.1 is achieved.

B. If 915 out of 1000 errored CRC-4 blocks are detected resulting in a loss of basic frame alignment as

described in ITU Rec. G.706 Section 4.3.2.

C. On-demand reframe is requested.

D. The receive framer is programmed to the non-CRC-4 mode.

3. The loss of basic frame alignment checking process runs continuously, irrespective of the state of the CRC-4

multiframe alignment process below it.

4. A new search for frame alignment is initiated if CRC-4 multiframe alignment cannot be achieved in 8 ms, as

described in ITU Rec. G.706 Section 4.2. This new search for basic frame alignment will not reset the 400 ms

timer or invoke consequent actions associated with loss of the primary basic frame alignment. In particular, all

searches for basic frame alignment are carried out in parallel with, and independent of, the primary basic frame

loss checking process. All subsequent searches for CRC-4 multiframe alignment are associated with each

basic framing sequence found during the parallel search.

5. During the search for CRC-4 multiframe alignment, traffic is allowed through, upon, and to be synchronized to,

the initially determined primary basic frame alignment.

6. Upon detection of the CRC-4 multiframe before the 400 ms timer elapsing, the basic frame alignment associ-

ated with the CRC-4 multiframe alignment replaces, if necessary, the initially determined basic frame align-

ment.

7. If CRC-4 multiframe alignment is not found before the 400 ms timer elapses, it is assumed that a condition of

interworking between equipment with and without CRC-4 capability exists and the actions described above are

taken.

8. If the 2.048 Mbits/s path is reconfigured at any time, then it is assumed that the (new) pair of path terminating

equipment will need to re-establish the complete framing process, and the algorithm is reset.

74

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms (continued)

OUT OF PRIMARY BFA:

• OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM

• OPTIONALLY TRANSMIT A BIT = 1 AND E BIT = 0 TO LINE

• INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING

PRIMARY

NO

BFA SEARCH?

YES

IN PRIMARY BFA:

• ENABLE TRAFFIC NOT TRANSMITTING AIS TO THE SYSTEM

• TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE

• START 400 ms TIMER

• ENABLE PRIMARY BFA LOSS CHECKING PROCESS

YES

CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2)

NO

PARALLEL

BFA SEARCH

?

NO

400 ms

TIMER

ELAPSED?

NO

CAN CRC-4

MFA BE FOUND

IN 8 ms?

YES

ASSUME CRC-4-TO-CRC-4 INTERWORKING:

ASSUME CRC-4-TO-NON-CRC-4 INTERWORKING:

• CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA

• ADJUST PRIMARY BFA IF NECESSARY

• KEEP A = 0 IN OUTGOING CRC-4 DATA

• CONFIRM PRIMARY BFA

• TRANSMIT A BIT = 0 TO THE LINE INTERFACE

• TRANSMIT E BIT = 0 TO THE LINE INTERFACE

• STOP INCOMING CRC-4 PROCESSING

• INDICATE “NO CRC-4 MFA”

START CRC-4 PERFORMANCE MONITORING:

• SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4

CRC-4

COUNT > 914

IN 1 SECOND OR

LFA = 1?

YES

NO

CONTINUE CRC-4 PERFORMANCE MONITORING:

• SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4

5-3909(F).fr.3

Figure 26. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment

Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991)

Agere Systems Inc.

75

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT Time Slot 16 Multiframe Structure

The T7633 supports three CEPT signaling modes: channel associated signaling (CAS) or per-channel signaling

(PSC0 and PSC1); common channel signaling (CCS) (T7230A mode)¹; and international remote switching module

(IRSM) signaling.

1. See Agere Systems T7230A Primary Access Framer/Controller Preliminary Data Sheet (DS96-007TIC) pages 49—50.

Channel Associated Signaling (CAS)

The channel associated signaling (CAS) mode utilizes time slot 16 of the FAS and NOT FAS frames. The CAS for-

mat is a multiframe consisting of 16 frames where frame 0 of the multiframe contains the multiframe alignment pat-

tern of four zeros in bits 1 through 4. Table 32 illustrates the CAS multiframe of time slot 16. The T7633 can be

programmed to force the transmitted line CAS multiframe alignment pattern to be transmitted in the FAS frame by

selecting the PCS0 option or in the NOT FAS frame by selecting the PCS1 option. Alignment of the transmitted line

CAS multiframe to the CRC-4 multiframe is arbitrary.

Table 32. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure

Frame

Bit

Number

1

2

3

4

5

6

7

8

0

1

0

X0

YM

X1

X2

A1

B1

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

D1

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

2

A2

B2

D2

3

A3

B3

D3

4

A4

B4

D4

5

A5

B5

D5

6

A6

B6

D6

7

A7

B7

D7

Time Slot 16

Channel

Associated

Signaling

8

A8

B8

D8

9

A9

B9

D9

10

11

12

13

14

15

A10

A11

A12

A13

A14

A15

B10

B11

B12

B13

B14

B15

D10

D11

D12

D13

D14

D15

Multiframe

Notes:

Frame 0 bits 1—4 define the time slot 16 multiframe alignment.

X0—X2 = time slot 16 spare bits defined in FRM_PR41 bit 0—bit 2.

Y^M= yellow alarm, time slot 16 remote multiframe alarm (RMA) bit (1 = alarm condition).

Common Channel Signaling (T7230A Mode) (CCS)

In the common channel signaling mode, selected if FRM_PR44 bit 4 = 1, data contained in the transmit signaling

registers, FRM_TSR0—FRM_TSR31, is written transparently into time slot 16 of the transmit line bit stream. The

received signaling data from time slot 16 is stored transparently in receive signaling registers FRM_RSR0—

FRM_RSR31.

76

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT Time Slot 16 Multiframe Structure (continued)

International Remote Switching Module (IRSM) Signaling

This signaling mode is similar to the channel associated signaling mode, i.e., time slot 16 contains the signaling

multiframe information (ABCD signaling bits). In addition, time slot 0 Sa5 to Sa8 bit positions of the NOT FAS

frame contains per-channel control information. The format of the time slot 0 per-channel control information is

illustrated in Table 33. The IRSM mode forces the transmit framer to align the time slot 16 multiframe to the FAS

frame (PCS0 mode).

Table 33. CEPT IRSM Signaling Multiframe Structure

Frame

IRSM Bits in Time Slot 0

Bits in Time Slot 16

Number

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

0

4

1

5

1

6

0

7

8

1

2

3

4

5

6

7

8

0

1

Si

1

0

X0

YM

X1

X2

A

0

D

1

E0

1

E1

0

E16 E17

A1

B1

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

2

1

A2

B2

3

A

0

D

1

E2

1

E3

0

E18 E19

A3

B3

4

1

A4

B4

5

A

0

D

1

E4

1

E5

0

E20 E21

A5

B5

6

1

A6

B6

7

A

0

D

1

E6

1

E7

0

E22 E23

A7

B7

8

1

A8

B8

9

A

0

D

1

E8

1

E9

0

E24 E25

A9

B9

10

11

12

13

14

15

1

A10

A11

A12

A13

A14

A15

B10

B11

B12

B13

B14

B15

A

0

D

1

E10 E11 E26 E27

1

0

1

A

0

D

1

E12 E13 E28 E29

1

0

1

A

D

E14 E15 E30 E31

Notes:

Si = time slot 0 control bits. If programmed for CRC-4 mode, then these bits contain the CRC-4 multiframe pattern, checksum, and E-bit

information.

Ei = IRSM per-channel control bits.

X0—X2 = time slot 16 spare bits defined in FRM_PR41 bit 0—bit 2.

Ai—Di = time slot 16 channel associated signaling bits.

Y^M= yellow alarm, time slot 16 remote multiframe alarm (RMA) bit (1 = alarm condition).

Agere Systems Inc.

77

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Frame Formats (continued)

CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA)

Loss of basic frame alignment forces the receive framer into a loss of time slot 16 signaling multiframe alignment

state. In addition, as defined in ITU Rec. G.732 Section 5.2, time slot 16 signaling multiframe is assumed lost when

two consecutive time slot 16 multiframe 4-bit all-zero patterns is received with an error. In addition, the time slot 16

multiframe is assumed lost when, for a period of two multiframes, all bits in time slot 16 are in state 0. This state is

reported by way of the status registers FRM_SR1 bit 1. Once basic frame alignment is achieved, the receive

framer will initiate a search for the time slot 16 multiframe alignment. During a loss of time slot 16 multiframe align-

ment state:

1. The updating of the signaling data is halted.

2. The received control bits forced to the binary 1 state.

3. The received remote multiframe alarm indication status bit is forced to the binary 0 state.

4. Optionally, the transmit framer can transmit to the line the time slot 16 signaling remote multiframe alarm if reg-

ister FRM_PR41 bit 4 is set to 1.

5. Optionally, the transmit framer can transmit the alarm indication signal (AIS) in the system transmit time slot 16

data if register FRM_PR44 bit 6 is set to 1.

CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm

The time slot 16 multiframe alignment recovery algorithm is as described in ITU Rec. G.732 Section 5.2. The rec-

ommendation states that if a condition of assumed frame alignment has been achieved, time slot 16 multiframe

alignment is deemed to have occurred when the 4-bit time slot 16 multiframe pattern of 0000 is found in time slot

16 for the first time, and the preceding time slot 16 contained at least one bit in the binary 1 state.

78

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

CEPT Time Slot 0 FAS/NOT FAS Control Bits

FAS/NOT FAS Si- and E-Bit Source

The Si bit can be used as an 8 kbits/s data link to and from the remote end, or in the CRC-4 mode, it can be used

to provide added protection against false frame alignment. The sources for the Si bits that are transmitted to the

line are the following:

1. CEPT with no CRC-4 and FRM_PR28 bit 0 = 1: the TSiF control bit (FRM_PR28 bit 1) is transmitted in bit 1 of

all FAS frames and the TSiNF control bit (FRM_PR28 bit 2) is transmitted in bit 1 of all NOT FAS frames.

2. The CHI system interface (CEPT with no CRC-4 and FRM_PR28 bit 0 = 0)¹.

This option requires the received system data (RCHIDATA) to maintain a biframe alignment pattern where

frames containing Si bit information for the NOT FAS frames have bit 2 of time slot 0 in the binary 1 state fol-

lowed by frames containing Si bit information for the FAS frames that have bit 2 of time slot 0 in the binary 0

state. This ensures the proper alignment of the Si received system data to the transmit line Si data. Whenever

this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition

(indication is given in the status registers) and then search for the pattern; in the loss of biframe alignment

state, transmitted line data is corrupted (only when the system interface is sourcing Sa or Si data). When the

transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the

transmit framer resumes normal operations.

3. CEPT with CRC-4²: manual transmission of E bit = 0:

A. If FRM_PR28 bit 0 = 0, then the TSiF bit (FRM_PR28 bit 1) is transmitted in bit 1 of frame 13 (E bit) and

the TSiNF bit (FRM_PR28 bit 2) is transmitted in bit 1 of frame 15 (E bit).

B. If FRM_PR28 bit 0 = 1, then each time 0 is written into TSiF (FRM_PR28 bit 1) one E bit = 0 is transmitted

in frame 13, and each time 0 is written into TSiNF (FRM_PR28 bit 2) one E bit = 0 is transmitted in frame

15.

4. CEPT with CRC-4², automatic transmission of E bit = 0:

A. Optionally, one transmitted E bit is set to 0 by the transmit framer, as described in ITU Rec. G.704 Section

2.3.3.4, for each received errored CRC-4 submultiframe detected by the receive framer if FRM_PR28

bit 3 = 1.

B. Optionally, as described in ITU Rec. G.704 Section 2.3.3.4, both E bits are set to 0 while in a received loss

of CRC-4 multiframe alignment state³if FRM_PR28 bit 4 = 1.

C. Optionally, when the 100 ms or 400 ms timer is enabled and the timer has expired, as described in ITU

Rec. G.706 Section B.2.2, both E bits are set to 0 for the duration of the loss of CRC-4 multiframe

alignment state³if FRM_PR28 bit 5 = 1.

Otherwise, the E bits are transmitted to the line in the 1 state.

1.Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx

(binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.

2.The receive E-bit processor will halt the monitoring of received E bits during loss of CRC-4 multiframe alignment.

3.Whenever loss of frame alignment occurs, then loss of CRC-4 multiframe alignment is forced. Once frame alignment is established, then and

only then, is the search for CRC-4 multiframe alignment initiated. The receive framer unit, when programmed for CRC-4, can be in a state of

LFA and LTS0MFA or in a state of LTS0MFA only, but cannot be in a state of LFA only.

Agere Systems Inc.

79

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)

NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources

The A bit, as described in ITU Rec. G.704 Section 2.3.2 Table 4a/G.704, is the remote alarm indication bit. In

undisturbed conditions, this bit is set to 0 and transmitted to the line. In the loss of frame alignment (LFA) state, this

bit may be set to 1 and transmitted to the line as determined by register FRM_PR27. The A bit is set to 1 and trans-

mitted to the line for the following conditions:

1. Setting the transmit A bit = 1 control bit by setting register FRM_PR27 bit 7 to 1.

2. Optionally for the following alarm conditions as selected through programming register FRM_PR27.

A. The duration of loss of basic frame alignment as described in ITU Rec. G.706 Section 4.1.1¹, or ITU Rec.

G.706 Section 4.3.2²if register FRM_PR27 bit 0 = 1.

B. The duration of loss of CRC-4 multiframe alignment if register FRM_PR27 bit 2 = 1.

C. The duration of loss of signaling time slot 16 multiframe alignment if register FRM_PR27 bit 1 = 1.

D. The duration of loss of CRC-4 multiframe alignment after either the 100 ms or 400 ms timer expires if

register FRM_PR27 bit 3 = 1.

E. The duration of receive Sa6_8hex³if register FRM_PR27 bit 4 = 1.

F. The duration of receive Sa6_Chex³if register FRM_PR27 bit 5 = 1.

1. LFA is due to framing bit errors.

2. LFA is due to detecting 915 out of 1000 received CRC-4 errored blocks.

3. See Table 41, Sa6 Bit Coding Recognized by the Receive Framer on page 95, for a definition of this Sa6 pattern.

NOT FAS Sa-Bit Sources*

The Sa bits, Sa4—Sa8, in the NOT FAS frame can be a 4 kbits/s data link to and from the remote end. The sources

and value for the Sa bits are:

1. The Sa source register FRM_PR29 bit 0—bit 4 if FRM_PR29 bit 7—bit 5 = 000 (binary) and FRM_PR30 bit 4—

bit 0 = 11111 (binary).

2. The facility data link external input (TFDL) if register FRM_PR29 bit 7 = 1 and register FRM_PR21 bit 6 = 1.

3. The internal FDL-HDLC if register FRM_PR29 bit 7 = 1 and register FRM_PR21 bit 6 = 0.

4. The Sa transmit stack if register FRM_PR29 bit 7—bit 5 are set to 01x (binary).

5. The CHI system interface if register FRM_PR29 bit 7—bit 5 are set to 001 (binary). This option requires the

received system data (RCHIDATA) to maintain a biframe alignment pattern where (1) frames containing Sa bit

information have bit 2 of time slot 0 in the binary 1 state and (2) these NOT FAS frames are followed by frames

not containing Sa bit information, the FAS frames, which have bit 2 of time slot 0 in the binary 0 state. This

ensures the proper alignment of the Sa received system data to the transmit line Sa data. Whenever this

requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition indi-

cated in the status register, FRM_SR1 bit 4, and then search for the pattern. In the loss of biframe alignment

state, transmitted line data is corrupted (only when the system interface is sourcing Sa or Si data). When the

transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the

transmit framer resumes normal operations.

The receive Sa data is present at:

A. The Sa received stack, registers FRM_SR54—FRM_SR63, if the T7633 is programmed in the Sa stack

mode.

B. The system transmit interface.

The status of the received Sa bits and the received Sa stack is available in status register FRM_SR4. The transmit

and receive Sa bit for the FDL can be selected by setting register FRM_PR43 bit 0—bit 2 as shown in Table 167.

*

Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx

(binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.

80

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)

Sa Facility Data Link Access

The data link interface may be used to source one of the Sa bits. Access is controlled by registers FRM_PR29,

FRM_PR30, and FRM_PR43, see NOT FAS Sa-Bit Sources on page 80. The receive Sa data is always present at

the receive facility data link output pin, RFDL, along with a valid clock signal at the receive facility clock output pin,

RFDLCK. During a loss of frame alignment (LFA) state, the RFDL signal is forced to a 1 state while RFDLCK

continues to toggle on the previous frame alignment. When basic frame alignment is found, RFDL is as received

from the selected receive Sa bit position and RFDLCK is forced (if necessary) to the new alignment. The data rate

for this access mode is 4 kHz. The access timing for the transmit and receive facility data is illustrated in Figure 27

below. During loss of receive clock (LOFRMRLCK), RFDL and RFDLCK are frozen in a state at the point of the

LOFRMRLCK being asserted.

t8

t8: TFDLCK CYCLE = 250 µs

TFDLCK

t9

t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns

TFDL

t10

t10: RFDLCK CYCLE = 250 µs

RFDLCK

RFDL

t11: RFDLCK TO RFDL DELAY = 40 ns

t11

5-3910(F).dr.1

Figure 27. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT

Mode

Agere Systems Inc.

81

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)

NOT FAS Sa Stack Source and Destination

The transmit Sa4 to Sa8 bits may be sourced from the transmit Sa stack, registers FRM_PR31—FRM_PR40. The

Sa stack consists of ten 8-bit registers that contain 16 NOT FAS frames of Sa information as shown in Table 23.

The transmit stack data may be transmitted either in non-CRC-4 mode or in CRC-4 mode to the line.

The receive stack data, registers FRM_SR54—FRM_SR63, is valid in both the non-CRC-4 mode and the CRC-4

mode. In the non-CRC-4 mode while in the loss of frame alignment (LFA) state, updating of the receive Sa stack is

halted and the transmit and receive stack interrupts are deactivated. In the CRC-4 mode while in the loss of time

slot 0 multiframe alignment (LTS0MFA) state, updating of the receive Sa stack is halted and the transmit and

receive stack interrupts are deactivated.

Table 34. Transmit and Receive Sa Stack Structure

Register

Number

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

1

2

Sa4-1

Sa4-17

Sa5-1

Sa4-3

Sa4-19

Sa5-3

Sa4-5

Sa4-21

Sa5-5

Sa4-7

Sa4-23

Sa5-7

Sa4-9

Sa4-25

Sa5-9

Sa4-11

Sa4-27

Sa5-11

Sa5-27

Sa6-11

Sa6-27

Sa7-11

Sa7-27

Sa8-11

Sa8-27

Sa4-13

Sa4-29

Sa5-13

Sa5-29

Sa6-13

Sa6-29

Sa7-13

Sa7-29

Sa8-13

Sa8-29

Sa4-15

Sa4-31

Sa5-15

Sa5-31

Sa6-15

Sa6-31

Sa7-15

Sa7-31

Sa8-15

Sa8-31

3

4

Sa5-17

Sa6-1

Sa5-19

Sa6-3

Sa5-21

Sa6-5

Sa5-23

Sa6-7

Sa5-25

Sa6-9

5

6

Sa6-17

Sa7-1

Sa6-19

Sa7-3

Sa6-21

Sa7-5

Sa6-23

Sa7-7

Sa6-25

Sa7-9

7

8

Sa7-17

Sa8-1

Sa7-19

Sa8-3

Sa7-21

Sa8-5

Sa7-23

Sa8-7

Sa7-25

Sa8-9

9

10

Sa8-17

Sa8-19

Sa8-21

Sa8-23

Sa8-25

The most significant bit of the first byte is transmitted to the line in frame 1 of a double CRC-4 multiframe. The least

significant bit of the second byte is transmitted to the line in frame 31 of the double CRC-4 multiframe. The protocol

for accessing the Sa Stack information for the transmit and receive Sa4 to Sa8 bits is shown in Figure 28 and

described briefly below.

The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 7 (CEPT

transmit Sa stack ready) high. At this time, the system has about 4 ms to update the stack. Data written to the stack

during this interval will be transmitted during the next double CRC-4 multiframe. By reading register FRM_SR4

bit 7, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the transmit stack

is not updated, then the content of the stack is retransmitted to the line. The 32-frame interval of the transmit framer

in the Non-CRC-4 mode is arbitrary. Enabling transmit CRC-4 mode forces the updating of the internal transmit

stack at the end of the 32-frame CRC-4 double multiframe; the transmit Sa stack is then transmitted synchronous

to the transmit CRC-4 multiframe structure.

On the receive side, the T7633 indicates that it has received data in the receive Sa stack, register FRM_SR54—

FRM_SR63, by setting register FRM_SR4 bit 6 (CEPT receive Sa stack ready) high. The system then has about

4 ms to read the contents of the stack before it is updated again (old data lost). By reading register FRM_SR4 bit 6,

the system clears this bit so that it can indicate the next time the receive stack is ready. The receive framer always

updates the content of the receive stack so unread data will be overwritten. The last 16 valid Sa4 to Sa8 bits are

always stored in the receive Sa stack on a double-multiframe boundary. The 32-frame interval of the receive framer

in the non-CRC-4 mode is arbitrary. Enabling the receive CRC-4 mode forces updating of the receive Sa stack at

the end of the 32-frame CRC-4 double multiframe. The receive Sa stack is received synchronous to the CRC-4

multiframe structure.

82

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)

NOT FAS Sa Stack Source and Destination (continued)

SYSTEM ACCESS Sa STACK (SASS) INTERVAL:

1) TRANSMIT FRAMER UNIT TRANSMITS TO THE LINE

THE DATA IN THE TRANSMIT Sa STACK WRITTEN DURING

THE PREVIOUS SASS INTERVAL.

2) THE SYSTEM CAN UPDATE THE TRANSMIT Sa STACK

REGISTERS FOR TRANSMISSION IN THE NEXT CRC-4

DOUBLE MULTIFRAME.

3) THE SYSTEM CAN READ THE RECEIVE Sa STACK REGISTERS

TO ACCESS THE Sa BITS EXTRACTED DURING THE PREVIOUS

VALID (IN MULTIFRAME ALIGNMENT) DOUBLE CRC-4

MULTIFRAME.

START OF CRC-4 DOUBLE MULTIFRAME:

• BASIC FRAME ALIGNMENT FOUND, OR,

• CRC-4 MULTIFRAME ALIGNMENT FOUND.

SYSTEM ACCESS Sa STACK INTERVAL

1-FRAME INTERVAL

1 FRAME

31 FRAMES

CRC-4 DOUBLE MULTIFRAME: 32 FRAMES

31 FRAMES

CRC-4 DOUBLE MULTIFRAME

(DMF): 32 FRAMES

START FRAME 1 OF 32 IN DMF.

INTERNAL Sa STACK UPDATE INTERVAL

SYSTEM ACCESS IS DISABLED DURING THIS INTERVAL:

1) THE INTERNAL TRANSMIT Sa STACK IS UPDATED

FROM THE FRAMER UNIT’S 10-byte TRANSMIT STACK CONTROL

REGISTERS DURING THIS 1-FRAME INTERVAL.

2) ACCESS TO THE STACK CONTROL REGISTERS IS DISABLED

DURING THIS 1-FRAME INTERVAL.

3)

ONCE LOADED, THE INFORMATION IN THE INTERNAL TRANSMIT

Sa STACK IS TRANSMITTED TO THE LINE DURING THE NEXT

CRC-4 DOUBLE MULTIFRAME, ALIGNED TO THE CRC-4 MULTIFRAME.

4)

IF THE TRANSMIT Sa STACK IS NOT UPDATED, THEN THE

CONTENT OF THE TRANSMIT Sa STACKS IS RETRANSMITTED

TO THE LINE.

5)

6)

THE SYSTEM READ-ONLY RECEIVE STACK IS UPDATED FROM

THE INTERNAL RECEIVE STACK INFORMATION REGISTERS.

IN NON-CRC-4 MODE, THE RECEIVE Sa STACK EXTRACTING

CIRCUITRY ASSUMES AN ARBITRARY DOUBLE 16-FRAME MULTIFRAME STRUCTURE

(32 FRAMES), AND DATA IS EXTRACTED ONLY IN THE FRAME ALIGNED STATE.

7)

IN CRC-4 MODE, THE RECEIVE Sa STACK INFORMATION IS ALIGNED

TO A CRC-4 DOUBLE MULTIFRAME STRUCTURE (32 FRAMES), AND THE

DATA IS EXTRACTED ONLY IN CRC-4 MULTIFRAME ALIGNED STATE.

5-3911(F).c

Figure 28. Transmit and Receive Sa Stack Accessing Protocol

Agere Systems Inc.

83

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)

NOT FAS Sa Stack Source and Destination (continued)

Interrupts indicating the transmit Sa stack or the receive Sa stack are ready for system access are available, see

register FRM_SR4 bit 6 and bit 7.

CEPT Time Slot 16 X0—X2 Control Bits

Each of the three X bits in frame 0 of the time slot 16 multiframe can be used as a 0.5 kbits/s data link to and from

the remote end. The transmitted line X bits are sourced from control register FRM_PR41 bit 0—bit 2. In the loss of

TS16 multiframe alignment (LTS16MFA) state, receive X bits are set to 1 in status register FRM_SR53.

84

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Signaling Access

Signaling information can be accessed by three different methods: transparently through the CHI, via the control

registers, or via the CHI associated signaling mode.

Transparent Signaling

This mode is enabled by setting register FRM_PR44 bit 0 to 1.

Data at the received RCHIDATA interface passes through the framer undisturbed. The framer generates an arbi-

trary signaling multiframe in the transmit and receive directions to facilitate the access of signaling information at

the system interface.

DS1: Robbed-Bit Signaling

Microprocessor Control Registers

To enable signaling, register FRM_PR44 bit 0 must be set to 0 (default).

The information written into the F and G bits of the transmit signaling registers, FRM_TSR0—FRM_TSR23, define

the robbed-bit signaling mode for each channel for both the transmit and receive directions. The per-channel pro-

gramming allows the system to combine voice channels with data channels within the same frame.

The receive-channel robbed-bit signaling mode is always defined by the state of the F and G bits in the corre-

sponding transmit signaling registers for that channel. The received signaling data is stored in the receive signaling

registers, FRM_RSR0—FRM_RSR23, while receive framer is in both the frame and superframe alignment states.

Updating the receive signaling registers can be inhibited on-demand, by setting register FRM_PR44 bit 3 to 1, or

automatically when either a framing error event, a loss of frame, or superframe alignment state is detected or a

controlled slip event occurs. The signaling inhibit state is valid for at least 32 frames after any one of the following:

a framing errored event, a loss of frame and/or superframe alignment state, or a controlled slip event.

In the common channel signaling mode, data written in the transmit signaling registers is transmitted in channel 24

of the transmit line bit stream. The F and G bits are ignored in this mode. The received signaling data from channel

24 is stored in receive signaling registers FRM_RSR0—FRM_RSR23 for T1.

Associated Signaling Mode

This mode is enabled by setting register FRM_PR44 bit 2 to 1.

Signaling information in the associated signaling mode (ASM) is allocated an 8-bit system time slot in conjunction

with the pay load data information for a particular channel. The default system data rate in the ASM mode is

4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its corresponding 8-bit sig-

naling time slot. The format of the signaling byte is identical to that of the signaling registers.

In the ASM mode, writing the transmit signaling registers will corrupt the transmit signaling data. In the transmit sig-

naling register ASM (TSR-ASM) format, enabled by setting register FRM_PR44 bit 2 and bit 5 to 1, the system

must write into the F and G bit¹of the transmit signaling registers to program the robbed-bit signaling state mode of

each DS0. The ABCD bits are sourced from the RCHI ports when TSR-ASM mode is enabled.

1. All other bits in the signaling registers are ignored, while the F and G bits in the received RCHIDATA stream are ignored.

Agere Systems Inc.

85

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Signaling Access (continued)

DS1: Robbed-Bit Signaling (continued)

Table 35 illustrates the ASM time-slot format for valid channels.

Table 35. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames

DS1: ASM CHI Time Slot

PAYLOAD DATA

SIGNALING INFORMATION*

P^†

1

2

3

4

5

6

7

8

A

B

C

D

X

F

G

* X indicates bits that are undefined by the framer.

† The identical sense of the received system P bit in the transmitted signaling data is echoed back to the system in the received signaling

information.

The DS1 framing formats require rate adaptation from the line-interface 1.544 Mbits/s bit stream to the system-

interface 4.096 Mbits/s bit stream. The rate adaptation results in the need for stuffed time slots on the system inter-

face. Table 36 illustrates the ASM format for T1 stuffed channels used by the T7633. The stuffed data byte contains

the programmable idle code in register FRM_PR23 (default = 7F (hex)), while the signaling byte is ignored.

Table 36. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels

ASM CHI Time Slot

PAYLOAD DATA

SIGNALING INFORMATION*

0

1

X

* X indicates bits which are undefined by the framer.

CEPT: Time Slot 16 Signaling

Microprocessor Control Registers

To enable signaling, register FRM_PR44 bit 0 must be set to 0 (default).

The information written into transmit signaling control registers FRM_TSR0—FRM_TSR31 define the state of the

ABCD bits of time slot 16 transmitted to the line.

The received signaling data from time slot 16 is stored in receive signaling registers FRM_RSR0—FRM_RSR31.

Associated Signaling Mode

Signaling information in the associated signaling mode (ASM), register FRM_PR44 bit 2 = 1, is allocated an 8-bit

system time slot in conjunction with the data information for a particular channel. The default system data rate in

the ASM mode is 4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its associ-

ated 8-bit signaling time slot. The format of the signaling byte is identical to the signaling registers.

Table 37 illustrates the ASM time-slot format for valid CEPT E1 time slots.

Table 37. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT

CEPT ASM CHI Time Slot

PAYLOAD DATA

SIGNALING INFORMATION

D E* X^†X^†P^‡

1

2

3

4

5

6

7

8

A

B

C

* In the CEPT IRSM format, this bit position contains the per-channel E0-31 control information. In all other formats, this bit is ignored.

† In the CEPT formats, these bits are undefined.

‡ The P bit is the parity-sense bit calculated over the 8 data bits, the ABCD (and E) bits, and the P bit. The identical sense of the received sys-

tem P bit in the transmitted signaling data is echoed back to the system in the received signaling information.

86

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Auxiliary Framer I/O Timing

Transmit and receive clock and data signals are provided by terminals RFRMCK (receive framer clock), RFRM-

DATA (receive framer data), RFS (receive frame sync), RSSFS (receive framer signaling superframe sync),

RCRCMFS (receive frame CRC-4 multiframe sync), TFS (transmit framer frame sync), TSSFS (transmit framer

signaling superframe sync), and TCRCMFS (transmit framer CRC-4 multiframe sync).

The receive signals are synchronized to the internal recovered receive line clock, RFRMCK, and the transmit sig-

nals are synchronized to the transmit line clock, TLCK. Note that TLCK is derived from the external PLLCK which

must be phase-locked to the system (CHI) clock, RCHICK, see Table 1, Pin Descriptions on page 20, pin 7 and pin

31.

Detailed timing specifications for these signals are given in Figure 29—Figure 36.

RFRMCK

125 µs

RFS

RFRMDATA

BIT 8 BIT 0 BIT 1

TIME SLOT 1

TIME SLOT 24

DATA VALID

5-6290(F)r.5

Figure 29. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode

TLCK

TFS

125 µs

TPD

(SINGLE

RAIL)

TS1

TS2

TS24

TS1

5-6292(F)r.6

Figure 30. Timing Specification for TFS, TLCK, and TPD in DS1 Mode

Agere Systems Inc.

87

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Auxiliary Framer I/O Timing (continued)

RFRMCK

RFS

125 µs

RFRMDATA

BIT 8 BIT 0 BIT 1

FAS/NFAS: TIME SLOT 0

DATA VALID

TIME SLOT 31

5-6294(F)r.5

Figure 31. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode

RFRMCK

RFS

125 µs

2 ms

RSSFS

RFRMDATA

TS0 OF THE FRAME AFTER THE

FRAME CONTAINING THE

SIGNALING MULTIFRAME

PATTERN (0000)

TS0 OF THE FRAME AFTER THE

FRAME CONTAINING THE

SIGNALING MULTIFRAME

PATTERN (0000)

5-6295(F)r.7

Figure 32. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode

88

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Auxiliary Framer I/O Timing (continued)

RFRMCLK

RFS

2 ms

RCRCMFS

RFRMDATA

TS0 OF FRAME #0

OF MULTIFRAME

TS0 OF FRAME #0

OF MULTIFRAME

5-6296(F)r.5

Figure 33. Timing Specification for RCRCMFS in CEPT Mode

TLCK

TFS

125 µs

TPD

(SINGLE

RAIL)

TS0 OF FRAME X

TS0 OF FRAME X + 1

5-6297(F)r.5

Figure 34. Timing Specification for TFS, TLCK, and TPD in CEPT Mode

Agere Systems Inc.

89

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Auxiliary Framer I/O Timing (continued)

TFS

11 CLOCK CYCLES

TLCK

2 ms

TSSFS

TPD

(SINGLE

RAIL)

TS0 OF THE FRAME

CONTAINING THE SIGNALING

MULTIFRAME PATTERN (0000)

5-6298(F)r.5

Figure 35. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode

TLCK

TFS

1 ms

TCRCMFS

TPD

(SINGLE

RAIL)

TS0 OF FRAME #0

OF MULTIFRAME

TS0 OF FRAME #8

OF MULTIFRAME

TS0 OF FRAME #0

OF MULTIFRAME

5-6299(F)r.5

Figure 36. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode

90

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring

Interrupt Generation

A global interrupt (pin 99) may be generated if enabled by register GREG1. This interrupt is clocked using channel

1 framer receive line clock (RLCK1). If RLCK1 is absent, the interrupt is clocked using RLCK2, the receive line

clock of channel 2. If both RLCK1 and RLCK2 are absent, clocking of interrupts is controlled by an interval 2.048

MHz clock generated from the CHI clock. Timing of the interrupt is shown in Figure 37. There is no relation

between MPCK (pin 101) and the interrupt, i.e., MPCK maybe asynchronous with any of the other terminator

clocks.

RLCK1

INTERRUPT

(PIN 99)

5-6563(F)

Figure 37. Relation Between RLCK1 and Interrupt (Pin 99)

Alarm Definition

The receive framer monitors the receive line data for alarm conditions and errored events, and then presents this

information to the system through the microprocessor interface status registers. The transmit framer, to a lesser

degree, monitors the receive system data and presents the information to the system through the microprocessor

interface status registers. Updating of the status registers is controlled by the receive line clock signal. When the

receive loss of clock monitor determines that the receive line clock signal is lost, the system clock is used to clock

the status registers and all status information should be considered corrupted.

Although the precise method of detecting or generating alarm and error signals differs between framing modes, the

functions are essentially the same. The alarm conditions monitored on the received line interface are:

1. Red alarm or the loss of frame alignment indication (FRM_SR1 bit 0).

The red alarm indicates that the receive frame alignment for the line has been lost and the data cannot be

properly extracted. The red alarm is indicated by the loss of frame condition for the various framing formats as

defined in Table 38.

Agere Systems Inc.

91

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Alarm Definition (continued)

Table 38. Red Alarm or Loss of Frame Alignment Conditions

Framing Format

D4

Number of Errored Framing Bits That Will Cause a Red Alarm (Loss of Frame

Alignment) Condition

2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1.

2 errored FT bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0.

SLC-96

2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1.

2 errored FT bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0.

DDS: Frame

ESF

3 errored frame bits (FT or FS) or channel 24 FAS pattern out of 12 consecutive frame bits.

2 errored FE bits out of 4 consecutive FE bits or, optionally, 320 or more CRC6 errored

checksums within a one second interval if loss of frame alignment due to excessive CRC-6

errors is enabled in FRM_PR9.

CEPT

Three consecutive incorrect FAS patterns or three consecutive incorrect NOT FAS patterns;

or optionally, greater than 914 received CRC-4 checksum errors in a one second interval if

loss of frame alignment due to excessive CRC-6 errors is enabled in FRM_PR9.

2. Yellow alarm or the remote frame alarm (FRM_SR1 bit 0).

This alarm is an indication that the line remote end is in a loss of frame alignment state. Indication of remote

frame alarm (commonly referred to as a yellow alarm) as for the different framing formats is shown in Table 39.

Table 39. Remote Frame Alarm Conditions

Framing Format

Superframe: D4

Remote Frame Alarm Format

Bit 2 of all time slots in the 0 state.

Superframe: D4-Japanese

The twelfth (12th) framing bit in the 1 state in two out of three consecutive super-

frames.

Superframe: DDS

Bit 6 of time slot 24 in the 0 state.

Extended Superframe (ESF)

CEPT: Basic Frame

An alternating pattern of eight 1s followed by eight 0s in the ESF data link.

Bit 3 of the NOT FAS frame in the 1 state in three consecutive frames.

Bit 6 of the time slot 16 signaling frame in the 1 state.

CEPT: Signaling Multiframe

3. Blue alarm or the alarm indication signal (AIS).

The alarm indication signal (AIS), sometimes referred to as the blue alarm, is an indication that the remote end

is out-of-service. Detection of an incoming alarm indication signal is defined in Table 40.

92

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Alarm Definition (continued)

Table 40. Alarm Indication Signal Conditions

Framing Format

Remote Frame Alarm Format

T1

Loss of frame alignment occurs and the incoming signal has two (2) or fewer zeros in

each of two consecutive double frame periods (386 bits).

CEPT ETSI

CEPT ITU

As described in Draft prETS 300 233:1992 Section 8.2.2.4, loss of frame alignment

occurs and the framer receives a 512 bit period containing two or less binary zeros. This

is enabled by setting register FRM_PR10 bit 1 to 0.

As described in ITU Rec. G.775, the incoming signal has two or fewer zeros in each of

two consecutive double frame periods (512 bits). AIS is cleared if each of two consecu-

tive double frame periods contains three or more zeros or frame alignment signal (FAS)

has been found. This is enabled by setting register FRM_PR10 bit 1 to 1.

4. The SLIP condition (FRM_SR3 bit 6 and bit 7).

SLIP is defined as the state in which the receive elastic store buffer’s write address pointer from the receive

framer and the read address pointer from the transmit concentration highway interface are equal¹.

A. The negative slip (Slip-N) alarm indicates that the receive line clock (RLCK) - transmit CHI clock (TCHICK)

monitoring circuit detects a state of overflow caused by RLCK and TCHICK being out of phase-lock and

the period of the received frame being less than that of the system frame. One system frame is deleted.

B. The positive slip (Slip-P) alarm indicates the line clock (RLCK) - transmit CHI clock (TCHICK) monitoring

circuit detects a state of underflow caused by RLCK and TCHICK being out of phase-lock and the period

of the received frame being greater than that of the system frame. One system frame is repeated.

5. The loss of framer receive clock (LOFRMRLCK, pins 2 and 38).

In the framer mode, FRAMER = 0 (pin 41/141), LOFRMRLCK alarm is asserted high when an interval of

250 µs has expired with no transition of RLCK (pin 135/47) detected. The alarm is disabled on the first transi-

tion of RLCK. In the terminator mode, FRAMER = 1 (pin 41/141), LOFRMRLCK is asserted high when SYSCK

(pin 3/35) does not toggle for 250 µs. The alarm is disabled on the first transition of SYSCK.

6. The loss of PLL clock (LOPLLCK, pins 39 and 143).

LOPLLCK alarm is asserted high when an interval of 250 µs has expired with no transition of PLLCK detected.

The alarm is disabled 250 µs after the first transition of PLLCK. Timing for LOPLLCK is shown in Figure 38.

1. After a reset, the read and write pointers of the receive path elastic store will be set to a known state.

PLLCK

250 µs

LOPLLCK

RCHICK

5-6564(F)r.2

Figure 38. Timing for Generation of LOPLLCK (Pin 39/143)

Agere Systems Inc.

93

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Alarm Definition (continued)

7. Received bipolar violation errors alarm, FRM_SR3 bit 0.

This alarm indicates any bipolar decoding error or detection of excessive zeros.

8. Received excessive CRC errors alarm, FRM_SR3 bit 3.

In ESF, this alarm is asserted when 320 or more CRC-6 checksum errors are detected within a one second

interval. In CEPT, this alarm is asserted when 915 or more CRC-4 checksum errors are detected within a one

second interval.

9. The CEPT continuous E-bit alarm (CREBIT) (FRM_SR2 bit 2).

CREBIT is asserted when the receive framer detects:

A. Five consecutive seconds where each 1 second interval contains ≥991 received E bits = 0 events.

B. Simultaneously no LFA occurred.

C. Optionally, no remote frame alarm (A bit = 1) was detected if register FRM_PR9 bit 0, bit 4, and bit 5 are

set to 1.

D. Optionally, neither Sa6-Fhex nor Sa6-Ehex codes were detected if register FRM_PR9 bit 0, bit 4, and bit 6

are set to 1.

The five second timer is started when:

E. CRC-4 multiframe alignment is achieved.

F. And optionally, A = 0 is detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1.

1

G. And optionally, neither Sa6_Fhex nor Sa6_Ehex is detected if register FRM_PR9 bit 0, bit 4, and bit 6 are

set to 1.

The five second counter is restarted when:

H. LFA occurs, or

I. ð990 E bit = 0 events occur in 1 second, or

J. Optionally, an A bit = 1 is detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1.

K. Optionally, a valid Sa6 pattern 1111 (binary) or Sa6 pattern 1110 (binary) code was detected if register

FRM_PR9 bit 0, bit 4, and bit 6 are set to 1.

This alarm is disabled during loss of frame alignment (LFA) or loss of CRC-4 multiframe alignment (LTS0MFA).

1. See Table 41, Sa6 Bit Coding Recognized by the Receive Framer on page 95, for the definition of this Sa6 pattern.

94

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Alarm Definition (continued)

10. Failed state alarm or the unavailable state alarm, FRM_SR5 bit 3 and bit 7 and FRM_SR6 bit 3 and bit 7.

This alarm is defined as the unavailable state at the onset of ten consecutive severely errored seconds. In this

state, the receive framer inhibits incrementing of the severely errored and errored second counters for the

duration of the unavailable state. The receive framer deasserts the unavailable state condition at the onset of

ten consecutive errored seconds which were not severely errored.

11. The 4-bit Sa6 codes (FRM_SR2 bit 3—bit 7).

Sa6 codes are asserted if three consecutive 4-bit patterns have been detected. The alarms are disabled when

three consecutive 4-bit Sa6 codes have been detected that are different from the pattern previously detected.

The receive framer monitors the Sa6 bits for special codes described in ETS Draft prETS 300 233:1992 Sec-

tion 9.2. The Sa6 codes are defined in Table 41 and Table 42. The Sa6 codes in Table 41 may be recognized

as an asynchronous bit stream in either non-CRC-4 or CRC-4 modes as long as the receive framer is in the

basic frame alignment state. In the CRC-4 mode, the receive framer can optionally recognize the received Sa6

codes in Table 41 synchronously to the CRC-4 submultiframe structure as long as the receive framer is in the

CRC-4 multiframe alignment state (synchronous Sa6 monitoring can be enabled by setting register

FRM_PR10 bit 1 to 1). The Sa6 codes in Table 42 are only recognized synchronously to the CRC-4 submulti-

frame and when the receive framer is in CRC-4 multiframe alignment. The detection of three (3) consecutive 4-

bit patterns are required to indicate a valid received Sa6 code. The detection of Sa6 codes is indicated in status

register FRM_SR2 bit 3—bit 7. Once set, any three-nibble (12-bit) interval that contains any other Sa6 code will

clear the current Sa6 status bit. Interrupts may be generated by the Sa6 codes given in Table 41.

Table 41. Sa6 Bit Coding Recognized by the Receive Framer

Code

First Receive Bit (MSB)

Last Received Bit (LSB)

Sa6_8hex

Sa6_Ahex

Sa6_Chex

Sa6_Ehex

Sa6_Fhex

1

0

1

0

1

0

1

0

1

Agere Systems Inc.

95

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Alarm Definition (continued)

Table 42 defines the three 4-bit Sa6 codes that are always detected synchronously to the CRC-4 submultiframe

structure, and are only used for counting NT1 events.

Table 42. Sa6 Bit Coding of NT1 Interface Events Recognized by the Receive Framer

First Receive

Bit (MSB)

Last Received Bit

(LSB)

Counter Size

(bits)

Code

Event at NT1

Sa6_1hex

Sa6_2hex

Sa6_3hex

0

1

0

1

E = 0

16

—

CRC-4 Error

CRC-4 Error & E = 0

This code will cause both

counters to increment.

The reference points for receive CRC-4, E bit, and Sa6 decoding are illustrated in Figure 39.

T REFERENCE

POINT

V REFERENCE

POINT

NT2

(NT1 REMOTE)

NT1

ET

CRC ERROR

DETECTED

CRC ERROR

DETECTED

CRC-4 ERRORS AT THE ET,

E BIT = 0, ERROR EVENT AT THE ET REMOTE

E BIT = 0

Sa6

E BIT = 0

COUNT:

1) CRC ERRORS,

2) E = 0,

CRC-4 ERRORS DETECTED FROM NT1 REMOTE, THEN SET Sa6 = 001X

E = 0 DETECTED FROM NT1 REMOTE, THEN SET Sa6 = 00X1

3) Sa6 = 001X, AND

4) Sa6 = 00X1

CRC-4 ERRORS AT THE NT1

E BIT = 0, ERROR EVENT DETECTED AT THE NT1 REMOTE

5-3913(F)r.8

Figure 39. The T and V Reference Points for a Typical CEPT E1 Application

12. CEPT auxiliary pattern alarm (AUXP) (FRM_SR1 bit 6).

The received auxiliary alarm, register FRM_SR1 bit 6 (AUXP), is asserted when the receive framer is in the

LFA state and has detected more than 253 10 (binary) patterns for 512 consecutive bits. In a 512-bit interval,

only two 10 (binary) patterns are allowable for the alarm to be asserted and maintained. The 512-bit interval is

a sliding window determined by the first 10 (binary) pattern detected. This alarm is disabled when three or more

10 (binary) patterns are detected in 512 consecutive bits. The search for AUXP is synchronized with the first

alternating 10 (binary) pattern as shown in Table 43.

Table 43. AUXP Synchronization and Clear Sychronization Process

00

—

10

—

01

—

11

—

11

00

—

00

—

0

10

00

10

sync

clear sync

—

sync

. . .

96

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Event Counters Definition

The error events monitored in the receive framer’s status registers are defined in Table 44 for the hardwired (default)

threshold values. The errored second and severely errored second threshold registers can be programmed through

FRM_PR11—FRM_PR13 such that the errored and severely errored second counters function as required by

system needs.

Table 44. Event Counters Definition

Counter Size

Error Event

Functional Mode

AMI

Definition

(bits)

Bipolar Viola-

tions (BPVs)

Any bipolar violation or 16 or more consecutive

zeros

16

B8ZS

Any BPV, code violation, or any 8-bit interval with no

one pulse

CEPT HDB3

SF: D4

Any BPV, code violation, or any 4-bit interval with no

one pulse

Frame Align-

ment Errors

(FERs)

Any FT or FS bit errors (FRM_PR10 bit 2 = 1) or any

FT bit errors (FRM_PR10 bit 2 = 0)

8

SF: SLC-96

Any FT or FS bit errors (FRM_PR10 bit 2 = 1) or any

FT bit errors (FRM_PR10 bit 2 = 0)

SF: DDS

ESF

Any FT, FS, or time slot 24 FAS bit error

Any FE bit error

CEPT

Any FAS (0011011) or NOT FAS (bit 2) bit error if

register FRM_PR10, bit 2 = 0.

Any FAS (0011011) bit error if register FRM_PR10,

bit 2 = 1.

CRC Checksum ESF or CEPT with CRC Any received checksum in error

Errors

16

Excessive CRC ESF

Errors

≥320 checksum errors in a one second interval

NONE

CEPT with CRC

≥915 checksum errors in a one second interval

Received

E bits = 0

CEPT with CRC-4

E bits = 0 in frame 13 and frame 15

16

Errored Second All

Events

Any one of the relevant error conditions enabled in

registers FRM_PR14—FRM_PR18 within a one sec-

ond interval

DS1: non ESF

Any framing bit errors within a one second interval

Any CRC-6 errors within a one second interval

Any framing errors within a one second interval

DS1: ESF

CEPT without CRC-4

CEPT with CRC-4 (ET1) Any CRC-4 errors within a one second interval

CEPT with CRC-4 (ET1 Any E bit = 0 event within a one second interval

remote)

CEPT with CRC-4 (NT1) Any Sa6 = 001x (binary) code event within a one

second interval

CEPT with CRC-4 (NT1 Any Sa6 = 00x1 (binary) code event within a one

remote)

second interval

Agere Systems Inc.

97

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Event Counters Definition (continued)

Table 44. Event Counters Definition (continued)

Counter Size

(bits)

Error Event

Functional Mode

Definition

Bursty Errored

Second Events

DS1: non ESF

Greater than 1 but less than 8 framing bit errors

within a one second interval

16

DS1: ESF

Greater than 1 but less than 320 CRC-6 errors within

a one second interval

CEPT without CRC-4

Greater than 1 but less than 16 framing bit errors

within a one second interval

CEPT with CRC-4 (ET1) Greater than 1 but less than 915 CRC-4 errors within

a one second interval

CEPT with CRC-4 (ET1 Greater than 1 but less than 915 E bit = 0 events

remote)

within a one second interval

CEPT with CRC-4 (NT1) Greater than 1 but less than 915 Sa6=001x (binary)

code events within a one second interval

CEPT with CRC-4 (NT1 Greater than 1 but less than 915 Sa6=00x1 (binary)

remote)

code events within a one second interval

SeverelyErrored All

Second Events

Any one of the relevant error conditions enabled in

registers FRM_PR14—FRM_PR18 within a one sec-

ond interval

16

DS1: non ESF

8 or more framing bit errors within a one second

interval

DS1: ESF

320 or more CRC-6 errors within a one second inter-

val

CEPT with no CRC-4

16 or more framing bit errors within a one second

interval

CEPT with CRC-4 (ET1) 915 or more CRC-4 errors within a one second inter-

val

CEPT with CRC-4 (ET1 915 or more E bit = 0 events within a one second

remote)

interval

CEPT with CRC-4 (NT1) 915 or more Sa6=001x (binary) code events within a

one second interval

CEPT with CRC-4 (NT1 915 or more Sa6=00x1 (binary) code events within a

remote)

one second interval

Unavailable

All

A one second period in the unavailable state

16

Second Events

The receive framer enters an unavailable state condition at the onset of ten consecutive severely errored second

events. When in the unavailable state, the receive framer deasserts the unavailable state alarms at the onset of ten

consecutive seconds which were not severely errored.

98

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Loopback and Transmission Modes

Primary Loopback Modes

Framer primary loopback mode is controlled by register FRM_PR24. There are seven primary loopback and trans-

mission test modes supported:

1. Line loopback (LLB).

2. Board loopback (BLB).

3. Single time-slot system loopback (STSSLB).

4. Single time-slot line loopback (STSLLB).

5. CEPT nailed-up broadcast transmission (CNUBT).

6. Payload loopback (PLLB).

7. CEPT nailed-up connect loopback (CNUCLB).

The loopback and transmission modes are described in detail below:

1. The LLB mode loops the receive line data and clock back to the transmit line. The received data is processed

by the receive framer and transmitted to the system interface. This mode can be selected by setting register

FRM_PR24 to 001xxxxx (binary).

2. The BLB mode loops the receive system data back to the system after:

A. The transmit framer processes the data, and

B. The receive framer processes the data.

In the BLB mode, AIS is always transmitted to the line interface. This mode can be selected by setting register

FRM_PR24 to 010xxxxx (binary).

3. The STSSLB mode loops one and only one received system time slot back to the transmit system interface.

The selected looped back time-slot data is not processed by either the transmit framer or the receive framer.

The selected time slot does not pass through the receive elastic store buffer and therefore will not be affected

by system-AIS, RLFA conditions, or controlled slips events. Once selected, the desired time-slot position has

the programmable idle code in register FRM_PR22 transmitted to the line interface one frame before imple-

menting the loopback and for the duration of the loopback. This mode can be selected by setting register

FRM_PR24 to 011A4A3A2A1A0, where A4A3A2A1A0 is the binary address of the selected time slot.

4. The STSLLB mode loops one and only one received line time slot back to the transmit line. The selected time-

slot data is looped to the line after being processed by the receive framer, and it passes through the receive

elastic store. The selected time slot has the programmable idle code in register FRM_PR22 transmitted to the

system interface one frame before implementing the loopback and for the duration of the loopback. In CEPT,

selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be

taken (time slot 0 will not be looped back to the line and should not be chosen). This mode can be selected by

setting register FRM_PR24 to 100A4A3A2A1A0, where A4A3A2A1A0 is the binary address of the selected time

slot.

5. The CNUBT mode transmits received-line time slot X to the system in time slots X and time slot 0 (of the next

frame). Any time slot can be broadcast. This mode can be selected by setting register FRM_PR24 to

101A4A3A2A1A0 where A4A3A2A1A0 is the binary address of the selected time slot.

Agere Systems Inc.

99

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Loopback and Transmission Modes (continued)

6. The PLLB mode loops the received line data and clock back to the transmit line while inserting (replacing) the

facility data link in the looped back data. Two variations of the payload loopback are available. In the pass

through framing/CRC bit mode (chosen by setting register FRM_PR24 to 111xxxxx (binary)), the framing and

CRC bits are looped back to the line transmit data. In the regenerated framing/CRC bit mode (chosen by

setting register FRM_PR24 to 110xxxxx (binary) and register FRM_PR10 bit 3 to 0), the framing and CRC bits

are regenerated by the transmit framer. The payload loopback is only available for ESF and CEPT modes.

7. The CNUCLB mode loops received system time slot X back to the system in time slot 0. The selected time slot

is not routed through the receive elastic store buffer and therefore will not be affected by system-AIS, RLFA

conditions, or controlled slips. Any time slot can be looped back to the system. Time slot X transmitted to the

line is not affected by this loopback mode. Looping received system time slot 0 has no effect on time slot 0

transmitted to the line, i.e., the transmit framer will always overwrite the FAS and NOT FAS data in time slot 0

transmitted to the line. This mode can be selected by setting register FRM_PR24 to 110A4A3A2A1A0 and

register FRM_PR10 bit 3 to 1, where A4A3A2A1A0 is the binary address of the selected time slot.

Secondary Loopback Modes

There are two secondary loopback modes supported:

1. Secondary-single time-slot system loopback (S-STSSLB)

2. Secondary-single time-slot line loopback (S-STSLLB)

The loopbacks are described in detail below:

1. The secondary-STSSLB mode loops one and only one received system time slot back to the transmit system

interface. The selected time-slot data looped back is not processed by either the transmit framer or the receive

framer. The selected time slot does not pass through the receive elastic store buffer and therefore will not be

affected by system-AIS, RLFA conditions, or controlled slips events. Whenever the secondary loopback register

is programmed to the same time slot as the primary register, the primary loopback mode will control that time

slot. Once selected, the desired time-slot position has the programmable line idle code in register FRM_PR22

transmitted to the line interface one frame before implementing the loopback and for the duration of the

loopback.

2. The secondary-STSLLB mode loops one and only one line time slot back to the line. The selected time slot data

is looped to the line after being processed by the receive framer and it passes through the receive elastic store.

The selected time slot has the programmable idle code in register FRM_PR22 transmitted to the system

interface one frame before implementing the loopback and for the duration of the loopback. In CEPT, selecting

time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot

0 will not be looped back to the line and should not be chosen in this mode).

Table 45 defines the deactivation of the two secondary loopback modes as a function of the activation of the pri-

mary loopback and test transmission modes.

Table 45. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function of Activating the

Primary Loopback Modes

Primary Loopback Mode

Deactivation of S-STSSLB

If primary time slot = secondary

Always

Deactivation of S-STSLLB

If primary time slot = secondary

Always

STSSLB

STSLLB

BLB

CNUBT

If the secondary time slot is TS0 or if the If primary time slot = secondary

primary time slot = secondary

LLB

Always

NUCLB

If the secondary time slot is TS0 or if the If primary time slot = secondary

primary time slot = secondary

PLLB

Always

100

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Loopback and Transmission Modes (continued)

Figure 40 illustrates the various loopback modes implemented by each framer unit.

FRAMER

AIS

RECEIVE SYSTEM DATA

IS IGNORED

LINE

SYSTEM

LINE

SYSTEM

ES

(1) LINE LOOPBACK

(2) BOARD LOOPBACK

TRANSMIT PROGRAMMABLE LINE IDLE CODE

TRANSMIT PROGRAMMABLE IDLE CODE

IN REGISTER FRM_PR22

IN OUTGOING LINE TS-X

IN REGISTER FRM_PR22

IN OUTGOING SYSTEM TS-X

FRAMER

SYSTEM

INSERT ONLY TIME SLOT X

LINE

SYSTEM

LOOPBACK TS-X

ES

(3) SINGLE TIME-SLOT SYSTEM LOOPBACK

FRAMER

(4) SINGLE TIME-SLOT LINE LOOPBACK

TRANSMIT FRAMER

LINE

SYSTEM

ES

TRANSMIT LINE TS-X IN

SYSTEM TS-X AND SYSTEM TS-0

(6) PAYLOAD LINE LOOPBACK

(5) CEPT NAILED-UP BROADCAST TRANSMISSION

FRAMER

SYSTEM

LINE

ES

LOOPBACK TS-X IN TS-0

(7) CEPT NAILED-UP CONNECT LOOPBACK

5-3914(F).cr.3

Figure 40. Loopback and Test Transmission Modes

Agere Systems Inc.

101

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Line Test Patterns

Test patterns may be transmitted to the line through either register FRM_PR20 or register FRM_PR29. Only one of

these sources may be active at the same time. Signaling must be inhibited while sending these test patterns.

Transmit Line Test Patterns—Using Register FRM_PR20

The transmit framer can be programmed through register FRM_PR20 to transmit various test patterns. These test

patterns, when enabled, overwrite the received CHI data. The test patterns available using register FRM_PR20

are:

1. The unframed-AIS pattern which consists of a continuous bit stream of 1s (. . . 111111 . . .) enabled by setting

register FRM_PR20 bit 0 to 1.

2. The unframed-auxiliary pattern which consists of a continuous bit stream of alternating 1s and 0s (. . .

10101010 . . .) enabled by setting register FRM_PR20 bit 1 to 1.

3. The quasi-random test signal, enabled by setting register FRM_PR20 bit 3 to 1, which consists of:

A. A pattern produced by means of a twenty stage shift register with feedback taken from the 17th and 20th

stages via an exclusive-OR gate to the first stage. The output is taken from the 20th stage and is forced to

a 1 state whenever the next 14 stages (19 through 6) are all 0. The pattern length is 1,048,575 or

2

²⁰– 1 bits. This pattern is described in detail in AT&T Technical Reference 62411 [5] Appendix and

illustrated in Figure 41.

B. Valid framing bits.

C. Valid transmit facility data link (TFDL) bit information.

D. Valid CRC bits.

A

C

D

B

XOR

#1

#2

D-TYPE FLIP-FLOPS

#17

#18

#19

#20

#6

QUASI-RANDOM TEST OUTPUT

#19

OR

NOR

#20

5-3915(F).dr.1

Figure 41. 20-Stage Shift Register Used to Generate the Quasi-Random Signal

4. The pseudorandom test pattern, enabled by setting register FRM_PR20 bit 2 to 1, which consists of:

A. A 2¹⁵– 1 pattern inserted in the entire payload (time slots 1—24 in DS1 and time slots 1—32 in CEPT), as

described by ITU Rec. 0.151 and illustrated in Figure 42.

B. Valid framing pattern.

C. Valid transmit facility data link (TFDL) bit data.

D. Valid CRC bits.

102

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Line Test Patterns (continued)

A

C

D

B

PSEUDORANDOM

TEST OUTPUT

#1

#2

#3

#13

#14

#15

XOR

D-TYPE FLIP-FLOPS

5-3915(F).er.1

Figure 42. 15-Stage Shift Register Used to Generate the Pseudorandom Signal

5. The idle code test pattern, enabled by setting register FRM_PR20 bit 6 to 1, which consists of:

A. The programmable idle code, programmed through register FRM_PR22, in time slots 1—24 in DS1 and

0—31 in CEPT.

B. Valid framing pattern.

C. Valid transmit facility data link (TFDL) bit data.

D. Valid CRC bits.

Transmit Line Test Patterns—Using Register FRM_PR69

Framed or unframed patterns indicated in Table 46 may be generated and sent to the line by register FRM_PR69

and by setting register FRM_PR20 to 00 (hex). Selection of transmission of either a framed or unframed test pat-

tern is made through FRM_PR69 bit 3. If one of the test patterns of register FRM_PR69 is enabled, a single bit

error can be inserted into the transmitted test pattern by toggling register FRM_PR69 bit 1 from 0 to 1.

Table 46. Register FRM_PR69 Test Patterns

Pattern

Register FRM_PR69

Bit 7 Bit 6 Bit 5 Bit 4

MARK (all ones AIS)

0

QRSS (2²⁰– 1 with zero suppression)

0

1

2⁵– 1

63 (2⁶– 1)

511 (2⁹– 1) (V.52)

2⁹– 1

2047 (2¹¹– 1) (O.151)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

¹¹– 1 (reversed)

¹⁵– 1 (O.151)

²⁰– 1 (V.57)

²⁰– 1 (CB113/CB114)

²³– 1 (O.151)

1:1 (alternating)

Agere Systems Inc.

103

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Line Test Patterns (continued)

Receive Line Pattern Monitor—Using Register FRM_SR7

The receive framer pattern monitor continuously monitors the received line, detects the following fixed framed pat-

terns, and indicates detection in register FRM_SR7 bit 6 and bit 7.

1. The pseudorandom test pattern as described by ITU Rec. O.151 and illustrated in Figure 42. Detection of the

pattern is indicated by register FRM_SR7 bit 6 = 1.

2. The quasi-random test pattern described in AT&T Technical Reference 62411[5] Appendix and illustrated in

Figure 41. Detection of the pattern is indicated by register FRM_SR7 bit 7 = 1.

In DS1 mode, the received 193 bit frame must consist of 192 bits of pattern plus 1 bit of framing information. In

CEPT mode, the received 256 bit frame must consist of 248 bits of pattern plus 8 bits (TS0) of framing information.

No signaling, robbed bit in the case of T1 and TS16 signaling in the case of CEPT, may be present for successful

detection of these two test patterns.

To establish lock to the pattern, 256 sequential bits must be received without error. When lock to the pattern is

achieved, the appropriate bit of register FRM_SR7 is set to a 1. Once pattern lock is established, the monitor can

withstand up to 32 single bit errors per frame without a loss of lock. Lock will be lost if more than 32 errors occur

within a single frame. When such a condition occurs, the appropriate bit of register FRM_SR7 is deasserted. The

monitor then resumes scanning for pattern candidates.

Receive Line Pattern Detector—Using Register FRM_PR70

Framed or unframed patterns indicated in Table 47 may be detected using register FRM_PR70. Detection of the

selected test pattern is indicated when register FRM_PR7 bit 4 is set to 1. Selection of a framed or unframed test

pattern is made through FRM_PR70 bit 3. Bit errors in the received test pattern are indicated when register

FRM_SR7 bit 5 = 1. The bit errors are counted and reported in registers FRM_SR8 and FRM_SR9, which are nor-

mally the BPV counter registers. (In this test mode, the BPV counter registers do not count BPVs but count only bit

errors in the received test pattern.)

Table 47. Register FRM_PR70 Test Patterns

Pattern

Register FRM_PR70

Bit 7 Bit 6 Bit 5 Bit 4

MARK (all ones AIS)

0

QRSS (2²⁰– 1 with zero suppression)

0

1

2⁵– 1

63 (2⁶– 1)

511 (2⁹– 1) (V.52)

2⁹– 1

2047 (2¹¹– 1) (O.151)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

¹¹– 1 (reversed)

¹⁵– 1 (O.151)

²⁰– 1 (V.57)

²⁰– 1 (CB113/CB114)

²³– 1 (O.151)

1:1 (alternating)

104

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Line Test Patterns (continued)

The pattern detector continuously monitors the received line for the particular pattern selected in register

FRM_PR70 bit 7—bit 4 (DPTRN). To establish detector lock to the pattern, 256 sequential bits must be detected.

Once the detector has locked onto the selected pattern, it will remain locked and count all single bit errors until reg-

ister FRM_PR70 bit 2 (DBLKSEL) is set to 0. If the lock to the selected pattern is lost, the detection indicator is

deasserted (register FRM_SR7 bit 4) and the detector resumes monitoring for the selected pattern.

To select a pattern or change the pattern to be detected, the following programming sequence must be followed.

■ DBLKSEL (register FRM_PR70 bit 2) is set to 0.

■ The new pattern to be detected is selected by setting register FRM_PR70 bit 7—bit 4 to the desired value.

■ DBLKSEL (register FRM_PR70 bit 2) is set to 1.

Agere Systems Inc.

105

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Automatic and On-Demand Commands

Various alarms can be transmitted either automatically as a result of various alarm conditions or on demand. After

reset, all automatic transmissions are disabled. The user can enable the automatic or on-demand actions by set-

ting the proper bits in the automatic and on-demand action registers as identified below in Table 48. Table 48

shows the programmable automatically transmitted signals and the triggering mechanisms for each. Table 49

shows the on-demand commands.

Table 48. Automatic Enable Commands

Action

Trigger

Enabling Register Bit

FRM_PR27 bit 0 = 1

Transmit Remote Frame Alarm Loss of frame alignment (RLFA)

(RFA)

Loss of CEPT time slot 16 multiframe FRM_PR27 bit 1 = 1

alignment (RTS16LMFA)

Loss of CEPT time slot 0 multiframe

alignment (RTS0LMFA)

FRM_PR27 bit 2 = 1

Detection of the timer (100 ms or

FRM_PR27 bit 3 = 1

400 ms) expiration due to loss of CEPT FRM_PR9 bit 7—bit 0 = 0xxxx1x1 or

multiframe alignment 0xxx1xx1

Detection of the CEPT RSa6 = 8 (hex) FRM_PR27 bit 4 = 1

code

Detection of the CEPT RSa6 = C (hex) FRM_PR27 bit 5 = 1

code

Transmit CEPT E Bit = 0

Transmit AIS to System

Detection of CEPT CRC-4 error

RTS0LMFA

FRM_PR28 bit 3 = 1

FRM_PR28 bit 4 = 1

FRM_PR28 bit 5 = 1

Detection of the timer (100 ms or

400 ms) expiration due to loss of CEPT FRM_PR9 bit 7—bit 0 = 0xxxx1x1 or

multiframe alignment

0xxx1xx1

RLFA

FRM_PR19 bit 0 = 1

FRM_PR19 bit 1 = 1

Detection of the timer (100 ms or

400 ms) expiration due to loss of CEPT FRM_PR9 bit 7—bit 0 = 0xxxx1x1 or

multiframe alignment

0xxx1xx1

Transmit CEPT Time Slot 16

Remote Multiframe Alarm to

Line

RTS16LMFA

FRM_PR41 bit 4 = 1

Transmit CEPT AIS in Time Slot RTS16LMFA

16 to System

FRM_PR44 bit 6 = 1

FRM_PR19 bit 4 =1

FRM_PR19 bit 6 =1

FRM_PR19 bit 7 =1

Automatic Enabling of DS1 Line Line loopback on/off code

Loopback On/Off

Automatic Enabling of ESF FDL ESF line loopback on/off code

Line Loopback On/Off

Automatic Enabling of ESF FDL ESF payload loopback on/off code

Payload Loopback On/Off

106

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Alarms and Performance Monitoring (continued)

Automatic and On-Demand Commands (continued)

Table 49. On-Demand Commands

Type

Frame Format

Action

Enabling Register Bit

FRM_PR27 bit 6 = 1

FRM_PR27 bit 7 = 1

Transmit Remote Frame Alarm D4 (Japanese) FS bit in frame 12 = 1

D4 (US)

DDS

Bit 2 of all time slots = 0

Bit 6 in time slot 24 = 0

ESF

Pattern of 1111111100000000 in

the FDL F-bit position

CEPT

A bit = 1

Transmit Time Slot 16 Remote CEPT

Time slot 16 remote alarm bit = 1 FRM_PR41 bit 5 = 1

Multiframe Alarm to the Line

Transmit Data Link AIS

(Squelch)

SLC-96, ESF Transmit data link bit = 1

FRM_PR21 bit 4 = 1

Transmit Line Test Patterns

All

Transmit test patterns to the line

interface

See Transmit Line Test

Patterns—Using Register

FRM_PR20 section on

page 102 and Transmit

Line Test Patterns—Using

Register FRM_PR69

section on page 103.

Transmit System AIS

All

Transmits AIS to the system

FRM_PR19 bit 3 = 1

FRM_PR44 bit 1 = 1

Transmit System Signaling AIS T1

(Squelch)

Transmit ABCD = 1111 to the

system

CEPT

All

Transmit AIS in system time slot 16 FRM_PR44 bit 7 = 1

Receive Signaling Inhibit

Suspend the updating of the

receive signaling registers

FRM_PR44 bit 3 = 1

Receive Framer Reframe

Transmit Line Time Slot 16

All

Force the receive framer to reframe FRM_PR26 bit 2 = 1

CEPT

Transmit AIS in time slot 16 to the FRM_PR41 bit 6 = 1

line

Enable Loopback

All

Enables system and line loopbacks See Loopback and

Transmission Modes

section on page 99.

Framer Software Reset

The framer and FDL are placed in FRM_PR26 bit 0 = 1

the reset state for four RCLK clock

cycles. The framer parameter

registers are forced to the default

value.

Framer Software Restart

All

The framer and FDL are placed in FRM_PR26 bit 1 = 1

the reset state as long as this bit is

set to 1. The framer parameter

registers are not changed from their

programmed values.

Agere Systems Inc.

107

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL)

Data may be extracted from and inserted into the facility data link in SLC-96, DDS, ESF, and CEPT framing

formats. In CEPT, any one of the Sa bits can be declared as the facility data link by programming register

FRM_PR43 bit 0—bit 2. Access to the FDL is made through:

1. The FDL pins (RFDL, RFDLCK, TFDL, and TFDLCK). Figure 27 shows the timing of these signals.

2. The 64-byte FIFO of the FDL HDLC block. FDL information passing through the FDL HDLC section may be

framed in HDLC format or passed through transparently.

t8

t8: TFDLCK CYCLE = 125 µs (DDS)

TFDLCK

250 µs (ALL OTHER

MODES)

t9

t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns

TFDL

t10

t10: RFDLCK CYCLE = 125 µs (DDS)

250 µs (ALL OTHER

MODES)

RFDLCK

RFDL

t11: RFDLCK TO RFDL DELAY = 40 ns

t11

5-3910(F).cr.1

Figure 43. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections

In the ESF frame format, automatic assembly and transmission of the performance report message (PRM) as

defined in both ANSI T1.403-1995 and Telcordia Technologies TR-TSY-000194 Issue 1, 12—87 is managed by

the receive framer and transmit FDL sections. The ANSI T1.403-1995 bit-oriented data link messages (BOM) can

be transmitted by the transmit FDL section and recognized and stored by the receive FDL section.

Receive Facility Data Link Interface

Summary

A brief summary of the receive facility data link functions is given below:

1. Bit-oriented message (BOM) operation. The ANSI T1.403-1995 bit-oriented data link messages are

recognized and stored in register FDL_SR3. The number of times that an ANSI code must be received for

detection can be programmed from 1 to 10 by writing to register FDL_PR0 bit 4— bit 7. When a valid ANSI

code is detected, register FDL_SR0 bit 7 (FRANSI) is set.

2. HDLC operation. This is the default mode of operation when the FDL receiver is enabled (register FDL_PR1

bit 2 = 1). The HDLC framer detects the HDLC flags, checks the CRC bytes, and stores the data in the FDL

receiver FIFO (register FDL_SR4) along with a status of frame (SF) byte.

3. HDLC operation with performance report messages (PRM). This mode is enabled by setting register

FDL_PR1 bit 2 and bit 6 to 1. In this case, the receive FDL will store the 13 bytes of the PRM report field in the

FDL receive FIFO (register FDL_SR4) along with a status of frame (SF) byte.

4. Transparent operation. Enabling the FDL and setting register FDL_PR9 bit 6 (FTM) to 1 disables the HDLC

processing. Incoming data link bits are stored in the FDL receive FIFO (register FDL_SR4).

108

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

Receive Facility Data Link Interface (continued)

5. Transparent operation with pattern match. Enabling the FDL and setting registers FDL_PR9 bit 5

(FMATCH) and FDL_PR9 bit 6 (FTM) to 1 forces the FDL to start storing data in the FDL receive FIFO (register

FDL_SR4) only after the programmable match character defined in register FDL_PR8 bit 0—bit 7 has been

detected. The match character and all subsequent bytes are placed into the FDL receive FIFO.

The FDL interface to the receive framer is illustrated in Figure 44.

RECEIVE LINE

DATA

LOSS OF FRAME

RECEIVE FDL

ALIGNMENT

DATA

EXTRACTER

RECEIVE

FRAMER

RFDLCK

RFDL

RECEIVE

FACILITY DATA

RECEIVE FACILITY

DATA LINK HDLC

TRANSPARENT

RFDLCK

ANSI T1.403-1995

BIT-ORIENTED DATA

LINK MESSAGES

MONITOR

RECEIVE FACILITY

DATA LINK FIFO

ONE 8-bit REGISTER

IDENTIFYING THE ESF

BIT-ORIENTED CODE

64 8-bit LOCATIONS

MICROPROCESSOR INTERFACE

5-4560(F).ar.1

Figure 44. Block Diagram for the Receive Facility Data Link Interface

Receive ANSI T1.403 Bit-Oriented Messages (BOM)

1. The receive FDL monitor will detect any of the ANSI T1.403 ESF bit-oriented messages (BOMs) and generate

an interrupt, enabled by register FDL_PR6 bit 7, upon detection. Register FDL_SR0 bit 7 (FRANSI) is set to 1

upon detection of a valid BOM and then cleared when read.

2. The received ESF FDL bit-oriented messages are received in the form 111111110X0X1X2X3X4X50 (the left-most

bit is received first). The bits designated as X are the defined ANSI ESF FDL code bits. These code bits are

written into the received ANSI FDL status register FDL_SR3 when the entire code is received.

3. The minimum number of times a valid code must be received before it is reported can be programmed from 1 to

10 using register FDL_PR0 bit 4—bit 7.

Agere Systems Inc.

109

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

Receive Facility Data Link Interface (continued)

The received ANSI FDL status byte, register FDL_SR3, has the following format.

Table 50. Receive ANSI Code

B7

B6

B5

B4

B3

B2

B1

B0

0

X5

X4

X3

X2

X1

X0

Receive ANSI Performance Report Messages (PRM)

As defined in ANSI T1.403, the performance report messages consist of 15 bytes, starting and ending with an

HDLC flag. The receive framer status information consists of four pairs of octets, as shown in Table 51. Upon

detection of the PRM message, the receive FDL extracts the 13 bytes of the PRM report field and stores it in the

receive FDL FIFO along with the status of frame byte.

Table 51. Performance Report Message Structure*

Octet

PRM B7 PRM B6 PRM B5 PRM B4 PRM B3 PRM B2 PRM B1 PRM B0

Number

1

Flag

2

SAPI

C/R

EA

3

TEI

Control

U1

4

5

G3

FE

G3

FE

G3

FE

G3

FE

LV

SE

LV

SE

LV

SE

LV

SE

G4

LB

G4

LB

G4

LB

G4

LB

U2

R

G5

G2

G5

G2

G5

G2

G5

G2

SL

Nm

SL

G6

Nl

6

G1

U1

G1

U1

G1

U1

G1

7

8

U2

R

G6

Nl

Nm

SL

9

U2

R

G6

Nl

10

Nm

SL

11

U2

R

G6

Nl

12

Nm

13—14

15

FCS

Flag

* The rightmost bit (bit 1) is transmitted first for all fields except for the 2 bytes of the FCS that are transmitted leftmost bit (bit 8) first.

The definition of each PRM field is shown in Table 52, and octet content is shown in Table 53.

110

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

Receive Facility Data Link Interface (continued)

Table 52. FDL Performance Report Message Field Definition

PRM Field

Definition

G1 = 1

G2 = 1

G3 = 1

G4 = 1

G5 = 1

G6 = 1

SE = 1

FE =1

CRC Error Event = 1

1 < CRC Error Event ≤ 5

5 < CRC Error Event ≤ 10

10 < CRC Error Event ≤ 100

100 < CRC Error Event ≤ 319

CRC Error Event ≥ 320

Severely Errored Framing Event ≥ 1 (FE will = 0)

Frame Synchronization Bit Error Event ≥ 1 (SE will = 0)

Line Code Violation Event ≥ 1

Slip Event ≥ 1

LV = 1

SL = 1

LB = 1

U1, U2 = 0

R = 0

Payload Loopback Activated

Reserved

Reserved (default value = 0)

One-Second Report Modulo 4 Counter

Nm, Nl = 00,

01, 10, 11

Table 53. Octet Contents and Definition

Octet

Definition

Number

Contents

1

2

01111110

Opening LAPD Flag

00111000

00111010

From CI: SAPI = 14, C/R = 0, EA = 0

From Carrier: SAPI = 14, C/R = 1, EA = 0

3

4

00000001

00000011

Variable

01111110

TEI = 0, EA = 1

Unacknowledged Frame

5, 6

7, 8

9, 10

11, 12

13, 14

15

Data for Latest Second (T)

Data for Previous Second (T – 1)

Data for Earlier Second (T – 2)

Data for Earlier Second (T – 3)

CRC-16 Frame Check Sequence

Closing LAPD Flag

Agere Systems Inc.

111

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

Receive Facility Data Link Interface (continued)

Receive HDLC Mode

This is the default mode of the FDL. The receive FDL receives serial data from the receive framer, identifies HDLC

frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive FIFO.

The receive queue manager forms a status of frame (SF) byte for each HDLC frame and stores the SF byte in the

receive FDL FIFO (register FDL_SR4) after the last data byte of the associated frame. HDLC frames consisting of

n bytes will have n + 1 bytes stored in the receive FIFO. The frame check sequence bytes (CRC) of the received

HDLC frame are not stored in the receive FIFO. When receiving ANSI PRM frames, the frame check sequence

bytes are stored in the receive FIFO.

The SF byte has the following format.

Table 54. Receive Status of Frame Byte

RSF B7

RSF B6

RSF B5

RSF B4

RSF B3

RSF B2

RSF B1

RSF B0

BAD CRC

ABORT

RFIFO

OVERRUN

BAD BYTE

COUNT

0

Bit 7 of the SF status byte is the CRC status bit. A 1 indicates that an incorrect CRC was detected. A 0 indicates

the CRC is correct. Bit 6 of the SF status byte is the abort status. A 1 indicates the frame associated with this status

byte was aborted (i.e., the abort sequence was detected after an opening flag and before a subsequent closing

flag). An abort can also cause bits 7 and/or 4 to be set to 1. An abort is not reported when a flag is followed by

seven 1s. Bit 5 is the FIFO overrun bit. A 1 indicates that a receive FIFO overrun occurred (the 64-byte FIFO size

was exceeded). Bit 4 is the FIFO bad byte count that indicates whether or not the bit count received was a multiple

of eight (i.e., an integer number of bytes). A 1 indicates that the bit count received after 0-bit deletion was not a

multiple of eight, and a 0 indicates that the bit count was a multiple of eight. When a non-byte-aligned frame is

received, all bits received are present in the receive FIFO. The byte before the SF status byte contains less than

eight valid data bits. The HDLC block provides no indication of how many of the bits in the byte are valid. User

application programming controls processing of non-byte-aligned frames. Bit 3—bit 0 of the SF status byte are not

used and are set to 0. A good frame is implied when the SF status byte is 00 (hex).

Receive FDL FIFO

Whenever an SF byte is present in the receive FIFO, the end of frame registers FDL_SR0 bit 4 (FREOF) and

FDL_SR2 bit 7 (FEOF) bits are set. The receiver queue status (register FDL_SR2 bit 0—bit 6) bits report the

number of bytes up to and including the first SF byte. If no SF byte is present in the receive FIFO, the count directly

reflects the number of data bytes available to be read. Depending on the FDL frame size, it is possible for multiple

frames to be present in the receive FIFO. The receive fill level indicator register FDL_PR6 bit 0—bit 5 (FRIL) can

be programmed to tailor the service time interval to the system. The receive FIFO full register FDL_SR0 bit 3 (FRF)

interrupt is set in the interrupt status register when the receive FIFO reaches the preprogrammed full position. An

FREOF interrupt is also issued when the receiver has identified the end of frame and has written the SF byte for

that frame. An FDL overrun interrupt register FDL_SR0 bit 5 (FROVERUN) is generated when the receiver needs

to write either status or data to the receive FIFO while the receive FIFO is full. An overrun condition will cause the

last byte of the receive FIFO to be overwritten with an SF byte indicating the overrun status. A receive idle register

FDL_SR0 bit 6 (FRIDL) interrupt is issued whenever 15 or more continuous 1s have been detected.

112

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

Receive Facility Data Link Interface (continued)

The receive queue status bits, register FDL_SR2 bit 0—bit 6 (FRQS), are updated as bytes are loaded into the

receive FIFO. The SF status byte is included in the byte count. When the first SF status byte is placed in the FIFO,

register FDL_SR0 bit 4 (FREOF) is set to 1, and the status freezes until the FIFO is read. As bytes are read from

the FIFO, the queue status decrements until it reads 1. The byte read when register FDL_SR2 bit 0—bit 6 =

0000001 and the FREOF bit is 1 is the SF status byte describing the error status of the frame just read. Once the

first SF status byte is read from the FIFO, the FIFO status is updated to report the number of bytes to the next SF

status byte, if any, or the number of additional bytes present. When FREOF is 0, no SF status byte is currently

present in the FIFO, and the FRQS bits report the number of bytes present. As bytes are read from the FIFO, the

queue status decrements with each read until it reads 0 when the FIFO is totally empty. The FREOF bit is also 0

when the FIFO is completely empty. Thus, the FRQS and FREOF bit provide a mechanism to recognize the end of

1 frame and the beginning of another. Reading the FDL receiver status register does not affect the FIFO buffers. In

the event of a receiver overrun, an SF status byte is written to the receive FIFO. Multiple SF status bytes can be

present in the FIFO. The FRQS reports only the number of bytes to the first SF status byte.

To allow users to tailor receiver FIFO service intervals to their systems, the receiver interrupt level bits in register

FDL_PR6 bit 0—bit 5 (FRIL) are provided. These bits are coded in binary and determine when the receiver full

interrupt, register FDL_SR0 bit 3 (FRF), is asserted. The interrupt pin transition can be masked by setting register

FDL_PR2 bit 3 (FRFIE) to 0. The value programmed in the FRIL bits equals the total number of bytes necessary to

be present in the FIFO to trigger an FRF interrupt. The FRF interrupt alone is not sufficient to determine the

number of bytes to read, since some of the bytes may be SF status bytes. The FRQS bits and FREOF bit allow the

user to determine the number of bytes to read. The FREOF interrupt can be the only interrupt for the final frame of

a group of frames, since the number of bytes received to the end of the frame cannot be sufficient to trigger an

FRF interrupt.

Programming Note: Since the receiver writing to the receive FIFO and the host reading from the receive FIFO are

asynchronous events, it is possible for a host read to put the number of bytes in the receive FIFO just below the

programmed FRIL level and a receiver write to put it back above the FRIL level. This causes a new FRF interrupt,

and has the potential to cause software problems. It is recommended that during service of the FRF interrupt, the

FRF interrupt be masked FRFIE = 0, and the interrupt register be read at the end of the service routine, discarding

any FRF interrupt seen, before unmasking the FRF interrupt.

Receiver Overrun

A receiver overrun occurs if the 64-byte limit of the receiver FIFO is exceeded, i.e., data has been received faster

than it has been read out of the receive FIFO. Upon overrun, an SF status byte with the overrun bit (bit 5) set to 1

replaces the last byte in the FIFO. The SF status byte can have other error conditions present. For example, it is

unlikely the CRC is correct. Thus, care should be taken to prioritize the possible frame errors in the software

service routine. The last byte in the FIFO is overwritten with the SF status byte regardless of the type of byte (data

or SF status) being overwritten. The overrun condition is reported in register FDL_SR0 bit 5 and causes the

interrupt pin to be asserted if it is not masked (register FDL_PR2 bit 5 (FROVIE)). Data is ignored until the

condition is cleared and a new frame begins. The overrun condition is cleared by reading register FDL_SR0 bit 5

and reading at least 1 byte from the receive FIFO. Because multiple frames can be present in the FIFO, good

frames as well as the overrun frame can be present. The host can determine the overrun frame by looking at the

SF status byte.

Agere Systems Inc.

113

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

Transmit Facility Data Link Interface

The FDL interface of the transmit framer is shown in Figure 45, indicating the priority of the FDL sources.

The remote frame alarm, enabled using register FRM_PR27, is given the highest transmission priority by the

transmit framer.

The ANSI T1.403-1995 bit-oriented data link message transmission is given priority over performance report

messages and the automatic transmission of the performance report messages is given priority over FDL HDLC

transmission. Idle code is generated by the FDL unit when no other transmission is enabled.

The FDL transmitter is enabled by setting register FDL_PR1 bit 3 to 1.

MICROPROCESSOR INTERFACE

RECEIVE

TRANSMIT

FRAMER

FDL FIFO

TRANSPARENT

TRANSMIT

TRANSMIT FDL

PERFORMANCE

REPORT MESSAGE

HDLC FRAMER

TRANSMIT ANSI

T1.403 FDL BIT

ASSEMBLER

CODE

GENERATOR

FDL

IDLE CODE

GENERATOR

TFDL

TFDLCK

FDL

YELLOW

ALARM

TRANSMIT FDL

CLOCK GENERATOR

TFDLCK

TRANSMIT

FRAME

ASSEMBLER

5-4561(F).a

Figure 45. Block Diagram for the Transmit Facility Data Link Interface

Transmit ANSI T1.403 Bit-Oriented Messages (BOM)

When the ANSI BOM mode is enabled by setting register FDL_PR10 bit 7 to 1, the transmit FDL can send any of

the ANSI T1.403 ESF bit-oriented messages automatically through the FDL bit in the frame.

The transmit ESF FDL bit-oriented messages of the form 111111110X0X1X2X3X4X50 are taken from the transmit

ANSI FDL parameter register FDL_PR10 bit 0—bit 5. The ESF FDL bit-oriented messages will be repeated while

register FDL_PR10 bit 7 (FTANSI) is set to 1.

114

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

Transmit Facility Data Link Interface (continued)

Transmit ANSI Performance Report Messages (PRM)

When the ANSI PRM mode is enabled by setting register FDL_PR1 bit 7 to 1, the transmit FDL assembles and

transmits the ANSI performance report message once every second.

After assembling the ANSI PRM message, the receive framer stores the current second of the message in

registers FRM_SR62 and FRM_SR63 and transfers the data to the FDL transmit FIFO. After accumulating three

seconds (8 bytes) of the message, the FDL transmit block appends the header and the trailer (including the

opening and closing flags) to the PRM messages and transmits it to the framer for transmission to the line.

Table 51—Table 53 show the complete format of the PRM HDLC packet.

HDLC Operation

HDLC operation is the default mode of operation. The transmitter accepts parallel data from the transmit FIFO,

converts it to a serial bit stream, provides bit stuffing as necessary, adds the CRC-16 and the opening and closing

flags, and sends the framed serial bit stream to the transmit framer. HDLC frames on the serial link have the

following format.

Table 55. HDLC Frame Format

Frame Check

Opening Flag

User Data Field

Closing Flag

Sequence (CRC)

01111110

≥8 bits

16 bits

01111110

All bits between the opening flag and the CRC are considered user data bits. User data bits such as the address,

control, and information fields for LAPB or LAPD frames are fetched from the transmit FIFO for transmission. The

16 bits preceding the closing flag are the frame check sequence, cyclic redundancy check (CRC), bits.

Zero-Bit Insertion/Deletion (Bit Stuffing/Destuffing)

The HDLC protocol recognizes three special bit patterns: flags, aborts, and idles. These patterns have the

common characteristic of containing at least six consecutive 1s. A user data byte can contain one of these special

patterns. Transmitter zero-bit stuffing is done on user data and CRC fields of the frame to avoid transmitting one of

these special patterns. Whenever five 1s occur between flags, a 0 bit is automatically inserted after the fifth 1, prior

to transmission of the next bit. On the receive side, if five successive 1s are detected followed by a 0, the 0 is

assumed to have been inserted and is deleted (bit destuffing).

Agere Systems Inc.

115

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

HDLC Operation (continued)

Flags¹

All flags have the bit pattern 01111110 and are used for frame synchronization. The FDL HDLC block automatically

sends two flags between frames. If the chip-configuration register FDL_PR0 bit 1 (FLAGS) is cleared to 0, the 1s

idle byte (11111111) is sent between frames if no data is present in the FIFO. If FLAGS is set to 1, the FDL HDLC

block sends continuous flags when the transmit FIFO is empty. The FDL HDLC does not transmit consecutive

frames with a shared flag; therefore, two successive flags will not share the intermediate 0.

An opening flag is generated at the beginning of a frame (indicated by the presence of data in the transmit FIFO

and the transmitter enable register FDL_PR1 bit 3 = 1). Data is transmitted per the HDLC protocol until a byte is

read from the FIFO while register FDL_PR3 bit 7 (FTFC) set to 1. The FDL HDLC block follows this last user data

byte with the CRC sequence and a closing flag.

The receiver recognizes the 01111110 pattern as a flag. Two successive flags may or may not share the

intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are recognized

as flags by the FDL HDLC block). When the second flag is identified, it is treated as the closing flag. As mentioned

above, a flag sequence in the user data or CRC bits is prevented by zero-bit insertion and deletion. The HDLC

receiver recognizes a single flag between frames as both a closing and opening flag.

1.Regardless of the time-fill byte used, there always is an opening and closing flag with each frame. Back-to-back frames are separated by two

flags.

Aborts

An abort is indicated by the bit pattern of the sequence 01111111. A frame can be aborted by writing a 1 to register

FDL_PR3 bit 6 (FTABT). This causes the last byte written to the transmit FIFO to be replaced with the abort

sequence upon transmission. Once a byte is tagged by a write to FTABT, it cannot be cleared by subsequent writes

to register FDL_PR3. FTABT has higher priority than FDL transmit frame complete (FTFC), but FTABT and FTFC

should never be set to 1 simultaneously since this causes the transmitter to enter an invalid state requiring a

transmitter reset to clear. A frame should not be aborted in the very first byte following the opening flag. An easy

way to avoid this situation is to first write a dummy byte into the queue and then write the abort command to the

queue.

When receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven

consecutive 1s. The receive FDL unit will abort a frame whenever the receive framer detects a loss of frame

alignment. This results in the abort bit, and possibly the bad byte count bit and/or bad CRC bits, being set in the

status of frame status byte (see Table 54, Receive Status of Frame Byte on page 112) which is appended to the

receive data queue. All subsequent bytes are ignored until a valid opening flag is received.

Idles

In accordance with the HDLC protocol, the HDLC block recognizes 15 or more contiguous received 1s as idle.

When the HDLC block receives 15 contiguous 1s, the receiver idle bit register FDL_SR0 bit 6 (RIDL) is set.

For transmission, the 1s idle byte is defined as the binary pattern 11111111 (FF (hex)). If the FLAGS control bit in

register FDL_PR0 bit 1 is 0, the 1s idle byte is sent as the time-fill byte between frames. A time-fill byte is sent

when the transmit FIFO is empty and the transmitter has completed transmission of all previous frames. Frames

are sent back-to-back otherwise.

116

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

HDLC Operation (continued)

CRC-16

For given user data bits, 16 additional bits that constitute an error-detecting code (CRC-16) are added by the

transmitter. As called for in the HDLC protocol, the frame check sequence bits are transmitted most significant bit

first and are bit stuffed. The cyclic redundancy check (or frame check sequence) is calculated as a function of the

transmitted bits by using the ITU-T standard polynomial:

x

¹⁶+ x ¹²+ x ⁵+ 1

The transmitter can be instructed to transmit a corrupted CRC by setting register FDL_PR2 bit 7 (FTBCRC) to 1.

As long as the FTBCRC bit is set, the CRC is corrupted for each frame transmitted by logically flipping the least

significant bit of the transmitted CRC.

The receiver performs the same calculation on the received bits after destuffing and compares the results to the

received CRC-16 bits. An error indication occurs if, and only if, there is a mismatch.

Transmit FDL FIFO

Transmit FDL data is loaded into the 64-byte transmit FIFO via the transmit FDL data register, FDL_PR4. The

transmit FDL status register indicates how many additional bytes can be added to the transmit FIFO. The transmit

FDL interrupt trigger level register FDL_PR3 bit 0—bit 5 (FTIL) can be programmed to tailor service time intervals

to the system environment. The transmitter empty interrupt bit is set in the FDL interrupt status register FDL_SR0

bit 1 (FTEM) when the transmit FIFO has sufficient empty space to add the number of bytes specified in register

FDL_PR3 bit 0—bit 5. There is no interrupt indicated for a transmitter overrun that is writing more data than empty

spaces exist. Overrunning the transmitter causes the last valid data byte written to be repeatedly overwritten,

resulting in missing data in the frame.

Data associated with multiple frames can be written to the transmit FIFO by the controlling microprocessor.

However, all frames must be explicitly tagged with a transmit frame complete, register FDL_PR3 bit 7 (FTFC), or a

transmit abort, register FDL_PR3 bit 6 (FTABT). The FTFC is tagged onto the last byte of a frame written into the

transmitter FIFO and instructs the transmitter to end the frame and attach the CRC and closing flag following the

tagged byte. Once written, the FTFC cannot be changed by another write to register FDL_PR3. If FTFC is not

written before the last data byte is read out for transmission, an underrun occurs (FDL_SR0 bit 2). When the

transmitter has completed a frame, with a closing flag or an abort sequence, register FDL_SR0 bit 0 (FTDONE) is

set to 1. An interrupt is generated if FDL_PR2 bit 0 (FTDIE) is set to 1.

Sending 1-Byte Frames

Sending 1-byte frames with an empty transmit FIFO is not recommended. If the FIFO is empty, writing two data

bytes to the FIFO before setting FTFC provides a minimum of eight TFDLCK periods to set FTFC. When 1 byte is

written to the FIFO, FTFC must be written within 1 TFDLCK period to guarantee that it is effective. Thus, 1-byte

frames are subject to underrun aborts. One-byte frames cannot be aborted with FTABT. Placing the transmitter in

1s-idle mode, register FDL_PR0 bit 1 (FLAGS) = 0, lessens the frequency of underruns. If the transmit FIFO is not

empty, then 1-byte frames present no problems.

Transmitter Underrun

After writing a byte to the transmit queue, the user has eight TFDLCK cycles in which to write the next byte before

a transmitter underrun occurs. An underrun occurs when the transmitter has finished transmitting all the bytes in

the queue, but the frame has not yet been closed by setting FTFC. When a transmitter underrun occurs, the abort

sequence is sent at the end of the last valid byte transmitted. A FTDONE interrupt is generated, and the transmitter

reports an underrun abort until the interrupt status register is read.

Agere Systems Inc.

117

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

HDLC Operation (continued)

Using the Transmitter Status and Fill Level

The transmitter-interrupt level bits, register FDL_PR3 bit 0—bit 5, allow the user to instruct the FDL HDLC block to

interrupt the host processor whenever the transmitter has a predetermined number of empty locations. The

number of locations selected determines the time between transmitter empty, register FRM_SR0 bit 1 (FTEM),

interrupts. The transmitter status bits, register FDL_SR1, report the number of empty locations in the FDL

transmitter FIFO. The transmitter empty dynamic bit, register FDL_SR1 bit 7 (FTED), like the FTEM interrupt bit, is

set to 1 when the number of empty locations is less than or equal to the programmed empty level. FTED returns to

0 when the transmitter is filled to above the programmed empty level. Polled interrupt systems can use FTED to

determine when they can write to the FDL transmit FIFO.

Transparent Mode

The FDL HDLC block can be programmed to operate in the transparent mode by setting register FDL_PR9 bit 6

(FTRANS) to 1. In the transparent mode of operation, no HDLC processing is performed on user data. The

transparent mode can be exited at any time by setting FDL_PR9 bit 6 (FTRANS) to 0. It is recommended that the

transmitter be disabled when changing in and out of transparent mode. The transmitter should be reset by setting

FDL_PR1 bit 5 (FTR) to 1 whenever the mode is changed.

In the transmit direction, the FDL HDLC takes data from the transmit FIFO and transmits that data exactly bit-for-bit

on the TFDL interface. Transmit data is octet-aligned to the first TFDLCK after the transmitter has been enabled.

The bits are transmitted least significant bit first. When there is no data in the transmit FIFO, the FDL HDLC either

transmits all 1s, or transmits the programmed HDLC transmitter idle character (register FDL_PR5) if register

FDL_PR9 bit 6 (FMATCH) is set to 1. To cause the transmit idle character to be sent first, the character must be

programmed before the transmitter is enabled.

The transmitter empty interrupt, register FDL_SR0 bit 1 (FTEM), acts as in the HDLC mode. The transmitter-done

interrupt, register FDL_SR0 bit 0 (FTDONE), is used to report an empty FDL transmit FIFO. The FTDONE interrupt

thus provides a way to determine transmission end. Register FDL_SR0 bit 2 (FTUNDABT) interrupt is not active in

the transparent mode.

In the receive direction, the FDL HDLC block loads received data from the RFDL interface directly into the receive

FIFO bit-for-bit. The data is assumed to be least significant bit first. If FMATCH register FDL_PR9 bit 6 is 0, the

receiver begins loading data into the receive FIFO beginning with the first RFDLCK detected after the receiver has

been enabled. If the FMATCH bit is set to 1, the receiver does not begin loading data into the FIFO until the

receiver match character has been detected. The search for the receiver match character is in a sliding window

fashion if register FDL_PR9 bit 4 (FALOCT) bit is 0 (align to octet), or only on octet boundaries if FALOCT is set to

1. The octet boundary is aligned relative to the first RFDLCK after the receiver has been enabled. The matched

character and all subsequent bytes are placed in the receive FIFO. An FDL receiver reset, register FDL_PR1 bit 4

(FRR) = 1, causes the receiver to realign to the match character if FMATCH is set to 1.

118

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

Transparent Mode (continued)

The receiver full (FRF) and receiver overrun (FROVERUN) interrupts in register FDL_SR0 act as in the HDLC

mode. The received end of frame (FREOF) and receiver idle (FRIDL) interrupts are not used in the transparent

mode. The match status (FMSTAT) bit is set to 1 when the receiver match character is first recognized. If the

FMATCH bit is 0, the FMSTAT (FDL_PR9 bit 3) bit is set to 1 automatically when the first bit is received, and the

octet offset status bits (FDL_PR9 bit 0—bit 2) read 000. If the FMATCH bit is programmed to 1, the FMSTAT bit is

set to 1 upon recognition of the first receiver match character, and the octet offset status bits indicate the offset

relative to the octet boundary at which the receiver match character was recognized. The octet offset status bits

have no meaning until the FMSTAT bit is set to 1. An octet offset of 111 indicates byte alignment.

An interrupt for recognition of the match character can be generated by setting the FRIL level to 1. Since the

matched character is the first byte written to the FIFO, the FRF interrupt occurs with the writing of the match

character to the receive FIFO.

Programming Note: The match bit (FMATCH) affects both the transmitter and the receiver. Care should be taken

to correctly program both the transmit idle character and the receive match character before setting FMATCH. If

the transmit idle character is programmed to FF (hex), the FMATCH bit appears to affect only the receiver.

The operation of the receiver in transparent mode is summarized in Table 56.

Table 56. Receiver Operation in Transparent Mode

FALOCT

FMATCH

Receiver Operation

X

0

Serial-to-parallel conversion begins with first RFDLCK after FRE, register

FDL_PR1 bit 2, is set. Data loaded to receive FIFO immediately.

0

1

Match user-defined character using sliding window. Byte aligns once character is

recognized. No data to receive FIFO until match is detected.

Match user-defined character, but only on octet boundary. Boundary based on

first RFDLCK after FRE, register FDL_PR1 bit 2, set. No data to receive FIFO

until match is detected.

Agere Systems Inc.

119

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

Diagnostic Modes

Loopbacks

The serial link interface can operate in two diagnostic loopback modes: (1) local loopback and (2) remote loopback.

The local loopback mode is selected when register FDL_PR1 bit 1 (FLLB) is set to 1. The remote loopback is

selected when register FDL_PR1 bit 0 (FRLB) is set to 1. For normal traffic, i.e., to operate the transmitter and

receiver independently, the FLLP bit and the FRLB bits should both be cleared to 0. Local and remote loopbacks

cannot be enabled simultaneously.

In the local loopback mode:

1. TFDLCK clocks both the transmitter and the receiver.

2. The transmitter and receiver must both be enabled.

3. The transmitter output is internally connected to the receiver input.

4. The TFDL is active.

5. The RFDL input is ignored.

6. The communication between the transmit and receive FIFO buffers and the microprocessor continues normally.

XMIT HDLC FDL BLOCK

TFDL

FDL XMIT

XMIT HDLC

XMIT FIFO

INTERFACE

TFDLCK

RFDLCK

FDL RCVR

RCVR FIFO

RCVR HDLC

INTERFACE

RFDL

RCVR HDLC FDL BLOCK

5-4562(F)r.2

Figure 46. Local Loopback Mode

120

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Facility Data Link (FDL) (continued)

Diagnostic Modes (continued)

In the remote loopback mode:

1. Transmitted data is retimed with a maximum delay of 2 bits.

2. Received data is retransmitted on the TFDL.

3. The transmitter should be disabled. The receiver can be disabled or, if desired, enabled. Received data is sent

as usual to the receive FIFO if the receiver is enabled.

XMIT HDLC FDL BLOCK

TFDL

FDL XMIT

INTERFACE

XMIT FIFO

XMIT HDLC

TFDLCK

RFDLCK

FDL RCVR

INTERFACE

RCVR FIFO

RCVR HDLC

RFDL

RCVR HDLC FDL BLOCK

5-4563(F)r.1

Figure 47. Remote Loopback Mode

Agere Systems Inc.

121

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Phase-Lock Loop Circuit

The T7633 allows for independent transmit path and receive path clocking. The device provides outputs to control

variable clock oscillators on both the transmit and receive paths. As such, the system may have both the transmit

and receive paths phase-locked to two autonomous clock sources.

The block diagram of the T7633 phase detector circuitry is shown in Figure 48 on page 123. The T7633 uses elas-

tic store buffers (two frames) to accommodate the transfer of data from the system interface clock rate of

2.048 Mbits/s to the line interface clock rate of either 1.544 Mbits/s or 2.048 Mbits/s.The transmit line side of the

T7633 does not have any mechanism to monitor data overruns or underruns (slips) in its elastic store buffer. This

interface relies on the requirement that the PLLCK clock signal (variable) is phase-locked to the RCHICK clock sig-

nal (reference). When this requirement is not met, uncontrolled slips may occur in the transmit elastic store buffer

that would result in corrupting data and no indication will be given. Typically, a variable clock oscillator (VCXO) is

used to drive the PLLCK signal. The T7633 provides a phase error signal (PLLCK-EPLL) that can be used to con-

trol the VCXO. The PLLCK-EPLL signal is generated by monitoring the divided-down PLLCK (DIV-PLLCK) and

RCHICK (DIV-RCHICK) signals. The DIV-RCHICK signal is used as the reference to determine the phase differ-

ence between DIV-RCHICK and DIV-PLLCK. While DIV-RCHICK and DIVPLLCK are phase-locked, the PLLCK-

EPLL signal is in a high-impedance state. A phase difference between DIV-RCHICK and DIV-PLLCK drives

PLLCK-EPLL to either 5 V or 0 V. An RC circuit (typically, R = 1 kΩ and C = 0.1 µF) is used to filter these PLLCK-

EPLL pulses to control the VCXO.

The system can force TCHICK to be phase-locked to RLCK by using RLCK as a reference signal to control a

VCXO that is sourcing the TCHICK signal. The T7633 uses the receive line signal (RLCK) as the reference and the

TCHICK signal as the variable signal. The T7633 provides a phase error signal (TCHICK-EPLL) that can be used

to control the VCXO generating TCHICK. The TCHICK-EPLL signal is generated by monitoring the divided-down

TCHICK signal (DIV-TCHICK) and RLCK (DIV-RLCK) signals. The DIV-RLCK signal is used as the reference to

determine the phase difference between DIV-TCHICK and DIV-RLCK. While DIV-RLCK and DIV-TCHICK are

phase-locked, the TCHICK-EPLL signal is in a high-impedance state. A phase difference between DIV-RLCK and

DIV-TCHICK drives TCHICK-EPLL to either 5 V or 0 V. An RC circuit (typically, R = 1 kΩ and C = 0.1 µF) is used to

filter these TCHICK-EPLL pulses to control the VCXO. In this mode, the T7633 can be programmed to act as a

master timing source and is capable of generating the system frame synchronization signal through the TCHIFS

pin by setting FRM_PR45 bit 4 to 1.

122

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Phase-Lock Loop Circuit (continued)

EXTERNAL CIRCUIT

VOLTAGE-

CONTROLLED

CRYSTAL

OSCILLATOR

(VCXO)

PLLCK

DIV-PLLCK

PLLCK-EPLL

DIV-RCHICK

RCHICK

DIVIDER

CIRCUIT

PLLCK

DIVIDER

CIRCUIT

DIGITAL

PHASE

DETECTOR

INTERNAL_XLCK

INTERNAL_RCHICK

RCHICK

READ ADDRESS

TRANSMIT

2-FRAME

ELASTIC STORE

BUFFER

RECEIVE

CONCENTRATION

HIGHWAY

TLCK

WRITE ADDRESS

SYSTEM DATA

TRANSMIT

RCHIFS

FRAMER

INTERFACE

RCHIDATA

FACILITY DATA

TPD, TND

BUFFER OVERRUN

SLIP

BUFFER UNDERRUN

MONITOR

WRITE ADDRESS

FACILITY DATA

READ ADDRESS

SYSTEM DATA

TCHIDATA

RPD, RND

RLCK

RECEIVE

2-FRAME

ELASTIC STORE

BUFFER

TRANSMIT

CONCENTRATION

HIGHWAY

RECEIVE

FRAMER

TCHIFS

TCHICK

INTERFACE

INTERNAL_TCHICK

INTERNAL_RLCK

TCHICK

DIVIDER

CIRCUIT

RLCK

DIVIDER

CIRCUIT

DIGITAL

PHASE

DETECTOR

DIV-TCHICK

DIV-RLCK

TCHICK_EPLL

VOLTAGE-

CONTROLLED

CRYSTAL

OSCILLATOR

(VCXO)

EXTERNAL CIRCUIT

5-5268(F)r.2

Figure 48. T7633 Phase Detector Circuitry

Agere Systems Inc.

123

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer-System (CHI) Interface

DS1 Modes

The DS1 framing formats require rate adaptation from the 1.544 Mbits/s line interface bit stream to the system

interface which functions at multiples of a 2.048 Mbits/s bit stream. The rate adaptation results in the need for eight

stuffed time slots on the system interface since there are only 24 DS1 (1.544 Mbits/s) payload time slots while

there are 32 system (2.048 Mbits/s) time slots. Placement of the stuffed time slots is defined by register

FRM_PR43 bit 0—bit 2.

CEPT Modes

The framer maps the line time slots into the corresponding system time slot one-to-one. Framing time slot 0, the

FAS and NFAS bytes, are placed in system time slot 0.

Receive Elastic Store

The receive interface between the framer and the system (CHI) includes a 2-frame elastic store buffer to enable

rate adaptation. The receive line elastic store buffer contains circuitry that monitors the read and write pointers for

potential data overrun and underrun (slips) conditions. Whenever this slip circuitry determines that a slip may occur

in the receive elastic store buffer, it will adjust the read pointer such that a controlled slip is performed. The con-

trolled slip is implemented by dropping or repeating a complete frame at the frame boundaries. The occurrence of

controlled slips in the receive elastic store are indicated in the status register FRM_SR3 bit 6 and bit 7.

Transmit Elastic Store

The transmit interface between the framer and the system (CHI) includes a 2-frame elastic store buffer to enable

rate adaptation. The line transmit clock applied to PLLCK (pins 7/31) must be phase-locked to RCHICK. No indica-

tion of a slip in the transmit elastic store is given.

124

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Concentration Highway Interface (CHI)

Each framer has a dual, high-speed, serial interface to the system known as the concentration highway interface

(CHI). This flexible bus architecture allows the user to directly interface to other Agere components which use this

interface, as well as to Mitel^®and AMD^®TDM highway interfaces, with no glue logic. Configured via the highway

control registers FRM_PR45 through FRM_PR66, this interface can be set up in a number of different configura-

tions.

The following is a list of the CHI features:

1. Agere standard interface for communication devices.

2. Two pairs of transmit and receive paths to carry data in 8-bit time slots.

3. Programmable definition of highways through offset and clock-edge options which are independent for transmit

and receive directions.

4. Programmable idle code substitution of received time slots.

5. Programmable 3-state control of each transmit time slot.

6. Independent transmit and receive framing signals to synchronize each direction of data flow.

7. An 8 kHz frame synchronization signal internally generated from the received line clock.

8. Compatible with Mitel and AMD PCM highways.

Supported is the optional configuration of the CHI which presents the signaling information along with the data in

any framing modes when the device is programmed for the associated signaling mode (ASM). This mode is dis-

cussed in the signaling section.

Data can be transmitted or received on either one of two interface ports, called CHIDATA and CHIDATAB. The

user-supplied clocks (RCHICLK and TCHICLK) control the timing on the transmit or receive paths. Individual time

slots are referenced to the frame synchronization (RCHIFS and TCHIFS) pulses. Each frame consists of 32 time

slots at a programmable data rate of 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s requiring a clock (TCHICK and

RCHICK) of the same rate. Alternatively, a mode is supported in which the clocks (TCHICK and RCHICK) can be

twice the data rate, the CMS mode. This mode is controlled by register FRM_PR45 bit 1. The clock and data rates

of the transmit and receive highways are programmed independently.

Rate adaptation is required for all DS1 formats between the 1.544 Mbits/s line rate and 2.048 Mbits/s,

4.966 Mbits/s, or 8.182 Mbits/s CHI rate. This is achieved by means of stuffing eight idle time slots into the existing

twenty-four time slots of the T1 frame. Idle time slots can occur every fourth time slot (starting in the first, second,

third, or fourth time slot) or be grouped together at the end of the CHI frame as described in register FRM_PR43

bit 0—bit 2. The positioning of the idle time slots is the same for transmit and receive directions. Idle time slots con-

tain the programmable code of register FRM_PR23. Unused time slots can be disabled by forcing the TCHIDATA

interface to a high-impedance state for the interval of the disabled time slots.

Agere Systems Inc.

125

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Concentration Highway Interface (CHI) (continued)

CHI Parameters

The CHI parameters that define the receive and transmit paths are given in Table 57.

Table 57. Summary of the T7633’s Concentration Highway Interface Parameters

Name

Description

HWYEN

Highway Enable (FRM_PR45 bit 7). A 1 in this bit enables the transmit and receive

concentration highway interfaces. This allows the framer to be fully configured before

transmission to the highway. A 0 forces the idle code as defined in register

FRM_PR22, to be transmitted to the line in all payload time slots while TCHIDATA is

forced to a high-impedance state for all CHI transmitted time slots.

CHIMM

Concentration Highway Master Mode (PRM_PR45 bit 4). The default mode

CHIMM = 0 enables an external system frame synchronization signal (TCHIFS) to

drive the transmit CHI. A 1 enables the transmit CHI to generate a system frame syn-

chronization signal from the receive line clock. The transmit CHI system frame syn-

chronization signal is generated on the TCHIFS output pin. Applications using the

receive line clock as the reference clock signal of the system are recommended to

enable this mode and use the TCHIFS signal generated by the framer. The receive

CHI path is not affected by this mode.

CHIDTS

CHI Double Time-Slot Mode (FRM_PR65 bit 1 and FRM_PR66 bit 1). CHIDTS

defines the 4.096 Mbits/s and 8.192 Mbits/s CHI modes. CHIDTS = 0 enables the 32

contiguous time-slot mode. This is the default mode. CHIDTS = 1 enables the double

time-slot mode in which the transmit CHI drives TCHIDATA for one time slot and then

3-states for the subsequent time slot, and the receive CHI latches data from RCHI-

DATA for one time slot and then ignores the following time slot and so on. CHIDTS =

1 allows two CHIs to interleave frames on a common bus.

TFE

Transmit Frame Edge (FRM_PR46 bit 3). TFE = 0 (or 1), TCHIFS is sampled on the

falling (or rising) edge of TCHICK. In CHIMM (CHI master mode), the TCHIFS pin

outputs a transmit frame strobe to provide synchronization for TCHIDATA. When

TFE = 1 (or 0), TCHIFS is centered around rising (or falling) edge of TCHICK. In this

mode, TCHIFS can be used for receive data on RCHIDATA. The timing for TCHIFS in

CHIMM = 1 mode is identical to the timing for TCHIFS in CHIMM = 0 mode.

RFE

Receive Frame Edge (FRM_PR46 bit 7). RFE = 0 (or 1), RCHIFS is sampled on the

falling (or rising) edge of RCHICK.

CDRS0—CDRS1

CHI Data Rate (FRM_PR45 bit 2 and bit 3). Two-bit control for selecting the CHI data

rate. The default state (00) enables the 2.048 Mbits/s.

CDRS Bit:

2 3

0 0

0 1

1 0

1 1

CHI Data Rate

2.048 Mbits/s

4.096 Mbits/s

8.192 Mbits/s

Reserved

CMS

Clock Select Mode (FRM_PR45 bit 1). When CMS = 0, the concentration highway

clocks (TCHICK and RCHCK) and data (RCHIDATA, RCHIDATAB, TCHIDATA, or

TCHIDATAB) have the same rate. When CMS = 1, the concentration highway clocks

are twice the rate of CHI data.

TCE

RCE

Transmitter Clock Edge (FRM_PR47 bit 6). TCE = 0 (or 1), TCHIDATA is clocked on

the falling (or rising) edge of TCHICK.

Receiver Clock Edge (FRM_PR48 bit 6). RCE = 0 (or 1), RCHIDATA is latched on

the falling (or rising) edge of RCHICK.

126

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Concentration Highway Interface (CHI) (continued)

CHI Parameters (continue)

Table 57. Summary of the T7633’s Concentration Highway Interface Parameters (continued)

Name

Description

TTSE31—TTSE0

Transmit Time-Slot Enable 31—0 (FRM_PR49—FRM_PR52). These bits define

which transmit CHI time slots are enabled. A 1 enables the TCHIDATA or TCHI-

DATAB time slot. A 0 forces the CHI transmit highway time slot to be 3-stated.

RTSE31—RTSE0

Receive Time-Slot Enable 31—0 (FRM_PR53—FRM_PR56). These bits define

which receive CHI time slots are enabled. A 1 enables the RCHIDATA or RCH-

DATAB time slots. A 0 disables the time slot and transmits the programmable idle

code of register FRM_PR22 to the line interface.

THS31—THS0

RHS31—RHS0

TOFF2—TOFF0

Transmit Highway Select 31—0 (FRM_PR57—FRM_PR60). These bits define

which transmit CHI highway, TCHIDATA or TCHIDATAB, contains valid data for the

active time slot. A 0 enables TCHIDATA; a 1 enables the TCHIDATAB.

Receive Highway Select 31—0 (FRM_PR61—FRM_PR64). These bits define which

receive CHI highway, RCHIDATA or RCHIDATAB, contains valid data for the active

time slot. A 0 enables RCHIDATA; a 1 enables the RCHIDATAB.

Transmitter Bit Offset (FRM_PR46 bit 0—bit 2). These bits are used in conjunction

with the transmitter byte offset to define the beginning of the transmit frame. They

determine the offset relative to TCHIFS, for the first bit of transmit time slot 0. For CMS

= 1, the offset is twice the number of TCHICK clock periods by which transmission of

the first bit is delayed. For CMS = 0, the offset is the number of TCHICK cycles by

which the first bit is delayed.

ROFF2—ROFF0

Receiver Bit Offset (FRM_PR46 bit 4—bit 6). These bits are used in conjunction with

the receiver byte offset to define the beginning of the receiver frame. They determine

the offset relative to the RCHIFS, for the first bit of receive time slot 0. For CMS = 1,

the offset is twice the number of RCHICK clock periods by which the first bit is delayed.

For CMS = 0, the offset is the number of RCHICK cycles by which the first bit is

delayed.

TBYOFF6—TBYOFF0 Transmitter Byte Offset (FRM_PR47 bit 0—bit 5 and FRM_PR65 bit 0). These bits

determine the offset from the TCHIFS to the beginning of the next frame on the

transmit highway. Note that in the ASM mode, a frame consists of 64 contiguous bytes;

whereas in other modes, a frame contains 32 contiguous bytes. Allowable offsets:

2.048 Mbits/s

4.096 Mbits/s

8.192 Mbits/s

0—31 bytes.

0—63 bytes.

0—127 bytes.

RBYOFF6—RBYOFF0 Receiver Byte Offset (FRM_PR48 bit 0—bit 5 and FRM_PR66 bit 0). These bits

determine the offset from RCHIFS to the beginning of the receive CHI frame. Note that

in the ASM mode, a frame consists of 64 contiguous bytes; whereas in other modes,

a frame contains 32 contiguous bytes. Allowable offsets:

2.048 Mbits/s

4.096 Mbits/s

8.192 Mbits/s

0—31 bytes.

0—63 bytes.

0—127 bytes.

Agere Systems Inc.

127

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Concentration Highway Interface (CHI) (continued)

CHI Parameters (continued)

Table 57. Summary of the T7633’s Concentration Highway Interface Parameters (continued)

Name

Description

TLBIT

Transmit Least Significant Bit First (FRM_PR47 bit 7). When TLBIT = 0 (the

default mode), the most significant bit (bit 0) of each time slot is transmitted first.

When TLBIT = 1, the least significant bit (bit 7) of each time slot is transmitted first.

RLBIT

ASM

Receive Least Significant Bit First (FRM_PR48 bit 7). When RLBIT = 0 (the default

mode), the first bit of each time slot received on the received data input is received as

the most significant bit (bit 0) of each time slot. When RLBIT = 1, the first bit of each

time slot on the received data input is received as the least significant bit (bit 7) of

each time slot.

Associated Signaling Mode (FRM_PR44 bit 2). When enabled, the associate sig-

naling mode configures the CHI to carry both payload data and its associated signal-

ing information. Enabling this mode must be in conjunction with the programming of

the CHI data rate to either 4.048 Mbits/s or 8.096 Mbits/s. Each time slot consists of

16 bits where 8 bits are data and the remaining 8 bits are signaling information.

STS0—STS2

Stuffed Time Slots (FRM_PR43 bit 0—bit 2). Valid only in T1 framing formats, these

3 bits define the location of the eight stuffed CHI (unused) time slots.

128

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Concentration Highway Interface (CHI) (continued)

CHI Frame Timing

CHI Timing with CHIDTS Disabled

Figure 49 illustrates the CHI frame timing when CHIDTS is disabled (registers FRM_PR65 bit 1 (TCHIDTS) and

FRM_PR66 bit 1 (RCHDTS) = 0) and the CHI is not in the associated signaling mode (FRM_PR44 bit 2 (ASM) =

0). The frames are 125 µs long and consist of 32 contiguous time slots.

In DS1 frame modes, the CHI frame consists of 24 payload time slots and eight stuffed (unused) time slots.

In CEPT frame modes, the CHI frame consists of 32 payload time slots.

125 µs

CHIFS

DS1 FORMAT

2.048 Mbits/s CHI:

FRAME 1

24 VALID TIME SLOTS

HIGH IMPEDANCE

TCHIDATA

FRAME 2

8 STUFFED

SLOTS*

24 VALID TIME SLOTS

RCHIDATA

CEPT FORMAT

2.048 Mbits/s CHI:

32 VALID TIME SLOTS

FRAME 1

TCHIDATA

or

FRAME 2

RCHIDATA

4.096 Mbits/s CHI:

TCHIDATA

HIGH IMPEDANCE

FRAME 1

FRAME 2

RCHIDATA

8.192 Mbits/s CHI:

TCHIDATA

HIGH IMPEDANCE

FRAME 1

FRAME 2

RCHIDATA

5-5269(F).ar.2

* The position of the stuffed time is controlled by register FRM_PR43 bit 0—bit 2.

Figure 49. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0—bit 2 = 100 (Binary))

Agere Systems Inc.

129

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Concentration Highway Interface (CHI) (continued)

CHI Frame Timing (continued)

CHI Timing with CHIDTS Enabled

Figure 50 illustrates the CHI frame timing when CHIDTS is enabled (registers FRM_PR65 bit 1 (TCHIDTS) and

FRM_PR66 bit 1 (RCHIDTS) = 1) and ASM is disabled (register FRM_PR44 bit 2 (ASM) = 0). In the CHIDTS

mode, valid CHI payload time slots are alternated with high-impedance intervals of one time-slot duration. This

mode is valid only for 4.096 Mbits/s and 8.192 Mbits/s CHI rates.

125 µs

CHIFS

FRAME 1

FRAME 2

4.096 Mbits/s CHI

TCHIDATA

TIME TIME

SLOT SLOT

TS0

TS1

TS2

TS3

TS4

TS30

T30

TS31

TS0

8 bits

TS0

TS1

RCHIDATA

8.192 Mbits/s CHI

TCHIDATA

HIGH IMPEDANCE

TS0

TS1

TS2

TS30

TS31

TS0

RCHIDATA

5-6454(F)r.3

Figure 50. CHIDTS Mode Concentration Highway Interface Timing

130

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Concentration Highway Interface (CHI) (continued)

CHI Frame Timing (continued)

CHI Timing with Associated Signaling Mode Enabled

Figure 51 illustrates the CHI frame timing when the associated signaling mode is enabled (register FRM_PR44 bit

2 (ASM) = 1) and the CHIDTS mode is disabled (registers FRM_PR65 bit 1 (TCHIDTS) = 0 and FRM_PR66 bit 1

(RCHDTS) = 0). The frames are 125 µs long and consist of 32 contiguous 16-bit time slots.

In DS1 frame formats, each frame consists of 24 time slots and eight stuffed time slots. Each time slot consists of

two octets.

In CEPT modes, each frame consists of 32 time slots. Each time slot consists of two octets.

125 µs

CHIFS

4.096 Mbits/s CHI:

FRAME = 64 bytes: 32 DATA + 32 SIGNALING

FRAME 1

TCHIDATA

or

FRAME 2

RCHIDATA

DATA AND SIGNALING BYTES ARE INTERLEAVED

DATA 0

SIGNALING 0

DATA 31

SIGNALING 31

DATA 0

FRAME

8.192 Mbits/s CHI:

TCHIDATA

HIGH IMPEDANCE

FRAME 1

FRAME 2

RCHIDATA

FRAME 1

5-5270(F).ar.3

Figure 51. Associated Signaling Mode Concentration Highway Interface Timing

CHI Timing with Associated Signaling Mode and CHIDTS Enabled

Figure 52 illustrates the CHI frame timing in the associated signaling mode (register FRM_PR44 bit 2 (ASM) = 1)

and CHIDTS enabled (registers FRM_PR65 bit 1 (TCHIDTS) = 1 and FRM_PR66 bit 1 (RCHIDTS) = 1).

8.192 Mbits/s CHI WITH ASM (ASSOCIATED SIGNALING MODE) ENABLED

TS0

TS1

TS31

TS0

TCHIDATA

OR

RCHIDATA

*

DATA SIGNALING

16 bits

1 TIME SLOT

5-6454(F).ar.2

* High-impedance state for TCHIDATA and not received (don’t care) for RCHIDATA.

Figure 52. CHI Timing with ASM and CHIDTS Enabled

Agere Systems Inc.

131

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Concentration Highway Interface (CHI) (continued)

CHI Offset Programming

To facilitate bit offset programming, two additional internal parameters are introduced: CEX is defined as the clock

edge with which the first bit of time slot 0 is transmitted; CER is defined as the clock edge on which bit 0 of time slot

0 is latched. CEX and CER are counted relative to the edge on which the CHIFS signal is sampled. Values of CEX

and CER depend upon the values of the parameters described above.

The following three tables give decimal values of CEX and CER for various values of CMS, TFE, RFE, TCE, RCE,

TOFF[2:0], and ROFF[2:0]. The byte (time slot) offsets are assumed to be zero in the following examples.

Table 58. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0

RFE/

TFE

RCE/

TCE

ROFF[2:0] or TOFF[2:0]

000

4

001

6

010

8

011

10

9

100

12

11

12

101

14

13

14

110

16

15

16

111

18

17

18

CER

or

CEX

0

1

0

1

0

1

3

5

7

(decimal)

3

5

7

9

4

6

8

10

Table 59. Programming Values for TOFF[2:0] when CMS = 1

TFE

TCE

TOFF[2:0]

000

4

001

8

010

12

011

16

15

16

100

20

19

20

101

110

111

CEX

(decimal)

0

1

0

1

0

1

24

23

24

28

27

28

32

31

32

3

7

11

3

7

11

4

8

12

Table 60. Programming Values for ROFF[2:0] when CMS = 1

RFE

RCE

ROFF[2:0]

000

6

001

10

9

010

14

13

14

011

18

17

18

100

22

21

22

101

26

110

30

29

30

111

34

33

34

CER

(decimal)

0

1

0

1

0

1

5

25

5

9

25

6

10

26

132

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Concentration Highway Interface (CHI) (continued)

CHI Offset Programming (continued)

Figure 53 shows an example of the relative timing of CHI 2.048 Mbits/s data with the following parameters:

1. CMS = 0, TFE, RFE = 0.

2. TCE = 1, TOFF[2:0] = 000, TBYOFF[6:0] = 0000000, TLBIT = 0,

3. RCE = 0, ROFF[2:0] = 000, RBYOFF[6:0] = 0000000, RLBIT = 0.

CHIFS IS SAMPLED ON THIS EDGE: FE = 0

1

3

5

7

CHICK

2

4

6

8

TCHIFS, RCHIFS

CEX = 3

HIGH IMPEDANCE

BIT 0, TS 0

CER = 4

BIT 0, TS 0

BIT 1, TS 0

BIT 2, TS 0

TCHIDATA: TCE = 1

RCHIDATA: RCE = 0

BIT 2, TS 0

5-2202(F).cr.1

Figure 53. TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 0 (CEX = 3 and CER = 4,

Respectively)

Figure 54 shows an example of the relative timing of CHI 2.048 Mbits/s data with the following parameters:

1. CMS = 1, TFE,RFE = 0.

2. TCE = 1, TOFF[2:0] = 000, TBYOFF[6:0] = 0000000, TLBIT = 0,

3. RCE = 0, ROFF[2:0] = 000, RBYOFF[6:0] = 0000000, RLBIT = 0.

CHIFS IS SAMPLED ON THIS EDGE: FE = 0

1

3

5

7

CHICK

2

4

6

8

TCHIFS, RCHIFS

CEX = 3

HIGH IMPEDANCE

TCHIDATA: TCE = 1

RCHIDATA: RCE = 0

BIT 1, TS 0

BIT 0, TS 0

CER = 6

BIT 1, TS 0

BIT 0, TS 0

5-2203(F).cr.1

Figure 54. CHI TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 1 (CEX = 3 and CER = 6,

Respectively)

Agere Systems Inc.

133

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Concentration Highway Interface (CHI) (continued)

CHI Offset Programming (continued)

Figure 55 and Figure 56 illustrate the CHI timing.

RCHICLK

t14S

t14H

t14S: RCHIFS SETUP = 30 ns min

t14H: RCHIFS HOLD = 45 ns min

RCHIFS

t15S

t15H

t15S: RCHIDATA SETUP = 25 ns min

t15S: RCHIDATA HOLD = 25 ns min

RCHIDATA

5-3916(F).cr.1

Note: For case illustrated, RFE = 0, and RCE = 0.

Figure 55. Receive CHI (RCHIDATA) Timing

TCHICLK

TCHIFS

t14S

t14H

t14S: TCHIFS SETUP = 35 ns min

t14H: TCHIFS HOLD = 45 ns min

t19

t19: TCHICK TO TCHIDATA DELAY = 25 ns max

TCHIDATA

5-3917(F).c

Note: For case illustrated, TFE = 0 and TCE = 0.

Figure 56. Transmit CHI (TCHIDATA) Timing

134

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

JTAG Boundary-Scan Specification

Principle of the Boundary Scan

The boundary scan (BS) is a test aid for chip, module, and system testing. The key aspects of BS are as follows:

1. Testing the connections between ICs on a particular board.

2. Observation of signals to the IC pins during normal operating functions.

3. Controlling the built-in self-test (BIST) of an IC. T7633 does not support BS-BIST.

Designed according to the IEEE^®Std. 1149.1-1990 standard, the BS test logic consists of a defined interface: the

test access port (TAP). The TAP is made up of four signal pins assigned solely for test purposes. The fifth test pin

ensures that the test logic is initialized asynchronously. The BS test logic also comprises a 16-state TAP controller,

an instruction register with a decoder, and several test data registers (BS register, BYPASS register, and IDCODE

register). The main component is the BS register that links all the chip pins to a shift register by means of special

logic cells. The test logic is designed in such a way that it is operated independently of the application logic of the

T7633 (the mode multiplexer of the BS output cells may be shared). Figure 57 illustrates the block diagram of the

T7633’s BS test logic.

BOUNDARY-SCAN REGISTER

CHIP KERNEL

OUT

IN

(UNAFFECTED BY BOUNDARY-SCAN TEST)

IDCODE REGISTER

TDO

MUX

BYPASS REGISTER

TDI

INSTRUCTION REGISTER

TRST

TMS

TCK

INSTRUCTION

DECODER

TAP

CONTROLLER

5-3923(F)r.4

Figure 57. Block Diagram of the T7633’s Boundary-Scan Test Logic

Agere Systems Inc.

135

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

JTAG Boundary-Scan Specification (continued)

Test Access Port Controller

The test access port controller is a synchronous sequence controller with 16 states. The state changes are preset

by the TMS, TCK, and TRST signals and by the previous state. The state change always take place when the TCK

edge rises. Figure 58 shows the TAP controller state diagram.

TRST = 0

TEST LOGIC

RESET

1

0

1

RUN TEST/

IDLE

SELECT DR

SELECT IR

0

CAPTURE DR

0

CAPTURE IR

0

1

SHIFT DR

1

SHIFT IR

0

1

0

1

EXIT1 DR

EXIT1 IR

0

PAUSE DR

1

0

PAUSE IR

1

0

EXIT2 DR

1

EXIT2 IR

1

0

UPDATE DR

UPDATE IR

0

1

0

1

5-3924(F)r.5

Figure 58. BS TAP Controller State Diagram

The value shown next to each state transition in Figure 58 represents the signal present at TMS at the time of a ris-

ing edge at TCK.

The description of the TAP controller states is given in IEEE Std. 1149.1-1990 Section 5.1.2 and is reproduced in

Table 61 and Table 62.

136

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

JTAG Boundary-Scan Specification (continued)

Test Access Port Controller (continued)

Table 61. TAP Controller States in the Data Register Branch

Name

Description

TEST LOGIC RESET The BS logic is switched in such a way that normal operation of the ASIC is

adjusted. The IDCODE instruction is initialized by TEST LOGIC RESET.

Irrespective of the initial state, the TAP controller has achieved TEST LOGIC

RESET after five control pulses at the latest when TMS = 1. The TAP controller

then remains in this state. This state is also achieved when TRST = 0.

RUN TEST/IDLE

Using the appropriate instructions, this state can activate circuit parts or initiate

a test. All of the registers remain in their present state if other instructions are

used.

SELECT DR

This state is used for branching to the test data register control.

CAPTURE DR

The test data is loaded in the test data register parallel to the rising edge of TCK

in this state.

SHIFT DR

The test data is clocked by the test data register serially to the rising edge of TCK

in the state. The TDO output driver is active.

EXIT (1/2) DR

PAUSE DR

This temporary state causes a branch to a subsequent state.

The input and output of test data can be interrupted in this state.

UPDATE DR

The test data is clocked into the second stage of the test data register parallel to

the falling edge of TCK in this state.

Table 62. TAP Controller States in the Instruction Register Branch

Name

Description

SELECT IR

CAPTURE IR

This state is used for branching to the instruction register control.

The instruction code 0001 is loaded in the first stage of the instruction register

parallel to the rising edge of TCK in this state.

SHIFT IR

The instructions are clocked into the instruction register serially to the rising edge

of TCK in the state. The TDO output driver is active.

EXIT (1/2) IR

PAUSE IR

This temporary state causes a branch to a subsequent state.

The input and output of instructions can be interrupted in this state.

UPDATE IR

The instruction is clocked into the second stage of the instruction register parallel

to the falling edge of TCK in this state.

Agere Systems Inc.

137

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

JTAG Boundary-Scan Specification (continued)

Instruction Register

The instruction register (IR) is 4 bits in length. Table 63 shows the BS instructions implemented by the T7633.

Table 63. T7633’s Boundary-Scan Instructions

Instruction

EXTEST

Code

0000

0001

Act. Register

TDI→TDO

Mode

TEST

NORMAL

X

Function

Output Defined Via

BS Register

Boundary Scan

Identification

BYPASS

Test external

connections

IDCODE

Read Manuf.

Register

Core Logic

HIGHZ

0100

0101

1111

—

3-state

Sample/load

Min. shift path

—

Output — High Impedance

Core Logic

SAMPLE/PRELOAD

BYPASS

Boundary Scan NORMAL

BYPASS

NORMAL

X

Core Logic

EVERYTHING ELSE

Output — High Impedance

The instructions not supported in T7633 are INTEST, RUNBIST, TOGGLE. A fixed binary 0001 pattern (the 1 into

the least significant bit) is loaded into the IR in the capture-IR controller state. The IDCODE instruction (binary

0001) is loaded into the IR during the test-logic-reset controller state and at powerup.

The following is an explanation of the instructions supported by T7633 and their effect on the devices’ pins.

EXTEST:

This instruction enables the path cells, the pins of the ICs, and the connections between ASICs to be tested via the

circuit board. The test data can be loaded in the chosen position of the BS register by means of the SAMPLE/PRE-

LOAD instruction. The EXTEST instruction selects the BS register as the test data register. The data at the function

inputs is clocked into the BS register on the rising edge of TCK in the CAPTURE-DR state. The contents of the BS

register can be clocked out via TDO in the SHIFT-DR state. The value of the function outputs is solely determined

by the contents of the data clocked into the BS register and only changes in the UPDATE-DR state on the falling

edge of TCK.

IDCODE:

Information regarding the manufacturer’s ID for Agere, the IC number, and the version number can be read out

serially by means of the IDCODE instruction. The IDCODE register is selected, and the BS register is set to normal

mode in the UPDATE-IR state. The IDCODE is loaded at the rising edge of TCK in the CAPTURE-DR state. The

IDCODE register is read out via TDO in the SHIFT-DR state.

HIGHZ:

All 3-statable outputs are forced to a high-impedance state, and all bidirectional ports to an input state by means of

the HIGHZ instruction. The impedance of the outputs is set to high in the UPDATE-IR state. The function outputs

are only determined in accordance with another instruction if a different instruction becomes active in the UPDATE-

IR state. The BYPASS register is selected as the test data register. The HIGHZ instruction is implemented in a sim-

ilar manner to that used for the BYPASS instruction.

SAMPLE/PRELOAD:

The SAMPLE/PRELOAD instruction enables all the inputs and outputs pins to be sampled during operation (SAM-

PLE) and the result to be output via the shift chain. This instruction does not impair the internal logic functions.

Defined values can be serially loaded in the BS cells via TDI while the data is being output (PRELOAD).

138

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

JTAG Boundary-Scan Specification (continued)

Instruction Register (continued)

BYPASS:

This instruction selects the BYPASS register. A minimal shift path exists between TDI and TDO. The BYPASS reg-

ister is selected after the UPDATE-IR. The BS register is in normal mode. A 0 is clocked into the BYPASS register

during CAPTURE-DR state. Data can be shifted by the BYPASS register during SHIFT-DR. The contents of the BS

register do not change in the UPDATE-DR state. Please note that a 0 that was loaded during CAPTURE-DR

appears first when the data is being read out.

Boundary-Scan Register

The boundary-scan register is a shift register, whereby one or more BS cells are assigned to every digital T7633

pin (with the exception of the pins for the BS architecture, analog signals, and supply voltages). The T7633’s

boundary-scan register bit-to-pin assignment is to be determined.

BYPASS Register

The BYPASS register is a one-stage, shift register that enables the shift chain to be reduced to one stage in the

T7633.

IDCODE Register

The IDCODE register identifies the T7633 by means of a parallel, loadable, 32-bit shift register. The code is loaded

on the rising edge of TCK in the CAPTURE-DR state. The 32-bit data is organized into four sections as follows.

Table 64. IDCODE Register

Version

Bits 31—28

0001

Part Number

Bits 27—12

Manufacturer ID

Bits 11—1

1

Bit 0

1

0111 011000110011

0000 0011101

3-State Procedures

The 3-state input participates in the boundary scan. It has a BS cell, but buffer blocking via this input is suppressed

for the EXTEST instruction. The 3-state input is regarded as a signal input that is to participate in the connection

test during EXTEST. The buffer blocking function should not be active during EXTEST to ensure that the update

pattern at the T7633 outputs does not become corrupted.

Agere Systems Inc.

139

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Microprocessor Interface

Overview

The T7633 device is equipped with a microprocessor interface that can operate with most commercially available

microprocessors. The microprocessor interface provides access to all the internal registers through a 12-bit

address bus and an 8-bit data bus. Inputs MPMODE and MPMUX (pins 74 and 76) are used to configure this inter-

face into one of four possible modes, as shown in Table 65. The MPMUX setting selects either a multiplexed (8-bit

address/data bus, AD[7:0]) or a demultiplexed (12-bit address bus, A[11:0] and an 8-bit data bus AD[7:0]) mode of

operation. The MPMODE setting selects the associated set of control signals required to access a set of registers

within the device.

The microprocessor interface can operate at speeds up to 33 MHz in interrupt-driven or polled mode without

requiring any wait-states. For microprocessors operating at greater than 33 MHz, the RDY_DTACK output (pin

100) may be used to introduce wait-states in the read/write cycles.

In the interrupt-driven mode, one or more device alarms will assert the INTERRUPT output (pin 99) once per alarm

activation. After the microprocessor identifies the source(s) of the alarm(s) (by reading the global interrupt register)

and reads the specific alarm status registers, the INTERRUPT output will deassert. In the polled mode, however,

the microprocessor monitors the various device alarm status by periodically reading the alarm status registers

within the line interface unit, framer, and HDLC blocks without the use of INTERRUPT. In both interrupt and polled

methods of alarm servicing, the status registers within an identified block will clear on a microprocessor read cycle

only when the alarm condition within that block no longer exists; otherwise, the alarm status register bit remains

set.

The powerup default states for the line interface unit, framer, and the HDLC blocks are discussed in their respec-

tive sections. All read/write registers within these blocks must be written by the microprocessor on system start-up

to guarantee proper device functionality. Register addresses not defined in this data sheet must not be writ-

ten.

Details concerning the microprocessor interface configuration modes, pinout definitions, clock specifications,

register address map, I/O timing specifications, and the I/O timing diagrams are described in the following sections.

Microprocessor Configuration Modes

Table 65 highlights the four microprocessor modes controlled by the MPMUX and MPMODE inputs (pins 76 and

74).

Table 65. Microprocessor Configuration Modes

Generic Control, Data, and

Mode

MPMODE

MPMUX

Address/Data Bus

Output Pin Names

Mode 1

Mode 2

Mode 3

Mode 4

0

1

0

1

0

1

DEMUXed*

MUXed

CS, AS, DS, R/W, A[11:0], AD[7:0], INT, DTACK^†

CS, AS, DS, R/W, A[11:8], AD[7:0], INT, DTACK^†

CS, ALE, RD, WR, A[11:0], AD[7:0], INT, RDY

CS, ALE, RD, WR, A[11:8], AD[7:0], INT, RDY

DEMUXed*

MUXed

*

ALE_AS may be connected to ground in this mode.

†

The DTACK signal is asynchronous to the MPCLK signal.

140

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Microprocessor Interface (continued)

Microprocessor Interface Pinout Definitions

The Mode [1—4] specific pin definitions are given in Table 66. Note that the microprocessor interface uses the

same set of pins in all modes.

Table 66. Mode [1—4] Microprocessor Pin Definitions

Generic

Pin Name

Assertion

Sense

Configuration

Pin Number Device Pin Name

Pin_Type

Function

Mode 1

107

75

WR_DS

RD_R/W

DS

Input

Active-Low

Data Strobe

Read/Write

R/W = 1 => Read

R/W = 0 => Write

R/W

Input

—

77

78

ALE_AS

CS

AS

CS

Input

Active-Low

Active-High/

Address Strobe

Chip Select

1

99

INTERRUPT

Output

Interrupt

4

Low

2

100

86—79

98—87

101

RDY_DTACK

AD[7:0]

DTACK

Output

I/O

Active-Low

Data Acknowledge

Data Bus

AD[7:0]

A[11:0]

MPCLK

DS

—

A[11:0]

Input

—

Address Bus

MPCLK

—

Active-Low

—

Microprocessor Clock

Data Strobe

Mode 2

107

WR_DS

RD_R/W

75

R/W

Read/Write

R/W = 1 => Read

R/W = 0 => Write

77

78

ALE_AS

CS

AS

CS

Input

Output

I/O

—

Active-Low

Active-High/Low

Active-Low

—

Address Strobe

Chip Select

1

99

INTERRUPT

RDY_DTACK

AD[7:0]

INTERRUPT

Interrupt

2

100

86—79

98—87

101

107

75

DTACK

Data Acknowledge

Address/Data Bus

Microprocessor Clock

Write

AD[7:0]

A[11:8], AD[7:0]

MPCLK

A[11:8], AD[7:0]

Input

Output

I/O

—

MPCLK

WR

—

Mode 3

WR_DS

Active-Low

Active-High/Low

Active-High

—

RD_R/W

ALE_AS

RD

Read

77

ALE

CS

Address Latch Enable

Chip Select

78

CS

1

99

INTERRUPT

RDY_DTACK

AD[7:0]

INTERRUPT

Interrupt

3

100

86—79

98—87

101

107

75

RDY

Ready

AD[7:0]

A[11:0]

MPCLK

WR

Data Bus

A[11:0]

Input

Output

I/O

—

Address Bus

Microprocessor Clock

Write

MPCLK

—

Mode 4

WR_DS

Active-Low

—

RD_R/W

ALE_AS

RD

Read

77

ALE

Address Latch Enable

Chip Select

78

CS

Active-Low

Active-High/Low

Active-High

—

1

99

INTERRUPT

RDY_DTACK

AD[7:0]

INTERRUPT

Interrupt

3

100

86—79

98—87

101

RDY

Ready

AD[7:0]

A[11:8], AD[7:0]

MPCLK

Address/Data Bus

Microprocessor Clock

A[11:8], AD[7:0]

MPCLK

Input

—

1. INTERRUPT output is synchronous to the internal clock source RLCK-LIU. If RLCK_LIU is absent, the reference clock for interrupt timing

becomes an interval 2.048 MHz clock derived from the CHI clock.

2. The DTACK output is asynchronous to MPCLK.

3. MPCLK is needed if RDY output is required to be synchronous to MPCLK.

4. In the default (reset) mode, INTERRUPT is active-high. It can be made active-low by setting register GREG4 bit 6 to 1.

Agere Systems Inc.

141

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Microprocessor Interface (continued)

Microprocessor Clock (MPCLK) Specifications

The microprocessor interface is designed to operate at clock speeds up to 33 MHz without requiring any wait-

states. Wait-states may be needed if higher microprocessor clock speeds are required. The microprocessor clock

(MPCLK, pin 101) specification is shown in Table 67. This clock must be supplied only if the RDY (MODE 3 and

MODE 4) is required to be synchronous to MPCLK.

Table 67. Microprocessor Input Clock Specifications

Name

Symbol

Period

and

Trise

Typ

Tfall

Typ

Duty Cycle

Unit

Tolerance

Min High

12

Min Low

MPCLK

t1

30 to 323

2

12

ns

Microprocessor Interface Register Address Map

The register address space is divided into eight (8) contiguous banks of 512 addressable units each. Each

addressable unit is an 8-bit register. These register banks are labeled as REGBANK[7:0]. The register address

map table gives the address range of these register banks and their associated circuit blocks. REGBANK0 con-

tains the global registers which are common to all the circuit blocks on T7633. REGBANK1 is reserved and must

not be written. REGBANK[2, 5] are attached to the LIU circuit blocks. REGBANK[3, 6] are attached to the framer

circuit blocks. REGBANK[4, 7] are attached to the FDL circuit blocks. The descriptions of the individual register

banks can be found in the appropriate sections of this document. In these descriptions, all addresses are given in

hexadecimal. Addresses out of the range specified by Table 68 must not be addressed. If they are written,

they must be written to 0. An inadvertent write to an out-of-range address may be corrected by a device

reset.

Table 68. T7633 Register Address Map

Start Address End Address

Register Bank Label

Circuit Block Name

(in Hex)

REGBANK0

REGBANK1

REGBANK2

REGBANK3

000

—

007

—

T7633 Global Registers¹

Reserved

400

406

Line Interface Unit 1 (LIU1)

Framer1

600,

6E0

6A6,

6FF

REGBANK4

REGBANK5

REGBANK6

800

A00

80E

A06

Facility Data Link 1 (FDL1)

Line Interface Unit 2 (LIU2)

Framer2

C00,

CE0

CA6,

CFF

REGBANK7

E00

E0E

Facility Data Link 2 (FDL2)

1.Core registers are common to all circuit blocks on T7633.

I/O Timing

The I/O timing specifications for the microprocessor interface are given in Table 69. The microprocessor interface

pins are compatible with CMOS/TTL I/O levels. All outputs, except the address/data bus AD[7:0], are rated for a

capacitive load of 50 pF. The AD[7:0] outputs are rated for a 100 pF load.

142

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Microprocessor Interface (continued)

I/O Timing (continued)

In modes 1 and 3, asserting ALE_AS signal low is used to enable the internal address bus. In modes 2 and 4, the

falling edge of ALE_AS signal is used to latch the address bus.

Table 69. Microprocessor Interface I/O Timing Specifications

Setup

(ns)

Hold

(ns)

Delay

(ns)

Symbol Configuration

Parameter

(Min)

(Max)

t1

t2

t3

t4

t5

Modes 1 & 2 AS Asserted Width

—

10

—

4

10

—

10

—

Address Valid to AS Deasserted

AS Deasserted to Address Invalid

—

R/W Valid to Both CS and DS Asserted

Address Valid and AS Asserted to DS Asserted

(Read)

t6

0

—

t7

CS Asserted to DTACK Low Impedance

DS Asserted to DTACK Asserted

—

5

12

15

25

—

12

10

—

t8

t9

DS Asserted to AD Low Impedance (Read)

DTACK Asserted to Data Valid

t10

t11

t12

t13

t14

t15

DS Deasserted to CS Deasserted (Read)

DS Deasserted to R/W Invalid

5

DS Deasserted to DTACK Deasserted

CS Deasserted to DTACK High Impedance

DS Deasserted to Data Invalid (Read)

—

5

Address Valid and AS asserted to DS Asserted

(Write)

t16

10

—

t17

t18

t19

t20

t21

t22

t23

t24

t25

Data Valid to DS Asserted

10

—

10

—

0

—

5

—

DS Deasserted to CS Deasserted (Write)

DS Deasserted to Data Valid

10

—

10

—

DS Asserted Width (Write)

Address Valid to AS Falling Edge

AS Falling Edge to Address Invalid

AS Falling Edge to DS Asserted (Read)

AS Falling Edge to DS Asserted (Write)

CS Asserted to DS Asserted (Write)

10

Agere Systems Inc.

143

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Microprocessor Interface (continued)

I/O Timing (continued)

Table 69. Microprocessor Interface I/O Timing Specifications (continued)

Setup

(ns)

Hold

(ns)

Delay

(ns)

Symbol Configuration

Parameter

(Min)

(Max)

t31

t32

t33

t34

t35

t36

t37

t38

t39

t40

t41

t42

t43

t44

t45

t46

t47

t48

t49

t50

t51

t52

t53

t54

t55

Modes 3 & 4 ALE Asserted Width

—

10

—

0

10

—

10

—

5

—

12

15

40

—

15

10

—

15

—

Address Valid to ALE Deasserted

ALE Deasserted to Address Invalid

CS Asserted to RD Asserted

Address Valid and ALE Asserted to RD Asserted

CS Asserted to RDY Low Impedance

Rising Edge MPCK to RDY Asserted

RD Asserted to AD Low Impedance

RD Asserted to Data Valid

0

—

0

RD Deasserted to CS Deasserted

RD Deasserted to RDY Deasserted

CS Deasserted to RDY High Impedance

RD Deasserted to Data Invalid (High Impedance)

CS Asserted to WR Asserted

—

5

—

5

Address Valid and ALE Asserted to WR Asserted

Data Valid to WR Asserted

10

—

10

—

0

WR Deasserted to CS Deasserted

WR Deasserted to RDY Deasserted

WR Deasserted to Data Invalid

—

10

40

10

—

10

—

RD Asserted Width

WR Asserted Width

Address Valid to ALE Falling Edge

ALE Falling Edge to Address Invalid

ALE Falling Edge to RD Asserted

ALE Falling Edge to WR Asserted

10

The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 59—66.

144

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Microprocessor Interface (continued)

I/O Timing (continued)

t11

CS

t1

AS

t2

t3

A[0:11]

R/W

VALID ADDRESS

t12

t5

DS

t6

t13

t14

t8

t7

DTACK

AD[0:7]

t10

t9

t15

VALID DATA

5-6422(F)r.1

Figure 59. Mode 1—Read Cycle Timing (MPMODE = 0, MPMUX = 0)

t18

CS

AS

t1

t2

t3

A[0:11]

R/W

VALID ADDRESS

t5

t12

t16

t20

DS

t25

t7

t13

t14

t8

DTACK

AD[0:7]

t17

t19

VALID DATA

5-6423(F)

Figure 60. Mode 1—Write Cycle Timing (MPMODE = 0, MPMUX = 0)

Agere Systems Inc.

145

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Microprocessor Interface (continued)

I/O Timing (continued)

t11

CS

t1

AS

t21

t22

A[8:11]

R/W

VALID ADDRESS

t5

t12

DS

t23

t13

t14

t8

t7

DTACK

AD[0:7]

t21

t22

t10

t9

t15

VALID ADDRESS

VALID DATA

5-6424(F)

Figure 61. Mode 2—Read Cycle Timing (MPMODE = 0, MPMUX = 1)

t18

CS

AS

t1

t21

t22

A[8:11]

R/W

VALID ADDRESS

t5

t12

t25

t20

DS

t24

t13

t14

t8

t7

DTACK

AD[0:7]

t17

t21

t22

t19

VALID ADDRESS

VALID DATA

5-6425(F)

Figure 62. Mode 2—Write Cycle Timing (MPMODE = 0, MPMUX = 1)

146

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Microprocessor Interface (continued)

I/O Timing (continued)

t40

CS

t31

ALE

t32

t33

A[0:11]

RD

VALID ADDRESS

t34

t50

t42

t35

t36

t37

t41

RDY

t39

t43

t38

VALID DATA

AD[0:7]

MPCK

5-6426(F)r.1

Figure 63. Mode 3—Read Cycle Timing (MPMODE = 1, MPMUX = 0)

t47

CS

t31

ALE

t32

t33

A[0:11]

WR

VALID ADDRESS

t44

t51

t42

t45

t36

t48

t49

t37

RDY

t46

VALID DATA

AD[0:7]

MPCK

5-6427(F)

Figure 64. Mode 3—Write Cycle Timing (MPMODE = 1, MPMUX = 0)

Agere Systems Inc.

147

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Microprocessor Interface (continued)

I/O Timing (continued)

t40

CS

t31

ALE

t52

t53

A[8:11]

RD

VALID ADDRESS

t34

t50

t54

t41

t42

t37

t36

RDY

t39

t52

t53

t43

VALID DATA

t38

AD

VALID ADDRESS

MPCK

5-6428(F)r.1

Figure 65. Mode 4—Read Cycle Timing (MPMODE = 1, MPMUX = 1)

t47

CS

t31

ALE

t52

t53

A[8:11]

WR

VALID ADDRESS

t44

t51

t55

t48

t42

t37

t36

RDY

t52

t53

t46

t49

VALID DATA

VALID ADDRESS

AD

MPCK

5-6429(F)r.1

Figure 66. Mode 4—Write Cycle Timing (MPMODE = 1, MPMUX = 1)

148

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Reset

Both hardware and software resets are provided.

Hardware Reset (Pin 43/139)

Hardware reset is enabled by asserting RESET to 0. Each channel has independent resets, RESET1 (pin 139) for

channel 1 and RESET2 (pin 43) for channel 2. The device is in an inactive condition when RESET is 0, and

becomes active when RESET is returned to 1. Upon completion of a reset cycle, the LIU register default values are

controlled by the setting of DS1/CEPT (pin 40/142), as given in Table 6, Transmit Line Interface Short-Haul Equal-

izer/Rate Control on page 34. If DS1/CEPT is 1, the defaults are set for DS1 with line equalization for a 1 ft. to

131 ft. span. If DS1/CEPT is 0, the defaults are set for CEPT with a line equalization for 120 Ω twisted pair or

75 Ω coax option 1.

Hardware reset of a single channel returns all LIU, framer, and FDL registers of that channel to their default values,

as listed in the individual register descriptions and register maps, Table 200—Table 206. Reset of a single channel

does not reset the global registers. Hardware reset of both channels simultaneously, both pin 43 and pin 139 set to

0, results in a complete device reset including a reset of the global registers.

Software Reset/Software Restart

Independent software reset for each functional block of the device is available. The LIU may be placed in restart

through register LIU_REG2 bit 5 (RESTART). The framer may be reset through register FRM_PR26 bit 0 (SWRE-

SET), or placed in restart through FRM_PR26 bit 1 (SWRESTART). The FDL receiver may be reset through regis-

ter FDL_PR26 bit 1 (FRR), and the FDL transmitter may be reset through FDL_PR1 bit 5 (FTR). The reset

functions, framer SWRESET (framer software reset), FDL FRR (FDL receiver reset), and FTR (FDL transmitter

reset), reset the block and return all parameter/control registers for the block to their default values. The restart

functions, LIU RESTART and framer SWRESTART (framer software restart), reset the block but do not alter the

value of the parameter/control registers.

Interrupt Generation

An interrupt may be generated by any of the conditions reported in the status registers. For a bit (condition) in a

status register to create an interrupt, the corresponding interrupt enable bit must be set and the interrupt block

enable in the global register for the source block must be set, see Table 70 below. Once the source interrupt regis-

ter is read, the interrupt for that condition is deasserted.

Table 70. Status Register and Corresponding Interrupt Enable Register for Functional Blocks

Functional Block

Primary Block

Status Register

GREG0

Interrupt Enable Register

GREG1

Line Interface

Framer

Facility Data Link

LIU_REG0

LIU_REG1

FRM_SR0—FRM_SR7

FDL_SR0

FRM_PR0—FRM_PR7

FDL_PR2

Default for interrupt assertion is a logical 1 (high) value. But the assertion value and deasserted state is program-

mable through register GREG4 bit 4 and bit 6 and may take on the following state, see Table 71 below.

Table 71. Asserted Value and Deasserted State for GREG4 Bit 4 and Bit 6 Logic Combinations

Greg4

INTERRUPT (Pin 99)

Functionality

Bit 4

Bit 6

Asserted Value

Deasserted Value

0

1

0

1

0

1

High

Low

3-state

High

—

Wired OR

—

Wired AND

3-state

Agere Systems Inc.

149

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Architecture

Table 72 is an overview of the register architecture. The table is a summary of the register function and address.

Complete detail of each register is given in the following sections.

Table 72. Register Summary

Register

Function

Register Address (hex)

Channel 1

Channel 2

Global Registers

GREG0

GREG1

GREG2

GREG3

GREG4

GREG5

GREG6

GREG7

Primary Block Interrupt Status

000

001

002

003

004

005

006

007

Primary Block Interrupt Enable

Global Loopback Control

Global Control

Device ID and Version

LIU Registers

LIU_REG0

LIU_REG1

LIU_REG2

LIU_REG3

LIU_REG4

LIU_REG5

LIU_REG6

LIU Alarm Status

LIU Alarm Interrupt Enable

LIU Control

400

401

402

403

404

405

406

A00

A01

A02

A03

A04

A05

A06

LIU Control

LIU Configuration

Framer Registers

Status Registers

FRM_SR0

FRM_SR1

FRM_SR2

FRM_SR3

FRM_SR4

FRM_SR5

Interrupt Status

600

601

602

603

604

605

C00

C01

C02

C03

C04

C05

Facility Alarm Condition

Remote End Alarm

Facility Errored Event

Facility Event

Exchange Termination and Exchange Termination Remote End

Interface Status

FRM_SR6

FRM_SR7

Network Termination and Network Termination Remote End

Interface Status

606

C06

Facility Event

607

C07

FRM_SR8,

FRM_SR9

Bipolar Violation Counter

608, 609

C08, C09

FRM_SR10, Framing Bit Error Counter

FRM_SR11

60A, 60B

60C, 60D

60E, 60F

C0A, C0B

C0C, C0D

C0E, C0F

FRM_SR12, CRC Error Counter

FRM_SR13

FRM_SR14, E-bit Counter

FRM_SR15

150

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Architecture (continued)

Table 72. Register Summary (continued)

Register

Function

Register Address (hex)

Channel 1

Channel 2

FRM_SR16, CRC-4 Error at NT1 from NT2 Counter

FRM_SR17

610, 611

C10, C11

FRM_SR18, E-bit at NT1 from NT2 Counter

FRM_SR19

612, 613

614, 615

616, 617

618, 619

61A, 61B

61C, 61D

61E, 61F

620, 621

622, 623

624, 625

626, 627

628, 629

62A, 62B

62C, 62D

62E, 62F

630, 631

632, 633

C12, C13

C14, C15

C16, C17

C18, C19

C1A, C1B

C1C, C1D

C1E, C1F

C20, C21

C22, C23

C24, C25

C26, C27

C28, C29

C2A, C2B

C2C, C2D

C2E, C2F

C30, C31

C32, C33

FRM_SR20, ET Errored Seconds Counter

FRM_SR21

FRM_SR22, ET Bursty Errored Seconds Counter

FRM_SR23

FRM_SR24, ET Severely Errored Seconds Counter

FRM_SR25

FRM_SR26, ET Unavailable Seconds Counter

FRM_SR27

FRM_SR28, ET-RE Errored Seconds Counter

FRM_SR29

FRM_SR30, ET-RE Bursty Errored Seconds Counter

FRM_SR31

FRM_SR32, ET-RE Severely Errored Seconds Counter

FRM_SR33

FRM_SR34, ET-RE Unavailable Seconds Counter

FRM_SR35

FRM_SR36, NT1 Errored Seconds Counter

FRM_SR37

FRM_SR38, NT1 Bursty Errored Seconds Counter

FRM_SR39

FRM_SR40, NT1 Severely Errored Seconds Counter

FRM_SR41

FRM_SR42, NT1 Unavailable Seconds Counter

FRM_SR43

FRM_SR44, NT1-RE Errored Seconds Counter

FRM_SR45

FRM_SR46, NT1-RE Bursty Errored Seconds Counter

FRM_SR47

FRM_SR48, NT1-RE Severely Errored Seconds Counter

FRM_SR49

FRM_SR50, NT1-RE Unavailable Seconds Counter

FRM_SR51

FRM_SR52 Receive NOT-FAS TS0

FRM_SR53 Received Sa

634

635

C34

C35

FRM_SR54— SLC-96 FDL/CEPT Sa Receive Stack

636—63F

C36—C3F

FRM_SR63

Agere Systems Inc.

151

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Architecture (continued)

Table 72. Register Summary (continued)

Register

Function

Register Address (hex)

Channel 1

Channel 2

Received Signaling Registers

FRM_RSR0— Received Signaling

FRM_RSR31

640—65F

C40—C5F

Parameter/Control Registers

FRM_PR0— Interrupt Group Enable

FRM_PR7

660—667

C60—C67

FRM_PR8

FRM_PR9

Framer Mode Option

Framer CRC Control Option

668

669

C68

C69

FRM_PR10 Alarm Filter

66A

C6A

FRM_PR11 Errored Second Threshold

66B

C6B

FRM_PR12, Severely Errored Second Threshold

FRM_PR13

66C. 66D

C6C, C6D

FRM_PR14 Errored Event Enable

66E

66F

C6E

C6F

FRM_PR15 ET Remote End Errored Event Enable

FRM_PR16 NT1 Errored Event Enable

670

C70

FRM_PR17, NT1 Remote End Errored Event Enable

FRM_PR18

671, 672

C71, C72

FRM_PR19 Automatic AIS to the System and Automatic Loopback Enable

FRM_PR20 Transmit to the Line Command

673

674

675

676

677

678

679

67A

67B

C73

C74

C75

C76

C77

C78

C79

C7A

C7B

FRM_PR21 Framer FDL Loopback Transmission Codes Command

FRM_PR22 Framer Transmit Line Idle Code

FRM_PR23 Framer Transmit System Idle Code

FRM_PR24 Primary Loopback Control

FRM_PR25 Secondary Loopback Control

FRM_PR26 System Frame Sync Mask Source

FRM_PR27 Transmission of Remote Frame Alarm and CEPT Automatic

Transmission of A bit = 1 Control

FRM_PR28 CEPT Automatic Transmission of E bit = 0

FRM_PR29 Sa4—Sa8 Source

67C

67D

C7C

C7D

FRM_PR30 Sa4—Sa8 Control

67E

C7E

FRM_PR31— Sa Transmit Stack/SLC-96 Transmit Stack

67F—688

C7F—C88

FRM_PR40

FRM_PR41 Si-bit Source

689

68A

68B

68C

68D

68E

68F

690

C89

C8A

C8B

C8C

C8D

C8E

C8F

C90

FRM_PR42 Frame Exercise

FRM_PR43 System Interface Control

FRM_PR44 Signaling Mode

FRM_PR45 CHI Common Control

FRM_PR46 CHI Common Control

FRM_PR47 CHI Transmit Control

FRM_PR48 CHI Receive Control

152

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Architecture (continued)

Table 72. Register Summary (continued)

Register

Function

Register Address (hex)

Channel 1

Channel 2

FRM_PR49— Transmit CHI Time-Slot Enable

FRM_PR52

691—694

C91—C94

FRM_PR53— Receive CHI Time-Slot Enable

FRM_PR56

695—698

699—69C

69D—6A0

C95—C98

C99—C9C

C9D—CA0

FRM_PR57— CHI Transmit Highway Select

FRM_PR60

FRM_PR61— CHI Receive Highway Select

FRM_PR64

FRM_PR65 CHI Transmit Control

6A1

6A2

6A5

6A6

CA1

CA2

CA5

CA6

FRM_PR66 CHI Receive Control

FRM_PR69 Auxiliary Pattern Generator Control

FRM_PR70 Auxiliary Pattern Detector Control

Transmit Signaling Registers

FRM_TSR0— Transmit Signaling

FRM_TSR31

6E0—6F7

CE0—CF7

Facility Data Link Registers

FDL Parameter/Control Registers

FDL_PR0

FDL_PR1

FDL_PR2

FDL_PR3

FDL_PR4

FDL_PR5

FDL_PR6

FDL_PR7

FDL_PR8

FDL_PR9

FDL_PR10

FDL Configuration Control

FDL Control

800

801

802

803

804

805

806

—

E00

E01

E02

E03

E04

E05

E06

—

FDL Interrupt Mask Control

FDL Transmitter Configuration Control

FDL Transmitter FIFO

FDL Transmitter Mask

FDL Receive Interrupt Level Control

Not Assigned

FDL Receive Match Character

FDL Transparent Control

808

809

80A

E08

E09

E0A

FDL Transmit ANSI ESF Bit Codes

FDL Status Registers

FDL_SR0

FDL_SR1

FDL_SR2

FDL_SR3

FDL_SR4

FDL Interrupt Status

80B

80C

80D

80E

807

E0B

E0C

E0D

E0E

E07

FDL Transmitter Status

FDL Receiver Status

FDL ANSI Bit Codes Status

FDL Receive FIFO

Agere Systems Inc.

153

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Global Register Architecture

REGBANK0 contains the status and programmable control registers for all global functions. The address of these

registers is 000 (hex) to 008 (hex). These registers control both channels of the terminator.

The register bank architecture is shown in Table 73. The register bank consists of 8-bit registers classified as pri-

mary block interrupt status register, primary block interrupt enable register, global loopback control register, global

terminal control register, device identification register, and global internal interface control register.

GREG0 is a clear on read (COR) register. This register is cleared by the framer internal received line clock

(LIU_RLCK of Figure 18, Block Diagram of Framer Line Interface on page 50). At least two RFRMCK cycles

(1.3 µs for DS1 and 1.0 µs for CEPT) must be allowed between successive reads of the same COR register to

allow it to properly clear.

The default values are shown in parentheses.

Table 73. Global Register Set (0x000—0x008)

Global Register

[Address (hex)]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FDL2INT

(0)

FRMR2INT

(0)

LIU2INT

(0)

Reserved

(0)

FDL1INT

(0)

FRMR1INT

(0)

LIU1INT

(0)

GREG0[000]

Reserved

(0)

Reserved

(0)

FDL2IE

(0)

FRMR2IE

(0)

LIU2IE

(0)

Reserved

(0)

FDL1IE

(0)

FRMR1IE

(0)

LIU1IE

(0)

GREG1[001]

GREG2[002]

GREG3[003]

GREG4[004]

TID2-RSD1 TSD2-RSD1 TID1-RSD1 TSD1-RSD1 TSD2-RID1

(0) (0) (0) (0) (0)

TID1-RSD2 TSD1-RSD2 TID2-RSD2 TSD2-RSD2 TSD1-RID2

TID2-RID1

(0)

TSD1-RID1

(0)

TID1-RID1

(0)

TID1-RID2

(0)

TSD2-RID2

(0)

TID2-RID2

(0)

Reserved

(0)

ALIE

(0)

SECCTRL

(0)

ITC

(0)

T1-R2

(0)

T2-R1

(0)

Reserved

(0)

Reserved

(0)

GREG5[005]

GREG6[006]

GREG7[007]

0

1

0

1

0

1

0

1

0

1

0

1

The following section describes the global registers in Table 74—Table 79.

154

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Global Register Structure

Primary Block Interrupt Status Register (GREG0)

A bit set to 1 indicates the block has recently generated an interrupt. This register is cleared on read.

Table 74. Primary Block Interrupt Status Register (GREG0) (000)

Bit

0

Symbol

Description

LIU1INT

Line Interface Unit 1 Interrupt. A 1 indicates LIU1 generated an interrupt.

1

FRMR1INT Framer 1 Interrupt. A 1 indicates framer 1 generated an interrupt.

2

FDL1INT

—

Facility Data Link 1 Interrupt. A 1 indicates FDL1 generated an interrupt.

Reserved.

3

4

LIU2INT

Line Interface Unit 2 Interrupt. A 1 indicates LIU2 generated an interrupt.

5

FRMR2INT Framer 2 Interrupt. A 1 indicates framer 2 generated an interrupt.

6

FDL2INT

—

Facility Data Link 2 Interrupt. A 1 indicates FDL2 generated an interrupt.

7

Reserved.

Primary Block Interrupt Enable Register (GREG1)

This register enables the individual blocks to assert the interrupt pin.

Table 75. Primary Block Interrupt Enable Register (GREG1) (001)

Bit

0

Symbol

LIU1IE

FRMR1IE

FDL1IE

—

Description

Line Interface 1 Interrupt Enable. A 1 enables LIU1 interrupts.

Framer 1 Interrupt Enable. A 1 enables framer 1 interrupts.

Facility Data Link 1 Interrupt Enable. A 1 enables FDL1 interrupts.

Reserved. Write to 0.

1

2

3

4

LIU2IE

FRMR2IE

FDL2IE

—

Line Interface 2 Interrupt Enable. A 1 enables LIU2 interrupts.

Framer 2 Interrupt Enable. A 1 enables framer 2 interrupts.

Facility Data Link 2 Interrupt Enable. A 1 enables FDL2 interrupts.

Reserved. Write to 0.

5

6

7

Agere Systems Inc.

155

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Global Register Structure (continued)

Global Loopback Control Register (GREG2)

This register enables the framer inputs RCHIDATA1 and RCHIDATAB1 to be driven by various internal sources. A

1 enables the specified loopback. The default of the register 00 (hex) disables all loopbacks and enables external

sources to drive these inputs.

Table 76. Global Loopback Control Register (GREG2) (002)

Bit

0

Symbol

Description

TID1—RID1 TCHIDATA1 to RCHIDATA1 Connection.

TSD1—RID1 TCHIDATAB1 to RCHIDATA1 Connection.

TID2—RID1 TCHIDATA2 to RCHIDATA1 Connection.

TSD2—RID1 TCHIDATAB2 to RCHIDATA1 Connection.

TSD1—RSD1 TCHIDATAB1 to RCHIDATAB1 Connection.

TID1—RSD1 TCHIDATA1 to RCHIDATAB1 Connection.

TSD2—RSD1 TCHIDATAB2 to RCHIDATAB1 Connection.

TID2—RSD1 TCHIDATA2 to RCHIDATAB1 Connection.

1

2

3

4

5

6

7

Global Loopback Control Register (GREG3)

This register enables the framer inputs RCHIDATA2and RCHIDATAB2 to be driven by various internal sources. A 1

enables the specified loopback. The default of the register 00 (hex) disables all loopbacks and enables external

sources to drive these inputs.

Table 77. Global Loopback Control Register (GREG3) (003)

Bit

0

Symbol

Description

TID2—RID2 TCHIDATA2 to RCHIDATA2 Connection.

TSD2—RID2 TCHIDATAB2 to RCHIDATA2 Connection.

TID1—RID2 TCHIDATA1 to RCHIDATA2 Connection.

TSD1—RID2 TCHIDATAB1 to RCHIDATA2 Connection.

TSD2—RSD2 TCHIDATAB2 to RCHIDATAB2 Connection.

TID2—RSD2 TCHIDATA2 to RCHIDATAB2 Connection.

TSD1—RSD2 TCHIDATAB1 to RCHIDATAB2 Connection.

TID1—RSD2 TCHIDATA1 to RCHIDATAB2 Connection.

1

2

3

4

5

6

7

156

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Global Register Structure (continued)

Global Control Register (GREG4)

This register enables LIU1 to LIU2 loopbacks (bit 2 and bit 3), interrupt 3-state control (bit 4), source of the output

second pulse (bit 5), and interrupt polarity (bit 6).

Table 78. Global Control Register (GREG4) (004)

Bit

0

Symbol

—

Description

Reserved. Write to zero.

1

—

2

T2-R1

TLCK2, TPD2, and TND2 to RLCK1, RPD1, and RND1 Connection. A 1 makes the indi-

cated loopback.

3

4

T1-R2

ITC

TLCK1, TPD1, and TND1 to RLCK2, RPD2, and RND2 Connection. A 1 makes the indi-

cated loopback.

INTERRUPT 3-State Control. This bit along with bit 6 in this register (ALIE) allows the

interrupt pin to be programmed for active-high, active-low, wire OR, or wire AND opera-

tion, as described below:

Bits

4 6

Description

0 0 Programs the interrupt pin to be active-high (1 state) when there is an interrupt

condition and to be inactive (0 state) when there is no interrupt condition.

0 1 Programs the interrupt pin to be active-low (0 state) when there is an interrupt

condition and to be inactive (1 state) when there is no interrupt condition.

1 0 Programs the interrupt pin to be active-high (1 state) when there is an interrupt

condition and to be in the high-impedance state (3-state) when there is no inter-

rupt condition. This allows the interrupt to be wire OR’d with other interrupt pins

on the system board. A pull-down resister is needed on the system board.

1 1 Programs the interrupt pin to be active-low (0 state) when there is an interrupt

condition and to be in the high-impedance state (3-state) when there is no inter-

rupt condition. This allows the interrupt to be wire AND’d with other interrupt

pins on the system board. A pull-up resister is needed on the system board.

5

SECCTRL SECOND Pulse Source Control. A 0 enables framer 1 to source the output second pulse

(SECOND). A 1 enables framer 2 to source the output second pulse.

6

7

ALIE

—

Active-Low Interrupt Enable. A 1 enables active-low interrupt.

Reserved. Write to zero.

Device ID and Version Registers (GREG5—GREG7)

These bits define the device and version number.

Table 79. Device ID and Version Registers (GREG5—GREG7) (005—007)

Register

GREG5

GREG6

GREG7

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Device Code

Version #

0

1

0

1

0

1

0

1

0

1

0

1

Agere Systems Inc.

157

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Unit (LIU) Register Architecture

REGBANK2 and REGBANK5 contain the status and programmable registers for the line interface unit channels

LIU1 and LIU2 respectively. The base address for REGBANK2 is 400(hex) and for REGBANK5 is A00(hex). Within

these register banks the bit map is identical for both LIU1 and LIU2.

The register bank architecture for LIU1 and LIU2 is shown in Table 80. The register bank consists of 8-bit registers

classified as alarm status register, alarm mask register, status register, status interrupt mask register, control regis-

ters, and configuration registers.

Register LIU_REG0 is the alarm status register used for storing the various LIU alarms and status. It is a read-only,

clear-on-read (COR) register. This register is cleared on the rising edge of MPCLK, if present, or on the rising edge

of the internally generated 2.048 MHz clock derived from the CHI clock if MPCLK is not present. Register

LIU_REG1 contains the individual interrupt enable bits for the alarms in LIU_REG0.

Register LIU_REG2, LIU_REG3, and LIU_REG4 are designated as control registers while LIU_REG5 and

LIU_REG6 are configuration registers. These are used to set up the individual LIU channel functions and parame-

ters.

The default values are shown in parentheses.

The following sections describe the LIU registers in more detail.

Table 80. Line Interface Units Register Set¹((400—40F); (A00—A0F))

LIU

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register

[Address

(HEX)]

Alarm Register (Read Only) (Latches Alarm, Clear On Read)

LOTC

Alarm Interrupt Enable Register (Read/Write)

LIU_REG0 400; A00

LIU_REG1 401; A01

0

TDM

DLOS

ALOS

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

LOTCIE

(0)

TDMIE

(0)

DLOSIE ALOSIE

(0) (0)

Control Registers (Read/Write)

Reserved

(0)

Reserved

(0)

RESTART

(0)

HIGHZ

(0)

Reserved

(0)

LOSST Reserved Reserved

LIU_REG2 402; A02

LIU_REG3 403; A03

LIU_REG4 404; A04

(0)

2

Reserved

(1)

Reserved

(1)

Reserved

LOSSD

(0)

DUAL

(0)

CODE

(1)

JAT

(0)

JAR

(0)

(1)

Reserved

0

Reserved

(0)

JABW0

(0)

PHIZALM

(0)

PRLALM

(0)

PFLALM RCVAIS ALTIMER

(0)

Configuration Registers (Read/Write)

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

LOOPA

(0)

LOOPB

(0)

XLAIS

(1)

PWRDN

(0)

LIU_REG5 405; A05

LIU_REG6 406; A06

EQ2

(0,DS1)

(1,CEPT) (1,CEPT)

EQ1

(0,DS1)

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

0

EQ0

(0)

1. The logic value in parentheses below each bit definition is the default state upon completion of hardware reset.

2. These bits must be written to 1.

158

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Alarm Register

Alarm Status Register (LIU_REG0)

Bits 0—3 of this register represent the status of the line interface receiver and transmitter alarms ALOS, DLOS,

TDM, and LOTC. The alarm indicators are active-high and automatically clear on a microprocessor read if the cor-

responding alarm conditions no longer exist. However, persistent alarm conditions will cause these bits to remain

set even after a microprocessor read. This is a read-only register.

Table 81. LIU Alarm Status Register (LIU_REG0) (400, A00)

Bit

Description

Symbol

Receive Analog Loss of Signal. A 1 indicates the LIU receive channel has detected

an analog loss of signal condition/event.

0

ALOS

Receive Digital Loss of Signal. A 1 indicates the LIU receive channel has detected a

digital loss of signal condition/event.

1

2

DLOS

TDM

Transmit Driver Monitor Alarm. A 1 indicates the LIU transmit channel has detected

a transmit driver monitor alarm condition/event.

Transmit Loss of Transmit Clock Alarm. A 1 indicates the LIU transmit channel has

detected a loss of transmit clock condition/event.

3

LOTC

—

4—7

Reserved.

Line Interface Alarm Interrupt Enable Register

Alarm Interrupt Enable Register (LIU_REG1)

The bits in the alarm interrupt enable register allow the user to selectively enable generation of an interrupt by

each channel alarm. The enable bits correspond to their associated alarm status bits in the alarm status register,

LIU-REG0. The interrupt enable function is active-high. When an enable bit is set, the corresponding alarm is

enabled to generate an interrupt. Otherwise, the alarm is disabled from generating an interrupt.

The enable function only impacts the ability to generate an interrupt signal. The proper alarm status will be

reflected in LIU_REG0 even when the corresponding enable bit is set to zero. Any other LIU behavior associated

with an alarm event will operate normally even if the interrupt is not enabled.

This is a read/write register.

Table 82. LIU Alarm Interrupt Enable Register (LIU_REG1) (401, A01)

Bit

Symbol

Description

Enable Analog Loss of Signal Interrupt. A 1 enables an interrupt in response to

ALOS alarm.

0

ALOSIE

Enable Digital Loss of Signal Interrupt. A 1 enables an interrupt in response to

DLOS alarm.

1

2

DLOSIE

TDMIE

Enable Transmit Driver Monitor Interrupt. A 1 enables an interrupt in response to

TDM alarm.

Enable loss of Transmit Clock Interrupt. A 1 enables an interrupt in response to

LOTC alarm.

3

LOTCIE

—

4—7

Reserved. Write to 0.

Agere Systems Inc.

159

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Control Registers

The bits in the control registers allow the user to configure the various device functions for the individual line inter-

face channels 1 and 2. All the control bits (with the exception of LOSSTD) are active-high.

LIU Control Register (LIU_REG2)

Table 83. LIU Control Register (LIU_REG2) (402, A02)

Bit

Symbol

Description

0

1

2

—

Reserved. Write to 0.

LOSSTD

The LOSSTD bit selects the conformance protocol for the DLOS receiver alarm

function. LOSSTD = 0 selects standards T1M1.3/93-005, ITU-T G.755 for DS1

mode and ITU-T G.755 for CEPT mode. LOSSTD = 1 selects standards TR-TSY-

000009 for DS1 and ITU-T G.775 for CEPT.

3

4

—

Reserved. Write to 0.

HIGHZ

The HIGHZ bit places the LIU in a high-impedance state. When HIGHZ = 1, the

TTIP and TRING transmit drivers for the specified channel are placed in a high-

impedance state.

5

RESTART

—

The RESTART bit is used for device initialization through the microprocessor inter-

face. RESTART = 1 resets the data path circuits. Data path circuits will be reset, but

the microprocessor registers state will not be altered by a restart action.

6—7

Reserved. Write to 0.

160

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Control Registers (continued)

LIU Control Register (LIU_REG3)

The default value of this register is E4 (hex).

Table 84. LIU Control Register (LIU_REG3) (403, A03)

Bit

Symbol

Description

0

JAR

The JAR bit is used to enable and disable the jitter attenuator function in the receive

path. The JAR and JAT control bits are mutually exclusive, i.e., either JAR or the JAT

control bit can be set, but not both. JAR = 1 places jitter attenuator in the receive path.

1

2

JAT

The JAT bit is used to enable and disable the jitter attenuator function in the transmit

path. The JAT and JAR control bits are mutually exclusive, i.e., either JAT or the JAR

control bit can be set, but not both. JAT = 1 places jitter attenuator in the transmit path.

CODE

The CODE bit is used to enable and disable the B8ZS/HDB3 zero substitution coding

in the transmit and decoding in the receive path. CODE is used in conjunction with the

DUAL bit and is valid only for single-rail operation. CODE = 1 activates the coding/

decoding functions. The default value is CODE = 1.

3

4

DUAL

The DUAL bit is used to select single- or dual-rail mode of operation. DUAL = 1 selects

the dual-rail mode.

LOSSD

The LOSSD bit selects the shut down function for the receiver during digital loss of sig-

nal alarm (DLOS). LOSSD operates in conjunction with the RCVAIS bit (see Table 3,

LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes), from

page 29 repeated below for reference.

1. These registers must be written to 1 for the LIU-to-framer interface to be functional.

LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) (from Table 3, page 29)

LOSSD

RCVAIS

ALARM

ALOS

DLOS

ALOS

DLOS

ALOS

DLOS

ALOS

DLOS

RPD/RND

RLCK

Free Runs

Recovered Clock

Free Runs

0

1

0

1

0

1

0

Normal Data

0

AIS (all ones)

0

Agere Systems Inc.

161

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Control Registers (continued)

LIU Control Register (LIU_REG4)

Table 85. LIU Register (LIU_REG4) (404, A04)

Bit

Symbol

Description

0

ALTIMER

The ALTIMER bit is used to select the time required to declare ALOS. ALTIMER =

0 selects 1 ms—2.6 ms. ALTIMER = 1 selects 10 bit to 255 bit periods.

1

RCVAIS

The RCVAIS bit selects the shut down function for the receiver during analog loss

of signal alarm (ALOS). RCVAIS operates in conjunction with the LOSSD bit. See

LIU-REG3.

2

3

4

PFLALM

PRLALM

PHIZALM

PFLALM prevents the DLOS alarm from occurring during FLLOOP activation.

PFLALM = 1 activates the PFLALM function.

PRLALM prevents the LOTC alarm from occurring during RLOOP activation/deac-

tivation. PRLALM = 1 activates the PRLALM function.

PHIZALM prevents the TDM alarm from occurring when the driver are in a high-

impedance state. PHIZALM = 1 activates the PHIZALM function.

5

JABW0

—

JABW0 = 1 selects the lower bandwidth jitter attenuator option in CEPT mode.

6—7

Reserved. Write to 0.

LIU Configuration Register (LIU_REG5)

The control bits in the channel configuration register 5 are used to select powerdown mode, AIS generation, and

loopbacks for the LIU. The PWRDN and XLAIS bits are active-high. This is a read/write register. The default value

of this register is 02 (hex).

Table 86. LIU Configuration Register (LIU_REG5) (405, A05)

Bit

Symbol

Description

0

1

PWRDN

XLAIS

PWRDN = 1 activates powerdown.

XLAIS = 1 enables transmission of an all 1s signal to the line interface. XLAIS = 1

after a reset allowing immediate generation of alarm signal as long as a clock

source is present. The default value is XLAIS = 1.

2

3

LOOPB

LOOPA

—

The LOOPA bit is used in conjunction with LOOPB to select the channel loopback

modes. See Table 10, Loopback Control, from page 44 repeated below for refer-

ence.

4—7

Reserved. Write to 0.

Loopback Control (from Table 10, page 44)

Operation

Normal¹

Symbol

LOOPA

LOOPB

—

0

1

0

1

0

1

Full Local Loopback

Remote Loopback

FLLOOP²

RLOOP³

DLLOOP

Digital Local Loopback

1. The reset default condition is LOOPA = LOOPB = 0 (no loopback).

2. During the transmit AIS condition, the looped data will be the transmitted data from the framer or system interface and not the all 1s signal.

3. Transmit AIS request is ignored.

162

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Line Interface Control Registers (continued)

LIU Configuration Register (LIU_REG6)

The control bits in the channel configuration register 6 are used to select LIU transmit equalization settings. This is

a read/write register. The default value of this register is 00 (hex) in DS1 when DS1/CEPT (pin 40/142) is set to 1,

and 06 (hex) in CEPT when DS1/CEPT (pin 40/142) is set to 0.

Table 87. LIU Configuration Register (LIU_REG6) (406, A06)

Bit

Symbol

Description

0

1

2

EQ0

EQ1

The EQ0, EQ1, and EQ2 bits select the type of service (DS1 or CEPT) and the

associated transmitter cable equalization/line build out/termination impedances.

See Table 6, Transmit Line Interface Short-Haul Equalizer/Rate Control, from

page 34 repeated below for reference.

EQ2

3—7

—

Reserved. Write to 0.

Transmit Line Interface Short-Haul Equalizer/Rate Control (from Table 6, page 34)

Short-Haul Applications

EQ2

EQ1

EQ0 Service

Clock Rate

Transmitter Equalization^1,2

Maximum

Cable Loss

to DSX³

Feet

Meters

dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DSX-1

CEPT⁴

1.544 MHz

0 to 131

0 to 40

40 to 80

0.6

1.2

1.8

2.4

3.0

—

131 to 262

262 to 393

393 to 524

524 to 655

80 to 120

120 to 160

160 to 200

2.048 MHz

75 Ω (Option 2)

120 Ω or 75 Ω (Option 1)

Not Used

1.In DS1 mode, the distance to the DSX for 22-Gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable

types. In CEPT mode, equalization is specified for coaxial or twisted-pair cable.

2.Reset default state is EQ2, EQ1, and EQ0 = 000 when pin DS1_CEPT = 1 and EQ2, EQ1, and EQ0 = 110 when pin DS1_CEPT = 0.

3.Loss measured at 772 kHz.

4.In 75 Ω applications, Option 1 is recommended over Option 2 for lower LIU power dissipation. Option 2 allows for the use of the same trans-

former as in CEPT 120 Ω applications (see Line Interface Unit: Line Circuitry section).

Agere Systems Inc.

163

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture

REGBANK3 and REGBANK6 contain the status and programmable control registers for the framer and system

(CHI) interface channels FRM1 and FRM2. The base address for REGBANK3 is 600 (hex) and for REGBANK6 is

C00 (hex). Within these register banks, the bit map is identical for both FRM1 and FRM2.

The framer registers are structures as shown in Table 88. Default values are given in the individual register defini-

tion tables.

Table 88. Framer Status and Control Blocks Address Range (Hexadecimal)

Framer Register Block

Status Registers (COR) ((600—63F); (C00—C3F))

Receive Signaling Registers ((640—65F); (C40—C5F))

Parameter (Configuration) Registers ((660—6A6); (C60—CA6))

Transmit Signaling Registers ((6E0—6FF); (CE0—CFF))

The complete register map for the framer is given in Table 202—Table 204 on page 220—page 223.

All status registers are clocked with the internal framer receive line clock (RFRMCK).

Bits in status registers FRM_SR1 and FRM_SR7 are set at the onset of the condition and are cleared on read

when the given condition is no longer present. These registers can generate interrupts if the corresponding register

bits are enabled in interrupt enable registers FRM_PR0—FRM_PR7.

On all 16-bit counter registers (FRM_SR8—FRM_SR51), both bytes are cleared only after reading both bytes,

regardless of the order in which they are read. Once a read is initiated on one of the bytes, the updating of that

counter is disabled and remains disabled until both bytes are read. All events during this interval are lost. Updating

of the counter registers is stopped when all of the bits are set to 1. Updating resumes after the registers are cleared

on read. These register pairs may be read in any order, but they must be read in pairs, i.e., a read of 1 byte must be

followed immediately by a read of the remaining byte of the pair.

Status registers FRM_SR0—FRM_SR63 are clear-on-read (COR) registers. These registers are cleared by the

framer internal received line clock (RFRMCK). At least two RFRMCK cycles (1.3 µs for DS1 and 1.0 µs for CEPT)

must be allowed between successive reads of the same COR register to allow it to properly clear.

164

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers

Registers FRM_SR0—FRM_SR63 report the status of each framer. All are clear-on-read, read only registers.

Interrupt Status Register (FRM_SR0)

The interrupt pin (INTERRUPT) goes active when a bit in this register and its associated interrupt enable bit in reg-

isters FRM_PR0—FRM_PR7 are set, and the interrupt for the framer block is enabled in register GREG1.

Table 89. Interrupt Status Register (FRM_SR0) (600; C00)

Bit

0

Symbol

FAC

Description

Facility Alarm Condition. A 1 indicates a facility alarm occurred (go read FRM_SR1).

Remote Alarm Condition. A 1 indicates a remote alarm occurred (go read FRM_SR2).

1

RAC

2

FAE

Facility Alarm Event. A 1 indicates a facility alarm occurred (go read FRM_SR3 and

FRM_SR4).

3

4

ESE

Errored Second Event. A 1 indicates an errored second event occurred (go read

FRM_SR5, FRM_SR6, and FRM_SR7).

TSSFE

Transmit Signaling Superframe Event. A 1 indicates that a MOS (or CCS for CEPT)

superframe block has been transmitted and the transmit signaling data buffers are ready

for new data.

5

RSSFE

Receive Signaling Superframe Event. A 1 indicates that a MOS (or CCS for CEPT)

superframe block has been received and the receive signaling data buffers must be read.

6

7

—

Reserved.

S96SR

SLC-96 Stack Ready. A 1 indicates that either the transmit framer SLC-96 stack is ready

for more data or the receive framer SLC-96 stack contains new data.

Agere Systems Inc.

165

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

Facility Alarm Condition Register (FRM_SR1)

The bits in the facility alarm condition register (FRM_SR1) indicate alarm state of the receive framer section. Inter-

rupts from this register are generated once at the onset of the alarm condition. If the alarm condition is still present

at the time of the read, the bit will remain in the 1 state for the duration of the alarm condition. If the alarm condition

is no longer present at the time of the read, then the bit is cleared on read.

Table 90. Facility Alarm Condition Register (FRM_SR1) (601; C01)

Bit

Symbol

Description

0

LFA

Loss of Frame Alignment. A 1 indicates the receive framer is in a loss of frame

alignment and is currently searching for a new alignment.

1

2

LSFA,

Loss of Signaling Superframe Alignment. A 1 indicates the receive framer is in a loss

of signaling superframe alignment in the DS1 framing formats. A search for a new

signaling superframe alignment starts once frame alignment is established.

LTS16MFA Loss of Time Slot 16 Signaling Multiframe Alignment. A 1 indicates the receive framer

is in a loss of time slot 16 signaling multiframe alignment in the CEPT mode. A search for

a new time slot 16 signaling multiframe alignment starts once frame alignment is

established. This bit is 0 when the T7633 is programmed for the transparent signaling

mode, register FRM_PR44 bit 0 (TSIG) = 1.

LTSFA,

Loss of Transmit Superframe Alignment. A 1 indicates superframe alignment pattern

in the transmit facility data link as defined for SLC-96 is lost. Only valid for SLC-96 mode.

This bit is 0 in all other DS1 modes.

LTS0MFA

Loss of Time Slot 0 CRC-4 Multiframe Alignment. A 1 indicates an absence of CRC-

4 multiframe alignment after initial basic frame alignment is established. A 0 indicates

either CRC-4 checking is disabled or CRC-4 multiframe alignment has been successfully

detected.

3

4

LFALR

LBFA

Loss of Frame Alignment Since Last Read. A 1 indicates that the LFA state indicated

in bit 0 of this register is the same LFA state as the previous read.

Loss of Biframe Alignment. A 1 indicates that the CEPT biframe alignment pattern

(alternating 10 in bit 2 of time slot 0 of each frame) in the receive system data is errored.

This alignment pattern is required when transmitting the Si or Sa bits transparently. Only

valid in the CEPT mode. This bit is 0 in all other modes.

5

6

7

RTS16AIS Receive Time Slot 16 Alarm Indication Signal. A 1 indicates the receive framer

detected time slot 16 AIS in the CEPT mode. This bit is 0 in the DS1 modes.

AUXP

AIS

Auxiliary Pattern. A 1 indicates the detection of a valid AUXP (unframed 1010 . . .

pattern) in the CEPT mode. This bit is 0 in the DS1 modes.

Alarm Indication Signal. A 1 indicates the receive framer is currently receiving an AIS

pattern from its remote line end.

166

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

Remote End Alarm Register (FRM_SR2)

A bit set to 1 indicates the receive framer has recently received the given alarm. Interrupts from this register are

generated once at the beginning of the alarm condition. If the alarm is still present at the time of the read, the bit

will remain in the 1 state for the duration of the alarm condition. If the alarm condition is no longer present at the

time of the read, then the bit is cleared on read.

Table 91. Remote End Alarm Register (FRM_SR2) (602; C02)

Bit

Symbol

Description

0

RFA

Remote Framer Alarm. A 1 indicates the receive framer detected a remote frame

(yellow) alarm.

1

RJYA,

Remote Japanese Yellow Alarm. A 1 indicates the receive framer detected the

Japanese format remote frame alarm.

RTS16MFA Remote Multiframe Alarm. A 1 indicates the receive framer detected a time slot 16

remote frame alarm in the CEPT mode.

2

3

4

5

6

7

CREBIT

Sa6=8

Sa6=A

Sa6=C

Sa6=E

Sa6=F

Continuous Received E Bits. A 1 indicates the detection of a five-second interval con-

taining ≥991 E bit = 0 events in each second. This bit is 0 in the DS1 mode.

Received Sa6 = 8. A 1 indicates the receive framer detected a Sa6 code equal to 1000.

This bit is 0 in the DS1 mode.

Received Sa6 = A. A 1 indicates the receive framer detected a Sa6 code equal to 1010.

This bit is 0 in the DS1 mode.

Received Sa6 = C. A 1 indicates the receive framer detected a Sa6 code equal to 1100.

This bit is 0 in the DS1 mode.

Received Sa6 = E. A 1 indicates the receive framer detected a Sa6 code equal to 1110.

This bit is 0 in the DS1 mode.

Received Sa6 = F. A 1 indicates the receive framer detected a Sa6 code equal to 1111.

This bit is 0 in the DS1 mode.

Agere Systems Inc.

167

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

Facility Errored Event Register (FRM_SR3)

A bit set to 1 indicates the receive framer has recently received the given errored event.

Table 92. Facility Errored Event Register-1 (FRM_SR3) (603; C03)

Bit

Symbol

Description

0

LFV

Line Format Violation. A 1 indicates the receive framer detected a bipolar line coding or

excessive zeros violation.

1

FBE

Frame-Bit Errored. A 1 indicates the receive framer detected a frame-bit or frame

alignment pattern error.

2

3

CRCE

ECE

CRC Errored. A 1 indicates the receive framer detected CRC errors.

Excessive CRC Errors. A 1 indicates the receive framer detected an excessive CRC

errored condition. This bit is only valid in the ESF and CEPT with CRC-4 modes;

otherwise, it is 0.

4

5

REBIT

Received E Bit = 0. A 1 indicates the receive framer detected a E bit = 0 in either frame

13 or 15 of the time slot 0 of CRC-4 multiframe. This bit is 0 in the DS1 modes.

LCRCATMX Lack of CRC-4 Multiframe Alignment Timer Expire Indication. A 1 indicates that either

the 100 ms or the 400 ms CRC-4 interworking timer expired. Active only immediately after

establishment of the initial basic frame alignment. This bit is 0 in the DS1 modes.

6

7

SLIPO

Receive Elastic Store Slip: Buffer Overflow. A 1 indicates the receive elastic store

performed a control slip due to an elastic buffer overflow condition.

SLIPU

Receive Elastic Store Slip: Buffer Underflow. A 1 indicates the receive elastic store

performed a control slip due to an elastic buffer underflow condition.

168

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

Table 93. Facility Event Register-2 (FRM_SR4) (604; C04)

Bit

Symbol

Description

0

NFA

New Frame Alignment. A 1 indicates the receive framer established a new frame

alignment which differs from the previous alignment.

1

2

SSFA

Signaling Superframe Alignment. A 1 indicates the receive framer has established the

signaling superframe alignment. In the SF modes (D4 and SLC-96) and CEPT modes,

this alignment is established only after primary frame alignment is determined.

LLBOFF,

BFA

T1 Line Loopback Off Code Detect. A 1 indicates the receive framer detected the DS1

line loopback disable code in the payload. This code is defined in AT&T Technical

Reference 62411 as a framed 001 pattern where the frame bit is inserted into the pattern.

New Biframe Alignment Established. A 1 indicates the transmit framer has established

a biframe alignment for the transmission of transparent Si and or Sa bits from the system

data in the CEPT mode.

3

LLBON,

CMA

T1 Line Loopback On Code Detect. A 1 indicates the receive framer detected the line

loopback enable code in the payload. This code is defined in AT&T Technical Reference

62411 as a framed 00001 pattern where the frame bit is inserted into the pattern.

New CEPT CRC-4 Multiframe Alignment. A 1 indicates the CEPT CRC-4 multiframe

alignment in the receive framer has been established.

Agere Systems Inc.

169

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

Table 93. Facility Event Register-2 (FRM_SR4) (604; C04) (continued)

Bit

Symbol

Description

4

FDL-PLBON, ESF FDL Payload Loopback On Code Detect. A 1 indicates the receive framer detected

the line loopback enable code in the payload. This code is defined in ANSI T1.403-1995

as a 1111111100101000 pattern in the facility data link, where the leftmost bit is the MSB.

SLCRFSR

SLC-96 Receive FDL Stack Ready. A 1 indicates that the receive FDL stack should be

read. This bit is cleared on read. Data in the receive FIFO must be read within 9 ms of this

interrupt. This bit is not updated during loss of frame or signaling superframe alignment.

5

6

7

FDL-PLBOFF, ESF FDL Payload Loopback Off Code Detect. A 1 indicates the receive framer

detected the line loopback disable code in the payload. This code is defined in ANSI

T1.403-1995 as a 1111111101001100 pattern in the facility data link, where the leftmost

SLCTFSR

bit is the MSB.

SLC-96 Transmit FDL Stack Ready. A 1 indicates that the transmit FDL stack is ready

for new data. This bit is cleared on read. Data written within 9 ms of this interrupt will be

transmitted in the next SLC-96 D-bit superframe interval.

FDL-LLBON, ESF FDL Line Loopback On Code Detect. A 1 indicates the receive framer detected the

line loopback enable code in the payload. This code is defined in ANSI T1.403-1995 as a

1111111101110000 pattern in the facility data link, where the left most bit is the MSB.

RSaSR

CEPT Receive Sa Stack Ready. A 1 indicates that the receive Sa6 stack should be read.

This bit is clear on the first access to the Sa receive stack or at the beginning of frame 0

of the CRC-4 double-multiframe. Data in the receive FIFO must be read within 4 ms of

this interrupt. This bit is not updated during LFA.

FDL-LLBOFF, ESF FDL Line Loopback Off Code Detect. A 1 indicates the receive framer detected the

line loopback disable code in the payload. This code is defined in ANSI T1.403-1995 as

a 1111111100011100 pattern in the facility data link, where the left most bit is the MSB.

TSaSR

CEPT Transmit Sa Stack Ready. A 1 indicates that the transmit Sa stack is ready for

new data. This bit is cleared on the first access to the Sa transmit stack or at the beginning

of frame 0 of the CRC-4 double multiframe. Data written within 4 ms of this interrupt will

be transmitted in the next CRC-4 double multiframe interval.

170

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

The following registers are dedicated to the exchange termination and its remote end interface. The alarm

conditions to trigger errored seconds and severely errored seconds are defined in Table 44, Event Counters

Definition on page 97 and the ET and ET-RE enable registers, FRM_PR14 and FRM_PR15. The thresholds are

defined in registers FRM_PR11—FRM_PR13.

Table 94. Exchange Termination and Exchange Termination Remote End Interface

Status Register (FRM_SR5) (605; C05)

Bit

Symbol

Description

0

ETES

ET Errored Second. A 1 indicates the receive framer detected an errored second at the

exchange termination (ET).

1

2

3

ETBES

ETSES

ETUAS

ET Bursty Errored Second. A 1 indicates the receive framer detected a bursty errored

second at the ET.

ET Severely Errored Second. A 1 indicates the receive framer detected a severely

errored second at the ET.

ET Unavailable State. A 1 indicates the receive framer has detected at least ten

consecutive severely errored seconds. Upon detecting ten consecutive nonseverely

errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is

used resulting in a ten-second delay in the reporting of this condition.

4

5

6

7

ETREES

ETREBES

ETRESES

ET-RE Errored Second. A 1 indicates the receive framer detected an errored second at

the exchange termination remote end (ET-RE).

ET-RE Bursty Errored Second. A 1 indicates the receive framer detected a bursty

errored second at the ET-RE.

ET-RE Severely Errored Second. A 1 indicates the receive framer detected a severely

errored second at the ET-RE.

ETREUAS ET-RE Unavailable State. A 1 indicates the receive framer has detected at least ten

consecutive severely errored seconds. Upon detecting ten consecutive nonseverely

errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is

used resulting in a ten-second delay in the reporting of this condition.

Agere Systems Inc.

171

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

The following status registers are dedicated to the NT1 and the NT1 remote end (NT1-RE) interface. The alarm

conditions to evaluate errored seconds and severely errored seconds are defined in Table 44, Event Counters

Definition on page 97 and the NT1 and NT1-RE enable registers, FRM_PR16—FRM_PR18. The thresholds are

defined in registers FRM_PR11—FRM_PR13.

Table 95. Network Termination and Network Termination Remote End Interface Status

Register (FRM_SR6) (606; C06)

Bit

Symbol

Description

0

NTES

NT Errored Second. A 1 indicates the receive framer detected an errored second at the

network termination (NT).

1

2

3

NTBES

NTSES

NTUAS

NT Bursty Errored Second. A 1 indicates the receive framer detected a bursty errored

second at the NT.

NT Severely Errored Second. A 1 indicates the receive framer detected a severely

errored second at the NT.

NT Unavailable State. A 1 indicates the receive framer has detected at least ten

consecutive severely errored seconds. Upon detecting ten consecutive nonseverely

errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used

resulting in a ten-second delay in the reporting of this condition.

4

5

6

7

NTREES

NT-RE Errored Second. A 1 indicates the receive framer detected an errored second at

the exchange termination remote end (ET-RE).

NTREBES NT-RE Bursty Errored Second. A 1 indicates the receive framer detected a bursty

errored second at the ET-RE.

NTRESES NT-RE Severely Errored Second. A 1 indicates the receive framer detected a severely

errored second at the NT-RE.

NTREUAS NT-RE Unavailable State. A 1 indicates the receive framer has detected at least ten

consecutive severely errored seconds. Upon detecting ten consecutive nonseverely

errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used

resulting in a ten-second delay in the reporting of this condition.

172

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

Bit 0—bit 4 in this register are set high when the receive framer comes out of the unavailable state, while bit 4—bit

7 report detection of the receive test patterns.

Table 96. Facility Event Register (FRM_SR7) (607; C07)

Bit

Symbol

Description

0

OUAS

Out of Unavailable State. A 1 indicates the receive framer detected ten consecutive

seconds that were not severely errored while in the unavailable state at the ET.

1

2

3

EROUAS

Out of Unavailable State at the ET-RE. A 1 indicates the receive framer detected ten

consecutive seconds that were not severely errored while in the unavailable state at the

ET-RE.

NT1OUAS Out of Unavailable State at the NT1. A 1 indicates the receive framer detected ten

consecutive seconds that were not severely errored while in the unavailable state at the

NT.

NROUAS

DETECT

Out of Unavailable State NT1-RE. A 1 indicates the receive framer detected ten

consecutive seconds that were not severely errored while in the unavailable state at the

NT-RE.

4

5

6

7

Test Pattern Detected. A 1 indicates the pattern detector has locked onto the pattern

specified by the PTRN configuration bits defined in register FRM_PR70.

PTRNBER Test Pattern Bit Error. A 1 indicates the pattern detector has found one or more single

bit errors in the pattern that it is currently locked onto.

RPSUEDO Receiving Pseudorandom Pattern. A 1 indicates the receive framer pattern monitor

circuit is currently detecting the 2¹⁵– 1 pseudorandom pattern*.

RQUASI

Receiving Quasi-Random Pattern. A 1 indicates the receive framer pattern monitor

circuit is currently detecting the 2²⁰– 1 quasi-random pattern*.

* It is possible for one of these bits to be set to 1, if the received line data is all zeros.

Bipolar Violation Counter Register (FRM_SR8—FRM_SR9)

This register contains the 16-bit count of received bipolar violations, line code violations, or excessive zeros.

Table 97. Bipolar Violation Counter Registers (FRM_SR8—FRM_SR9) ((608—609); (C08—C09))

Register

FRM_SR8

FRM_SR9

Byte

MSB

LSB

Bit

7—0

Symbol

Description

BPV15—BPV8 BPVs Counter.

BPV7—BPV0 BPVs Counter.

Frame Bit Errored Counter Register (FRM_SR10—FRM_SR11)

This register contains the 16-bit count of framing bit errors. Framing bit errors are not counted during loss of frame

alignment.

Table 98. Framing Bit Error Counter Registers (FRM_SR10—FRM_SR11) ((60A—60B); (C0A—C0B))

Register

FRM_SR10

FRM_SR11

Byte

MSB

LSB

Bit

Symbol

Description

7—0

FBE15—FBE8 Frame Bit Counter.

FBE7—FBE0 Frame Bit Errored Counter.

Agere Systems Inc.

173

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

CRC Error Counter Register (FRM_SR12—FRM_SR13)

This register contains the 16-bit count of CRC errors. CRC errors are not counted during loss of CRC multiframe

alignment.

Table 99. CRC Error Counter Registers (FRM_SR12—FRM_SR13) ((60C—60D); (C0C—C0D))

Register

FRM_SR12

FRM_SR13

Byte

MSB

LSB

Bit

Symbol

Description

7—0

CEC15—CEC8 CRC Errored Counter.

CEC7—CEC0 CRC Errored Counter.

E-Bit Counter Register (FRM_SR14—FRM_SR15)

This register contains the 16-bit count of received E bit = 0 events. E bits are not counted during loss of CEPT

CRC-4 multiframe alignment.

Table 100. E-Bit Counter Registers (FRM_SR14—FRM_SR15) ((60E—60F); (C0E—C0F))

Register

FRM_SR14

FRM_SR15

Byte

MSB

LSB

Bit

Symbol

Description

7—0

REC15—REC8 E-Bit Counter.

REC7—REC0 E-Bit Counter.

CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16—FRM_SR17)

This register contains the 16-bit count of each occurrence of Sa6 code 001X, detected synchronously to the CEPT

CRC-4 multiframe.

Table 101. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16—FRM_SR17) ((610—611);

(C10—C11))

Register

FRM_SR16

FRM_SR17

Byte

MSB

LSB

Bit

Symbol

Description

7—0

CNT15—CNT8 CRC-4 Errors at NT1 Counter.

CNT7—CNT0 CRC-4 Errors at NT1 Counter.

E Bit at NT1 from NT2 Counter Registers (FRM_SR18—FRM_SR19)

This register contains the 16-bit count of each occurrence of Sa6 code 00X1, detected synchronously to the CEPT

CRC-4 multiframe. E bits are not counted during loss of CEPT CRC-4 multiframe alignment.

Table 102. E Bit at NT1 from NT2 Counter (FRM_SR18—FRM_SR19) ((612—613); (C12—C13))

Register

FRM_SR18

FRM_SR19

Byte

MSB

LSB

Bit

Symbol

Description

7—0

ENT15—ENT8 E Bit at NT1 Counter.

ENT7—ENT0 E Bit at NT1 Counter.

174

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

The following status registers, FRM_SR20—FRM_SR51, contain the 16-bit count of errored seconds, bursty

errored seconds, severely errored seconds, and unavailable seconds at the ET, ET-RE, NT1, and NT1-RE

terminals.

Table 103. ET Errored Seconds Counter (FRM_SR20—FRM_SR21) ((614—615); (C14—C15))

Register

FRM_SR20

FRM_SR21

Byte

MSB

LSB

Bit

Symbol

Description

ET Errored Seconds Counter.

7—0

ETES15—ETES8

ETES7—ETES0

Table 104. ET Bursty Errored Seconds Counter (FRM_SR22—FRM_SR23) ((616—617); (C16—C17))

Register

FRM_SR22

FRM_SR23

Byte

MSB

LSB

Bit

Symbol

Description

7—0

ETBES15—ETBES8 ET Bursty Errored Seconds Counter.

ETBES7—ETBES0 ET Bursty Errored Seconds Counter.

Table 105. ET Severely Errored Seconds Counter (FRM_SR24—FRM_SR25) ((618—619); (C18—C19))

Register

FRM_SR24

FRM_SR25

Byte

MSB

LSB

Bit

Symbol

Description

7—0

ETSES15—ETSES8 ET Severely Errored Seconds Counter.

ETSES7—ETSES0 ET Severely Errored Seconds Counter.

Table 106. ET Unavailable Seconds Counter (FRM_SR26—FRM_SR27) ((61A—61B); (C1A—C1B))

Register

FRM_SR26

FRM_SR27

Byte

MSB

LSB

Bit

Symbol

Description

7—0

ETUS15—ETUS8

ETUS7—ETUS0

ET Unavailable Seconds Counter Bits.

Table 107. ET-RE Errored Seconds Counter (FRM_SR28—FRM_SR29) ((61C—61D); (C1C—C1D))

Register

FRM_SR28

FRM_SR29

Byte

MSB

LSB

Bit

7—0 ETREES15—ETREES8 ET-RE Errored Seconds Counter.

7—0 ETREES7—ETREES0 ET-RE Errored Seconds Counter.

Symbol

Description

Table 108. ET-RE Bursty Errored Seconds Counter (FRM_SR30—FRM_SR31) ((61E—61F); (C1E—C1F))

Register Byte Bit Symbol Description

FRM_SR30 MSB 7—0 ETREBES15—ETREBES8 ET-RE Bursty Errored Seconds Counter.

FRM_SR31 LSB 7—0 ETREBES7—ETREBES0 ET-RE Bursty Errored Seconds Counter.

Table 109. ET-RE Severely Errored Seconds Counter (FRM_SR32—FRM_SR33) ((620—621); (C20—C21))

Register Byte Bit Symbol Description

FRM_SR32 MSB 7—0 ETRESES15—ETRESES8 ET-RE Severely Errored Seconds Counter.

FRM_SR33 LSB 7—0 ETRESES7—ETRESES0 ET-RE Severely Errored Seconds Counter.

Agere Systems Inc.

175

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

Table 110. ET-RE Unavailable Seconds Counter (FRM_SR34—FRM_SR35) ((622—623); (C22—C23))

Register

FRM_SR34 MSB

FRM_SR35 LSB

Byte

Bit

Symbol

Description

7—0

ETREUS15—ETRESES8 ET-RE Unavailable Seconds Counter.

ETRESES7—ETRESES0 ET-RE Unavailable Seconds Counter.

Table 111. NT1 Errored Seconds Counter (FRM_SR36—FRM_SR37) ((624—625); (C24—C25))

Register

FRM_SR36 MSB

FRM_SR37 LSB

Byte

Bit

Symbol

Description

NT1 Errored Seconds Counter.

7—0

NTES15—NTES8

NTES7—NTES0

Table 112. NT1 Bursty Errored Seconds Counter (FRM_SR38—FRM_SR39) ((626—627); (C26—C27))

Register

FRM_SR38

FRM_SR39

Byte

MSB

LSB

Bit

Symbol

Description

7—0

NTBES15—NTBES8

NTBES7—NTBES0

NT1 Bursty Errored Seconds Counter.

Table 113. NT1 Severely Errored Seconds Counter (FRM_SR40—FRM_SR41) ((628—629); (C28—C29))

Register

FRM_SR40 MSB

FRM_SR41 LSB

Byte

Bit

Symbol

Description

7—0

NTSES15—NTSES8

NTSES7—NTSES0

NT1 Severely Errored Seconds Counter.

Table 114. NT1 Unavailable Seconds Counter (FRM_SR42—FRM_SR43) ((62A—62B); (C2A—C2B))

Register

FRM_SR42 MSB

FRM_SR43 LSB

Byte

Bit

Symbol

Description

7—0

NTUS15—NTUS8

NTUS7—NTUS0

NT1 Unavailable Seconds Counter Bits.

Table 115. NT1-RE Errored Seconds Counter (FRM_SR44—FRM_SR45) ((62C—62D); (C2C—C2D))

Register

FRM_SR44 MSB

FRM_SR45 LSB

Byte

Bit

Symbol

NTREES15—NTREES8 NT1-RE Errored Seconds Counter.

NTREES7—NTREES0 NT1-RE Errored Seconds Counter.

Description

7—0

176

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

Table 116. NT1-RE Bursty Errored Seconds Counter (FRM_SR46—FRM_SR47) ((62E—62F); (C2E—C2F))

Register Byte Bit Symbol Description

FRM_SR46 MSB 7—0 NTREBES15—NTREBES8 NT1-RE Bursty Errored Seconds Counter.

FRM_SR47 LSB 7—0 NTREBES7—NTREBES0 NT1-RE Bursty Errored Seconds Counter.

Table 117. NT1-RE Severely Errored Seconds Counter (FRM_SR48—FRM_SR49) ((630—631); (C30—C31))

Register Byte Bit Symbol Description

FRM_SR48 MSB 7—0 NTRESES15—NTRESES8 NT1-RE Severely Errored Seconds Counter.

FRM_SR49 LSB 7—0 NTRESES7—NTRESES0 NT1-RE Severely Errored Seconds Counter.

Table 118. NT1-RE Unavailable Seconds Counter (FRM_SR50—FRM_SR51) ((632—633); (C32—C33))

Register

FRM_SR50 MSB

FRM_SR51 LSB

Byte

Bit

Symbol

Description

7—0

NTREUS15—NTREUS8 NT1-RE Unavailable Seconds Counter Bits.

NTREUS7—NTREUS0 NT1-RE Unavailable Seconds Counter Bits.

Received NOT-FAS TS0 RSa Register (FRM_SR52)

This register contains the last (since last read) valid received RSa8— RSa4 bits, A bit, and Si bit of NOT-FAS time

slot 0 and the Si bit of FAS time slot 0 while the receive framer was in basic frame alignment.

Table 119. Receive NOT-FAS TS0 Register (FRM_SR52) (634; C34)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

NOT-FAS bit 1

FAS bit 1

A bit

Sa4

Sa5

Sa6

Sa7

Sa8

(CEPT without CRC-4) (CEPT without CRC-4)

or

frame 15 E bit

(CEPT with CRC-4)

frame 13 E bit

(CEPT with CRC-4)

Received Sa Register (FRM_SR53)

This register contains the last (since last read) valid time slot 16 spare bits of the frame containing the time slot 16

signaling multiframe alignment. These bits are updated only when the receive framer is in signaling multiframe

alignment.

Table 120. Receive Sa Register (FRM_SR53) (635; C35)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

X2

X1

X0

Agere Systems Inc.

177

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

SLC-96 FDL/CEPT Sa Receive Stack (FRM_SR54—FRM_SR63)

In the SLC-96 frame format, FRM_SR54 through FRM_SR58 contain the received SLC-96 facility data link data

block. When the framer is in a loss of frame alignment or loss of signaling superframe alignment, these registers

are not updated.

Note: The RSP[1:4] are the received spoiler bits.

Table 121. SLC-96 FDL Receive Stack (FRM_SR54—FRM_SR63) ((636—63F); (C36—C3F))

Register

Bit 7

0

Bit 6

0

Bit 5

R-0

RC3

RC11

RA2

0

Bit 4

R-0

Bit 3

R-0

Bit 2

R-1

Bit 1

R-1

RC7

RM1

RS4

0

Bit 0

R-1

FRM_SR54

FRM_SR55

FRM_SR56

FRM_SR57

FRM_SR58

0

R-0

R-1

RC1

RC9

RM3

0

RC2

RC10

RA1

0

RC4

RC5

RC6

RC8

RSPB1 = 0 RSPB2 = 1 RSPB3 = 0

RM2

RS1

0

RS2

0

RS3

0

RSPB4 = 1

0

FRM_SR59—

FRM_SR61

In the CEPT frame format, FRM_SR54 through FRM_SR63 contain the received Sa4 through Sa8 from the last

valid CRC-4 double-multiframe. In non-CRC-4 mode, these registers are only updated during a basic frame

aligned state. In CRC-4 mode, these registers are only updated during the CRC-4 multiframe alignment state.

Table 122. CEPT Sa Receive Stack (FRM_SR54—FRM_SR63) ((636—63F); (C36—C3F))

Register

Bit 7

Sa4-1

Sa4-17

Sa5-1

Sa5-17

Sa6-1

Sa6-17

Sa7-1

Sa7-17

Sa8-1

Sa8-17

Bit 6

Sa4-3

Sa4-19

Sa5-3

Sa5-19

Sa6-3

Sa6-19

Sa7-3

Sa7-19

Sa8-3

Sa8-19

Bit 5

Sa4-5

Sa4-21

Sa5-5

Sa5-21

Sa6-5

Sa6-21

Sa7-5

Sa7-21

Sa8-5

Sa8-21

Bit 4

Sa4-7

Sa4-23

Sa5-7

Sa5-23

Sa6-7

Sa6-23

Sa7-7

Sa7-23

Sa8-7

Sa8-23

Bit 3

Sa4-9

Sa4-25

Sa5-9

Sa5-25

Sa6-9

Sa6-25

Sa7-9

Sa7-25

Sa8-9

Sa8-25

Bit 2

Bit 1

Bit 0

FRM_SR54

FRM_SR55

FRM_SR56

FRM_SR57

FRM_SR58

FRM_SR59

FRM_SR60

FRM_SR61

FRM_SR62

FRM_SR63

Sa4-11

Sa4-27

Sa5-11

Sa5-27

Sa6-11

Sa6-27

Sa7-11

Sa7-27

Sa8-11

Sa8-27

Sa4-13

Sa4-29

Sa5-13

Sa5-29

Sa6-13

Sa6-29

Sa7-13

Sa7-29

Sa8-13

Sa8-29

Sa4-15

Sa4-31

Sa5-15

Sa5-31

Sa6-15

Sa6-31

Sa7-15

Sa7-31

Sa8-15

Sa8-31

178

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Status/Counter Registers (continued)

The receive framer stores the current second of the ANSI Performance Report Message transmitted to the

remote end in registers FRM_SR62 and FRM_SR63. The structure of the PRM status registers is shown in Table

123.

Table 123. Transmit Framer ANSI Performance Report Message Status Register Structure

Transmit

TSPRM B7

TSPRM B6

TSPRM B5 TSPRM B4 TSPRM B3 TSPRM B2 TSPRM B1

TSPRM B0

Framer PRM

Status Bytes

FRM_SR62

FRM_SR63

G3

FE

LV

G4

LB

U1

G1

U2

R

G5

G2

SL

G6

Nl

SE

Nm

Received Signaling Registers: DS1 Format

Table 124. Received Signaling Registers: DS1 Format (FRM_RSR0—FRM_RSR23) ((640—658); (C40—C58))

Received Signal Registers

Bit 7 Bit Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

6¹

X

DS1 Received Signaling Registers (0—23)

Voice Channel with 16-State Signaling

Voice Channel with 4-State Signaling

Voice Channel with 2-State Signaling

Data Channel

P

X

G

0

1

F

0

1

0

D

X

C

X

B

A

X

A

X

1.Bit 6 and Bit 5 of the DS1 receive signaling registers are copied from bit 6 and bit 5 of the DS1 transmit signaling registers.

Receive Signaling Registers: CEPT Format

Table 125. Receive Signaling Registers: CEPT Format (FRM_RSR0—FRM_RSR31) ((640—65F); (C40—

C5F))

Receive Signal Registers

Bit 7

Bit 6—5

Bit 4¹

Bit 3

Bit 2

Bit 1

Bit 0

X

E0

X

FRM_RSR0: IRSM Mode

Only

P

X

P

X

E[1:15]

E16

D[1:15]

X

C[1:15]

X

B[1:15]

B

A[1:15]

A

FRM_RSR1—FRM_RSR15

FRM_RSR16: IRSM Only

FRM_RSR[17:31]

E[17:31]

D[17:31]

C[17:31]

B[17:31]

A[17:31]

1.This bit contains the IRSM information in time slot 0. In PCS0 or PCS1 signaling mode, this bit is undefined.

Agere Systems Inc.

179

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers

Registers FRM_PR0—FRM_PR70 define the mode configuration of each framer. All are read/write registers.

These registers are initially set to a default value upon a hardware reset, which is indicated in the register defini-

tion.

Interrupt Group Enable Registers (FRM_PR0—FRM_PR7)

The bits in this register group enable the status registers FRM_SR0—FRM_SR7 to assert the interrupt pin. The

default value of these registers is 00 (hex).

FRM_PR0 is the primary interrupt group enable register which enables the event groups in interrupt status register

FRM_SR0. A bit set to 1 in this register enables the corresponding bit in the interrupt status register FRM_SR0 to

assert the interrupt pin.

FRM_PR1—FRM_PR7 are the secondary interrupt enable registers. A bit set to 1 in these registers enables the

corresponding bit in the status register to assert the interrupt pin.

Table 126. Summary of Interrupt Group Enable Registers (FRM_PR0—FRM_PR7) ((660—667); (C60—C67))

Parameter/

Control

Register

Status

Register

Enabled

Status

Register

Bit 7

Status

Register

Bit 6

Status

Register

Bit 5

Status

Register

Bit 4

Status

Register

Bit 3

Status

Register

Bit 2

Status

Register

Bit 1

Status

Register

Bit 0

FRM_PR0 FRM_SR0

S96SR

Reserved

RSSFE

TSSFE

ESE

FAE

RAC

FAC

(read

FRM_SR5, FRM_SR3 FRM_SR2) FRM_SR1)

FRM_SR6,

and

FRM_SR4)

FRM_SR7)

FRM_PR1 FRM_SR1

FRM_PR2 FRM_SR2

AIS

AUXP

RTS16AIS

RSa6=C

LBFA

LFALR

LTSFA

(LTS0MFA) (LTS16MFA)

LSFA

LFA

RFA

RSa6=F

RSa6=E

RSa6=A

RSa6=8

CREBIT

RJYA

(RTS16MFA

)

FRM_PR3 FRM_SR3

FRM_PR4 FRM_SR4

SLIPU

SLIPO

LCRCATMX

REBIT

ECE

CRCE

FBE

LFV

CFA

FDL_LLBOFF

(TSaSR)

FDL_PLBOFF

(SLCTFSR)

FDL_LLBON

(RSaSR)

FDL_PLBON

(SLCRFSR)

LLBON

(CMA)

LLBOFF

(BFA)

SSFA

FRM_PR5 FRM_SR5 ETREUAS

FRM_PR6 FRM_SR6 NTREUAS

ETRESES

NTRESES

RPSUEDO

ETREBES

NTREBES

PTRNBER

ETREES

NTREES

DETECT

ETUAS

NTUAS

ETSES

NTSES

ETBES

NTBES

ETES

NTES

OUAS

FRM_PR7 FRM_SR7

RQUASI

NROUAS NT1OUAS

EROUAS

180

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Primary Interrupt Enable Register (FRM_PR0)

The default value of this register is 00 (hex).

Table 127. Primary Interrupt Group Enable Register (FRM_PR0) (660; C60)

Bit

0

Symbol

SR1IE

Description

Status Register 1 Interrupt Enable Bit. A 1 enables register FRM_SR1 event interrupts.

Status Register 2 Interrupt Enable Bit. A 1 enables register FRM_SR2 event interrupts.

1

SR2IE

2

SR34IE

Status Registers 3 and 4 Interrupt Enable Bit. A 1 enables registers FRM_SR3 and

FRM_SR4 event interrupts.

3

4

5

SR567IE

TSRIE

Status Registers 5, 6, and 7 Interrupt Enable Bit. A 1 enables registers FRM_SR5,

FRM_SR6, and FRM_SR7 event interrupts.

Transmit Signaling Ready Interrupt Enable Bit. A 1 enables interrupts when transmit

signaling buffers are ready (MOS or CCS modes).

RSRIE

Receive Signaling Ready Interrupt Enable Bit. A 1 enables interrupts when receive

signaling buffers are ready (MOS or CCS modes).

6

—

Reserved. Write to 0.

7

SLCIE

SLC-96 Interrupt Enable Bit. A 1 enables interrupts when SLC-96 receive or transmit

stacks are ready.

Agere Systems Inc.

181

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Secondary Interrupt Enable Registers (FRM_PR1—FRM_PR7)

A bit set to 1 in registers FRM_PR1—FRM_PR7 enables the generation of interrupts whenever the corresponding

bit in registers FRM_SR1—FRM_SR7 is set. The default value of these registers is 00 (hex).

Table 128. Interrupt Enable Register (FRM_PR1) (661; C61)

Bit

Symbol

Description

0—7

SR1B0IE— Status Register 1 Interrupt Enable. A 1 enables events monitored in register FRM_SR1

to generate interrupts. Each bit position in this enable register corresponds to the same

bit position in the status register.

SR1B7IE

Table 129. Interrupt Enable Register (FRM_PR2) (662; C62)

Bit

Symbol

Description

0—7

SR2B0IE— Status Register 2 Interrupt Enable. A 1 enables events monitored in register FRM_SR2

to generate interrupts. Each bit position in this enable register corresponds to the same

bit position in the status register.

SR2B7IE

Table 130. Interrupt Enable Register (FRM_PR3) (663; C63)

Bit

Symbol

Description

0—7

SR3B0IE— Status Register 3 Interrupt Enable. A 1 enables events monitored in register FRM_SR3

to generate interrupts. Each bit position in this enable register corresponds to the same

bit position in the status register.

SR3B7IE

Table 131. Interrupt Enable Register (FRM_PR4) (664; C64)

Bit

Symbol

Description

0—7

SR4B0IE— Status Register 4 Interrupt Enable. A 1 enables events monitored in register FRM_SR4

to generate interrupts. Each bit position in this enable register corresponds to the same

bit position in the status register.

SR4B7IE

Table 132. Interrupt Enable Register (FRM_PR5) (665; C65)

Bit

Symbol

Description

0—7

SR5B0IE— Status Register 5 Interrupt Enable. A 1 enables events monitored in register FRM_SR5

to generate interrupts. Each bit position in this enable register corresponds to the same

bit position in the status register.

SR5B7IE

Table 133. Interrupt Enable Register (FRM_PR6) (666; C66)

Bit

Symbol

Description

0—7

SR6B0IE— Status Register 6 Interrupt Enable. A 1 enables events monitored in register FRM_SR6

to generate interrupts. Each bit position in this enable register corresponds to the same

bit position in the status register.

SR6B7IE

Table 134. Interrupt Enable Register (FRM_PR7) (667; C67)

Bit

Symbol

Description

0—7

SR7B0IE— Status Register 7 Interrupt Enable. A 1 enables events monitored in register FRM_SR7

to generate interrupts. Each bit position in this enable register corresponds to the same

bit position in the status register.

SR7B7IE

182

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Framer Mode Option Register (FRM_PR8)

The default value of this register is C0 (hex).

Table 135. Framer Mode Bits Decoding (FRM_PR8) (668; C68)

FRM_PR8 Frame Format Bit 7 Bit 6 Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FMODE4 FMODE3 FMODE2 FMODE1 FMODE0

ESF

D4

X

0

1

0

1

0

1

0

1

0

1

0

DDS

DDS with FDL

SLC-96

Transmit ESF

Receive D4

Transmit D4

Receive ESF

X

1

0

1

CEPT

with No CRC-4

CCS

X

0

1

0

1

0

1

0

1

0

1

0

1

0

PCS Mode 0

PCS Mode 1

CCS

CEPT

with CRC-4

PCS Mode 1

PCS Mode 0

Table 136. Line Code Option Bits Decoding (FRM_PR8) (668; C68)

Line Code Format

Bit 7

LC2

Bit 6

LC1

Bit 5

LC0

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

B8ZS (T/R)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

ZCS (T/R)

HDB3 (T/R)

Single Rail (DEFAULT)

AMI (T/R)

B8ZS (T), AMI (R)

ZCS (T), B8ZS (R)

AMI (T), B8ZS (R)

Agere Systems Inc.

183

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Framer CRC Control Option Register (FRM_PR9)

This register defines the CRC options for the framer. The default setting is 00 (hex).

Table 137. CRC Option Bits Decoding (FRM_PR9) (669, C69)

FRM_PR9 CRC Options

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Loss of Frame Alignment Due to Excessive CRC

Errors (ESF ≥ 320, CEPT ≥ 915 in a one-second

interval)

0

X

1

CRC-4 with 100 ms Timer

0

X

1

X

1

X

1

X

1

X

1

CRC-4 Interworking Search with 400 ms Timer

CRC-4 with 990 REB Counter

X

CRC-4 with 990 REB Counter: A Bit = 1 Restart

CRC-4 with 990 REB Counter: Sa6-F or Sa6-E

Restart

X

XCRC-4/R-NO CRC-4

X-NOCRC-4/RCRC4

1

0

X

0

X

0

X

0

X

0

X

0

X

0

1

0

CRC Default Mode (No CRC)

184

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Alarm Filter Register (FRM_PR10)

The bits in this register enable various control options. The default setting is 00 (hex).

Table 138. Alarm Filter Register (FRM_PR10) (66A; C6A)

Bit

Symbol

Description

0

SSa6M

Synchronous Sa6 Monitoring. A 0 enables the asynchronous monitoring of the Sa6

codes relative to the receive CRC-4 submultiframe. A 1 enables synchronous monitoring

of the Sa6 pattern relative to the receive CRC-4 submultiframe.

1

2

AISM

AIS Detection Mode. A 0 enables the detection of received line AIS as described in

ETSI Draft prETS 300 233:1992. A 1 enables the detection of received line AIS as

described in ITU Rec. G.775.

FEREN

NFFE

FER Enable (DS1 Only). A 0 enables only the detection of FT framing bit errors in D4

and SLC-96 modes. A 1 enables the detection of FT and FS framing bit errors.

Not FAS Framing Bit Error Control (CEPT Only). A 0 enables the monitoring of

errored FAS and errored NOT FAS frames in the framing bit error counter, registers

FRM_SR10 and FRM_SR11. A 1 enables the monitoring of only errored FAS frames in

this error counter.

3

CNUCLBEN CNUCLB Enable (CEPT Only). A 0 enables payload loopback with regenerated framing

and CRC bits in register FRM_PR24. A 1 enables CEPT nailed-up connect loopback in

register FRM_PR24.

4

—

Reserved. Set to 0.

5

RABF

Receive A-Bit Filter (CEPT Only). A 0 makes the occurrence of three consecutive

A bit = 1 events assert and three consecutive A bit = 0 events deassert the remote frame

alarm, register FRM_SR2 bit 0. A 1 enables the occurrence of a single A-bit event to

deassert the remote frame alarm.

Bit 6 and bit 7 of FRM_PR10 control the evaluation of the bursty errored parameter as defined in Table 139 below.

The EST parameter refers to the errored second threshold defined in register FRM_PR11. The SEST parameter

refers to the severely errored second threshold defined in registers FRM_PR12 and FRM_PR13.

Table 139. Errored Event Threshold Definition

Bit 7,

FRM_PR10

ESM1

Bit 6,

FRM_PR10

ESM0

Errored Second (ES)

Definition

Severely Errored

Second (SES)

Definition

Bursty Errored Second

(BES) Definition

0

1

Default values in Table 44, Event Counters Definition on page 97.

ES = 1 when:

BES = 0

SES = 1 when:

Errored events > EST

Errored events > SEST

Other Combinations

Reserved.

Agere Systems Inc.

185

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Errored Second Threshold Register (FRM_PR11)

This register defines the errored event threshold for an errored second (ES). A one-second interval with errors less

than the ES threshold value will not be detected as an errored second. Programming 00 (hex) into this register dis-

ables the errored second threshold monitor circuitry if register FRM_PR10 bit 6 = 1 and bit 7 = 0. The default value

of this register is 00 (hex).

Table 140. Errored Second Threshold Register (FRM_PR11) (66B; C6B)

Register

Symbol

Description

FRM_PR11

EST7—EST0

ES Threshold Register.

Severely Errored Second Threshold Register (FRM_PR12—FRM_PR13)

This 16-bit register defines the errored event threshold for a severely errored second (SES). A one-second interval

with errors less than the SES threshold value is not a severely errored second. Programming 00 (hex) into these

two registers disables the severely errored second threshold monitor circuitry if register FRM_PR10 bit 6 = 1 and

bit 7 = 0. The default value of these registers is 00 (hex).

Table 141. Severely Errored Second Threshold Registers (FRM_PR12—FRM_PR13) ((66C—66D;

C6C—C6D))

Register

FRM_PR12 SEST15—SEST8 SES MSB Threshold Register.

FRM_PR13 SEST7—SEST0 SES LSB Threshold Register.

Symbol

Description

ET1 Errored Event Enable Register¹(FRM_PR14)

These bits enable the errored events used to determine errored and severely errored seconds at the local ET inter-

face. ETSLIP, ETAIS, ETLMFA, and ETLFA are the SLIP, AIS, LMFA, and LFA errored events, respectively, as

referred to the local ET interface. A 1 in the bit position enables the corresponding errored event. The default value

of this register is 00 (hex).

Table 142. ET1 Errored Event Enable Register (FRM_PR14) (66E; C6E)

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FRM_PR14

0

ETSLIP

ETAIS

ETLMFA

ETLFA

186

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

ET1 Remote End Errored Event Enable Register¹(FRM_PR15)

These bits enable the errored events used to determine errored and severely errored seconds at the ET’s remote

end interface. ETRESa6-F, ETRESa6-E, ETRESa6-8, ETRERFA, ETRESLIP, ETREAIS, ETRELMFA, and ETRELFA

are the Sa6-F, Sa6-E, Sa6-8, RFA, SLIP, AIS, LMFA, and LFA errored events, respectively, as referred to the ET

remote end interface. A 1 in the bit position enables the corresponding errored event. The default value of this reg-

ister is 00 (hex).

Table 143. ET1 Remote End Errored Event Enable Register (FRM_PR15) (66F; C6F)

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FRM_PR15 ETRESa6-F ETRESa6-E ETRESa6-8 ETRERFA ETRESLIP ETREAIS ETRELMFA ETRELFA

NT1 Errored Event Enable Register¹(FRM_PR16)

These bits enable the errored events used to determine errored and severely errored seconds at the network ter-

mination-1 interface. NTSa6-C, NTSa6-8, NTSLIP, NTAIS, NTLMFA, and NTLFA are the Sa6-C, Sa6-8, SLIP, AIS,

LMFA, and LFA errored events, respectively, as referred to the NT1 interface. A 1 in the bit position enables the

corresponding errored event. The default value of this register is 00 (hex).

Table 144. NT1 Errored Event Enable Register (FRM_PR16) (670; C70)

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FRM_PR16 NTSa6-C

0

NTSa6-8

0

NTSLIP

NTAIS

NTLMFA

NTLFA

NT1 Remote End Errored Event Enable Register¹(FRM_PR17—FRM_PR18)

These bits enable the errored events used to determine errored and severely errored seconds at the network ter-

mination-1 remote end interface. NTRERFA, NTRESLIP, NTREAIS, NTRELMFA, NTRELFA, NTRESa6-C,

NTRESa6-F, NTRESa6-E, and NTRESa6-8 are the RFA, SLIP, AIS, LMFA, LFA, Sa6-C, Sa6-F, Sa6-E, and Sa6-8

errored events, respectively, as referred to the NT-1 remote end interface. The default value of this register is 00

(hex).

Table 145. NT1 Remote End Errored Event Enable Registers (FRM_PR17—FRM_PR18) ((671—672);

(C71—C72))

Register

FRM_PR17

FRM_PR18

Bit 7

Bit 6

Bit 5

Bit 4

NTRERFA NTRESLIP

NTRESa6-C NTRESa6-F NTRESa6-E NTRESa6-8

Bit 3

Bit 2

Bit 1

Bit 0

0

NTREAIS NTRELMFA NTRELFA

0

1. One occurrence of any one of these events causes an errored second count increment and a severely errored second count increment.

Agere Systems Inc.

187

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Automatic AIS to the System and Automatic Loopback Enable Register

The default value of this register is 00 (hex).

Table 146. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (673; C73)

Bit

Symbol

Description

0

ASAIS

Automatic System AIS. A 1 transmits AIS to the system whenever the receive framer is

in the loss of receive frame alignment (RLFA) state.

1

ASAISTMX Automatic System AIS CEPT CRC-4 Timer Expiration. A 1 transmits AIS to the sys-

tem after the CRC-4 100 ms or 400 ms timer expires. AIS is transmitted for the duration

of the loss of CRC-4 multiframe alignment state.

2

3

4

—

Reserved. Set to 0.

TSAIS

ALLBE

Transmit System AIS. A 1 transmits AIS to the system.

Automatic Line Loopback Enable. A 1 enables the framer section to execute the DS1

line loopback on or off commands without system intervention.

5

6

—

Reserved. Set to 0.

AFDLLBE

Automatic FDL Line Loopback Enable. A 1 enables the framer section to execute a

line ESF FDL loopback on or off command without system intervention.

7

AFDPLBE

Automatic FDL Payload Loopback Enable. A 1 enables the framer section to execute

a payload ESF FDL loopback on or off command without system intervention.

Transmit Test Pattern to the Line Enable Register¹

This register enables the transmit framer to transmit various test signals to the line interface. The default value of

this register is 00 (hex). Note that between enabling the transmission of line loopback on and off codes this register

must be set to 00 (hex) (i.e., to enable transmission of line loopback on code and then off code, write into this reg-

ister 10 (hex), then 00 (hex), and finally 20 (hex)).

Table 147. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (674; C74)

Bit

0

Symbol

TUFAIS

Description

Unframed AIS to Line Interface (All Ones Pattern).

1

TUFAUXP

Unframed AUXP to Line Interface in CEPT Mode (Alternating 010101 Unframed

Pattern).

2

3

4

5

6

TPRS

TQRS

Transmit Pseudorandom Signal to Line Interface (2¹⁵– 1).

Transmit Quasi-Random Signal to Line Interface (2²⁰– 1) (ANSI T1.403).

Transmit Framed Payload Line Loopback On Code: 00001.

Transmit Framed Payload Line Loopback Off Code: 001.

TLLBON

TLLBOFF

TLIC

Transmit Line Idle Code of FRM_PR22. When this bit = 1, the line idle code of

FRM_PR22 is transmitted to the line in all time slots.

7

TICRC

Transmit Inverted CRC.

1. To transmit test signals using this register, registers FRM_PR69 and FRM_PR70 must be set to 00 (hex).

188

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Framer FDL Control Command Register (FRM_PR21)

The default value of this register is 00 (hex).

Table 148. Framer FDL Control Command Register (FRM_PR21) (675; C75)

Bit

0

Symbol

Description

—

Reserved. Must be set to 0.

1

—

2

3

—

4

TFDLLAIS

Transmit Facility Data Link AIS to the Line. A 1 sends AIS in the line side data link.

5

TFDLSAIS Transmit Facility Data Link AIS to the System. A 1 sends AIS in the system data link

side.

6

7

TFDLC

TC/R=1

Transmit FDL Control Bit. A 0 enables the transmission of the FDL bit from the internal

FDL-HDLC unit (default). A 1 enables the transmission of the FDL bit from either TFDL

input (pin 67 and 115) or from the internal transmit stack depending on the state of

FRM_PR29 bit 5—bit 7. When the SLC-96 stack transmission is enabled (register

FRM_PR26 bit 5—bit 7 = x10 (binary), the FDL bit is sourced from the SLC-96 transmit

stack (register FRM_PR31—FRM_PR35). Otherwise, it is sourced from TFDL

(pins 67/115).

Transmit ESF_PRM C/R = 1 (TC/R = 1). A 0 transmits the ESF performance report mes-

sage with the C/R bit = 0. (See ANSI T1.403-1995 for the PRM structure and content.) A

1 transmits the ESF performance report message with the C/R bit = 1.

Framer Transmit Line Idle Code Register (FRM_PR22)

The value programmed in this register is transmitted as the line idle code. The default value is 7F (hex).

Table 149. Framer Transmit Line Idle Code Register (FRM_PR22) (676; C76)

Bit

Symbol

Description

0—7

TLIC0—TLIC7 Transmit Line Idle Code 0—7. These 8 bits define the idle code transmitted to the

line.

Framer System Stuffed Time-Slot Code Register (FRM_PR23)

The value programmed in this register is transmitted in the stuffed time slots on the CHI in the DS1 modes. The

default value is 7F (hex).

Table 150. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (677; C77)

Bit

Symbol

Description

0—7

SSTSC0—

SSTSC7

System Stuffed Time-Slot Code 0—7. These 8 bits define the idle code transmitted

in the stuffed time slots to the system (CHI).

Agere Systems Inc.

189

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Primary Loopback Mode Control and Time Slot Address (FRM_PR24)

This register contains the loopback mode control and the 5-bit address of the line or system time slot to be looped

back. The default value is 00 (hex) (no loopback).

Table 151. Primary Time-Slot Loopback Address Register (FRM_PR24) (678; C78)

Bit

Symbol

Description

0—4

TSLBA0—

TSLBA4

Time-Slot Loopback Address.

Loopback Control Bits[2:0].

5—7

LBC0—LBC2

Table 152. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7—5

LBC2 LBC1 LBC0 Function

0

1

0

1

0

No Loopback.

Line Loopback (LLB). The received line data is looped back to the transmit line data.

Board Loopback (BLB). The received system data is looped back to the transmit

system data and AIS is sent as the line transmit data.

0

1

0

1

0

Single Time-Slot System Loopback (STSSLB). System (CHI) loopback of the time

slot selected by bit 4—bit 0. Idle code selected by FRM_PR22 is inserted in the line

payload in place of the looped back time slot.

Single Time-Slot Line Loopback (STSSLB). Line loopback of time slot selected by

bit 4—bit 0. Idle code selected by FRM_PR22 is inserted in the system (CHI) payload

in place of the looped back time slot.

1

0

1

0

CEPT Nailed-up Broadcast Transmission (CNUBT). Time slot selected by

bit 4—bit 0 is transmitted normally and also placed into time slot 0.

Payload Line Loopback with Regenerated Framing and CRC Bits. This mode is

selected if FRM_PR10 bit 3 = 0. The received channelized-payload data is looped

backed to the line. The framing bits are generated within the transmit framer. The

regenerated framing information includes the F-bit pattern, the CRC checksum bit,

and the system’s facility data link bit stream. This loopback mode can be used with

the CEPT framing mode. The entire time slot 0 data (FAS and NOT FAS) is regener-

ated by the transmit framer. The receive framer processes and monitors the incoming

line data normally in this loopback mode and transmits the formatted data to the sys-

tem in the normal format via the CHI.

CEPT Nailed-up Connect Loopback (CNUCLB). The received system time slot

selected by this register bit 4—bit 0 is looped back to the system in time slot 0. This

mode is selected if FRM_PR10 bit 3 = 1.

1

Payload Line Loopback with Passthrough Framing and CRC Bits. The received

channelized/payload data, the CRC bits, and the frame alignment bits are looped

back to the line. The system’s facility data link bit stream is inserted into the looped

back data and transmitted to the line. In ESF, the FDL bits are ignored when calculat-

ing the CRC-6 checksum. In CEPT, the FDL bits are included when calculating the

CRC-4 checksum, and as such this loopback mode generates CRC-4 errors back at

the remote end.

190

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Secondary Loopback Control and ID and Address (FRM_PR25)

This register allows for a second single-time-slot loopback mode. This loopback is valid if the secondary time slot

loopback address is different from the primary loopback address and the device is not in a line, board, or payload

loopback, see FRM_PR24. This register contains the secondary loopback mode control and the 5-bit address for

the secondary line or system time slot to be looped back to the line or system. The default value is 00 (hex) (no

loopback).

Table 153. Secondary Time-Slot Loopback Address Register (FRM_PR25) (679; C79)

Bit

0—4

5—6

7

Symbol

Description

STSLBA0—STSLBA4 Secondary Time-Slot Loopback Address.

SLBC0—SLBC1

—

Secondary Loopback Control Bits[1:0].

Reserved. Write to 0.

Table 154. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6—5

LBC1

LBC0

Function

0

1

0

1

0

1

No Loopback.

Secondary Single Time-Slot System Loopback.

Secondary Single Time-Slot Line Loopback.

Reserved.

Agere Systems Inc.

191

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Framer Reset and Transparent Mode Control Register (FRM_PR26)

The default value of this register is 00 (hex).

Table 155. Framer Reset and Transparent Mode Control Register (FRM_PR26) (67A, C7A)

Bits

Symbol

Description

0

SWRESET Framer Software Reset. The framer and FDL sections are placed in the reset state for

four clock cycles of the frame internal line clock (RFRMCK). The parameter registers are

forced to the default values. This bit is self-cleared.

1

SWRESTART Framer Software Restart. The framer and FDL sections are placed in the reset state as

long as this bit is set to 1. The framer’s parameter registers are not changed from their

programmed state. The FDL parameter registers are changed from their programmable

state. This bit must be cleared.

2

3

FRFRM

Framer Reframe. A 0-to-1 transition of this bit forces the receive framer into the loss of

frame alignment (LFA) state which forces a search of frame alignment. Subsequent

reframe commands must have this bit in the 0 state first.

TFM1

Transparent Framing Mode 1. A 1 forces the transmit framer to pass system data

unmodified to the line and the receive framer to pass line data unmodified to the system.

The receive framer is forced not to align to the input receive data.

DS1: register FRM_PR43 bit 2—bit 0 must be set to 000. The F bit is located in time slot

0, bit 7. The transmit framer extracts bit 7 of time slot 0 from RCHIDATA and places this

bit in the F-bit position of the transmit line data. The receive framer inserts the bit in the

F-bit position of the receive line data into time slot 0, bit 7 of the TCHIDATA.

CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data. Receive

line time slot 0 is inserted into time slot 0 of TCHIDATA.

4

TFM2

Transparent Framing Mode 2. A 1 forces the transmit framer to pass system data

unmodified to the line. The receive framer functions normally as programmed.

DS1: register FRM_PR43 bit 2—bit 0 must be set to 000. The F bit is located in

time slot 0, bit 7. The transmit framer extracts bit 7 of time slot 0 from RCHIDATA and

places this bit in the F-bit position of the transmit line data.

CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data.

5

SYSFSM

System Frame Sync Mask. A 1 masks the system frame synchronization signal in the

transmit framer section.

Note: The transmit framer must see at least one valid system synchronization pulse to

initialize its counts; afterwards, this bit may be set. For those applications that have jitter

on the transmit clock signal relative to the system clock signal, enable this bit so that the

jitter is isolated from the transmit framer.

6—7

—

Reserved. Write to 0.

192

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Automatic and Manual Transmission of the Remote Frame Alarm Control Register (FRM_PR27)

The default value of this register is 00 (hex).

Table 156. Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A Bit = 1

Control Register (FRM_PR27) (67B, C7B)

Bit

Symbol

Description

0

ARLFA

Automatic Remote Frame Alarm on LFA (ARLFA). A 1 transmits the remote frame

alarm to the line whenever the receive framer detects loss of frame alignment (RLFA).

1

AAB16LMFA Automatic A Bit on LMFA (CEPT only). A 1 transmits A = 1 to the line whenever the

receive framer detects loss of time slot 16 signaling multiframe alignment

(RTS16LMFA).

2

3

AAB0LMFA Automatic A Bit on LMFA (CEPT only). A 1 transmits A = 1 to the line whenever the

receive framer detects loss of time slot 0 multiframe alignment (RTS0LMFA).

ATMRX

Automatic A Bit on CRC-4 Multiframe Reframer Timer Expiration (CEPT only). A 1

transmits A = 1 to the line when the receive framer detects the expiration of either the

100 ms or 400 ms timers due to loss of multiframe alignment.

4

5

6

7

AARSa6_8 Automatic A Bit on RSa6_8 (CEPT only). A 1 transmits A = 1 to the line whenever the

receive framer detects the Sa6 = 1000 pattern.

AARSa6_C Automatic A Bit on RSa6_C (CEPT only). A 1 transmits A = 1 to the line whenever the

receive framer detects the Sa6 = 1100 pattern.

TJRFA

TRFA

Transmit D4 Japanese Remote Frame Alarm. A 1 transmits a valid Japanese remote

frame alarm for the D4 frame format.

Transmit Remote Frame Alarm. A 1 transmits a valid remote frame alarm for the corre-

sponding frame format.

Agere Systems Inc.

193

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Automatic and Manual Transmission of E Bit = 0 Control Register

The default value of this register is 00 (hex).

Table 157. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (67C; C7C)

Bit

Symbol

Description

0

SIS,

Si-Bit Source. In CEPT with NO CRC-4 mode, a 1 transmits TSiF and TSiNF in the Si

bit position to the line in FAS and NOT FAS, respectively. A 0, in non-CRC-4 mode,

transmits system Si data to the line transparently*.

T1E

Transmit One E = 0. In CEPT with CRC-4 mode, a 0 transmits E = TSiF in frame 13 and

E = TSiNF in frame 15. A 1 transmits one E bit = 0 for each write access to TSiF = 0 or

TSiNF = 0.

1

2

3

4

TSiF

Transmit Bit 1 in FAS. In CEPT with no CRC-4, this bit can be transmitted to the line in

bit 1 of the FAS. In CRC-4 mode, this bit is used for E-bit data in frame 13.

TSiNF

Transmit Bit 1 in NOT FAS. In CEPT with no CRC-4, this bit can be transmitted to the

line in bit 1 of the NOT FAS. In CRC-4 mode, this bit is used for E-bit data in frame 15.

ATERCRCE Automatic Transmit E Bit = 0 for Received CRC-4 Errored Events. A 1 transmits

E = 0 to the line whenever the receive framer detects a CRC-4 errored checksum.

ATELTS0MFA Automatic Transmit E Bit = 0 for Received Loss of CRC-4 Multiframe Alignment. A

1 transmits E = 0 to the line whenever the receive framer detects a loss of CRC-4 multi-

frame alignment condition.

5

ATERTX

Automatic Transmit E Bit = 0 on Expiration of CEPT CRC-4 Loss of Multiframe

Timer. A 1 transmits E = 0 to the line whenever the receive framer detects the expiration

of either the 100 ms or 400 ms timer due to the loss of CRC-4 multiframe alignment.

6—7

—

These Bits Are Zero.

* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001XXXXX

(binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.

194

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Sa4—Sa8 Source Register (FRM_PR29)

These bits contain the fixed transmit Sa bits and define the source of the Sa bits. The default value of this register

is 00 (hex).

Table 158. Sa4—Sa8 Source Register (FRM_PR29) (67D; C7D)

Bit

Symbol

Description

0—4

5—7

TSa4—TSa8

SaS5—SaS7

Transmit Sa4—Sa8 Bit.

Sa Source Control Bits[2:0].

Table 159. Sa Bits Source Control for Bit 5—Bit 7 in FRM_PR29

SaS7

SaS6

SaS5

Function

1

0

A single Sa bit, selected in register FRM_PR43, is sourced from either the external

transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDL-

HDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are sourced by this register

bit 0—bit 4 if enabled in register FRM_PR30, or transparently from the system inter-

face*.

1

0

1

x

A single Sa bit, selected in register FRM_PR43, is sourced from either the external

transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDL-

HDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are transmitted transpar-

ently from the system interface*.

A single Sa bit, selected in register FRM_PR43, is sourced from either the external

transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDL-

HDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are sourced from the trans-

mit Sa stack registers (FRM_PR31—FRM_PR40) if enabled in register FRM_PR30,

or transparently from the system interface*.

0

1

x

SLC-96 Mode. Transmit SLC-96 stack and the SLC-96 interrupts are enabled. The

SLC-96 FDL bits are sourced from the transmit SLC-96 stack, registers FRM_PR31—

FRM_PR40.

CEPT Mode. Transmit Sa stack and the Sa interrupts are enabled. The Sa bits are

sourced from the transmit Sa stack (FRM_PR31—FRM_PR40) if enabled in register

FRM_PR30, or transparently from the system interface*.

0

1

0

Sa[4:8] bits are transmitted from the system interface transparently through the

framer*.

Sa[4:8] bits are sourced by bit 0—bit 4 of this register if enabled in register

FRM_PR30, or transparently from the system interface*.

* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001XXXXX

(binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.

Agere Systems Inc.

195

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Sa4—Sa8 Control Register (FRM_PR30)

In conjunction with FRM_PR29 bit 5—bit 7, these bits define the source of the individual Sa4—Sa8 bits. The

default value of this register is 00 (hex).

Table 160. Sa4—Sa8 Control Register (FRM_PR30) (67E; C7E)

Bit

Symbol

Description

0—4

TESa4—TESa8 Transparent Enable Sa4—Sa8 Bit Mask. A 1 enables the transmission of the cor-

responding Sa bits from the Sa source register (FRM_PR29 bit 0—bit 4) or from the

transmit Sa stack. A 0 allows the corresponding Sa bit to be transmitted transpar-

ently from the system interface.

5—6

7

—

Reserved. Write to 0.

TDNF

Transmit Double NOTFAS System Time Slot. A 0 enables the transmission of the

FAS and NOTFAS on the TCHIDATA interface. A 1 enables the NOTFAS to be

transmitted twice on the TCHIDATA interface, and the received time slot 0 from the

RCHIDATA is assumed to carry NOTFAS data that is repeated twice.

196

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Sa Transmit Stack Register (FRM_PR31—FRM_PR40)

In CEPT frame format, registers FRM_PR31—FRM_PR40 are used to program the Sa bits in the CEPT multiframe

NOT-FAS words. If CRC-4 is enabled, this data is transmitted to the line synchronously to the CRC-4 multiframe.

The default value of these registers is 00 (hex).

Table 161. Sa Transmit Stack (FRM_PR31—FRM_PR40) ((67F—688); (C7F—C88))

Register

Bit 7

Sa4-1

Sa4-17

Sa5-1

Sa5-17

Sa6-1

Sa6-17

Sa7-1

Sa7-17

Sa8-1

Sa8-17

Bit 6

Sa4-3

Sa4-19

Sa5-3

Sa5-19

Sa6-3

Sa6-19

Sa7-3

Sa7-19

Sa8-3

Sa8-19

Bit 5

Sa4-5

Sa4-21

Sa5-5

Sa5-21

Sa6-5

Sa6-21

Sa7-5

Sa7-21

Sa8-5

Sa8-21

Bit 4

Sa4-7

Sa4-23

Sa5-7

Sa5-23

Sa6-7

Sa6-23

Sa7-7

Sa7-23

Sa8-7

Sa8-23

Bit 3

Sa4-9

Sa4-25

Sa5-9

Sa5-25

Sa6-9

Sa6-25

Sa7-9

Sa7-25

Sa8-9

Sa8-25

Bit 2

Bit 1

Bit 0

FRM_PR31

FRM_PR32

FRM_PR33

FRM_PR34

FRM_PR35

FRM_PR36

FRM_PR37

FRM_PR38

FRM_PR39

FRM_PR40

Sa4-11

Sa4-27

Sa5-11

Sa5-27

Sa6-11

Sa6-27

Sa7-11

Sa7-27

Sa8-11

Sa8-27

Sa4-13

Sa4-29

Sa5-13

Sa5-29

Sa6-13

Sa6-29

Sa7-13

Sa7-29

Sa8-13

Sa8-29

Sa4-15

Sa4-31

Sa5-15

Sa5-31

Sa6-15

Sa6-31

Sa7-15

Sa7-31

Sa8-15

Sa8-31

SLC-96 Transmit Stack (FRM_PR31—FRM_PR40)

In SLC-96 frame format, registers FRM_PR31—FRM_PR35 are used to source the transmit facility data link bits in

the FS bit positions. The default value of these registers is 00 (hex).

Table 162. SLC-96 Transmit Stack (FRM_PR31—FRM_PR40) ((67F—688); (C7F—C88))

Register

Bit 7

0

Bit 6

0

Bit 5

X-0

XC3

XC11

XA2

0

Bit 4

X-0

Bit 3

X-0

Bit 2

X-1

Bit 1

X-1

XC7

XM1

XS4

0

Bit 0

X-1

FRM_PR31

FRM_PR32

FRM_PR33

FRM_PR34

FRM_PR35

0

X-0

X-1

XC1

XC9

XM3

0

XC2

XC10

XA1

0

XC4

XC5

XC6

XC8

XSPB1 = 0 XSPB2 = 1 XSPB3 = 0

XM2

XSPB4=1

0

XS1

XS2

XS3

FRM_PR36—

FRM_PR40

0

In SLC-96 frame format, the bits in registers FRM_PR31—FRM_PR35 are transmitted using the format shown in

Table 163.

Table 163. Transmit SLC-96 FDL Format

FS= 000111000111 XC1 XC2 XC3 XC4 XC5 XC6 XC7 XC8 XC9 XC10 XC11 XSPB1 XSPB2 XSPB3 XM1 XM2 XM3 XA1 XA2 XS1 XS2 XS3 XS4 XSPB4

Agere Systems Inc.

197

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register (FRM_PR41)

The default value of this register is 00 (hex).

Table 164. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register (FRM_PR41) (689;

C89)

Bit

Symbol

Description

0—2 TTS16X0—TTS16X2 Transmit Time Slot 16 X0—X2 Bits. The content of these bits are written into

CEPT signaling multiframe time slot 16 X bits.

3

4

XS

X-Bit Source. A 1 enables the TTS16X[2:0] bits to be written into CEPT time slot

16 signaling multiframe frame. A 0 transmits the X bits transparently.

ALTTS16RMFA

Automatic Line Transmit Time Slot 16 Remote Multiframe Alarm. A 1

enables the transmission of CEPT time slot 16 signaling remote multiframe alarm

when the receive framer is in the loss of CEPT signaling (RTS16LMFA) state.

5

6

7

TLTS16RMFA

TLTS16AIS

—

Transmit Line Time Slot 16 Remote Multiframe Alarm. A 1 enables the trans-

mission of CEPT time slot 16 signaling remote multiframe alarm.

Transmit Line Time Slot 16 AIS. A 1 enables the transmission of CEPT time

slot 16 alarm indication signal.

Reserved. Write to 0.

Framer Exercise Register (FRM_PR42)

This register is used for exercising the device in a test mode. In normal operation, it and should be set to 00 (hex).

The default value of this register is 00 (hex).

Table 165. Framer Exercise Register (FRM_PR42) (68A; C8A)

Bit

Description

FEX0—FEX5

Framer Exercise Bits 0—5 (FEX0—FEX5). See Table 166.

FEX6

FEX7 Second Pulse Interval.

0

1

0

1

0

1

1 Second Pulse.

500 ms Pulse.

100 ms Pulse.

Reserved.

198

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Table 166. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (68A; C8A)

Exercise FEX5 FEX4 FEX3 FEX2 FEX1 FEX0

Type

Exercise

Framing

Format

Facility

Status

0

1

0

1

Line format violation

All

CRC checksum error

ESF or CEPT

D4 or ESF

All

Receive remote frame alarm

Alarm indication signal detection

Loss of frame alignment

Receive remote frame alarm

Time slot 0 1-bit shift

CEPT

Japanese D4

CEPT

0

1

0

1

0

1

Transmit corrupt CRC

ESF & CEPT

Frame-bit error & loss of frame align- All

ment

Loss of time slot 16 multiframe align- CEPT

ment

Remote frame alarm

CRC bit errors

D4 & DDS

ESF & CEPT

0

1

0

1

Frame-bit errors

All

Frame-bit errors & loss of frame

alignment

Loss of time slot 16 multiframe align- CEPT

ment

0

1

0

1

Frame-bit error & loss of frame align- All

ment

Change of frame alignment

ESF, DDS &

CEPT

Loss of time slot 16 multiframe align- CEPT

ment

Excessive CRC checksum errors

ESF & CEPT

Agere Systems Inc.

199

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Table 166. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (68A; C8A) (continued)

Exercise Type FEX5 FEX4 FEX3 FEX2 FEX1 FEX0

Exercise

Framing

Format

Performance

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Errored second

All

Bursty errored second

Severely errored second

Severely errored second count

Unavailable state

Factory test

Increment status counters

SR6—SR14

0

1

0

1

Increment status counters

SR6—SR14

Status Counters

1

0

X

0

1

0

1

0

1

0

1

0

1

0

1

CRC error counter

All

Errored event counter

Errored second counter

Severely errored second counter

Unavailable second counter

Line format violation counter

Frame bit error counter

Reserved

—

All other combinations

—

200

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43)

The default value of this register is 00 (hex).

Table 167. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (68B; C8B)

Bit

Symbol

Description

0—2 STS0—STS2 In DS1 mode, bit 0—bit 2 program the positions of the stuffed time slots on the CHI. The

content of the stuffed time slot can be programmed using register FRM_PR23.

Bits

210

000 = SDDDSDDDSDDDSDDDSDDDSDDDSDDDSDDD

001 = DSDDDSDDDSDDDSDDDSDDDSDDDSDDDSDD

010 = DDSDDDSDDDSDDDSDDDSDDDSDDDSDDDSD

011 = DDDSDDDSDDDSDDDSDDDSDDDSDDDSDDDS

100 = DDDDDDDDDDDDDDDDDDDDDDDDSSSSSSSS

SaFDL0—

SaFDL2

In CEPT mode, bit 0—bit 2 program the Sa bit source of the facility data link.

Bits

210

000: Sa4 = FDL

001: Sa5 = FDL

010: Sa6 = FDL

011: Sa7 = FDL

100: Sa8 = FDL

In both DS1 and CEPT modes, only the bit values shown above may be selected.

3

SSC

—

SLC-96 Signaling Control (DS1 Only). A 1 enables the SLC-96 9-state signaling mode.

A 0 enables 16-state signaling in the SLC-96 framing mode.

4—7

Reserved. Write to 0.

Agere Systems Inc.

201

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Signaling Mode Register (FRM_PR44)

This register programs various signaling modes. The default value is 00 (hex).

Table 168. Signaling Mode Register (FRM_PR44) (68C; C8C)

Bit

Symbol

Description

0

TSIG

Transparent Signaling. A 0 enables signaling information to be inserted into and

extracted from the data stream. The signaling source is either the signaling registers or

the system data (in the associated signaling mode). In DS1 modes, the choice of data or

voice channels assignment for each channel is a function of the programming of the F

and G bits in the transmit signaling registers. A 1 enables data to pass through the

device transparently. All channels are treated as data channels.

1

2

STOMP

Stomp Mode. A 0 allows the received signaling bits to pass through the receive signal-

ing circuit unmodified. In DS1 robbed-bit signaling modes, a 1 enables the receive sig-

naling circuit to replace (in those time slots programmed for signaling) all signaling bits

(in the receive line bit stream) with a 1, after extracting the valid signaling information. In

CEPT time slot 16 signaling modes, a 1 enables the received signaling circuit substitute

of the signaling combination of ABCD = 0000 to ABCD = 1111.

ASM

RSI

Associated Signaling Mode. A 1 enables the associate signaling mode which config-

ures the CHI to carry both data and its associated signaling information. Enabling this

mode must be in conjunction with the programming of the CHI data rate to 4.096 Mbits/s

or 8.192 Mbit/s. Each channel consists of 16 bits where 8 bits are data and the remaining

8 bits are signaling information.

3

4

Receive Signaling Inhibit. A 1 inhibits updating of the receive signaling buffer.

MOS_CCS Message-Oriented Signaling or Common Channel Signaling. DS1: A 1 enables the

channel 24 message-oriented signaling mode. CEPT: A 1 enables the time slot 16 com-

mon channel signaling mode.

5

IRSM

IRSM Mode (CEPT Only). A 1 enables the CEPT IRSM mode.

TSR-ASM

TSR-ASM Mode (DS1 Only). In the DS1 mode, setting this bit and FRM_PR44 bit 2

(ASM) to 1 enables the transmit signaling register F and G bits to define the robbed-bit

signaling format while the ABCD bit information is extracted from the CHI interface. The

F and G bits are copied to the receive signaling block and are used to extract the signal-

ing information from the receive line.

6

7

ASTSAIS

TCSS

Automatic System Transmit Signaling AIS (CEPT Only). A 1 transmits AIS in system

time slot 16 during receive loss of time slot 16 signaling multiframe alignment state.

Transmit CEPT System Signaling Squelch (CEPT Only). AIS is transmitted in time

slot 16 of the transmit system data.

202

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

CHI Common Control Register (FRM_PR45)

These bits define the common attributes of the CHI for TCHIDATA, TCHIDATAB, RCHIDATA, and RCHDATAB.

The default value of this register is 00 (hex).

Table 169. CHI Common Control Register (FRM_PR45) (68D; C8D)

Bit

Symbol

Description

0

HFLF

High-Frequency/Low-Frequency PLLCK Clock Mode. A 0 enables the low-frequency

PLLCK mode for the divide down circuit in the internal phase-lock loop section (DS1

PLLCK = 1.544 MHz; CEPT PLLCK = 2.048 MHz). The divide down circuit will produce

an 8 kHz signal on DIV-PLLCK, pin 6 and pin 32. A 1 enables the high-frequency PLLCK

mode for the divide down circuit in the internal phase-lock loop section (DS1: PLLCK =

6.176 (4 x 1.544) MHz; CEPT: 8.192 (4 x 2.048) MHz). The divide down circuit will pro-

duce a 32 kHz signal on DIV-PLLCK.

1

CMS

Concentration Highway Clock Mode. A 0 enables the CHI clock frequency and CHI

data rate to be equal. A 1 enables CHI clock frequency to be twice the CHI data rate.

This control bit affects both the transmit and receive interfaces.

2—3

CDRS0—

CDRS1

Concentration Highway Interface Data Rate Select.

Bits

2 3

0 0

0 1

1 0

1 1

CHI Data Rate

2.048 Mbits/s

4.096 Mbits/s

8.192 Mbits/s

Reserved

4

CHIMM

Concentration Highway Master Mode. A 0 enables external system’s frame synchroni-

zation signal (TCHIFS) to drive the transmit path of the framer’s concentration highway

interface. A 1 enables the framer’s transmit concentration interface to generate a system

frame synchronization signal derived from the receive line interface. The framer’s system

frame synchronization signal is generated on the TCHIFS output pin. Applications using

the receive line clock as the reference clock signal of the system are recommended to

enable this mode and use the TCHIFS signal generated by the framer. The receive CHI

path is not affected by this mode.

5—6

7

—

Reserved. Write to 0.

HWYEN

Highway Enable. A 1 in this bit position enables transmission to the concentration high-

way. This allows the T7633 to be fully configured before transmission to the highway. A 0

forces the idle code as defined in register FRM_PR22 to be transmitted to the line in all

payload time slots and the Transmit CHI pin is forced to a high-impedance state for all

CHI transmitted time slots.

Agere Systems Inc.

203

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

CHI Common Control Register (FRM_PR46)

This register defines the common attributes of the transmit and receive CHI. The default value is 00 (hex).

Table 170. CHI Common Control Register (FRM_PR46) (68E; C8E)

Bit

Symbol

Description

0—2

TOFF0—

TOFF2

Transmit CHI Bit Offset. These 3 bits define the bit offset from TCHIFS for each trans-

mit time slot.

CMS = 0: the offset is the number of TCHICK clock periods by which the first bit is

delayed from TCHIFS.

CMS = 1: the offset is twice the number of TCHICK clock periods by which the first bit is

delayed from TCHIFS.

3

TFE

Transmit Frame Clock Edge. A 0 (1) enables the falling (rising) edge of TCHICK to

latch in the frame synchronization signal, TCHIFS.

4—6

ROFF0—

ROFF2

Receive CHI Bit Offset. These 3 bits define the bit offset from RCHIFS for each

received time slot.

CMS = 0: the offset is the number of RCHICK clock periods by which the first bit is

delayed from RCHIFS.

CMS = 1: the offset is twice the number of RCHICK clock periods by which the first bit is

delayed from RCHIFS.

7

RFE

Received Frame Clock Edge. A 0 (1) enables the falling (rising) edge of RCHICK to

latch in the frame synchronization signal, RCHIFS.

204

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

CHI Transmit Control Register (FRM_PR47)

The default value of this register is 00 (hex).

Table 171. CHI Transmit Control Register (FRM_PR47) (68F; C8F)

Bit

Symbol

Description

0—5

TBYOFF0— Transmit Byte Offset. Combined with FRM_PR65 bit 0 (TBYOFF6), these 6 bits define

TBYOFF5

TCE

the byte offset from TCHIFS to the beginning of the next transmit CHI frame on TCHI-

DATA.

6

7

Transmitter Clock Edge. A 1 (0) enables the rising (falling) edge of TCHICK to clock out

data on TCHIDATA.

TLBIT

Transmit Least Significant Bit First. A 0 forces the most significant bit of each time slot

(bit 0) to be transmitted first. A 1 forces the least significant bit of each time slot to be

transmitted first.

CHI Receive Control Register (FRM_PR48)

The default value of this register is 00 (hex).

Table 172. CHI Receive Control Register (FRM_PR48) (690; C90)

Bit

Symbol

Description

0—5

RBYOFF0— Receiver Byte Offset. Combined with FRM_PR66 bit 0 (RBYOFF6), these 6 bits define

RBYOFF5 the byte offset from RCHIFS to the beginning of the next receive CHI frame on RCHI-

DATA.

6

7

RCE

Receiver Clock Edge. A 1 (0) enables the rising (falling) edge of RCHICK to latch

data on RCHIDATA.

RLBIT

Receive Least Significant Bit First. A 0 forces bit 0 of the time slot as the most signifi-

cant bit of the time slot. A 1 forces bit 7 of the time slot as the most significant bit of the

time slot.

Agere Systems Inc.

205

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52)

These four registers define which transmit CHI time slots are enabled. A 1 enables the TCHIDATA or TCHIDATAB

time slot. A 0 forces the CHI transmit highway time slot to be 3-stated. The default value of this register is 00 (hex).

Table 173. CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52) ((691—694); (C91—C94))

Register

Bit

Symbol

Description

FRM_PR49

FRM_PR50

FRM_PR51

FRM_PR52

7—0 TTSE31—TTSE24 Transmit Time-Slot Enable Bits 31—24.

7—0 TTSE23—TTSE16 Transmit Time-Slot Enable Bits 23—16.

7—0

TTSE15—TTSE8 Transmit Time-Slot Enable Bits 15—8.

TTSE7—TTSE0 Transmit Time-Slot Enable Bits 7—0.

CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56)

These four registers define which receive CHI time slots are enabled. A 1 enables the RCHIDATA or RCHI-

DATAB time slots. A 0 disables the time slot and transmits the programmable idle code of register FRM_PR22 to

the line in the corresponding time slot. The default value of this register is FF (hex).

Table 174. CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56) ((695—698); (C95—C98))

Register

Bit

Symbol

Description

FRM_PR53

7—0

RTSE31—

RTSE24

Receive Time-Slot Enable Bits 31—24.

FRM_PR54

7—0

RTSE23—

RTSE16

Receive Time-Slot Enable Bits 23—16.

FRM_PR55

FRM_PR56

7—0 RTSE15—RTSE8 Receive Time-Slot Enable Bits 15—8.

7—0 RTSE7—RTSE0 Receive Time-Slot Enable Bits 7—0.

CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60)

These four registers define which transmit CHI highway TCHIDATA or TCHIDATAB contains valid data for the

active time slot. A 0 enables TCHIDATA, and a 1 enables TCHIDATAB. The default value of this register is

00 (hex).

Table 175. CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60) ((699—69C); (C99—C9C))

Register

Bit

Symbol

Description

FRM_PR57

FRM_PR58

FRM_PR59

FRM_PR60

7—0

THS31—THS24 Transmit Highway Select Bits 31—24.

THS23—THS16 Transmit Highway Select Bits 23—16.

THS15—THS8

THS7—THS0

Transmit Highway Select Bits 15—8.

Transmit Highway Select Bits 7—0.

206

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64)

These four registers define which receive CHI highway RCHIDATA or RCHIDATAB contains valid data for the

active time slot. A 0 enables RCHIDATA and a 1 enables RCHIDATAB. The default value of these registers is 00

(hex).

Table 176. CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64) ((69D—6A0); (C9D—CA0))

Register

Bit

Symbol

Description

FRM_PR61

FRM_PR62

FRM_PR63

FRM_PR64

7—0

RHS31—RHS24 Receive Highway Select Bits 31—24.

RHS23—RHS16 Receive Highway Select Bits 23—16.

RHS15—RHS8 Receive Highway Select Bits 15—8.

RHS7—RHS0

Receive Highway Select Bits 7—0.

CHI Transmit Control Register (FRM_PR65)

The default value of this register is 00 (hex).

Table 177. CHI Transmit Control Register (FRM_PR65) (6A1; CA1)

Bit

Symbol

Description

0

TBYOFF6

Transmit CHI 64-Byte Offset. A 1 enables a 64-byte offset from TCHIFS to the begin-

ning of the next transmit CHI frame on TCHIDATA. A 0 enables a 0-byte offset (if bit 0—

bit 5 of FRM_PR47 = 0). Combing bit 0—bit 5 of FRM_PR47 with this bit allows pro-

gramming the byte offset from 0—127.

1

TCHIDTS

—

Transmit CHI Double Time-Slot Mode. A 1 enables the transmit CHI double time-slot

mode. In this mode, the TCHI clock runs at twice the rate of TCHIDATA.

2—7

Reserved. Write to 0.

CHI Receive Control Register (FRM_PR66)

The default value of this register is 00 (hex).

Table 178. CHI Receive Control Register (FRM_PR66) (6A2; CA2)

Bit

Symbol

Description

0

RBYOFF6

Receive CHI 64-Byte Offset. A 1 enables a 64-byte offset from RCHIFS to the begin-

ning of the next receive CHI frame on RCHIDATA. A 0 enables a 0-byte offset (if bit 0—

bit 5 of FRM_PR48 = 0). Combing bit 0—bit 5 of FRM_PR48 with this bit allows pro-

gramming the byte offset from 0—127.

1

RCHIDTS

—

Receive CHI Double Time-Slot Mode. A 1 enables the transmit CHI double time-slot

mode. In this mode, the RCHI clock runs at twice the rate of RCHIDATA.

2—7

Reserved. Write to 0.

Reserved Parameter/Control Registers

Registers FRM_PR67 and FRM_PR68, addresses 6A3 and 6A4 or CA3 and CA4, are reserved. Write these regis-

ters to 0.

Agere Systems Inc.

207

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Auxiliary Pattern Generator Control Register (FRM_PR69)

The following register programs the auxiliary pattern generator in the transmit framer. The default value of this reg-

ister is 00 (hex).

Table 179. Auxiliary Pattern Generator Control Register (FRM_PR69) (6A5; CA5)*

Bit

0

Symbol

ITD

Description

Invert Transmit Data. Setting this bit to 1 inverts the transmitted pattern.

1

TPEI

Test Pattern Error Insertion. Toggling this bit from a 0 to a 1 inserts a single bit error in

the transmitted test pattern.

2

3

GBLKSEL

Generator Block Select. Setting this bit to 1 enables the generation of test patterns in

this register.

GFRMSEL Generator Frame Test Pattern. Setting this bit to 1 results in the generation of an

unframed pattern. A 0 results in a framed pattern (T1 and CEPT).

4—7

GPTRN0— Generator Pattern Select. These 4 bits select which random pattern is to be transmit-

GPTRN3

ted.

Bits

7

0

1

6

5

0

1

0

1

0

1

0

4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MARK (all ones) (AIS)

QRSS (2²⁰– 1 with zero suppression)

2⁵– 1

63 (2⁶– 1)

511 (2⁹– 1) (V.52)

2⁹– 1

2047 (2¹¹– 1) (O.151)

2

¹¹– 1 (reversed)

¹⁵– 1 (O.151)

²⁰– 1 (V.57)

²⁰– 1 (CB113/CB114)

²³– 1 (O.151)

1:1 (alternating)

* To generate test pattern signals using this register, register FRM_PR20 must be set to 00 (hex).

208

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Pattern Detector Control Register (FRM_PR70)

The following register programs the pattern detector in the receive framer. The default value of this register is 00

(hex).

Table 180. Pattern Detector Control Register (FRM_PR70) (6A6; CA6)*

Bit

Symbol

Description

0

IRD

Invert Receive Data. Setting this bit to 1 enables the pattern detector to detect the

inverse of the selected pattern.

1

—

Reserved. Write to 0.

2

DBLKSEL

Detector Block Select. Setting this bit to 1 enables the detection of test patterns in this

register.

3

DUFTP

Detect Unframed Test Pattern. Setting this bit to 1 results in the search for an unframed

pattern. A 0 results in a search for a framed pattern (T1 and CEPT).

4—7

DPTRN0— Detector Pattern Select. These 4 bits select which random pattern is to be detected.

DPTRN3 Bits

7

0

1

6

5

0

1

0

1

0

1

0

4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MARK (all ones) (AIS)

QRSS (2²⁰– 1 with zero suppression)

2⁵– 1

63 (2⁶– 1)

511 (2⁹– 1) (V.52)

2⁹– 1

2047 (2¹¹– 1) (O.151)

2

¹¹– 1 (reversed)

¹⁵– 1 (O.151)

²⁰– 1 (V.57)

²⁰– 1 (CB113/CB114)

²³– 1 (O.151)

1:1 (alternating)

* To generate/detect test pattern signals using this register, register FRM_PR20 must be set to 00 (hex).

Agere Systems Inc.

209

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Framer Register Architecture (continued)

Framer Parameter/Control Registers (continued)

Transmit Signaling Registers: DS1 Format (FRM_TSR0—FRM_TSR23)

These registers program the transmit signaling registers for the DS1 and CEPT mode. The default value of these

registers is 00 (hex).

Table 181. Transmit Signaling Registers: DS1 Format (FRM_TSR0—FRM_TSR23) ((6E0—6F7); (CE0—CF7))

Transmit Signal Registers

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DS1 Transmit Signaling Registers (0—23)

P

X

G

0

F

0

X

D

C

B

A

ESF Format: Voice Channel with 16-State Signaling

SLC-96: 9-State Signaling (depending on the setting in

register FRM_PR43)

Voice Channel with 4-State Signaling

Voice Channel with 2-State Signaling

Data Channel (no signaling)

X

0

1

0

X

B

A

X

A

X

Transmit Signaling Registers: CEPT Format (FRM_TSR0—FRM_TSR31)

Table 182. Transmit Signaling Registers: CEPT Format (FRM_TSR0—FRM_TSR31) ((6E0—6FF); (CE0—

CFF))

Transmit Signal Registers

Bit 7

Bit 6—5

Bit 4*

Bit 3

Bit 2

Bit 1

Bit 0

FRM_TSR0: IRSM Mode

Only

X

E0

X

FRM_TSR1—FRM_TSR15

P

X

E[1:15]

E16

D[1:15]

X

C[1:15]

X

B[1:15]

B

A[1:15]

A

FRM_TSR16: IRSM Mode

Only

FRM_TSR17—FRM_TSR31

P

X

E[17:31]

D[17:31]

C[17:31]

B[17:31]

A[17:31]

* This bit contains the IRSM information in time slot 0. In PCS0 or PCS1 signaling mode, this bit is undefined.

210

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

FDL Register Architecture

REGBANK5 and REGBANK7 contain the status and programmable control registers for the facility data link chan-

nels FDL1 and FDL2, respectively. The base address for REGBANK5 is 400 (hex) and for REGBANK7 is

E00 (hex). Within these register banks, the bit map is identical for both FDL1 and FDL2.

The register bank architecture for FDL1 and FDL2 is shown in Table 183. The register bank consists of 8-bit regis-

ters classified as either (programmable) parameter registers or status registers. Default values are shown in paren-

theses.

Table 183. FDL Register Set (800—80E); (E00—E0E)

FDL Register

[Address (hex)]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FRANSIT3 FRANSIT2

FRANSIT1

(1)

FRANSIT0 Reserved

Reserved

(0)

FLAGS

(0)

FDINT

(0)

FDL_PR0[800;E00]

(1)

(0)

FTPRM

(0)

FRPF

(0)

FTR

(0)

FRR

(0)

FTE

(0)

FRE

(0)

FLLB

(0)

FRLB

(0)

FDL_PR1[801;E01]

FDL_PR2[802;E02]

FDL_PR3[803;E03]

FDL_PR4[804;E04]

FDL_PR5[805;E05]

FDL_PR6[806;E06]

FDL_PR8[808;E08]

FDL_PR9[809;E09]

FDL_PR10[80A;E0A]

FTBCRC

(0)

FRIIE

(0)

FROVIE

(0)

FREOFIE

(0)

FRFIE

(0)

FTUNDIE

(0)

FTEIE

(0)

FTDIE

(0)

FTFC

(0)

FTABT

(0)

FTIL5

(0)

FTIL4

(0)

FTIL3

(0)

FTIL2

(0)

FTIL1

(0)

FTIL0

(0)

FTD7

(0)

FTD6

(0)

FTD5

(0)

FTD4

(0)

FTD3

(0)

FTD2

(0)

FTD1

(0)

FTD0

(0)

FTIC7

(0)

FTIC6

(0)

FTIC5

(0)

FTIC4

(0)

FTIC3

(0)

FTIC2

(0)

FTIC1

(0)

FTIC0

(0)

FRANSIE

(0)

AFDLBPM

(0)

FRIL5

(0)

FRIL4

(0)

FRIL3

(0)

FRIL2

(0)

FRIL1

(0)

FRIL0

(0)

FRMC7

(0)

FRMC6

(0)

FRMC5

(0)

FRMC4

(0)

FRMC3

(0)

FRMC2

(0)

FRMC1

(0)

FRMC0

(0)

Reserved

(0)

FTM

(0)

FMATCH

(0)

FALOCT

(0)

FMSTAT

(0)

FOCTOF2

(0)

FOCTOF1 FOCTOF0

(0)

FTANSI

(0)

Reserved

(0)

FTANSI5

(0)

FTANSI4

(0)

FTANSI3

(0)

FTANSI2

(0)

FTANSI1

(0)

FTANSI0

(0)

FDL_SR0[80B;E0B]

FDL_SR1[80C;E0C]

FDL_SR2[80D;E0D]

FDL_SR3[80E;E0E]

FDL_SR4[807;E0F]

FRANSI

FTED

FREOF

0

FRIL

FTQS6

FRQS6

0

FROUERUN

FTQS5

FRQS5

X5

FREOF

FTQS4

FRQS4

X4

FRF

FTQS3

FRQS3

X3

FTUNDABT

FTQS2

FRQS2

X2

FTE77

FTQS1

FRQS1

X1

FTDONE

FTQS0

FRQS0

X0

FRD7

FRD6

FRD5

FRD4

FRD3

FRD2

FRD1

FRD0

Agere Systems Inc.

211

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

FDL Parameter/Control Registers (800—80E; E00—E0E)

These registers define the mode configuration of each framer unit. These registers are initially set to a default value

upon a hardware reset. These registers are all read/write registers.

Default states of all bits in this register group are also indicated in the parameter/control register map.

Table 184. FDL Configuration Control Register (FDL_PR0) (800; E00)

Bit

Symbol

Description

0

FDINT

Dynamic Interrupt. FDINT = 0 causes multiple occurrences of the same event to gener-

ate a single interrupt before the interrupt bit is cleared by reading register FDL_SR0.

FDINT = 1 causes multiple interrupts to be generated. This bit should normally be set to

0.

1

FLAGS

Flags. FLAGS = 0 forces the transmission of the idle pattern (11111111) in the absence

of transmit FDL information. FLAGS = 1 forces the transmission of the flag pattern

(01111110) in the absence of transmit FDL information. This bit resets to 0.

2—3

—

Reserved. Write to 0.

4—7 FRANSIT0— Receive ANSI Bit Code Threshold. These bits define the number of ESF ANSI bit

FRANSIT3 codes needed for indicating a valid code. The default is ten (1010 (binary))*.

* The FRANSIT bits (FDL_PR0 bits 4—7) must be changed only following an FDL reset or when the FDL is idle.

Table 185. FDL Control Register (FDL_PR1) (801; E01)

Bit

Symbol

Description

0

FRLB

Remote Loopback. FRLB = 1 loops the received facility data back to the transmit facility

data interface. This bit resets to 0.

1

FLLB

Local Loopback. FLLB = 1 loops transmit facility data back to the receive facility data

link interface. The receive facility data link information from the framer interface is

ignored. This bit resets to 0.

2

3

4

FRE

FTE

FRR

FDL Receiver Enable. FRE = 1 activates the FDL receiver. FRE = 0 forces the FDL

receiver into an inactive state. This bit resets to 0.

FDL Transmitter Enable. FTE = 1 activates the FDL transmitter. FTE = 0 forces the FDL

transmitter into an inactive state. This bit resets to 0.

FDL Receiver Reset. FRR = 1 generates an internal pulse that resets the FDL receiver.

The FDL receiver FIFO and related circuitry are cleared. The FREOF, FRF, FRIDL, and

OVERRUN interrupts are cleared. This bit resets to 0.

5

FTR

FDL Transmitter Reset. FTR = 1 generates an internal pulse that resets the FDL trans-

mitter. The FDL transmit FIFO and related circuitry are cleared. The FTUNDABT bit is

cleared, and the FTEM interrupt is set; the FTDONE bit is forced to 0 in the HDLC mode

and forced to 1 in the transparent mode. This bit resets to 0.

6

7

FRPF

FDL Receive PRM Frames. FRPF = 1 allows the receive FDL unit to write the entire

receive performance report message including the frame header and CRC data into the

receive FDL FIFO. This bit resets to 0.

FTPRM

Transmit PRM Enable. When this bit is set, the receive framer will write into the transmit

FDL FIFO its performance report message data. The current second of this data is

stored in the receive framer’s status registers. The receive framer’s PRM is transmitted

once per second. The PRM is followed by either idles or flags transmitted after the PRM.

When this bit is 0, the transmit FDL expects data from the microprocessor interface.

212

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

FDL Parameter/Control Registers (800—80E; E00—E0E) (continued)

Table 186. FDL Interrupt Mask Control Register (FDL_PR2) (802; E02)

Bit

Symbol

Description

0

FTDIE

FDL Transmit-Done Interrupt Enable. When this interrupt enable bit is set, an

INTERRUPT pin transition is generated after the last bit of the closing flag or abort

sequence is sent. In the transparent mode (register FDL_PR9 bit 6 = 1), an INTERRUPT

pin transition is generated when the transmit FIFO is completely empty. FTDIE is cleared

upon reset.

1

2

3

4

5

6

7

FTEIE

FTUNDIE

FRFIE

FDL Transmitter-Empty Interrupt Enable. When this interrupt-enable bit is set, an

INTERRUPT pin transition is generated when the transmit FIFO has reached the pro-

grammed empty level (see register FDL_PR3). FTEIE is cleared upon reset.

FDL Transmit Underrun Interrupt Enable. When this interrupt-enable bit is set, an

INTERRUPT pin transition is generated when the transmit FIFO has underrun. FTUNDIE

is cleared upon reset and is not used in the transparent mode.

FDL Receiver-Full Interrupt Enable. When this interrupt-enable bit is set, an

INTERRUPT pin transition is generated when the receive FIFO has reached the pro-

grammed full level (see register FDL_PR6). FRFIE is cleared upon reset.

FREOFIE

FROVIE

FRIIE

FDL Receive End-of-Frame Interrupt Enable. When this interrupt-enable bit is set, an

INTERRUPT pin transition is generated when an end-of-frame is detected by the FDL

receiver. FREOFIE is cleared upon reset and is not used in the transparent mode.

FDL Receiver Overrun Interrupt Enable. When this interrupt-enable bit is set, an

INTERRUPT pin transition is generated when the receive FIFO overruns. FROVIE is

cleared upon reset.

FDL Receiver Idle-Interrupt Enable. When this interrupt-enable bit is set, an

INTERRUPT pin transition is generated when the receiver enters the idle state. FRIIR is

cleared upon reset and is not used in the transparent mode.

FTBCRC

FDL Transmit Bad CRC. Setting this bit to 1 forces bad CRCs to be sent on all transmit-

ted frames (for test purposes) until the FTBCRC bit is cleared to 0.

Agere Systems Inc.

213

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

FDL Parameter/Control Registers (800—80E; E00—E0E) (continued)

Table 187. FDL Transmitter Configuration Control Register (FDL_PR3) (803; E03)

Bit

Symbol

Description

0—5 FTIL0—FTIL5 FDL Transmitter Interrupt Level. These bits specify the minimum number of empty

positions in the transmit FIFO which triggers a transmitter-empty (FTEM) interrupt.

Encoding is in binary; bit 0 is the least significant bit. A code of 001010 will generate an

interrupt when the transmit FIFO has ten or more empty locations. The code 000000

generates an interrupt when the transmit FIFO is empty. The number of empty transmit

FIFO locations is obtained by reading the transmit FDL status register FDL_SR1.

6¹

FTABT

FDL Transmitter Abort. FTABT = 1 forces the transmit FDL unit to abort the frame at the

last user data byte waiting for transmission. When the transmitter reads the byte tagged

with FTABT, the abort sequence (01111111) is transmitted in its place. A full byte is guar-

anteed to be transmitted. Once set for a specific data byte, the internal FTABT status

cannot be cleared by writing to this bit. Clearing this bit has no effect on a previously writ-

ten FTABT. The last value written to FTABT is available for reading.

7¹

FTFC

FDL Transmitter Frame Complete. FTFC = 1 forces the transmit FDL unit to terminate

the frame normally after the last user data byte is written to the transmit FIFO. The CRC

sequence and a closing flag are appended. FTFC should be set to 1 within 1 ms of writ-

ing the last byte of the frame in the transmit FIFO. When the transmit FIFO is empty, writ-

ing two data bytes to the FIFO before setting FTCF provides a minimum of 1 ms to write

FTFC = 1. Once set for a specific data byte, the internal FTFC status bit cannot be

cleared by writing to this bit. Clearing this bit has no effect on a previously written FTFC.

The last value written to FTFC is available for reading.

1. Do not set FTABT = 1 and FTFC = 1 at the same time.

Table 188. FDL Transmitter FIFO Register (FDL_PR4) (804; E04)

Bit

Symbol

Description

0—7 FTD0—FTD7 FDL Transmit Data. The user data to be transmitted via the FDL block are loaded

through this register.

Table 189. FDL Transmitter Mask Register (FDL_PR5) (805; E05)

Bit

Symbol

Description

0—7

FTIC0—

FTIC7

FDL Transmitter Idle Character. This character is used only in transparent mode (regis-

ter FDL_PR9 bit 6 = 1). When the pattern match bit (register FDL_PR9 bit 5) is set to 1,

the FDL transmit unit sends this character whenever the transmit FIFO is empty. The

default is to send the 1s idle character, but any character can be programmed by the

user.

214

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

FDL Parameter/Control Registers (800—80E; E00—E0E) (continued)

Table 190. FDL Receiver Interrupt Level Control Register (FDL_PR6) (806; E06)

Bit

Symbol

Description

0—5 FRIL0—FRIL5 FDL Receive Interrupt Level. Bit 0—bit 5 define receiver FIFO full threshold value that

will generate the corresponding FRF interrupt. FRIL = 000000 forces the receive FDL

FIFO to generate an interrupt when the receive FIFO is completely full. FRIL = 001111

will force the receive FDL FIFO to generate an interrupt when the receive FIFO contains

15 or more bytes.

6

7

—

Reserved. Write to 0.

FRANSIE

FDL Receiver ANSI Bit Codes Interrupt Enable. If this bit is set to 1, an interrupt pin

condition is generated whenever a valid ANSI code is received.

Table 191. FDL Register FDL_PR7

Bit

Symbol

Description

0—7

—

Reserved.

Table 192. FDL Receiver Match Character Register (FDL_PR8) (808; E08)

Bit

Symbol

Description

0—7

FRMC0—

FRMC7

Receiver FDL Match Character. This character is used only in transparent mode (regis-

ter FDL_PR9 bit 6 = 1). When the pattern match bit (register FDL_PR9 bit 5) is set to 1,

the receive FDL unit searches the incoming bit stream for the receiver match character.

Data is loaded into the receive FIFO only after this character has been identified. The

byte identified as matching the receiver match character is the first byte loaded into the

receive FIFO. The default is to search for a flag, but any character can be programmed

by the user. The search for the receiver match character can be in a sliding window fash-

ion (register FDL_PR9 bit 4 = 0) or only on byte boundaries (register FDL_PR9 bit 4 = 1).

Agere Systems Inc.

215

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

FDL Parameter/Control Registers (800—80E; E00—E0E) (continued)

Table 193. FDL Transparent Control Register (FDL_PR9) (809; E09)

Bit

Symbol

Description

0—2

FOCTOF0— FDL Octet Offset (Read Only). These bits record the offset relative to the octet bound-

FOCTOF2

FMSTAT

ary when the receive character was matched. The FOCTOF bits are valid when register

FDL_PR9 bit 3 (FMSTAT) is set to 1. A value of 111 (binary) indicates byte alignment.

3

Match Status (Read Only). When this bit is set to 1 by the receive FDL unit, the receiver

match character has been recognized. The octet offset status bits (FDL_PR9 bit[2:0])

indicates the offset relative to the octet boundary* at which the receive character was

matched. If no match is being performed (register FDL_PR9 bit 5 = 0), the FMSTAT bit is

set to 1 automatically when the first byte is received, and the octet offset status bits (reg-

ister FDL_PR9 bit 0—bit 2) are set to 111 (binary).

4

5

FALOCT

FMATCH

Frame-Sync Align. When this bit is set to 1, the receive FDL unit searches for the

receive match character (FDL-PR8) only on an octet boundary. When this bit is 0, the

receive FDL unit searches for the receive match character in a sliding window fashion.

Pattern Match. FMATCH affects both the transmitter and receiver. When this bit is set to

1, the FDL does not load data into the receive FIFO until the receive match character

programmed in register FDL_PR8 has been detected. The search for the receive match

character is in a sliding window fashion if register FDL_PR9 bit 4 is 0, or only on octet

boundaries if register FDL_PR9 bit 4 is set to 1. When this bit is 0, the receive FDL unit

loads the matched byte and all subsequent data directly into the receive FIFO. On the

transmit side, when this bit is set to 1 the transmitter sends the transmit idle character

programmed into register FDL_PR5 when the transmit FIFO has no user data. The

default idle is to transmit the HDLC 1s idle character (FF hexadecimal); however, any

value can be used by programming the transmit idle character register FDL_PR5. If this

bit is 0, the transmitter sends 1s idle characters when the transmit FIFO is empty.

6

7

FTM

—

FDL Transparent Mode. When this bit is set to 1, the FDL unit performs no HDLC pro-

cessing on incoming or outgoing data.

Reserved. Write to 0.

* The octet boundary is relative the first receive clock edge after the receiver has been enabled (ENR, FDL_PR1 bit 2 = 1).

Table 194. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (80A; E0A)

Bit

Symbol

Description

0—5

FTANSI0— FDL ESF Bit-Oriented Message Data. The transmit ESF FDL bit messages are in the

FTANSI5

—

form 111111110X0X1X2X3X4X50, where the order of transmission is from left to right.

Reserved. Write to 0.

6

7

FTANSI

Transmit ANSI Bit Codes. When this bit is set to 1, the FDL unit will continuously trans-

mit the ANSI code defined using register FDL_PR10 bit 0—bit 5 as the ESF bit code

messages. This bit must stay high long enough to ensure the ANSI code is sent at least

10 times.

216

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

FDL Parameter/Control Registers (800—80E; E00—E0E) (continued)

Table 195. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (80B; E0B)

Bit

Symbol

Description

0

FTDONE

Transmit Done. This status bit is set to 1 when transmission of the current FDL frame

has been completed, either after the last bit of the closing flag or after the last bit of an

abort sequence. In the transparent mode (FDL_PR9 bit 6 = 1), this status bit is set when

the transmit FIFO is completely empty. A hardware interrupt is generated only if the cor-

responding interrupt-enable bit (FDL_PR2 bit 0) is set. This status bit is cleared to 0 by a

read of this register.

1

FTEM

Transmitter Empty. If this bit is set to 1, the FDL transmit FIFO is at or below the pro-

grammed depth. A hardware interrupt is generated only if the corresponding interrupt-

enable bit (FDL_PR2 bit 1) is set. If DINT (FDL_PR0 bit 0) is 0, this status bit is cleared

by a read of this register. If FDINT (FDL_PR0 bit 0) is set to 1, this bit actually represents

the dynamic transmit empty condition, and is cleared to 0 only when the transmit FIFO is

loaded above the programmed empty level.

2

3

FTUNDABT FDL Transmit Underrun Abort. A 1 indicates that an abort was transmitted because of

a transmit FIFO underrun. A hardware interrupt is generated only if the corresponding

interrupt-enable bit (FDL_PR2 bit 2) is set. This status bit is cleared to 0 by a read of this

register. This bit must be cleared to 0 before further transmission of data is allowed. This

interrupt is not generated in the transparent mode.

FRF

FDL Receiver Full. This bit is set to 1 when the receive FIFO is at or above the pro-

grammed full level (FDL_PR6). A hardware interrupt is generated if the corresponding

interrupt-enable bit (FDL_PR2 bit 3) is set. If FDINT (FDL_PR0 bit 0) is 0, this status bit

is cleared to 0 by a read of this register. If FDINT (FDL_PR0 bit 0) is set to 1, then this bit

is cleared only when the receive FIFO is read (or emptied) below the programmed full

level*.

4

FREOF

FDL Receive End of Frame. This bit is set to 1 when the receiver has finished receiving

a frame. It becomes 1 upon reception of the last bit of the closing flag of a frame or the

last bit of an abort sequence. A hardware interrupt is generated only if the corresponding

interrupt-enable bit (FDL_PR2 bit 4) is set. This status bit is cleared to 0 by a read of this

register. This interrupt is not generated in the transparent mode.

5

6

FROVERUN FDL Receiver Overrun. This bit is set to 1 when the receive FIFO has overrun its

capacity. A hardware interrupt is generated only if the corresponding interrupt-enable bit

(FDL_PR2 bit 5) is set. This status bit is cleared to 0 by a read of this register*.

FRIDL

FDL Receiver Idle. This bit is set to 1 when the FDL receiver is idle (i.e., 15 or more

consecutive 1s have been received). A hardware interrupt is generated only if the corre-

sponding interrupt-enable bit (FDL_PR2 bit 6) is set. This status bit is cleared to 0 by a

read of this register. This interrupt is not generated in the transparent mode.

7

FRANSI

FDL Receive ANSI Bit Codes. This bit is set to 1 when the FDL receiver recognizes a

valid T1.403 ESF FDL bit code. The receive ANSI bit code is stored in register

FDL_SR3. An interrupt is generated only if the corresponding interrupt enable of register

FDL_PR6 bit 7 = 1. This status bit is cleared to 0 by a read this register.

* If an FDL receive FIFO overrun occurs, as indicated by register FDL_SR0 bit 5 (FROVERUN) = 1, the FDL must be reset to restore proper

operation of the FIFO. Following an FDL receive FIFO overrun, data extracted prior to the required reset may be corrupted.

Agere Systems Inc.

217

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

FDL Parameter/Control Registers (800—80E; E00—E0E) (continued)

Table 196. FDL Transmitter Status Register (FDL_SR1) (80C; E0C)

Bit

Symbol

Description

0—6

FTQS0—

FTQS6

FDL Transmit Queue Status. Bit 0—bit 6 indicate how many bytes can be added to the

transmit FIFO. The bits are encoded in binary where bit 0 is the least significant bit.

7

FTED

FDL Transmitter Empty Dynamic. FTED = 1 indicates that the number of empty loca-

tions available in the transmit FIFO is greater than or equal to the value programmed in

the FTIL bits (FDL_PR3).

Table 197. FDL Receiver Status Register (FDL_SR2) (80D; E0D)

Bit

Symbol

Description

0—6

FRQS0—

FRQS6

FDL Receive Queue Status. Bit 0—bit 6 indicate how many bytes are in the receive

FIFO, including the first status of Frame (SF) byte. The bits are encoded in binary where

bit 0 is the least significant bit*.

7

FEOF

FDL End of Frame. When FEOF = 1, the receive queue status indicates the number of

bytes up to and including the first SF byte.

* Immediately following an FDL reset, the value in bit 0—bit 6 of this status register equals the number of bytes that may be read from the FDL

receive FIFO, register FDL_SR4. After the initial read of the FDL receive FIFO, the value is bit 0—bit 6 of this status register is one greater

than the actual number of bytes that may be read from the FIFO. Only valid FIFO bytes, as specified by this status register, may be read from

the FIFO.

Received FDL ANSI Bit Codes Status Register (FDL_SR3)

The 6-bit code extracted from the ANSI code 111111110X0X1X2X3X4X50 is stored in this register.

Table 198. Receive ANSI FDL Status Register (FDL_SR3) (80E; E0E)

B7

B6

B5

B4

B3

B2

B1

B0

0

X5

X4

X3

X2

X1

X0

Receive FDL FIFO Register (FDL_SR4)

This FIFO stores the received FDL data. Only valid FIFO bytes indicated in register FDL_SR2 may be read. Read-

ing nonvalid FIFO locations or reading the FIFO when it is empty will corrupt the FIFO pointer and will require an

FDL reset to restore proper FDL operation.

Table 199. FDL Receiver FIFO Register (FDL_SR4) (807; E07)

Bit

Symbol

Description

0—7 FRD0—FRD7 FDL Receive Data. The user data received via the FDL block are read through this reg-

ister.

218

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Maps

Global Registers

Table 200. Global Register Set

CLEAR-

ON-READ

REGISTER

REG

(COR)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADDRESS

READ (R)

WRITE (W)

(hexadecimal)

COR

R/W

Reserved

(0)

FDL2INT

(0)

FRMR2INT

(0)

LIU2INT

(0)

Reserved

(0)

FDL1INT

(0)

FRMR1INT

(0)

LIU1INT

(0)

000

001

002

003

004

GREG0

GREG1

GREG2

GREG3

GREG4

Reserved

(0)

FDL2IE

(0)

FRMR2IE

(0)

LIU2IE

(0)

Reserved

(0)

FDL1IE

(0)

FRMR1IE

(0)

LIU1IE

(0)

TID2-RSD1

(0)

TSD2-RSD1

(0)

TID1-RSD1

(0)

TSD1-RSD1

(0)

TSD2-RID1

(0)

TID2-RID1

(0)

TSD1-RID1

(0)

TID1-RID1

(0)

TID1-RSD2

(0)

TSD1-RSD2

(0)

TID2-RSD2

(0)

TSD2-RSD2

(0)

TSD1-RID2

(0)

TID1-RID2

(0)

TSD2-RID2

(0)

TID2-RID2

(0)

Reserved

(0)

ALIE

(0)

SECCTRL

(0)

ITC

(0)

T1-R2

(0)

T2-R1

(0)

Reserved

(0)

Reserved

(0)

R

005

006

007

GREG5

GREG6

GREG7

0

1

0

1

0

1

0

1

0

1

0

1

Line Interface Unit Parameter/Control and Status Registers

Table 201. Line Interface Unit Register Set¹

CLEAR-

ON-READ

(COR)

READ (R)

WRITE

(W)

REGISTER ADDRESS

(hexadecimal)

LIU_REG

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FRAMER 1

FRAMER 2

LIU_REG0

LIU_REG1

COR

R/W

served

LOTC

TDM

DLOS

ALOS

400

401

A00

A01

served

(0)

served

(0)

served

(0)

served

(0)

LOTCIE

(0)

TDMIE

(0)

DLOSIE

(0)

ALOSIE

(0)

LIU_REG2

LIU_REG3

LIU_REG4

LIU_REG5

LIU_REG6

R/W

served

(0)

served

(0)

RESTART

(0)

HIGHZ

(0)

Reserved

(0)

LOSSTD

(0)

Reserved

(0)

Reserved

(0)

402

403

404

405

406

A02

A03

A04

A05

A06

LOSSD

(0)

DUAL

(0)

CODE

(1)

JAT

(0)

JAR

(0)

(1)

served

(0)

served

(0)

JABW0

(0)

PHIZALM

(0)

PRLALM

(0)

PFLALM

(0)

RCVAIS

(0)

ALTIMER

(0)

served

(0)

served

(0)

served

(0)

served

(0)

LOOPA

(0)

LOOPB

(0)

XLAIS

(1)

PWRDN

(0)

served

(0)

served

(0)

served

(0)

served

(0)

Reserved

(0)

EQ2

(0,DS1)

(1,CEPT)

EQ1

(0,DS1)

(1,CEPT)

EQ0

(0)

1. The logic value in parentheses below each bit definition is the default state upon completion of hardware reset.

2. These bits must be written to 1.

Agere Systems Inc.

219

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Maps (continued)

Framer Parameter/Control Registers (READ-WRITE)

Table 202. Framer Unit Status Register Map

FRAMER

STATUS

REGISTER ADDRESS

(hexadecimal)

CLEAR-ON-

READ

(COR)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

READ (R)

WRITE (W)

FRAMER

1

FRAMER

2

FRM_SR0

FRM_SR1

COR

S96SR

AIS

0

RSSFE

TSSFE

LBFA

ESE

FAE

RAC

FAC

LFA

600

601

C00

C01

AUXP

RTS16AIS

LFALR

LTSFA

LSFA

LTS0MFA

LTS16MFA

FRM_SR2

COR

RSa6=F

SLIPU

RSa6=E

SLIPO

RSa6=C

RSa6=A

REBIT

RSa6=8

ECE

CREBIT

RJYA

RTS16MFA

RFA

602

C02

FRM_SR3

FRM_SR4

COR

LCRCATMX

CRCE

FBE

LFV

NFA

603

604

C03

C04

FDL-LLBOFF

TSaSR

FDL-LLBON

RSaSR

FDL-PLBOFF FDL-PLBON

LLBON

CMA

LLBOFF

BFA

SSFA

FRM_SR5

FRM_SR6

FRM_SR7

FRM_SR8

FRM_SR9

FRM_SR10

FRM_SR11

FRM_SR12

FRM_SR13

FRM_SR14

FRM_SR15

FRM_SR16

FRM_SR17

FRM_SR18

FRM_SR19

FRM_SR20

FRM_SR21

FRM_SR22

FRM_SR23

FRM_SR24

FRM_SR25

FRM_SR26

FRM_SR27

FRM_SR28

FRM_SR29

FRM_SR30

FRM_SR31

FRM_SR32

FRM_SR33

FRM_SR34

FRM_SR35

COR

ETREUAS

NTREUAS

RQUASI

BPV15

ETRESES

NTRESES

RPSEUDO

BPV14

ETREBES

NTREBES

PTRNBER

BPV13

ETREES

NTREES

DETECT

BPV12

ETUAS

NTUAS

ETSES

NTSES

ETBES

NTBES

EROUAS

BPV9

ETES

NTES

605

606

607

608

609

60A

60B

60C

60D

60E

60F

610

611

612

613

614

615

616

617

618

619

61A

61B

61C

61D

61E

61F

620

621

622

623

C05

C06

C07

C08

C09

C0A

C0B

C0C

C0D

C0E

C0F

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C1A

C1B

C1C

C1D

C1E

C1F

C20

C21

C22

C23

NROUAS

BPV11

NT1OUAS

BPV10

OUAS

BPV8

BPV7

BPV6

BPV5

BPV4

BPV3

BPV2

BPV1

BPV0

FE15

FE14

FE13

FE12

FE11

FE10

FE9

FE8

FE7

FE6

FE5

FE4

FE3

FE2

FE1

FE0

CEC15

CEC14

CEC13

CEC12

CEC11

CEC10

CEC9

CEC8

CEC7

CEC6

CEC5

CEC4

CEC3

CEC2

CEC1

CEC0

REC15

REC14

REC13

REC12

REC11

REC10

REC9

REC8

REC7

REC6

REC5

REC4

REC3

REC2

REC1

REC0

CNT15

CNT14

CNT13

CNT12

CNT11

CNT10

CNT9

CNT8

CNT7

CNT6

CNT5

CNT4

CNT3

CNT2

CNT1

CNT0

ENT15

ENT14

ENT13

ENT12

ENT11

ENT10

ENT9

ENT8

ENT7

ENT6

ENT5

ENT4

ENT3

ENT2

ENT1

ENT0

ETES15

ETES7

ETES14

ETES6

ETES13

ETES5

ETES12

ETES4

ETES11

ETES3

ETES10

ETES2

ETES9

ETES8

ETES0

ETBES8

ETBES0

ETSES8

ETSES0

ETUS8

ETUS0

ETREES8

ETREES0

ETREBES8

ETREBES0

ETRESES8

ETRESES0

ETREUS8

ETREUS0

ETES1

ETBES15

ETBES7

ETSES15

ETSES7

ETUS15

ETUS7

ETBES14

ETBES6

ETSES14

ETSES6

ETUS14

ETUS6

ETBES13

ETBES5

ETSES13

ETSES5

ETUS13

ETUS5

ETBES12

ETBES4

ETSES12

ETSES4

ETUS12

ETUS4

ETBES11

ETBES3

ETSES11

ETSES3

ETUS11

ETUS3

ETBES10

ETBES2

ETSES10

ETSES2

ETUS10

ETUS2

ETBES9

ETBES1

ETSES9

ETSES1

ETUS9

ETUS1

ETREES9

ETREES1

ETREBES9

ETREBES1

ETRESES9

ETRESES1

ETREUS9

ETREUS1

ETREES15

ETREES7

ETREBES15

ETREBES7

ETRESES15

ETRESES7

ETREUS15

ETREUS7

ETREES14

ETREES6

ETREBES14

ETREBES6

ETRESES14

ETRESES6

ETREUS14

ETREUS6

ETREES13

ETREES5

ETREBES13

ETREBES5

ETRESES13

ETRESES5

ETREUS13

ETREUS5

ETREES12

ETREES4

ETREBES12

ETREBES4

ETRESES12

ETRESES4

ETREUS12

ETREUS4

ETREES11

ETREES3

ETREBES11

ETREBES3

ETRESES11

ETRESES3

ETREUS11

ETREUS3

ETREES10

ETREES2

ETREBES10

ETREBES2

ETRESES10

ETRESES2

ETREUS10

ETREUS2

220

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Maps (continued)

Framer Parameter/Control Registers (READ-WRITE) (continued)

Table 202. Framer Unit Status Register Map (continued)

FRAMER

STATUS

REGISTER ADDRESS

(hexadecimal)

CLEAR-ON-

READ (COR)

READ (R)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WRITE (W)

FRAMER 1 FRAMER 2

FRM_SR36

FRM_SR37

FRM_SR38

FRM_SR39

FRM_SR40

FRM_SR41

FRM_SR42

FRM_SR43

FRM_SR44

FRM_SR45

FRM_SR46

FRM_SR47

FRM_SR48

FRM_SR49

FRM_SR50

FRM_SR51

FRM_SR52

COR

NTES15

NTES7

NTES14

NTES6

NTES13

NTES5

NTES12

NTES4

NTES11

NTES3

NTES10

NTES2

NTES9

NTES1

NTES8

NTES0

624

625

626

627

628

629

62A

62B

62C

62D

62E

62F

630

631

632

633

634

C24

C25

C26

C27

C28

C29

C2A

C2B

C2C

C2D

C2E

C2F

C30

C31

C32

C33

C34

NTBES15

NTBES7

NTSES15

NTSES7

NTUS15

NTUS7

NTBES14

NTBES6

NTSES14

NTSES6

NTUS14

NTUS6

NTBES13

NTBES5

NTSES13

NTSES5

NTUS13

NTUS5

NTBES12

NTBES4

NTSES12

NTSES4

NTUS12

NTUS4

NTBES11

NTBES3

NTSES11

NTSES3

NTUS11

NTUS3

NTBES10

NTBES2

NTSES10

NTSES2

NTUS10

NTUS2

NTBES9

NTBES1

NTSES9

NTSES1

NTUS9

NTBES8

NTBES0

NTSES8

NTSES0

NTUS8

NTUS1

NTUS0

NTREES15

NTREES7

NTREES14

NTREES6

NTREES13

NTREES5

NTREES12

NTREES4

NTREES11

NTREES3

NTREES10

NTREES2

NTREES9

NTREES1

NTREBES9

NTREBES1

NTRESES9

NTRESES1

NTREUS9

NTREUS1

Sa7

NTREES8

NTREES0

NTREBES8

NTREBES0

NTRESES8

NTRESES0

NTREUS8

NTREUS0

Sa8

NTREBES15 NTREBES14 NTREBES13 NTREBES12 NTREBES11 NTREBES10

NTREBES7 NTREBES6 NTREBES5 NTREBES4 NTREBES3 NTREBES2

NTRESES15 NTRESES14 NTRESES13 NTRESES12 NTRESES11 NTRESES10

NTRESES7

NTREUS15

NTREUS7

NTRESES6

NTREUS14

NTREUS6

NTRESES5

NTREUS13

NTREUS5

A bit

NTRESES4

NTREUS12

NTREUS4

Sa4

NTRESES3

NTREUS11

NTREUS3

Sa5

NTRESES2

NTREUS10

NTREUS2

Sa6

NFB1

[FI5E]

FBI

[FI3E]

FRM_SR53

COR

0

RX2

RX1

RX0

635

636

C35

C36

1

FRM_SR54

FRM_SR55

FRM_SR56

FRM_SR57

FRM_SR58

FRM_SR59

FRM_SR60

0

R-0

[Sa4-5]

R-0

[Sa4-7]

R-0

[Sa4-9]

R-1

[Sa4-11]

R-1

[Sa4-13]

R-1

[Sa4-15]

[Sa4-1]

[Sa4-3]

1

COR

0

R-0

[Sa4-21]

R-0

[Sa4-23]

R-0

[Sa4-25]

R-1

[Sa4-27]

R-1

[Sa4-29]

R-1

[Sa4-31]

637

638

639

63A

63B

63C

63D

63E

63F

C37

C38

C39

C3A

C3B

C3C

C3D

C3E

C3F

[Sa4-17]

[Sa4-19]

RC1

[Sa5-1]

RC2

[Sa5-3]

RC3

[Sa5-5]

RC4

[Sa5-7]

RC5

[Sa5-9]

RC6

[Sa5-11]

RC7

[Sa5-13]

RC8

[Sa5-15]

RC9

[Sa5-17]

RC10

[Sa5-19]

RC11

[Sa5-21]

RSPB1 = 0

[Sa5-23]

RSPB2 = 1

[Sa5-25]

RSPB3 = 0

[Sa5-27]

RM1

[Sa5-29]

RM2

[Sa5-31]

RM3

[Sa6-1]

RA1

[Sa6-3]

RA2

[Sa6-5]

RS1

[Sa6-7]

RS2

[Sa6-9]

RS3

[Sa6-11]

RS4

[Sa613]

RSPB4 = 1

[Sa6-15]

0

[Sa6-17]

[Sa6-19]

[Sa6-21]

[Sa6-23]

[Sa6-25]

[Sa6-27]

[Sa6-29]

[Sa6-31]

0

[Sa7-1]

[Sa7-3]

[Sa7-5]

[Sa7-7]

[Sa7-9]

[Sa7-11]

[Sa7-13]

[Sa7-15]

1

FRM_SR61

0

[Sa7-17]

[Sa7-19]

[Sa7-21]

[Sa7-23]

[Sa7-25]

[Sa7-27]

[Sa7-29]

[Sa7-31]

1

FRM_SR62

FRM_SR63

G3

[Sa8-1]

LV

[Sa8-3]

G4

[Sa8-5]

U1

[Sa8-7]

U2

[Sa8-9]

G5

[Sa8-11]

SL

[Sa8-13]

G6

[Sa8-15]

1

FE

SE

LB

G1

R

G2

Nm

Nl

[Sa8-17]

[Sa8-19]

[Sa8-21]

[Sa8-23]

[Sa8-25]

[Sa8-27]

[Sa8-29]

[Sa8-31]

1. Unbracketed contents are valid for DS1 modes. Bracketed contents, [], are valid for CEPT mode.

Agere Systems Inc.

221

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Maps (continued)

Receive Framer Signaling Registers (READ-ONLY)

Table 203. Receive Signaling Registers Map

Receive

CLEAR-

REGISTER ADDRESS

(hexadecimal)

Signaling

ON-READ

(COR)

1

1,2

3

4

5

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

READ (R)

WRITE (W)

FRAMER 1 FRAMER 2

6

FRM_RSR0

R

P

G_0

G_1

F_0

F_1

F_2

F_3

F_4

F_5

F_6

F_7

F_8

F_10

F_11

F_12

F_13

F_14

F_15

F_16

F_17

F_18

F_19

F_20

F_21

F_22

F_23

X

E_0

E_1

D_0

D_1

C_0

C_1

B_0

B_1

B_2

B_3

B_4

B_5

B_6

B_7

B_8

A_0

A_1

640

641

642

643

644

645

646

647

648

649

64A

64B

64C

64D

64E

64F

650

651

652

653

654

655

656

657

658

659

65A

65B

65C

65D

65E

65F

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

C4A

C4B

C4C

C4D

C4E

C4F

C50

C51

C52

C53

C54

C55

C56

C57

C58

C59

C5A

C5B

C5C

C5D

C5E

C5F

FRM_RSR1

FRM_RSR2

FRM_RSR3

FRM_RSR4

FRM_RSR5

FRM_RSR6

FRM_RSR7

FRM_RSR8

FRM_RSR9

FRM_RSR10

FRM_RSR11

FRM_RSR12

FRM_RSR13

FRM_RSR14

FRM_RSR15

G_2

E_2

D_2

C_2

A_2

G_3

E_3

D_3

C_3

A_3

G_4

E_4

D_4

C_4

A_4

G_5

E_5

D_5

C_5

A_5

G_6

E_6

D_6

C_6

A_6

G_7

E_7

D_7

C_7

A_7

G_8

E_8

D_8

C_8

A_8

G_9

E_8

D_8

C_8

A_8

G_10

G_11

G_12

G_13

G_14

G_15

G_16

G_17

G_18

G_19

G_20

G_21

G_22

G_23

E_10

E_11

E_12

E_13

E_14

E_15

E_16

E_17

E_18

E_19

E_20

E_21

E_22

E_23

E_24

E_25

E_26

E_27

E_28

E_29

E_30

E_31

D_10

D_11

D_12

D_13

D_14

D_15

D_16

D_17

D_18

D_19

D_20

D_21

D_22

D_23

D_24

D_25

D_26

D_27

D_28

D_29

D_30

D_31

C_10

C_11

C_12

C_13

C_14

C_15

C_16

C_17

C_18

C_19

C_20

C_21

C_22

C_23

C_24

C_25

C_26

C_27

C_28

C_29

C_30

C_31

B_10

B_11

B_12

B_13

B_14

B_15

B_16

B_17

B_18

B_19

B_20

B_21

B_22

B_23

B_24

B_25

B_26

B_27

B_28

B_29

B_30

B_31

A_10

A_11

A_12

A_13

A_14

A_15

A_16

A_17

A_18

A_19

A_20

A_21

A_22

A_23

A_24

A_25

A_26

A_27

A_28

A_29

A_30

A_31

6

FRM_RSR16

FRM_RSR17

FRM_RSR18

FRM_RSR19

FRM_RSR20

FRM_RSR21

FRM_RSR22

FRM_RSR23

3

7

FRM_RSR24

FRM_RSR25

FRM_RSR26

FRM_RSR27

FRM_RSR28

FRM_RSR29

FRM_RSR30

FRM_RSR31

X

3

X

1. In the CEPT IRSM signaling modes, these bits are in the 0 state and should be ignored.

2. In the DS1 robbed-bit signaling modes, these bits are copied from the corresponding transmit signaling registers. In the CEPT signaling

modes, these bits are in the 0 state and should be ignored.

3. In the DS1 signaling modes, these registers contain unknown data.

4. In DS1 4-state and 2-state signaling, these bits contain unknown data.

5. In DS1 2-state signaling, these bits contain unknown data.

6. In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data.

7. Signifies unknown data.

222

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Maps (continued)

Framer Unit Parameter Register Map

Table 204. Framer Unit Parameter Register Map

FRAMER

CLEAR-

REGISTER ADDRESS

(hexadecimal)

CONTROL

ON-READ

(COR)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

READ (R)

WRITE (W)

FRAMER 1 FRAMER 2

FRM_PR0

FRM_PR1

FRM_PR2

FRM_PR3

FRM_PR4

FRM_PR5

FRM_PR6

FRM_PR7

FRM_PR8

FRM_PR9

FRM_PR10

SLCIE

(0)

Reserved

(0)

RSRIE

(0)

TSRIE

(0)

SR567IE

(0)

SR34IE

(0)

SR2IE

(0)

SR1IE

(0)

660

661

662

663

664

665

666

667

668

669

66A

C60

C61

C62

C63

C64

C65

C66

C67

C68

C69

C6A

R/W

SR1B7IE

(0)

SR1B6IE

(0)

SR1B5IE

(0)

SR1B4IE

(0)

SR1B3IE

(0)

SR1B2IE

(0)

SR1B1IE

(0)

SR1B0IE

(0)

SR2B7IE

(0)

SR2B6IE

(0)

SR2B5IE

(0)

SR2B4IE

(0)

SR2B3IE

(0)

SR2B2IE

(0)

SR2B1IE

(0)

SR2B0IE

(0)

SR3B7IE

(0)

SR3B6IE

(0)

SR3B5IE

(0)

SR3B4IE

(0)

SR3B3IE

(0)

SR3B2IE

(0)

SR3B1IE

(0)

SR3B0IE

(0)

SR4B7IE

(0)

SR4B6IE

(0)

SR4B5IE

(0)

SR4B4IE

(0)

SR4B3IE

(0)

SR4B2IE

(0)

SR4B1IE

(0)

SR4B0IE

(0)

SR5B7IE

(0)

SR5B6IE

(0)

SR5B5IE

(0)

SR5B4IE

(0)

SR5B3IE

(0)

SR5B2IE

(0)

SR5B1IE

(0)

SR5B0IE

(0)

SR6B7IE

(0)

SR6B6IE

(0)

SR6B5IE

(0)

SR6B4IE

(0)

SR6B3IE

(0)

SR6B2IE

(0)

SR6B1IE

(0)

SR6B0IE

(0)

SR7B7IE

(0)

SR7B6IE

(0)

SR7B5IE

(0)

SR7B4IE

(0)

SR7B3IE

(0)

SR7B2IE

(0)

SR7B1IE

(0)

SR7B0IE

(0)

LC2

(1)

LC1

(1)

LC0

(0)

FMODE4

(0)

FMODE3

(0)

FMODE2

(0)

FMODE1

(0)

FMODE0

(0)

CRCO7

(0)

CRCO6

(0)

CRCO5

(0)

CRCO4

(0)

CRCO3

(0)

CRCO2

(0)

CRCO1

(0)

CRCO0

(0)

ESM1

(0)

ESM0

(0)

RABF

(0)

Reserved

(0)

CNUCLBEN

(0)

FEREN

AISM

(0)

SSa6M

(0)

1

[NFFE]

(0)

FRM_PR11

FRM_PR12

FRM_PR13

FRM_PR14

FRM_PR15

FRM_PR16

FRM_PR17

FRM_PR18

FRM_PR19

FRM_PR20

EST7

(0)

EST6

(0)

EST5

(0)

EST4

(0)

EST3

(0)

EST2

(0)

EST1

(0)

EST0

(0)

66B

66C

66D

66E

66F

670

671

672

673

674

C6B

C6C

C6D

C6E

C6F

C70

C71

C72

C73

C74

R/W

SEST15

(0)

SEST14

(0)

SEST13

(0)

SEST12

(0)

SEST11

(0)

SEST10

(0)

SEST9

(0)

SEST8

(0)

SEST7

(0)

SEST6

(0)

SEST5

(0)

SEST4

(0)

SEST3

(0)

SEST2

(0)

SEST1

(0)

SEST0

(0)

0

ETSLIP

(0)

ETAIS

(0)

ETLMFA

(0)

ETLFA

(0)

ETRESa6-F ETRESa6-E

ETRESa6-8

(0)

ETRERFA

(0)

ETRESLIP

(0)

ETREAIS

(0)

ETRELMFA

(0)

ETRELFA

(0)

NTSa6-C

(0)

0

NTSa6-8

(0)

0

NTSLIP

(0)

NTAIS

(0)

NTLMFA

(0)

NTLFA

(0)

0

NTRERFA

(0)

NTRESLIP

(0)

NTREAIS

(0)

NTRELMFA

(0)

NTRELFA

(0)

0

NTRESa6-C

(0)

NTRESa6-F

(0)

NTRESa6-E

(0)

NTRESa6-8

(0)

AFDPLBE

(0)

AFDLLBE

(0)

Reserved

(0)

ALLBE

(0)

TSAIS

(0)

Reserved

(0)

ASAISTMX

(0)

ASAIS

(0)

TICRC

(0)

TLIC

(0)

TLLBOFF

(0)

TLLBON

(0)

TQRS

(0)

TPRS

(0)

TUFAUXP

(0)

TUFAIS

(0)

1. Definition in CEPT mode.

Agere Systems Inc.

223

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Maps (continued)

Framer Unit Parameter Register Map (continued)

Table 204. Framer Unit Parameter Register Map (continued)

FRAMER

CLEAR-

REGISTER ADDRESS

(hexadecimal)

CONTROL

ON-READ

(COR)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

READ (R)

WRITE (W)

FRAMER 1 FRAMER 2

FRM_PR21

FRM_PR22

FRM_PR23

FRM_PR24

FRM_PR25

FRM_PR26

FRM_PR27

FRM_PR28

TC/R=1

(0)

TFDLC

(0)

TFDLSAIS

(0)

TFDLLAIS

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

675

676

677

678

679

67A

67B

67C

C75

C76

C77

C78

C79

C7A

C7B

C7C

R/W

TLIC7

(0)

TLIC6

(1)

TLIC5

(1)

TLIC4

(1)

TLIC3

(1)

TLIC2

(1)

TLIC1

(1)

TLIC0

(1)

SSTSC7

(0)

SSTSC6

(1)

SSTSC5

(1)

SSTSC4

(1)

SSTSC3

(1)

SSTSC2

(1)

SSTSC1

(1)

SSTSC0

(1)

LBC2

(0)

LBC1

(0)

LBC0

(0)

TSLBA4

(0)

TSLBA3

(0)

TSLBA2

(0)

TSLBA1

(0)

TSLBA0

(0)

Reserved

(0)

SLBC1

(0)

SLBC0

(0)

STSLBA4

(0)

STSLBA3

(0)

STSLBA2

(0)

STSLBA1

(0)

STSLBA0

(0)

Reserved

(0)

Reserved

(0)

SYSFSM

(0)

TFM2

(0)

TFM1

(0)

FRFRM

(0)

SWRESTART

(0)

SWRESET

(0)

TRFA

(0)

TJRFA

(0)

AARSa6_C

(0)

AARSa6_8

(0)

ATMX

(0)

AAB0LMFA

(0)

AAB16LMFA

(0)

ARLFA

(0)

0

ATERTX

(0)

ATELTS0MFA

(0)

ATECRCE

(0)

TSiNF

(0)

TSiF

(0)

SIS,

T1E

(0)

FRM_PR29

FRM_PR30

FRM_PR31

FRM_PR32

FRM_PR33

FRM_PR34

FRM_PR35

SaS7

(0)

SaS6

(0)

SaS5

(0)

TSa8

(0)

TSa7

(0)

TSa6

(0)

TSa5

(0)

TSa4

(0)

67D

67E

67F

680

681

682

683

C7D

C7E

C7F

C80

C81

C82

C83

R/W

TDNF

(0)

Reserved

(0)

Reserved

(0)

TESa8

(0)

TESa7

(0)

TESa6

(0)

TESa5

(0)

TESa4

(0)

0

X-0

Sa4-5

X-0

Sa4-7

X-0

Sa4-9

X-1

Sa4-11

X-1

Sa4-13

X-1

Sa4-15

Sa4-1

Sa4-3

0

X-0

Sa4-21

X-0

Sa4-23

X-0

Sa4-25

X-1

Sa4-27

X-1

Sa4-29

X-1

Sa4-31

Sa4-17

Sa4-19

XC1

Sa5-1

XC2

Sa5-3

XC3

Sa5-5

XC4

Sa5-7

XC5

Sa5-9

XC6

Sa5-11

XC7

Sa5-13

XC8

Sa5-15

XC9

Sa5-17

XC10

Sa5-19

XC11

Sa5-21

XSPB1 = 0

Sa5-23

XSPB2 = 1

Sa5-25

XSPB3 = 0

Sa5-27

XM1

Sa5-29

XM2

Sa5-31

XM3

Sa6-1

XA1

Sa6-3

XA2

Sa6-5

XS1

Sa6-7

XS2

Sa6-9

XS3

Sa6-11

XS4

Sa613

XSPB4 = 1

Sa6-15

FRM_PR36

FRM_PR37

FRM_PR38

FRM_PR39

FRM_PR40

FRM_PR41

Sa6-17

Sa7-1

Sa6-19

Sa7-3

Sa6-21

Sa7-5

Sa6-23

Sa7-7

Sa6-25

Sa7-9

Sa6-27

Sa7-11

Sa7-27

Sa8-11

Sa8-27

Sa6-29

Sa7-13

Sa7-29

Sa8-13

Sa8-29

Sa6-31

Sa7-15

Sa7-31

Sa8-15

Sa8-31

684

685

686

687

688

689

C84

C85

C86

C87

C88

C89

R/W

Sa7-17

Sa8-1

Sa7-19

Sa8-3

Sa7-21

Sa8-5

Sa7-23

Sa8-7

Sa7-25

Sa8-9

Sa8-17

Sa8-19

Sa8-21

Sa8-23

Sa8-25

Reserved

(0)

TLTS16AIS

(0)

TLTS16RMFA ALTTS16RMF

XS

(0)

TTS16X2

(0)

TTS16X1

(0)

TTS16X0

(0)

A

(0)

224

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Maps (continued)

Framer Unit Parameter Register Map (continued)

Table 204. Framer Unit Parameter Register Map (continued)

FRAMER

CLEAR-

REGISTER

ADDRESS

(hexadecimal)

CONTROL

ON-READ

(COR)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

READ (R)

WRITE (W)

FR 1

FR 2

FRM_PR42

FRM_PR43

R/W

FEX7

(0)

FEX6

(0)

FEX5

(0)

FEX4

(0)

FEX3

(0)

FEX2

(0)

FEX1

(0)

FEX0

(0)

68A

C8A

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

SSC

(0)

STS2

[SaFDL2]

(0)

STS1

[SaFDL1]

(0)

STS0

[SaFDL0]

(1)

68B

68C

C8B

C8C

FRM_PR44

R/W

TCSS

(0)

ASTSAIS

(0)

IRSM

TSR-ASM

(0)

MOS_CSS

(0)

RSI

(0)

ASM

(0)

STOMP

(0)

TSIG

(0)

FRM_PR45

FRM_PR46

FRM_PR47

FRM_PR48

FRM_PR49

FRM_PR50

FRM_PR51

FRM_PR52

FRM_PR53

FRM_PR54

FRM_PR55

FRM_PR56

FRM_PR57

FRM_PR58

FRM_PR59

FRM_PR60

FRM_PR61

FRM_PR62

FRM_PR63

FRM_PR64

FRM_PR65

FRM_PR66

R/W

HWYEN

(0)

Reserved

(0)

Reserved

(0)

CHIMM

(0)

CDRS1

(0)

CDRS0

(0)

CMS

(0)

HFLF

(0)

68D

68E

68F

690

691

692

693

694

695

696

697

698

699

69A

69B

69C

69D

69E

69F

6A0

6A1

6A2

C8D

C8E

C8F

C90

C91

C92

C93

C94

C95

C96

C97

C98

C99

C9A

C9B

C9C

C9D

C9E

C9F

CA0

CA1

CA2

RFE

(0)

ROFF2

(0)

ROFF1

(0)

ROFF0

(0)

TFE

(0)

TOFF2

(0)

TOFF1

(0)

TOFF0

(0)

TLBIT

(0)

TCE

(0)

TBYOFF5

(0)

TBYOFF4

(0)

TBYOFF3

(0)

TBYOFF2

(0)

TBYOFF1

(0)

TBYOFF0

(0)

RLBIT

(0)

RCE

(0)

RBYOFF5

(0)

RBYOFF4

(0)

RBYOFF3

(0)

RBYOFF2

(0)

RBYOFF1

(0)

RBYOFF0

(0)

TTSE31

(0)

TTSE30

(0)

TTSE29

(0)

TTSE28

(0)

TTSE27

(0)

TTSE26

(0)

TTSE25

(0)

TTSE24

(0)

TTSE23

(0)

TTSE22

(0)

TTSE21

(0)

TTSE20

(0)

TTSE19

(0)

TTSE18

(0)

TTSE17

(0)

TTSE16

(0)

TTSE15

(0)

TTSE14

(0)

TTSE13

(0)

TTSE12

(0)

TTSE11

(0)

TTSE10

(0)

TTSE9

(0)

TTSE8

(0)

TTSE7

(0)

TTSE6

(0)

TTSE5

(0)

TTSE4

(0)

TTSE3

(0)

TTSE2

(0)

TTSE1

(0)

TTSE0

(0)

RTSE31

(0)

RTSE30

(0)

RTSE29

(0)

RTSE28

(0)

RTSE27

(0)

RTSE26

(0)

RTSE25

(0)

RTSE24

(0)

RTSE23

(0)

RTSE22

(0)

RTSE21

(0)

RTSE20

(0)

RTSE19

(0)

RTSE18

(0)

RTSE17

(0)

RTSE16

(0)

RTSE15

(0)

RTSE14

(0)

RTSE13

(0)

RTSE12

(0)

RTSE11

(0)

RTSE10

(0)

RTSE9

(0)

RTSE8

(0)

RTSE7

(0)

RTSE6

(0)

RTSE5

(0)

RTSE4

(0)

RTSE3

(0)

RTSE2

(0)

RTSE1

(0)

RTSE0

(0)

THS31

(0)

THS30

(0)

THS29

(0)

THS28

(0)

THS27

(0)

THS26

(0)

THS25

(0)

THS24

(0)

THS23

(0)

THS22

(0)

THS21

(0)

THS20

(0)

THS19

(0)

THS18

(0)

THS17

(0)

THS16

(0)

THS15

(0)

THS14

(0)

THS13

(0)

THS12

(0)

THS11

(0)

THS10

(0)

THS9

(0)

THS8

(0)

THS7

(0)

THS6

(0)

THS5

(0)

THS4

(0)

THS3

(0)

THS2

(0)

THS1

(0)

THS0

(0)

RHS31

(0)

RHS30

(0)

RHS29

(0)

RHS28

(0)

RHS27

(0)

RHS26

(0)

RHS25

(0)

RHS24

(0)

RHS23

(0)

RHS22

(0)

RHS21

(0)

RHS20

(0)

RHS19

(0)

RHS18

(0)

RHS17

(0)

RHS16

(0)

RHS15

(0)

RHS14

(0)

RHS13

(0)

RHS12

(0)

RHS11

(0)

RHS10

(0)

RHS9

(0)

RHS8

(0)

RHS7

(0)

RHS6

(0)

RHS5

(0)

RHS4

(0)

RHS3

(0)

RHS2

(0)

RHS1

(0)

RHS0

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

TCHIDTS

(0)

TBYOFF6

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

Reserved

(0)

RCHIDTS

(0)

RBYOFF6

(0)

FRM_PR67

FRM_PR68

FRM_PR69

—

Reserved

6A3

6A4

6A5

CA3

CA4

CA5

R/W

GPTRN3

(0)

GPTRN2

(0)

GPTRN1

(0)

GPTRN0

(0)

GFRMSEL

(0)

GBLKSEL

(0)

TPEI

(0)

ITD

(0)

FRM_PR70

R/W

DPTRN3

(0)

DPTRN2

(0)

DPTRN1

(0)

DPTRN0

(0)

DUFTP

(0)

DBLKSEL

(0)

reserved

(0)

IRD

(0)

6A6

CA6

Agere Systems Inc.

225

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Maps (continued)

Transmit Signaling Registers (READ/WRITE)

Table 205. Transmit Signaling Registers Map

TRANSMIT

CLEAR-

REGISTER ADDRESS

(hexadecimal)

SIGNALING

ON-READ

(COR)

1

2

3

4

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

READ (R)

WRITE (W)

FR 1

FR 2

5

FRM_TSR0

R/W

P

G_0

G_1

F_0

F_1

F_2

F_3

F_4

F_5

F_6

F_7

F_8

E_0

E_1

D_0

D_1

C_0

C_1

B_0

B_1

B_2

B_3

B_4

B_5

B_6

B_7

B_8

A_0

A_1

6E0

6E1

6E2

6E3

6E4

6E5

6E6

6E7

6E8

6E9

6EA

6EB

6EC

6ED

6EE

6EF

6F0

6F1

6F2

6F3

6F4

6F5

6F6

6F7

6F8

6F9

6FA

6FB

6FC

6FD

6FE

6FF

CE0

CE1

CE2

CE3

CE4

CE5

CE6

CE7

CE8

CE9

CEA

CEB

CEC

CED

CEE

CEF

CF0

CF1

CF2

CF3

CF4

CF5

CF6

CF7

CF8

CF9

CFA

CFB

CFC

CFD

CFE

CFF

FRM_TSR1

FRM_TSR2

FRM_TSR3

FRM_TSR4

FRM_TSR5

FRM_TSR6

FRM_TSR7

FRM_TSR8

FRM_TSR9

FRM_TSR10

FRM_TSR11

FRM_TSR12

FRM_TSR13

FRM_TSR14

FRM_TSR15

G_2

E_2

D_2

C_2

A_2

G_3

E_3

D_3

C_3

A_3

G_4

E_4

D_4

C_4

A_4

G_5

E_5

D_5

C_5

A_5

G_6

E_6

D_6

C_6

A_6

G_7

E_7

D_7

C_7

A_7

G_8

E_8

D_8

C_8

A_8

G_9

E_8

D_8

C_8

A_8

G_10

G_11

G_12

G_13

G_14

G_15

G_16

G_17

G_18

G_19

G_20

G_21

G_22

G_23

F_10

F_11

F_12

F_13

F_14

F_15

F_16

F_17

F_18

F_19

F_20

F_21

F_22

F_23

X

E_10

E_11

E_12

E_13

E_14

E_15

E_16

E_17

E_18

E_19

E_20

E_21

E_22

E_23

E_24

E_25

E_26

E_27

E_28

E_29

E_30

E_31

D_10

D_11

D_12

D_13

D_14

D_15

D_16

D_17

D_18

D_19

D_20

D_21

D_22

D_23

D_24

D_25

D_26

D_27

D_28

D_29

D_30

D_31

C_10

C_11

C_12

C_13

C_14

C_15

C_16

C_17

C_18

C_19

C_20

C_21

C_22

C_23

C_24

C_25

C_26

C_27

C_28

C_29

C_30

C_31

B_10

B_11

B_12

B_13

B_14

B_15

B_16

B_17

B_18

B_19

B_20

B_21

B_22

B_23

B_24

B_25

B_26

B_27

B_28

B_29

B_30

B_31

A_10

A_11

A_12

A_13

A_14

A_15

A_16

A_17

A_18

A_19

A_20

A_21

A_22

A_23

A_24

A_25

A_26

A_27

A_28

A_29

A_30

A_31

5

FRM_TSR16

FRM_TSR17

FRM_TSR18

FRM_TSR19

FRM_TSR20

FRM_TSR21

FRM_TSR22

FRM_TSR23

6

7

FRM_TSR24

FRM_TSR25

FRM_TSR26

FRM_TSR27

FRM_TSR28

FRM_TSR29

FRM_TSR30

FRM_TSR31

X

6

X

1. In the normal DS1 robbed-bit signaling modes, these bits define the corresponding receive channel signaling mode and are copied into the

received signaling registers. In the CEPT signaling modes, these bits are ignored.

2. In the CEPT IRSM signaling mode, E-bit information is valid. In all other CEPT modes, these bits contain unknown data. In DS1 modes, this

bit contains unknown data.

3. In DS1 4-state and 2-state signaling modes, these bits contain unknown data.

4. In DS1 2-state signaling mode, these bits contain unknown data.

5. In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data.

6. In the DS1 signaling modes, these registers contain unknown data.

7. Signifies known data.

226

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Register Maps (continued)

Facility Data Link Parameter/Control and Status Registers (READ-WRITE)

Table 206. Facility Data Link Register Map

TRANSMIT

CLEAR-

REGISTER ADDRESS

(hexadecimal)

SIGNALING

ON-READ

(COR)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

READ (R)

WRITE

(W)

FR 1

FR 2

FDL_PR0

FDL_PR1

FDL_PR2

FDL_PR3

FDL_PR4

FDL_PR5

FDL_PR6

R/W

FRANSIT3 FRANSIT2

FRANSIT1

(1)

FRANSIT0

(0)

Reserved

(0)

Reserved

(0)

FLAGS

(0)

FDINT

(0)

800

801

802

803

804

805

806

E00

E01

E02

E03

E04

E05

E06

(1)

(0)

FTPRM

(0)

FRPF

(0)

FTR

(0)

FRR

(0)

FTE

(0)

FRE

(0)

FLLB

(0)

FRLB

(0)

FTBCRC

(0)

FRIIE

(0)

FROVIE

(0)

FREOFIE

(0)

FRFIE

(0)

FTUNDIE

(0)

FTEIE

(0)

FTDIE

(0)

FTFC

(0)

FTABT

(0)

FTIL5

(0)

FTIL4

(0)

FTIL3

(0)

FTIL2

(0)

FTIL1

(0)

FTIL0

(0)

FTD7

(0)

FTD6

(0)

FTD5

(0)

FTD4

(0)

FTD3

(0)

FTD2

(0)

FTD1

(0)

FTD0

(0)

FTIC7

(0)

FTIC6

(0)

FTIC5

(0)

FTIC4

(0)

FTIC3

(0)

FTIC2

(0)

FTIC1

(0)

FTIC0

(0)

FRANSIE

(0)

Reserved

(0)

FRIL5

(0)

FRIL4

(0)

FRIL3

(0)

FRIL2

(0)

FRIL1

(0)

FRIL0

(0)

FDL_PR7

FDL_PR8

Reserved

—

R/W

FRMC7

(0)

FRMC6

(0)

FRMC5

(0)

FRMC4

(0)

FRMC3

(0)

FRMC2

(0)

FRMC1

(0)

FRMC0

(0)

808

E08

FDL_PR9

R/W

Reserved

(0)

FTM

(0)

FMATCH

(0)

FALOCT

(0)

FMSTAT

(0)

FOCTOF2

(0)

FOCTOF1

(0)

FOCTOF0

(0)

809

80A

E09

E0A

FDL_PR10

FTANSI

(0)

Reserved

(0)

FTANSI5

(0)

FTANSI4

(0)

FTANSI3

(0)

FTANSI2

(0)

FTANSI1

(0)

FTANSI0

(0)

FDL_SR0

FDL_SR1

FDL_SR2

FDL_SR3

FDL_SR4

COR

R

FRANSI

FTED

FREOF

0

FRIDL

FTQS6

FRQS6

0

FROVERUN

FTQS5

FRQS5

X5

FREOF

FTQS4

FRQS4

X4

FRF

FTQS3

FRQS3

X3

FTUNDABT

FTQS2

FRQS2

X2

FTEM

FTQS1

FRQS1

X1

FTDONE

FTQS0

FRQS0

X0

80B

80C

80D

80E

807

E0B

E0C

E0D

E0E

E07

R

FRD7

(0)

FRD6

(0)

FRD5

(0)

FRD4

(0)

FRD3

(0)

FRD2

(0)

FRD1

(0)

FRD0

(0)

Agere Systems Inc.

227

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Parameter

VDD Supply Voltage Range

Symbol

VDD

—

Min

0

Max

4.6

0.3

—

Unit

V

Maximum Voltage (digital pins) with Respect to VDD

—

V

Minimum Voltage (digital pins) with Respect to GRND

—

–0.3

—

V

Maximum Allowable Voltages (RTIP, RRING) with

—

0.5

V

Respect to VDD

Minimum Allowable Voltages (RTIP, RRING) with

Respect to GRND

—

–0.5

–65

—

V

Storage Temperature Range

Tstg

125

°C

Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Power Supply

VDD

PD

3.13

—

3.30

400

—

3.47

650

85

V

Power Dissipation

mW

°C

Ambient Temperature

TA

–40

Handling Precautions

Although ESD protection circuitry has been designed into this device, proper precautions must be taken to avoid

exposure to electrostatic discharge (ESD) and electrical overstress (EOS) during all handling, assembly, and test

operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification

requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresh-

olds are dependent on the circuit parameters used in each of the models, as defined by JEDEC’s JESD22-A114

(HBM) and JESD22-C101 (CDM) standards.

Table 207. ESD Protection Characteristics

Minimum Threshold

Device

CDM

HBM

Corner

Noncorner

T7633

2000 V

1000 V

CAUTION:MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling

and packaging MOS devices should be observed.

228

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Electrical Characteristics

Logic Interface Characteristics

Table 208. Logic Interface Characteristics (TA = –40 °C to +85 °C, VDD = 3.3 V ± 5%, VSS = 0)

Parameter

Input Voltage:

Symbol

Test Conditions

Min

Max

Unit

Low

High

VIL

VIH

IIL = –70 µA*

IIH = 10 µA^†

0

2.0

0.8

VDD

V

Input Leakage

IL

—

10

µA

Output Voltage:

Low

High

VOL

VOH

IOL = –5.0 mA*

IOH = 5.0 mA^†

0

0.5

VDD

V

VDD – 0.5

Input Capacitance

Load Capacitance^‡

CI

—

3.0

50

pF

CL

* Sinking.

† Sourcing.

‡ 100 pF allowed for AD[7:0] (pins 86 to 79), and A[11:0] (pins 98 to 87).

Notes:

All buffers use TTL levels.

All inputs are driven between 2.4 V and 0.4 V.

An internal 50 kΩ pull-up is provided on the 3-STATE, RESET, DS1/CEPT, FRAMER, SYSCLK, CKSEL, MPMODE, MPMUX, CS, MPCLK,

JTAGTDI, JTAGTCK, and JTAGTMS pins.

An internal 50 kΩ pull-down is provided on the JTAGRST pin.

Power Supply Bypassing

External bypassing is required for each channel. A 1.0 µF capacitor must be connected between VDDX and

GRNDX. In addition, a 0.1 µF capacitor must be connected between VDD and GRND, and a 0.1 µF capacitor must

be connected between VDDA and GRNDA. Ground plane connections are required for GRNDX, GRND, and

GRNDA. Power plane connections are also required for VDDX and VDD. The need to reduce high-frequency cou-

pling into the analog supply (VDDA) may require an inductive bead to be inserted between the power plane and the

VDDA pin of each channel.

Capacitors used for power supply bypassing should be placed as close as possible to the device pins for maximum

effectiveness.

Agere Systems Inc.

229

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Outline Diagram

144-Pin TQFP

Dimensions are in millimeters.

22.00 ± 0.20

20.00 ± 0.20

PIN #1 IDENTIFIER ZONE

144

109

1

108

20.00

± 0.20

22.00

± 0.20

36

73

37

72

DETAIL A

DETAIL B

1.40 ± 0.05

1.60 MAX

SEATING PLANE

0.08

0.05/0.15

0.50 TYP

1.00 REF

0.25

0.106/0.200

GAGE PLANE

0.19/0.27

SEATING PLANE

0.45/0.75

0.08

M

DETAIL B

DETAIL A

5-3815(F)r.6

230

Agere Systems Inc.

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

Ordering Information

Device Code

Package

Temperature

Comcode

(Ordering Number)

T - 7633 - - - TL - DB

144-Pin TQFP

–40 °C to +85 °C

108194895

Agere Systems Inc.

231

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

C

Index

CAS 76

CEPT

Numerics

High-Density Bipolar of Order 3 (HDB3) 54

CEPT 2.048 frame 66

100 ms timer 72

1-byte Frames 117

3-State Procedures 139

8 ms 72

CEPT Loss of Basic Frame Alignment 69

CEPT Loss of Frame Alignment Recovery Algorithm 69

CEPT nailed-up broadcast transmission (CNUBT) 99

CEPT nailed-up connect loopback (CNUCLB) 99

CEPT Sa Receive Stack 178

CER 132

A

A bit 80, 94, 107

Aborts 116

aborts 115

Absolute Maximum Ratings 228

AIS 102, 106

Alarm Filter Register 185

Alarm Indication Signal 35

alarm indication signal 62, 92

Alarm Register 159

alternate mark inversion 52

AMI 52

CEX 132

Channel Associated Signaling 76

channel associated signaling multiframe structures 66

CHI 125

CHI Common Control Register 204

CHI Data Rate 126

CHI Offset Programming 132

CHI parameters 126

CHI Receive Control Register 205, 207

CHI Receive Highway Select Registers 207

CHI system interface 79

CHI timing with associated signaling mode enabled 131

CHI Transmit Control Register 205, 207

CHI Transmit Highway Select Registers 206

CHIDATA 125

Clock Select Mode 126

clocking 122

CMS 132, 133

CNUBT mode 99

CNUCLB mode 100

Concentration Highway Interface (CHI) 125

Concentration Highway Master Mode 126

continuous E-bit 94

CRC Error Counter Register 174

CRC Option Bits Decoding 184

CRC-16 117

AMI Encoding 52

Analog Loss of Signal 30, 31

Analog Loss of Signal (ALOS) 28

Analog Loss of Signal (ALOS) Alarm 28

ANSI 108

ASM 85

ASM time-slot format 86

Associated Signaling Mode 85, 128

Automatic AIS 188

Automatic and On-Demand Commands 106

automatically transmitting E bits 79

auxiliary pattern 102

B

B8ZS 27

B8ZS Encoding 53

Basic Frame Structure 66, 67

biframe alignment 79, 80

Binary 8 Zero Code Suppression 53

Bipolar Violation Counter Register 173

bit destuffing 115

bit offset 132

bit stuffing 115

BLB 99

Blue alarm 92

CRC-4 70, 79, 82

CRC-4 error counter 71

CRC-4 Errors at NT1 from NT2 Counter Register 174

CRC-4 multiframe 66, 70

CRC-4 multiframe alignment 74

CRC-4 Multiframe Alignment Algorithm with 100 ms

Timer 72

CRC-4 Multiframe Alignment Algorithm with 8 ms Timer

72

CRC-4 Multiframe Alignment Search Algorithm with

400 ms Timer 74

CRC-4/Non-CRC-4 Equipment Interworking 75

CRC-4-to-Non-CRC-4 equipment interworking 74

cyclic redundancy check-4 70

Cyclic redundancy checking 62

Board loopback 99

boundary scan 135

Boundary-Scan Register 139

Boundary-Scan Test Logic 135

BYPASS 139

BYPASS Register 139

BYPASS register 135

Bypassing 47, 229

Index (continued)

232

Agere Systems Inc.

Advance Data Sheet

May 2002

70 W, 1 GTH7z6,3238 VD,uNa-Cl hTa1n/Ene1l,3L.a3teVraSllyh-Doirftf-uHseadu,lETnehramncinemateonrt

F

D

D4 57

F and G bits 85

D4 Frame Format 57

data link interface 81

Facility Alarm Condition Register 166

Facility Data Link 108

Data Recovery 26

facility data link 80

DDS 58

default mode 52

Delay 45

Facility Data Link Access Timing 58

Facility Errored Event Register-1 168

Facility Event Register 173

Facility Event Register-3 170

Failed state 95

Device ID and Version Registers 157

diagnostic loopback modes 120

Digital Data Service 58

Digital Local Loopback (DLLOOP) 44

Digital Loss of Signal 30, 31

Digital Loss of Signal (DLOS) 28

Digital Loss of Signal (DLOS) Alarm 28

double CRC-4 multiframe 82

DS0 55

FAS 67

FAS/NOT FAS Si- and E-Bit Source 79

FDL 108

FDL Control Command Register 189

FDL Control Register 212

FDL HDLC 108

FDL interface 109

DS1 55

FDL Interrupt Mask Control Register 213

FDL Interrupt Status Register 217

FDL Parameter/Control Registers 212

FDL Receiver Interrupt Level Control Register 215

Alternate Mark Inversion (AMI) 52

Binary 8 Zero Code Suppression (B8ZS) 53

Zero Code Suppression (ZCS) 53

DSX-1 Transmitter Pulse Template and Specifications

37

DUAL 27

FDL Receiver Match Character Register 215

FDL Receiver Status Register 218

FDL Transmit ANSI ESF Bit Codes 216

FDL Transmitter Configuration Control Register 214

FDL Transmitter Mask Register 214

FDL Transmitter Status Register 218

FDL Transparent Control Register 216

Flags 116

flags 115

Frame Alignment Signal 67

frame check sequence 117

Frame Format 55

E

E bit 106

E Bit at NT1 from NT2 Counter Register 174

E bits 70

E-bit 94

E-Bit Counter Register 174

E-bit monitoring 71

elastic store buffers 122

Electrical Characteristics 229

electrostatic discharge 228

Frame Formats 55

Frame, Superframe, and Extended Superframe Defini-

tions 55

error events 97

Framer Exercise Register 198

Errored Event Threshold Definition 185

Errored Second Threshold Register 186

ESF 61

Framer Mode Bits Decoding 183

Framer Parameter/Control Registers 180, 181, 182,

183, 184, 185, 186, 187, 188, 189, 190, 191,

192, 193, 194, 195, 196, 197, 198, 199, 200,

201, 202, 203, 204, 205, 206, 207, 208, 209,

210

Framer Register Structure 164

Framer Status/Counter Registers 165, 166, 167, 168,

169, 170, 171, 172, 173, 174, 175, 176, 177,

178, 179

ESF bit-oriented messages 109, 114

ET Bursty Errored Seconds Counter 175

ET Errored Seconds Counter 175

ET Severely Errored Seconds Counter 175

ET Unavailable Seconds Counter 175

ET1 Errored Event Enable Register 186

ET1 Remote End Errored Event Enable Register 187

ET-RE Bursty Errored Seconds Counter 175

ET-RE Errored Seconds Counter 175

ET-RE Severely Errored Seconds Counter 175

ET-RE Unavailable Seconds Counter 176

Exchange Termination and Exchange Termination Re-

mote End Interface Status Register 171

Extended Superframe 61

Framer Transmit Line Idle Code 189

Framer Transmit System Idle Code 189

Framing Bit Errored Counter Register 173

Full Local Loopback (FLLOOP) 44

EXTEST 138

Agere Systems Inc.

233

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

J

Index (continued)

JAR 41

Jitter 27

G

Jitter Accommodation 27, 30, 31, 41

Jitter Attenuator 27, 40

Jitter Attenuator Enable (Transmit or Receive Path) 41

Jitter Tolerance 41

Jitter Transfer 27, 30, 31, 40

Jitter Transfer Function 40

Generated (Intrinsic) Jitter 40

Global Internal Interface Control Register 157

Global Loopback Control Register 156

Global Register Architecture 154

Global Register Set 154

Global Register Structure 155

Global Terminal Control Register 157

L

LFA 62

Line Code Option Bits Decoding 183

Line Enable Register 188

Line Interface Unit 26

Jitter Attenuator 40

Line Circuitry 48

Loopbacks 44

Receiver 26

Transmit 34

Line Interface Units (LIU) Register Architecture 158

Line Interface Units Register Set 158

Line loopback 99

Line Termination 48

LIU Alarms 28

H

Handling Precautions 228

HDB3 27

HDB3 Coding 54

HDLC Operation 115

High-Impedance State 45

Highway Enable 126

HIGHZ 138

human-body model 228

I

IDCODE 138

IDCODE Register 139

IDCODE register 135

idle code 86, 103

Idles 116

idles 115

In-Circuit Testing 45

instruction register 138

Interrupt Enable Register 159

Interrupt Generation 149

Interrupt Group Enable Registers 180

Interrupt Status Register 165

interworking 168

IRSM Signaling 77

ITU 66

ITU Rec. 0.151 102

ITU Rec. 706 Annex B 74

ITU Rec. G.704 Section 2.3.1 67

ITU Rec. G.704 Section 2.3.3.1 70

ITU Rec. G.704 Section 2.3.3.4 79

ITU Rec. G.704 Section 2.3.3.5.2 71

ITU Rec. G.704 Section 2.3.3.5.3 71

ITU Rec. G.706 Annex C 67

ITU Rec. G.706 Section 4.1.1 69

ITU Rec. G.706 Section 4.2 72, 74

ITU Rec. G.706 Section 4.3.2 69

ITU Rec. G.706 Section B.2.2 79

ITU Rec. G.706 Section B.2.3 74

ITU Rec. G.706.4.1.2 69

ITU Rec. G.732 Section 5.2 78

ITU Rec. G.775 93

LIU Powerdown (PD) 45

LIU Receiver Bipolar Violation (BPV) Alarm 29

LIU Transmitter Alarm Indication Signal Generator

(XLAIS) 35

LIU Transmitter Alarms 35

LIU Transmitter Configuration Modes 35

LIU Transmitter Driver Monitor (TDM) Alarm 36

LIU Transmitter Zero Substitution Encoding (CODE) 35

LIU-bypass mode 51

LIU-Framer Physical Interface 50

LLB 99

local loopback 120

Logic Interface Characteristics 229

loopback 99

Loopback Decoding 190, 191

Loopbacks 44

loss of CRC-4 multiframe alignment 71

Loss of Frame Alignment 62

loss of frame alignment 91

Loss of LIU Transmit Clock (LOTC) Alarm 35

loss of PLL clock 93

loss of receive clock 93

Loss of SYSCK (LORLCK) 45

loss of time slot 16 signaling multiframe alignment 78

Loss Shutdown (LOSSD) and Receiver AIS (RCVAIS)

29

LOSSD and RCVAIS Control Configurations 29

ITU-T standard polynomial 117

234

Agere Systems Inc.

Advance Data Sheet

May 2002

70 W, 1 GTH7z6,3238 VD,uNa-Cl hTa1n/Ene1l,3L.a3teVraSllyh-Doirftf-uHseadu,lETnehramncinemateonrt

Q

Index (continued)

quasi-random test signal 102

M

R

Maintenance

Rate adaptation 125

RCE 133

LoopBack and Transmission Modes 99, 100, 101

match bit 119

Rec. G.704 66

Microprocessor Clock (MPCLK) Specifications 142

microprocessor interface 140

microprocessor modes 140

MPMODE 140

Receive ANSI FDL Status Register 218

Receive ANSI T1.403 Bit-Oriented Messages 109

Receive CRC-4 Multiframe Search Algorithm Using the

100 ms Internal Timer 73

Receive Facility Data Link Interface 108

Receive FDL FIFO 112

MPMUX 140

N

Receive Frame Edge 126

receive framer 50

negative slip 93

Network Termination and Network Termination Remote

End Interface Status Register 172

no CRC-4 79

NOT FAS 80

NOT FAS frames 67

Receive Framer Reframe 107

Receive HDLC Mode 112

Receive Highway Select 127

Receive Least Significant Bit First 128

receive line elastic store buffer 124

Receive Line Interface Configuration Modes 27

Receive NOT-FAS TS0 Register 177

receive queue status 113

receive Sa stack 71

Receive Signaling Inhibit 107

Receive Signaling Registers

CEPT Format 179

Receive Time-Slot Enable 127

Receive Time-Slot Enable Registers 206

received E-bit counter 71

received end of frame 119

Received Sa Register 177

Received Signaling Registers 179

DS1 Format 179

Receiver Alarms 28, 29

Receiver Bit Offset 127

Receiver Byte Offset 127

Receiver Clock Edge 126

Receiver FDL FIFO Register 218

receiver full 113, 119

receiver idle 119

receiver overrun 113, 119

Red alarm 91

NOT FAS Sa Stack Source and Destination 82, 83, 84

NOT FAS Sa4 bit Sources 80

NT1 Bursty Errored Seconds Counter 176

NT1 Errored Event Enable Register 187

NT1 Errored Seconds Counter 176

NT1 Remote End Errored Event Enable Register 187

NT1 Severely Errored Seconds Counter 176

NT1 Unavailable Seconds Counter 176

NT1-RE Bursty Errored Seconds Counter 177

NT1-RE Errored Seconds Counter 176

NT1-RE Severely Errored Seconds Counter 177

NT1-RE Unavailable Seconds Counter 177

O

Operating Conditions 228

Ordering 231

Ordering Information 231

Outline Diagram 230

Output Pulse Generation 34

P

Parameters 126, 127, 128

Payload loopback 99

performance report message 108, 115

Performance Report Messages 110

performance report messages 114

phase-lock 122

PLLB 100

positive slip 93

Power Supply 47, 229

Powerdown 45

Register Maps 219

remote alarm indication 67

Remote End Alarm Register 167

Remote Frame Alarm 106

remote frame alarm 62, 92

remote loopback 120, 121

Remote Loopback (RLOOP) 44

Reset 149

Return Loss 30, 31

RFE 132, 133

Robbed-Bit Signaling 85

Primary Block Interrupt Enable Register 155

Primary Block Interrupt Status Register 155

Principle of the Boundary Scan 135

PRM 110

pseudorandom test pattern 102

Pulse Template 37, 38, 39

Agere Systems Inc.

235

Advance Data Sheet

May 2002

T7633 Dual T1/E1 3.3 V Short-Haul Terminator

TFE 132, 133

Index (continued)

time slot 16 multiframe alignment recovery algorithm 78

Time Slot 16 Signaling 86

timing requirements for the transmit and receive framer

interfaces 51

Transformer 48

Transmission of E Bit 194

Transmit ANSI T1.403 Bit-Oriented Messages 114

transmit elastic store buffer 122

Transmit Facility Data Link Interface 114

Transmit FDL FIFO 117

Transmit Frame Edge 126

Transmit Framer ANSI Performance Report Message

Status Register 179

transmit framer interface 50

Transmit Highway Select 127

transmit idle character 118

Transmit Least Significant Bit First 128

Transmit Remote Frame Alarm 107

Transmit Signaling Registers

CEPT Format 210

S

Sa bits 80, 81

Sa Bits Sourcing Decoding 195

Sa Facility Data Link Access 81

Sa stack 80, 82

Sa4—Sa8 Control Register 196

Sa4—Sa8 Source Register 195

Sa6 code monitoring 71

Sa6 codes 95, 96

Sa6 patterns 95

SAMPLE/PRELOAD 138

Secondary Loopback Control 191

secondary loopback modes 100

Secondary System Time-Slot Loopback Address 191

Secondary-single time-slot line loopback 100

Secondary-single time-slot system loopback 100

Severely Errored Second Threshold Register 186

Si bit 79

Si bits in frames 13 and 15 79

Si-Bit Source Register 198

Signaling Access 85

Signaling Mode Register 202

Single Rail 52

Single time-slot line loopback (STSLLB) 99

Single time-slot system loopback (STSSLB) 99

SLC-96 58

SLC-96 9-State Signaling 64

SLC-96 Data Link Block Format 59

SLC-96 FDL Receive Stack 178

SLC-96 FDL stack 60

SLC-96 Transmit Stack 197

SLIP 93

spurious frame alignment 72

status of frame (SF) byte 112

status registers 91

DS1 Format 210

transmit signaling registers 85

Transmit Time Slot 16 Remote Multiframe Alarm 107

Transmit Time-Slot Enable 127

Transmit Time-Slot Enable Registers 206

Transmitter FDL FIFO Register 214

Transmitter Bit Offset 127

Transmitter Byte Offset 127

Transmitter Clock Edge 126

transmitter empty 118

Transmitter Underrun 117

Transparent Framing 56

transparent framing mode 1 56

transparent framing mode 2 56

Transparent Mode 118

transparent mode 119

TR-TSY-000194 Issue 1, 12-87 108

STSLLB 99

STSSLB 99

Stuffed Time Slots 128

U

unavailable state alarm 95

System Frame Sync Mask Source 192

System Interface Control Register 201

System Time-Slot Loopback Address 190

X

XCE 133

T

Y

T1 Frame Recovery Alignment Algorithms 63

T1 Frame Structure 55

Yellow alarm 92

T1 framing formats 128

T1 Framing Structures 55

T1 Robbed-Bit Signaling 64, 65

T1 stuffed channels 86

T1.403-1995 108

TAP 135

Telcordia Technologies 108

test access port 135

Z

ZCS 53

ZCS Encoding 53

Zero Code Suppression 53

Zero Substitution 27

Zero Substitution Decoding (CODE) 27

Zero-Bit Insertion/Deletion 115

test access port controller 136

236

Agere Systems Inc.

Advance Data Sheet

May 2002

70 W, 1 GTH7z6,3238 VD,uNa-Cl hTa1n/Ene1l,3L.a3teVraSllyh-Doirftf-uHseadu,lETnehramncinemateonrt

Notes

Agere Systems Inc.

237

SLC is a registered trademark of Lucent Technologies Inc.

AT&T is a registered trademark of AT&T Inc.

ANSI is a registered trademark of the American National Standards Institute.

Intel is a registered trademark of Intel Corporation.

Motorola is a registered trademark of Motorola, Inc.

Telcordia Technologies is a registered trademark of Telcordia Technologies Inc.

Mitel is a registered trademark of Mitel Corporation.

AMD is a registered trademark of Advanced Micro Devices, Inc.

IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET:

E-MAIL:

http://www.agere.com

docmaster@agere.com

N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA:

Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

Tel. (44) 7000 624624, FAX (44) 1344 488 045

EUROPE:

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.

May 2002

DS02-244BBAC (Replaces DS98-244TIC)


型号：	T7633
厂家：	AGERE SYSTEMS
描述：	Dual T1/E1 3.3 V Short-Haul Terminator 双T1 / E1 3.3 V短程终结者
文件：	总250页 (文件大小：1849K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

T7633 [AGERE]

相关型号：

T76651B

T77-G37-10.0MHZ

T77-G37-12.0MHZ

T77-G37-20.0MHZ

T77-G37-50.000MHZ

T77-G37-50.0MHZ

T77-G37-FREQ

T77-N57-10.000MHZ

T77-N57-10.0MHZ

T77-N57-20.0MHZ

T77-N57-50.000MHZ

T77-N57-50.0MHZ