LUCL9217GAR-D [AGERE]
Low-Cost Line Interface with Reverse Battery and PPM; 与反向电池和PPM低成本线路接口型号: | LUCL9217GAR-D |
厂家: | AGERE SYSTEMS |
描述: | Low-Cost Line Interface with Reverse Battery and PPM |
文件: | 总30页 (文件大小:398K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data Sheet
November 2001
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Features
Description
■ Basic forward/reverse battery SLIC functionality at
This general-purpose electronic subscriber loop
a low cost
interface circuit (SLIC) is optimized for low cost, while
still providing a satisfactory set of features. This part
is a pin-for-pin replacement for the Agere L9218/
L9219 SLIC.
■ Pin compatible with Agere Systems Inc. L9218/
L9219 SLIC
■ Low active power (typical 154 mW during on-hook
transmission)
The L9217 requires a 5 V power supply and single
battery to operate. This device offers forward and
reverse battery operation. The rate of battery rever-
sal may be ramped to meet international require-
ments. Additionally, a low-power scan mode, wherein
all circuitry except the off-hook supervision is shut
down to conserve power, is available.
■ Low-power scan mode for low-power, on-hook
power dissipation (57 mW typical)
■ Distortion-free, on-hook transmission
■ Convenient operating states:
— Forward powerup
— Reverse powerup
— Low-power scan
— Disconnect (high impedance)
— PPM operational states
The dc current limit may be programmed via a single
external resistor. Both the loop supervision and ring
trip supervision functions are offered with user-
controlled thresholds via external resistors. Over-
head is adequate for 3.14 dBm into 900 Ω of on-hook
transmission.
■ Minimal external components required
■ Two gain options to optimize the codec interface
The device is periodic pulse metering (PPM) compat-
ible, offering a convenient point for meter pulse injec-
tion and filter point for rejection of the meter pulse
signal. In the PPM active modes, overhead voltage is
automatically increased to accommodate on-hook
transmission of meter pulse signals. The level that
the overhead is increased to is set by a single exter-
nal resistor. In this way, the L9217 can accommodate
high-voltage meter pulse signals.
■ Adjustable supervision functions:
— Off-hook detector with hysteresis
— Ring trip detector
■ Adjustable loop current limit
■ Adjustable overhead voltage
■ Ramped rate of battery reversal
■ Periodic pulse metering (PPM) compatible
The L9217 is offered with a receive gain that is opti-
mized to interface to a first-generation type codec
(L9217A). It is also offered with a gain option that is
optimized to interface to a third- or fourth-generation
type codec (L9217G). In both cases, minimizing
external components is required at this interface.
■ Thermal protection with thermal shutdown indica-
tion
Data control is via a parallel data control scheme.
The device is available in a 28-pin PLCC package. It
is built by using a 90 V complementary bipolar
(CBIC) process.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Table of Contents
Page Figures
Contents
Page
Figure 13. Loop Current vs. Loop Voltage.............. 19
Figure 14. Off-Hook Detection Circuit..................... 20
Figure 15. Ring Trip Equivalent Circuit
and Equivalent Application .................... 21
Figure 16. ac Equivalent Circuit.............................. 24
Figure 17. Interface Circuit Using First-
Features ......................................................................1
Description...................................................................1
Pin Information ............................................................4
Functional Description.................................................6
Absolute Maximum Ratings (at TA = 25 °C)................7
Recommended Operating Conditions .........................7
Electrical Characteristics .............................................8
Ring Trip Requirements..........................................12
Test Configurations ...................................................13
Applications ...............................................................15
dc Applications........................................................19
Battery Feed.........................................................19
Overhead Voltage ................................................19
Rate of Battery Reversal......................................20
Loop Range..........................................................20
Off-Hook Detection...............................................20
Ring Trip Detection...............................................21
Longitudinal Balance...............................................21
Periodic Pulse Metering (PPM)...............................22
ac Design................................................................23
Codec Types........................................................23
ac Interface Network ............................................23
Receive Interface .................................................23
Example 1: Real Termination (First-
Generation Codec (±5 V Codec) ........... 27
Figure 18. Interface Circuit Using First-
Generation Codec (5 V Only Codec)..... 27
Tables
Page
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Pin Descriptions ..................................... 4
Input State Coding .................................. 6
Supervision Coding ................................. 6
Power Supply .......................................... 8
2-Wire Port .............................................. 9
Analog Pin Characteristics .................... 10
PPM ...................................................... 10
ac Feed Characteristics ........................ 11
Logic Inputs and Outputs ...................... 12
Table 10. Parts List for Loop Start Application
Circuit Using T7504-Type Codec .......... 16
Table 11. 900 W Termination, 850 W + 50 nF
Hybrid First-Generation Codec Design
Parameters ........................................... 17
Table 12. Parts List for Loop Start Application
Circuit Using T8536-Type Codec .......... 18
Table 13. FB1/FB2 Values vs. Typical Ramp
Time ...................................................... 20
Generation Codec)...............................................24
Example 2: Complex Termination (First-
Generation Codec)...............................................26
Power Derating .......................................................28
Pin-for-Pin Compatibility with L9218/L9219............28
PCB Layout Information ............................................28
Outline Diagram.........................................................29
28-Pin PLCC...........................................................29
Ordering Information..................................................30
Figures
Page
Figure 1. Functional Diagram...................................3
Figure 2. 28-Pin PLCC.............................................4
Figure 3. Ring Trip Circuits ....................................12
Figure 4. L9217 Basic Test Circuit.........................13
Figure 5. Metallic PSRR.........................................13
Figure 6. Longitudinal PSRR .................................13
Figure 7. Longitudinal Balance ..............................14
Figure 8. RFI Rejection..........................................14
Figure 9. Longitudinal Impedance..........................14
Figure 10. ac Gains..................................................14
Figure 11. Basic Loop Start Application
Circuit Using T7504-Type Codec............15
Figure 12. Basic Loop Start Application
Circuit Using T8536-Type Codec............17
2
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Description (continued)
POWER CONDITIONING AND REFERENCE
FORWARD AND REVERSE BATTERY
DCOUT
VTX
RECTIFIER
3
+
AX
–
β = 41 V/A
TG
TXI
AAC
VITR
β = 9.66
PPMOUT
PPMIN
–
PT
PR
A = 1
PPM
β = 5
+
TIP/RING
CURRENT
SENSE
–
+
RCVN
RCVP
+
A = –1
–
A VERSION GAIN = 3.93
G VERSION GAIN = 1
B0
B1
B2
BATTERY FEED
STATE CONTROL
LOOP CLOSURE DETECTOR
+
–
LCTH
+
–
RTSP
RTSN
NSTAT
RING TRIP DETECTOR
12-3557 (F)
Figure 1. Functional Diagram
Agere Systems Inc.
3
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Pin Information
4
3
2
1
28
27
26
RCVP
RCVN
LCTH
DCOUT
VBAT
5
25
24
23
22
21
20
19
VTX
6
TXI
7
VITR
8
NSTAT
PPMIN
RTSP
RTSN
28-PIN PLCC
9
PR
10
11
CF2
12
13
14
15
16
17
18
12-3558 (F).c
Figure 2. 28-Pin PLCC
Table 1. Pin Descriptions
PLCC Symbol Type
Description
PROG
1
2
3
I
I
Current-Limit Program Input. A resistor to DCOUT sets the dc current limit of the
device.
FB2
—
—
Polarity Reversal Slowdown. Connect a capacitor to ground to control the rate of bat-
tery reversal.
FB1
Polarity Reversal Slowdown. Connect a capacitor to ground to control the rate of bat-
tery reversal.
CC
4
5
V
—
I
5 V Power Supply.
RCVP
Receive ac Signal Input (Noninverting). This high-impedance input controls the ac
differential voltage on tip and ring.
6
RCVN
I
Receive ac Signal Input (Inverting). This high-impedance input controls the ac differ-
ential voltage on tip and ring.
4
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued)
PLCC Symbol Type
Description
7
LCTH
I
Loop Closure Threshold Input. Connect a resistor to DCOUT to set off-hook
threshold.
8
DCOUT
O
dc Output Voltage. This output is a voltage that is directly proportional to the abso-
lute value of the differential tip/ring current.
BAT
V
9
—
Battery Supply. Negative high-voltage power supply.
10
PR
I/O Protected Ring. The output of the ring driver amplifier and input to loop sensing cir-
cuitry. Connect to the loop through overvoltage protection.
11
12
13
CF2
CF1
B2
—
—
I
Filter Capacitor 2. Connect a 0.1 µF capacitor from this pin to AGND.
Filter Capacitor 1. Connect a 0.47 µF capacitor from this pin to pin CF2.
State Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2.
Pin B2 has internal pull-down.
14
15
B1
B0
I
I
State Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2.
Pin B1 has internal pull-down.
State Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2.
Pin B0 has internal pull-down.
16
17
18
AGND
BGND
PT
—
—
Analog Signal Ground.
Battery Ground. Ground return for the battery supply.
I/O Protected Tip. The output of the tip driver amplifier and input to loop sensing cir-
cuitry. Connect to loop through overvoltage protection.
19
20
21
RTSN
RTSP
I
I
I
Ring Trip Sense Negative. Connect this pin to the ringing generator signal through a
high-value resistor.
Ring Trip Sense Positive. Connect this pin to the ring relay and the ringer series
resistor through a high-value resistor.
PPMIN
Receive PPM Signal Input. This high-impedance input controls the PPM differential
voltage on tip and ring. The PPM signal may be present at this pin at all times: how-
ever, PPM will only be transmitted to tip and ring if the appropriate PPM state is cho-
sen. ac couple the PPM signal to this node.
22
23
NSTAT
VITR
O
O
Ring Trip Detector Output/Loop Detector Output. When low, this logic output indi-
cates that ringing is tripped or that an off-hook condition exists.
ac Output Voltage. The voltage at this point is directly proportional to the differential
tip/ring current.
24
25
TXI
I
ac/dc Separation. Connect a 0.1 µF capacitor from this point to VTX.
VTX
O
ac Output Voltage. This output is a voltage that is directly proportional to the differ-
ential tip/ring current.
26
27
28
TG
OVH
—
I
Transmit Gain. Connect an 8.06 kΩ from TG to VTX to set the transmit gain of the
SLIC.
PPM Overhead. Connect a resistor from this node to ground to set the overhead volt-
age during PPM high overhead modes.
PPMOUT
O
PPM Signal Output. Connect a resistor from this node to TG for hybrid cancellation
of the periodic pulse metering (PPM) signal.
Agere Systems Inc.
5
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Functional Description
Table 2. Input State Coding
B0 B1 B2
State/Definition
1
1
1
1
1
0
1
0
1
1
0
0
Powerup, Forward Battery, Normal Overhead. Normal talk and battery feed state. Pin PT is
positive with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is un-
affected by resistor OVH and is adequate for 3.14 dBm overload into 900 Ω.
Powerup, Reverse Battery, Normal Overhead. Normal talk and battery feed state. Pin PT is
negative with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is un-
affected by resistor OVH and is adequate for 3.14 dBm overload into 900 Ω.
Powerup, Forward Battery, High Overhead. Normal talk and battery feed state. Pin PT is posi-
tive with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is in-
creased via resistor OVH.
Powerup, Reverse Battery, High Overhead. Normal talk and battery feed state. Pin PT is neg-
ative with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is in-
creased via resistor OVH.
0
0
0
1
0
0
1
1
0
Low-Power Scan. Except for off-hook detection, all circuits are shut down to conserve power. Pin
PT is positive with respect to pin PR. On-hook transmission is disabled.
Disconnect. The tip and ring amplifiers are turned off, and the SLIC goes to a high-impedance
state (>100 kΩ). Supervision outputs read on hook. Device will power up in this state.
Powerup, Reverse Battery, High Overhead with PPM. Normal talk and battery feed state. Pin
PT is negative with respect to PR. On-hook transmission is enabled. PPM is active. Overhead is
increased via resistor OVH.
0
1
0
Powerup, Forward Battery, High Overhead with PPM. Normal talk and battery feed state. Pin
PT is positive with respect to PR. On-hook transmission is enabled. PPM is active. Overhead is
increased via resistor OVH.
Table 3. Supervision Coding
NSTAT
0 = off-hook or ring trip.
1 = on-hook and no ring trip.
6
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
A
Absolute Maximum Ratings (at T = 25 °C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
5 V Power Supply
Symbol
Min
—
Typ
—
Max
7.0
–75
7.0
7.0
—
Unit
V
CC
V
Battery (Talking) Supply
VBAT
—
—
—
V
Logic Input Voltage
–0.5
–7.0
150
—
V
Analog Input Voltage
—
—
V
J
Maximum Junction Temperature
Storage Temperature Range
Relative Humidity Range
T
—
°C
°C
%
V
stg
T
–40
—
125
95
H
R
5
—
Ground Potential Difference (BGND to AGND)
PT or PR Fault Voltage (dc)
PT or PR Fault Voltage (10 x 1000 µs)
Current into Ring Trip Inputs
—
—
±3
—
—
VPT, VPR
VPT, VPR
IRTSP, IRTSN
VBAT – 5
VBAT – 15
—
3
V
—
15
V
±240
—
µA
Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when
powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the
device ratings. Some of the known examples of conditions that cause such potentials during powerup are the following:
1. An inductor connected to tip and ring can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters.
2. Inductance in the VBAT lead could resonate with the VBAT filter capacitor to cause a destructive overvoltage.
Recommended Operating Conditions
Parameter
Min
–40
4.75
–24
Typ
—
Max
85
Unit
°C
V
Ambient Temperature
CC
V
V
Supply Voltage
5.0
–48
5.25
–70
BAT
Supply Voltage
V
Agere Systems Inc.
7
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Electrical Characteristics
Minimum and maximum values are testing requirements in the temperature range of 25 °C to 85 °C and battery
range of –24 V to –70 V. These minimum and maximum values are guaranteed to –40 °C based on component
simulations and design verification of samples, but devices are not tested to –40 °C in production. The test circuit
shown in Figure 4 is used, unless otherwise noted. Positive currents flow into the device.
Typical values are characteristics of the device design at 25 °C based on engineering evaluations and are not part
CC
BAT
of the test requirements. Supply values used for typical characterization are V = 5.0 V, V
= –48 V, unless oth-
erwise noted.
Table 4. Power Supply
Parameter
Min
Typ
Max
Unit
Power Supply—Powerup, No Loop Current:
CC
I
—
—
—
5.2
–2.66
154
6.5
–2.95
175
mA
mA
mW
BAT
I
BAT
(V
= –48 V)
BAT
Power Dissipation (V
= –48 V)
Power Supply—Scan, No Loop Current:
CC
I
—
—
—
3.4
–0.9
57
4.3
–1
70
mA
mA
mW
BAT
I
BAT
(V
= –48 V)
BAT
Power Dissipation (V
= –48 V)
Power Supply—Disconnect, No Loop Current:
CC
I
—
—
—
1.9
–0.1
14
—
—
—
mA
mA
mW
BAT
I
BAT
(V
= –48 V)
BAT
Power Dissipation (V
= –48 V)
Power Supply Rejection 500 Hz to 3 kHz
(See Figures 5, 6, 16, and 17.)1:
30
36
—
—
—
—
dB
dB
CC
V
BAT
V
Thermal Protection Shutdown (Tjc)1
150
165
—
°C
1, 2
JA
Thermal Resistance Still Air, Junction to Ambient (θ )
Natural Convection 2S2P Board
:
—
—
—
—
30
43
27
36
—
—
—
—
°C/W
°C/W
°C/W
°C/W
Natural Convection 2S0P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Airflow, PCB board layers, and other factors can greatly affect this parameter.
8
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Electrical Characteristics (continued)
Table 5. 2-Wire Port
Parameter
Min
Typ
Max
Unit
—
—
Tip or Ring Drive Current = dc + Longitudinal + Signal
Currents
80
mA
—
—
—
Signal Current
15
mArms
mArms
Longitudinal Current Capability per Wire1
15
8.5
dc Loop Current Limit2:
Allowed Range Including Tolerance3
15
—
—
±5
45
—
mA
%
LOOP
Accuracy (R
BAT
= –48 V)
= 100 Ω, V
Powerup Open Loop Voltage Levels (PPMOFF):
Common-mode Voltage
BAT
—
V
/2
—
V
V
V
Differential Voltage VBAT = –48 V4 (Gain = 2)
Differential Voltage VBAT = –48 V4 (Gain = 7.86)
BAT
BAT
BAT
|V
|V
+ 7.5|
+ 8.0|
|V
|V
+ 6.5|
+ 6.5|
|V
|V
+ 5.9|
+ 5.9|
BAT
BAT
BAT
Powerup Open Loop Voltage Levels (PPMON)
Minimum Programmed Overhead:
Differential Voltage VBAT = –48 V (Gain = 7.86)
BAT
—
—
|V
+ 18.67|
V
Disconnect State:
Leakage
—
—
10
72
150
100
µA
LOOP
dc Feed Resistance (for I
below regulation level)
Ω
(does not include protection resistor)
Loop Resistance Range (–3.17 dBm overload into
900 Ω; not including protection):
—
—
LOOP
I
BAT
= 20 mA at V
= –48 V
1800
Ω
Longitudinal to Metallic Balance—IEEE® Std. 455
(See Figure 7.)5:
200 Hz to 3400 Hz
61
—
—
—
58
40
dB
dB
Metallic to Longitudinal Balance (open loop):
200 Hz to 4 kHz
RFI Rejection (See Figure 8.)3, 0.5 Vrms, 50 Ω Source,
30% AM Mod 1 kHz:
—
—
—
–55
—
–45
—
dBV
500 kHz to 100 MHz
1. The longitudinal current is independent of dc loop current.
2. Current-limit ILIM is programmed by a resistor, RPROG, from pin IPROG to DCOUT. ILIM is specified at the loop resistance where current limiting
begins (see Figure 13).
3. This parameter is not tested in production. It is guaranteed by design and device characterization.
4. Specification is reduced to |VBAT1 + 10.5 V| minimum when VBAT1 = –70 V at 85 °C.
5. Longitudinal balance of circuit card will depend on loop series protection resistor matching and magnitude. More information is available in
the Applications section of this document.
Agere Systems Inc.
9
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Electrical Characteristics (continued)
Table 6. Analog Pin Characteristics
Parameter
Min
Typ
Max
Unit
Differential PT/PR Current Sense (DCOUT):
Gain (PT/PR to DCOUT)
121
–100
125
—
129
100
V/A
mV
LOOP
Offset Voltage at I
= 0
1
LCTH
Loop Closure Detector Threshold (R
= 22.1 kΩ) :
8.8
6.0
—
—
13.6
10.2
mA
mA
On- to Off-hook Threshold (scan mode)
Off- to On-hook Threshold (active mode)
Ring Trip Comparator:
Input Offset Voltage2
Internal Voltage Source
Current at Input RTSP3
—
–9.1
I – 0.5
±10
–8.6
—
–8.1
I + 0.5
mV
V
µA
N
N
I
N
RCVN, RCVP:
Input Bias Current
Input Resistance
—
—
–0.2
1
–1
—
µA
MΩ
1. Loop closure threshold is programmed by resistor RLCTH from pin LCTH to pin DCOUT. The programming equation or relationship between
off-hook threshold and resistor value is different for active mode versus scan mode (see Applications section for more details).
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. IN is the sourcing current at RTSN. Guaranteed if IN is within 5 µA to 30 µA.
Table 7. PPM
Parameter
Min
Typ
Max
Unit
PPM Source*:
Frequency (f1)
Frequency (f2)
Input Signal
11.88
15.80
0
12
16
—
12.12
16.20
0.525
kHz
kHz
Vrms
Signal Gain (from PPMIN to amplifier outputs)
Harmonic Distortion
9
10
5
11
—
—
—
%
—
50
Isolation
—
dB
*
PPM signal should be ac-coupled into PPMIN.
10
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Electrical Characteristics (continued)
Table 8. ac Feed Characteristics
Parameter
ac Termination Impedance1
Longitudinal Impedance at PT/PR2
Min
150
—
Typ
—
0
Max
1300
—
Unit
Ω
Ω
Total Harmonic Distortion—200 Hz to 4 kHz2:
—
—
—
—
0.3
1.0
%
%
Off-hook
On-hook
Transmit Gain, f = 1 kHz (PT/PR to VITR) (current limit)
–391
–403
–415
V/A
L9217A, Open Loop:
Receive + Gain, f = 1 kHz (RCVP to PT/PR)3
7.62
–7.62
7.86
–7.86
8.09
–8.09
—
—
Receive – Gain, f = 1 kHz (RCVN to PT/PR)3
L9217G, Open Loop:
Receive + Gain, f = 1 kHz (RCVP to PT/PR)4
Receive – Gain, f = 1 kHz (RCVN to PT/PR)4
1.94
–1.94
2.00
–2.00
2.06
–2.06
—
—
Gain vs. Frequency (transmit and receive)
(600 Ω termination; reference 1 kHz2):
200 Hz to 300 Hz
–1.00
–0.3
–3.0
—
0.0
0.0
–0.1
—
0.05
0.05
0.3
dB
dB
dB
dB
300 Hz to 3.4 kHz
3.4 kHz to 16 kHz
16 kHz to 266 kHz
2.5
Gain vs. Level (transmit and receive)(reference 0 dBV2):
–55 dB to +3 dB
–0.05
0
0.05
dB
2-Wire Idle-channel Noise (600 Ω termination):
Psophometric2
C-message
3 kHz Flat2
—
—
—
–87
2
10
–77
12
20
dBmp
dBrnC
dBrn
Transmit Idle-channel Noise:
Psophometric2
C-message
3 kHz Flat2
—
—
—
–82
7
15
–77
12
20
dBmp
dBrnC
dBrn
1. With a first-generation codec, this parameter is set by external components. Any complex impedance R1 + R2 || C between 150 Ω and
1300 Ω can be synthesized. With a third-generation codec, this parameter is set by a codec or by a combination of a codec and an external
network.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. Use this gain option with an Agere first-generation or third-generation codec.
4. Use this gain option with an Agere third-generation codec.
Agere Systems Inc.
11
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Electrical Characteristics (continued)
Table 9. Logic Inputs and Outputs
All outputs are open collectors with internal, 30 kΩ pull-up resistor. Input pins have internal pull-down or some
method to power up in the disconnect state.
Parameter
Symbol
Min
Typ
Max
Unit
Input Voltages:
Low Level (permissible range)
High Level (permissible range)
IL
V
V
–0.5
2.0
0.4
2.4
0.7
V
V
IH
CC
V
Input Currents:
Low Level (V = 5.25 V, V = 0.4 V)
CC
I
IL
I
I
0
10
4
24
10
50
µA
µA
CC
I
IH
High Level (V = 5.25 V, V = 2.4 V)
Output Voltages (open collector with internal pull-up resistor):
CC
OL
OL
Low Level (V = 4.75 V, I = 200 µA)
V
V
0
2.4
0.2
—
0.4
V
V
CC
OH
OH
CC
High Level (V = 4.75 V, I = –20 µA)
V
Ring Trip Requirements
8 µF
TIP
TIP
RING
■ Ringing signal:
— Voltage, minimum 35 Vrms, maximum 100 Vrms.
— Frequency, 17 Hz to 33 Hz.
— Crest factor, 1.2 to 1.6.
10 kΩ
2 µF
■ Ring trip:
— ≤100 ms (typical).
100 Ω
RING
12-2572 (F).f
■ Pretrip:
— The circuits in Figure 3 will not cause ring trip.
Figure 3. Ring Trip Circuits
12
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Test Configurations
VBAT
0.1 µF
VCC
0.1 µF
VBAT
BGND VCC AGND
VITR
50 Ω
TIP
XMT
75 kΩ
RLOOP
100 Ω/600 Ω
RCVN
RCVP
46 kΩ
L9217
SLIC
RCV
50 Ω
19.4 kΩ
RING
PPMOUT
6.19 kΩ
DCOUT
IPROG
TG
43.2 kΩ
22.1 kΩ
2 MΩ
8.06 kΩ
0.1 µF
VTX
TXI
B0
B1
LCTH
B2
NSTAT
PPMIN
CF1
RTSP
RTSN
402 Ω
274 kΩ
VBAT
2 MΩ
0.47 µF
0.1 µF
CF2
OVH
V
12-3559 (F).Em
Figure 4. L9217 Basic Test Circuit
VBAT OR VCC
VBAT OR VCC
100 Ω
4.7 µF
DISCONNECT
BYPASS CAPACITOR
DISCONNECT
BYPASS CAPACITOR
100 Ω
4.7 µF
VS
VS
VBAT OR
VCC
VBAT OR
VCC
67.5 Ω
TIP
TIP
+
BASIC
TEST CIRCUIT
10 µF
BASIC
TEST CIRCUIT
900 Ω
VT/R
67.5 Ω
56.3 Ω
+
–
RING
RING
VM
–
10 µF
VS
VT/R
VS
VM
PSRR = 20log
PSRR = 20log
12-2582 (F).b
12-2583 (F).b
Figure 5. Metallic PSRR
Figure 6. Longitudinal PSRR
Agere Systems Inc.
13
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Test Configurations (continued)
ILONG
TIP
100 µF
+
VPT
–
TIP
VS
368 Ω
368 Ω
+
BASIC
TEST CIRCUIT
BASIC
TEST CIRCUIT
VM
–
–
ILONG
VPR
+
RING
100 µF
RING
VS
VM
∆ VPT
∆ ILONG
∆VPR
∆ ILONG
LONGITUDINAL BALANCE = 20 log
ZLONG =
OR
12-2585 (F).a
12-2584 (F).c
Figure 9. Longitudinal Impedance
Figure 7. Longitudinal Balance
0.01 µF
82.5 Ω
TIP
600 Ω
1
XMT
6, 7
2
50 Ω
VS
TIP
BASIC TEST
CIRCUIT
L7591
4
+
VBAT
BASIC
TEST CIRCUIT
0.01 µF
2.15 µF
600 Ω
VT/R
RING
82.5 Ω
–
RCV
RING
HP® 4935A
TIMS
VS
5-6756 (F).bm
VS = 0.5 Vrms 30% AM 1 kHz modulation,
f = 500 kHz—1 MHz
VXMT
VT/R
GXMT =
device in powerup mode, 600 Ω termination.
VT/R
VRCV
GRCV =
Figure 8. RFI Rejection
12-2587 (F).e
Figure 10. ac Gains
14
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Applications
A basic loop start reference circuit, using bused ringing with the L9217 SLIC and the T7504 first-generation codec,
is shown in Figure 11. This circuit is designed for a 900 Ω termination impedance and an 850 Ω + 50 nF transhy-
brid. Transmit gain is set at 0 dBm and receive gain is set at –7 dBm.
V
BAT
C
0.1
BAT
C
HY
4.7 nF
µ
F
PPMIN
V
CC
C
CC
0.1
µ
F
C
PPM
0.01
R
FLT
*
R
PROG
R
PPM
6.19 k
µ
F
Ω
Ω
9
21
28
OPEN
1
4
35.7 k
Ω
26
I
PROG
V
BAT
V
CC
PPMIN
PPMOUT
TG
VTX
R
LCTH
7
R
GP1
LCTH
8.06 k
25
24
R
X
22.1 k
Ω
86.6 k
Ω
C
B
8
0.1
µ
F
DCOUT
OVH (for 2.5 Vrms PPM)
GSX
DX
C
B1
TXI
R
OVH
µ
0.47 F
27
VITR
–
+
23
49.9 k
Ω
R
T2
R
HB1
97.6 k
45.3 k
Ω
Ω
+2.4 V
R
T1
Ω
PCM
HIGHWAY
R
PT
TIP
18
C
HB
R
HB
33.2 k
PT
86.6 k
Ω
0.47 nF
50
Ω
R
RCV
63.4 k
Ω
5
L7591
RCVP
EMR
LCAS
DR
L9217
SLIC
C
B2
0.47
µ
F
R
PR
RING
10
20
19
PR
RGP
14.7 k
Ω
50
Ω
FSX CONTROL
FSR
MCLK
AND
CLOCK
R
TSP
R
VF O
R
GN
9.76 k
2.94 M
Ω
Ω
RTSP
RTSN
Ω
6
RCVN
R
TS1
C
0.015
RTS1
402
Ω
µ
F
1/4 T7504
CODEC
SUPERVISION
OUTPUT
22
NSTAT
R
TSN
3.32 M
B2 13
CONTROL
INPUTS
V
RING
B1 14
B0 15
CF2
11
CF1
12
AGND BGND
16 17
V
BAT
C
F1
0.47
µ
F
C
0.1
F2
µ
F
2797 (F)
*
Placeholder for potential resistor to form filter against PPM generator noise if necessary.
Figure 11. Basic Loop Start Application Circuit Using T7504-Type Codec
Table 10 shows the design parameters of the application circuit shown in Figure 11. Components that are adjusted
to program these values are also shown.
Table 10. 900 Ω Termination, 850 Ω + 50 nF Hybrid First-Generation Codec Design Parameters
Design Parameter
Loop Closure Threshold
Parameter Value
10 mA
Components Adjusted
LCTH
R
PROG
dc Loop Current Limit
ac Termination Impedance
Hybrid Balance Line Impedance
Transmit Gain
20 mA
R
T1
GP
RCV, GP1
900 Ω
R , R , R
R
HB
HB
HB1
850 Ω + 50 nF
0 dBm
C , R , R
T2
X, N1, N2,
N
R , R R
R
C
RCV
GP
, R , R
T1
Receive Gain
–7 dBm
R
Agere Systems Inc.
15
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Applications (continued)
Table 11. Parts List for Loop Start Application Circuit Using T7504-Type Codec
Name
Integrated Circuits
SLIC
Value
Function
L9217
Subscriber loop interface circuit (SLIC).
Secondary protection.
Protector
Agere L7591
Ringing Relay
Codec
Agere L7581/2/3 or EMR
T7504
Switches ringing signals.
First-generation codec.
Overvoltage Protection
PT
R
50 Ω, Fusible
50 Ω, Fusible
Protection resistor.
Protection resistor.
PR
R
Power Supply
BAT1
BAT
C
0.1 µF, 20%, 100 V
0.1 µF, 20%, 10 V
0.47 µF, 20%, 100 V
0.1 µF, 20%, 100 V
V
filter capacitor.
filter capacitor.
F2
CC
CC
V
C
F1
C
With C , improves idle-channel noise.
F2
F1
C
With C , improves idle-channel noise.
dc Characteristics
PROG
R
35.7 kΩ, 1%, 1/16 W
Set low current limit.
ac Characteristics
B1
C
0.47 µF, 20%, 10 V
0.47 µF, 20%, 10 V
0.1 µF, 20%, 10 V
ac/dc separation capacitor.
ac/dc separation capacitor.
dc blocking capacitor.
B2
C
B
C
T1
GP
RCV
R
33.2 kΩ, 1%, 1/16 W
63.4 kΩ, 1%, 1/16 W
14.7 kΩ, 1%, 1/16 W
With R and R , sets ac termination impedance.
RCV
GP
T1
R
With R and R , sets receive gain.
GP
T1
RCV
R
With R and R , sets ac termination impedance
and receive gain.
T2
X
R
45.3 kΩ, 1%, 1/16 W
86.6 kΩ, 1%, 1/16 W
97.6 kΩ, 1%, 1/16 W
0.47 nF, 10%, 10 V
86.6 kΩ, 1%, 1/16 W
8.06 kΩ, 1%, 1/16 W
9.76 kΩ, 1%, 1/16 W
With R , sets transmit gain in codec.
X
T2
R
With R , sets transmit gain in codec.
HB1
R
Sets hybrid balance.
HB
GS
C
With R provides gain shaping for hybrid.
HB
GS
R
With C provides gain shaping for hybrid.
GP1
R
Sets dc transmit gain of SLIC.
dc offset.
GN
R
Meter Pulse
HY
C
4.7 nF, 20%, 10 V
0.01 µF, 20%, 10 V
6.19 kΩ, 1%, 1/16 W
49.9 kΩ, 1%, 1/16 W
Meter pulse rejection.
PPM
C
Meter pulse injection.
PPM
R
Meter pulse rejection.
OVH
R
Increases PPM overhead mode.
Supervision
LCTH
R
22.1 kΩ, 1%, 1/16 W
402 Ω, 5%, 2 W
Sets loop closure (off-hook) threshold.
Ringing source series resistor.
TS1
R
RTS1
TSN
TSP
C
0.015 µF, 20%, 10 V
3.32 MΩ, 1%, 1/16 W
2.94 MΩ, 1%, 1/16 W
With R , R , forms filter pole.
TSN
TSP
R
With R , sets threshold.
TSP
RTS1
With C
TSN
R
, R , sets threshold.
16
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Applications (continued)
A basic loop start reference circuit, using bused ringing with the L9217 SLIC and the T8536 third-generation codec,
is shown in Figure 12.
VBAT CBAT
CHY
4.7 nF
0.1 µF
PPMIN
VCC
CCC
0.1 µF
CPPM
RFLT*
RPROG
0.01 µF
RPPM
6.19 kΩ
OPEN
1
4
9
21
28
35.7 kΩ
RLCTH
IPROG VCC
LCTH
VBAT
PPMIN
PPMOUT
TG
7
26
25
RGP1
8.06 kΩ
22.1 kΩ
8
VTX
TXI
DCOUT
CB
0.1 µF
ROVH
61.9 kΩ
27
OVH (for 3.5 Vrms PPM)
24
23
DX1
RCIN
20 M
1/4 T8536
CODEC
RPT
DX2
DR1
DR2
Ω
TIP
PCM
HIGHWAY
18
PT
VITR
VFXI
50 Ω
CB1 0.1 µF
5
6
L9217
SLIC
RCVP
VFROP
VFRON
SLIC0a
SLIC3a
SLIC2a
SLIC4a
L7591
EMR
LCAS
RCVN
NSTAT
B0
CONTROL
AND
FS
BCLK
VDD
22
15
14
13
RPR
CLOCK
RING
10
20
19
PR
50 Ω
RTSP
2.94 MΩ
CVDD
0.1 µF
B1
RTSP
RTSN
DGND
CRTS1
0.015 µF
RTS1
510 Ω
B2
RTSN
3.4 MΩ
CF2
11
CF1
12
CF1
0.47 µF
AGND BGND
16 17
VRING
CF2
0.1 µF
VBAT
2798 (F)
*
Placeholder for potential resistor to form filter against PPM generator noise if necessary.
Figure 12. Basic Loop Start Application Circuit Using T8536-Type Codec
Agere Systems Inc.
17
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Applications (continued)
Table 12. Parts List for Loop Start Application Circuit Using T8536-Type Codec
Name
Integrated Circuits
SLIC
Value
Function
L9217
Subscriber loop interface circuit (SLIC).
Secondary protection.
Protector
Agere L7591
Ringing Relay
Codec
Agere L7581/2/3 or EMR
T8536
Switches ringing signals.
Third-generation codec.
Overvoltage Protection
PT
R
50 Ω, Fusible
50 Ω, Fusible
Protection resistor.
Protection resistor.
PR
R
Power Supply
BAT1
BAT
C
0.1 µF, 20%, 100 V
0.1 µF, 20%, 10 V
0.47 µF, 20%, 100 V
0.1 µF, 20%, 100 V
V
filter capacitor.
filter capacitor.
F2
CC
CC
V
C
F1
C
With C , improves idle-channel noise.
F2
F1
C
With C , improves idle-channel noise.
dc Characteristics
PROG
R
35.7 kΩ, 1%, 1/16 W
Set low current limit.
ac Characteristics
B1
C
0.1 µF, 20%, 10 V
0.1 µF, 20%, 10 V
8.06 kΩ, 1%, 1/16 W
20 MΩ, 5%, 1/16 W
ac/dc separation capacitor.
dc blocking capacitor.
Sets dc transmit gain of SLIC.
dc bias.
B
C
GP1
R
CIN
R
Supervision
LCTH
R
22.1 kΩ, 1%, 1/16 W
510 Ω, 5%, 2 W
Sets loop closure (off-hook) threshold.
Ringing source series resistor.
TS1
R
RTS1
TSN
TSP
C
0.015 µF, 20%, 10 V
3.4 MΩ, 1%, 1/16 W
2.94 MΩ, 1%, 1/16 W
With R
and R , forms second 2 Hz filter pole.
TSN
TSP
R
With R , sets threshold.
TSP
TSN
R
With R , sets threshold.
Meter Pulse
HY
C
4.7 nF, 20%, 10 V
0.01 µF, 20%, 10 V
6.19 kΩ, 1%, 1/16 W
61.9 kΩ, 1%, 1/16 W
Meter pulse rejection.
PPM
C
Meter pulse injection.
PPM
R
Meter pulse rejection.
OVH
R
Increases PPM overhead mode.
18
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Starting from the on-hook condition and going through
to a short circuit, the curve passes through the follow-
ing two regions:
Applications (continued)
dc Applications
Region 1: On-hook and low-loop currents. The slope
Battery Feed
dc1
corresponds to the dc resistance of the SLIC, R
(default is 72 Ω typical). The open circuit voltage is
the battery voltage minus the overhead voltage of the
The dc feed characteristic can be described by:
OH
device, V (default is 6.5 V typical). These values are
BAT
OH
L
( V
– V ) × R
suitable for most applications but can be adjusted if
needed.
T/R
V
= ---------------------------------------------
L
P
dc
R + 2R + R
Region 2: Current limit. The dc current is limited to a
BAT
OH
V
– V
L
I = ---------------------------------
PROG
starting value determined by external resistor R
,
L
P
dc
R + 2R + R
an internal current source, and the gain from tip/ring to
pin VITR. Current limit with a 100 Ω load is set by the
following equation:
where:
L
I = dc loop current.
T/R
V
= dc loop voltage.
PROG
LIM
0.637 R
(kΩ) + 2 mA = I x (mA)
|VBAT| = battery voltage magnitude.
OH
V
= overhead voltage. This is the difference between
the battery voltage and the open loop tip/ring
voltage.
Overhead Voltage
In order to drive an on-hook ac signal, the SLIC must
set up the tip and ring voltage to a value less than the
battery voltage. The amount that the open loop voltage
is decreased relative to the battery is referred to as the
overhead voltage. This is expressed as the following
equation:
L
R = loop resistance, not including protection resistors.
P
R = protection resistor value.
dc
R
= SLIC internal dc feed resistance.
50
OH
V
BAT
PT
PR
= |V | – (V – V )
40
Without this buffer voltage, amplifier saturation will
occur and the signal will be clipped. In modes without
PPM, the L9217 is set to allow undistorted on-hook
transmission of a 3.17 dBm signal into a 900 Ω loop
impedance. A minimum 11.1 V overhead is needed to
pass 3.5 Vrms meter pulse.
ILIM TESTED
ILIM ONSET
1
30
20
12.5 kΩ
–1
Rdc1
10
0
In high overhead and PPM modes, overhead is auto-
matically increased to accommodate on-hook trans-
mission of meter pulse signals. The increase in
overhead is set by a resistor from pin OVH to ground.
This is expressed as the following equation:
0
10
20
30
40
50
LOOP VOLTAGE (V)
12-3050 (F).i
OVH
OVH
V
(V) = 6.37 + 0.09535 x R
(kΩ)
Note: VBAT = –48 V; ILIM = 22 mA; Rdc1 = 115 Ω.
Figure 13. Loop Current vs. Loop Voltage
Agere Systems Inc.
19
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Off-Hook Detection
Applications (continued)
The loop closure detection threshold is set by resistor
dc Applications (continued)
LCTH
R
. The supervision output bit NSTAT is high in an
on-hook condition. The off-hook comparator goes low
during an off-hook condition:
Rate of Battery Reversal
The rate of battery reversal is controlled or ramped by
capacitors FB1 and FB2. A chart showing FB1/FB2 val-
ues versus typical ramp rate is given below. Leave
FB1/FB2 open if it is not desired to ramp the rate of
battery reversal.
TR
LTCH
I
I
(mA) = 0.4167 R
(kΩ) –1.9 mA
ACTIVE off-hook to on-hook
TR
LTCH
(mA) = 0.4167 R
(kΩ) + 2.7 mA
SCAN on-hook to off-hook
Table 13. FB1/FB2 Values vs. Typical Ramp Time
RP
CFB1/CFB2
0.01 µF
0.1 µF
Transition Time
20 ms
TIP
0.125 V/mA
ITR
DCOUT
+
–
220 ms
440 ms
900 ms
1.8 s
RL
RLCTH
0.22 µF
0.47 µF
1.0 µF
RING
LCTH
NSTAT
RP
+
–
0.05 mA
1.22 µF
1.3 µF
2.25 s
2.5 s
1.4 µF
2.7 s
12-2553 (F)
1.6 µF
3.2 s
Loop Range
Figure 14. Off-Hook Detection Circuit
The equation below can be rearranged to provide the
loop range for a required loop current:
BAT
OH
V
– V
L
----------------------------
P
DC
R =
– 2R – R
L
I
20
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Applications (continued)
dc Applications (continued)
Ring Trip Detection
The ring trip circuit is a comparator that has a special input section optimized for this application. The equivalent
circuit is shown in Figure 15, along with its use in an application using unbalanced, battery-backed ringing.
PHONE
HOOK SWITCH
RLOOP
RTSP
+
–
RTSP
2.94 M
Ω
NSTAT
RC PHONE
IP = IN
IN
RS
402 510
CRTS1
8.6 V
+
–
Ω/
Ω
0.015
F
µ
VBAT
VRING
RTSN
RTSN
15 k
Ω
3.32 M 3.40 M
Ω/
Ω
2799 (F)
Figure 15. Ring Trip Equivalent Circuit and Equivalent Application
Ring trip detection threshold is given by the following equation:
[RTSN(MΩ) + 0.015 – RTSP(MΩ)] × [ VBAT – 8.6] × 1000
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
(mA) =
TH
I
[RTSN(MΩ) + 0.015] × RS
Longitudinal Balance
The SLIC is graded to certain longitudinal balance specifications. The numbers are guaranteed by testing (Figure 5
and Figure 8). However, for specific applications, the longitudinal balance may also be determined by termination
impedance, protection resistance, and especially by the mismatch between protection resistors at tip and ring. This
can be illustrated by the following equation:
(368 + RP) × (368 + ZT – RP)
368 × (2 × [ZT – 2 × RP] × ∆ + ε)
------------------------------------------------------------------------------------------
LB = 20 x log
where:
LB: longitudinal balance.
RP: protection resistor value in Ω.
ZT: magnitude of the termination impedance in Ω.
ε: protection resistor mismatch in Ω.
∆: SLIC internal tip/ring sensing mismatch.
The ∆ can be calculated using the above equation with these exceptions: ε = 0, ZT = 600 Ω, RP = 100 Ω, and the
longitudinal balance specification on a specific code.
Now with ∆ available, the equation will predict the actual longitudinal balance for RP, ZT, and ε.
Be aware that ZT may vary with frequency for complex impedance applications.
Agere Systems Inc.
21
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
PPM input signals may be a maximum 0.525 Vrms at
PPMIN. The gain from PPMIN tip/ring is 10. Thus, for
2.5 Vrms at tip and ring, apply a 0.375 Vrms signal at
PPMIN. The PPM signal should be ac coupled to
PPMIN through a 0.01 µF capacitor.
Applications (continued)
Periodic Pulse Metering (PPM)
Periodic pulse metering (PPM), also referred to as
TTX, is input to the PPMIN input of the L9217. Upon
application of appropriate logic control, this signal is
presented to the tip/ring subscriber loop. The state of
the L9217 may be changed while applying PPM sig-
nals. The L9217 assumes that a shaped PPM signal is
applied to the PPMIN input.
When applied to tip and ring, the PPM signal will also
be returned through the SLIC and will appear at the
SLIC VITR output. The concern is that this high-voltage
signal can overload the codec input and cause distor-
tion of the (desired) ac signal. Therefore, some sort of
PPM rejection scheme must be employed, see Figure
1. The L9217 outputs on the PPMOUT pin, which is the
output of the PPM input amplifier. Connecting a resis-
tor, RPPM, from PPMOUT to node TG will provide a path
for a hybrid reject of the returned meter pulse signal.
The return path from tip and ring to VITR for the PPM
signal is through the internal AX amplifier. TG is the
PPM
Sufficient drive current is available in the tip and ring
drive amplifiers to support 3.5 Vrms PPM signals into a
200 Ω load with a 45 mA dc current limit.
PPM signals are input to a separate PPMIN input. This
input is controlled via the logic table. PPMIN is off dur-
ing all states except the forward/reverse PPM active
state. Thus, PPM signals may be present at all times,
even during non-PPM active times. To apply PPM to
tip/ring, from a normal overhead state first switch to a
high overhead state without PPM; the overhead volt-
age at tip/ring will increase to 7 V to 13 V. The ramp up
time of the overhead increase is on the order of hun-
dreds of milliseconds. Thus, wait 1 s before applying
the PPM signal by going to a PPM active high over-
head state. Once in a high overhead, there is no timing
requirement in switching in and out of a PPM active
mode. Without the initial 1 s delay, AT/AR will get into
saturation and PPM signal at T/R will get distorted, pro-
ducing crosstalk in the handset.
input to this amplifier. Through R
, by applying a
PPM signal equal in magnitude, but 180 degrees out of
phase to the returned PPM signal at TG, the PPM sig-
nal is cancelled, preventing overload at the codec
input. Even if the cancellation is not perfect, the idea is
to reduce the PPM signal so as not to overload the
codec. Codecs typically have a low-pass filter at their
input to reject any residual meter pulse signal.
PPM
The value of R
is selected by:
–1
PPM
PPMIN
PPMLOAD
DC
P
R
= [{(V
x 10)/(R
+ R + 2R )}/201.2]
For undistorted transmission of meter pulse signals,
increase the overhead as described in the Overhead
Voltage section of this data sheet.
22
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
ac Interface Network
Applications (continued)
The ac interface network between the L9217 and the
codec will vary depending on the codec selected. With
a first-generation codec, the interface between the
L9217 and codec actually sets the ac parameters. With
a third-generation codec, all ac parameters are set dig-
itally, internal to the codec; thus, the interface between
the L9217 and this type of codec is designed to avoid
overload at the codec input in the transmit direction,
and to optimize signal-to-noise ratio (S/N) in the
receive direction.
ac Design
Codec Types
At this point in the design, the codec needs to be
selected. The interface network between the SLIC and
codec can then be designed. There are four key ac
design parameters. Termination impedance is the
impedance looking into the 2-wire port of the line card.
It is set to match the impedance of the telephone loop
in order to minimize echo return to the telephone set.
Transmit gain is measured from the 2-wire port to the
PCM highway, while receive gain is done from the PCM
highway to the transmit port. Finally, the hybrid balance
network cancels the unwanted amount of the receive
signal that appears at the transmit port.
Receive Interface
Because the design requirements are very different
with a first- or third-generation codec, the L9217 is
offered with two different receive gains. Each receive
gain was chosen to optimize, in terms of external com-
ponents required, the ac interface between the L9217
and the codec.
Below is a brief codec feature summary.
First-Generation Codecs. These perform the basic fil-
tering, A/D (transmit), D/A (receive), and µ-law/A-law
companding. They all have an op amp in front of the
A/D converter for transmit gain setting and hybrid bal-
ance (cancellation at the summing node). Depending
on the type, some have differential analog input stages,
differential analog output stages, 5 V only or ±5 V oper-
ation, and µ-law/A-law selectability. These are avail-
able in single and quad designs. This type of codec
requires continuous time analog filtering via external
resistor/capacitor networks to set the ac design param-
eters. An example of this type of codec is the Agere
T7504 quad 5 V only codec.
With a first-generation codec, the termination imped-
ance is set by providing gain shaping through a feed-
back network from the SLIC VITR output to the SLIC
RCVN/RCVP inputs. The L9217 provides a transcon-
ductance from T/R to VITR in the transmit direction and
a single ended to differential gain in the receive direc-
tion from either RCVN or RCVP to T/R. Assuming a
short from VITR to RCVN or RCVP, the maximum
impedance that is seen looking into the SLIC is the
product of the SLIC transconductance times the SLIC
receive gain, plus the protection resistors. The various
specified termination impedance can range over the
voice band as low as 300 Ω up to over 1000 Ω. Thus, if
the SLIC gains are too low, it will be impossible to syn-
thesize the higher termination impedances. Further-
more, the termination that is achieved will be far less
than what is calculated by assuming a short for SLIC
output to SLIC input. In the receive direction, in order to
control echo, the gain is typically a loss, which requires
a loss network at the SLIC RCVN/RCVP inputs, which
will reduce the amount of gain that is available for ter-
mination impedance. For this reason a high-gain SLIC
is required with a first-generation codec.
This type of codec tends to be the most economical in
terms of piece part price, but tends to require more
external components than a third-generation codec.
Furthermore, ac parameters are fixed by the external
R/C network, so software control of ac parameters is
difficult.
Third-Generation Codecs. This class of devices
includes all ac parameters set digitally under micropro-
cessor control. Depending on the device, it may or may
not have data control latches. Additional functionality
sometimes offered includes tone plant generation and
reception, TTX generation, test algorithms, and echo
cancellation. Again, this type of codec may be 5 V
only or ±5 V operation, single quad or 16-channel, and
µ-law/A-law or 16-bit linear coding selectable. Exam-
ples of this type of codec are the Agere T8535/6 (5 V
only, quad, standard features), T8533/4 (5 V only, quad
with echo cancellation), and the T8531/36 (5 V only
16-channel with self-test).
Agere Systems Inc.
23
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
S/N. The problem is, if the codec is feeding a high-gain
SLIC, either an external resistor divider is needed to
knock the gain down to meet the TLP requirements, or
the codec is not operating near maximum signal levels,
thus compromising the S/N.
Applications (continued)
ac Design (continued)
Receive Interface (continued)
It appears the solution is to have a SLIC with a low
gain, especially in the receive direction. This will allow
the codec to operate near its maximum output signal
(to optimize S/N), without an external resistor divider
(to minimize cost).
With a third-generation codec, the line card designer
has different concerns. To design the ac interface, the
designer must first decide upon all termination imped-
ance, hybrid balances, and transmission level points
(TLP) requirements that the line card must meet. In the
transmit direction, the only concern is that the SLIC
does not provide a signal that is too hot and overloads
the codec input. Thus, for the highest TLP that is being
designed to, given the SLIC gain, the designer, as a
function of voice band frequency, must ensure that the
codec is not overloaded. With a given TLP and a given
SLIC gain (if the signal will cause a codec overload),
the designer must insert some sort of loss, typically a
resistor divider, between the SLIC output and codec
input.
Note also that some third-generation codecs require
the designer to provide an inherent resistive termina-
tion via external networks. The codec will then provide
gain shaping, as a function of frequency to meet the
return loss requirements. Further stability issues may
add external components or excessive ground plane
requirements to the design.
To meet the unique requirements of both types of
codecs, the L9217 offers two receive gain choices.
These receive gains are mask programmable at the
factory and are offered as two different code variations.
For interface with a first-generation codec, the L9217A
is offered with a receive gain of 7.86. For interface with
a third-generation codec, the L9217G is offered with a
receive gain of 2. In either case, the transconductance
in the transmit direction, or the transmit gain is 403 Ω.
In the receive direction, the issue is to optimize S/N.
Again, the designer must consider all the considered
TLPs. The idea is, for all desired TLPs, to run the
codec at or as close as possible to its maximum output
signal, to optimize the S/N. Remember noise floor is
constant, so the hotter the signal from the codec, the
better the
Example 1: Real Termination (First-Generation Codec)
ac equivalent circuits for real termination using a T7504 codec is shown in Figure 15.
RX
VGSX
–0.403 V/mA
RT2
VFXIN
VFXIP
–
+
VITR
RT1
RCVN
RHB1
2.4 V
–
–
ZT/R
RP
TIP
AV =
3.93
AV = 1
RRCV
RCVP
VFR
+
+
IT/R
+
CURRENT
SENSE
VS
ZT
VT/R
RG
–
+
AV = –1
–
RP
RING
L9217 SLIC
1/4 T7504 CODEC
12-3581 (F).Cm
Figure 16. ac Equivalent Circuit
24
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Applications (continued)
ac Design (continued)
Example 1: Real Termination (First-Generation Codec) (continued)
The following design equations refer to the circuit in Figure 16. Use these to synthesize real termination imped-
ance.
Termination Impedance:
T ⁄ R
V
–I
--------------
ZT =
T ⁄ R
3168
P
ZT = 2R +
----------------------------------
T3
T3
R
R
1 + -------- + -----------
GP
RCV
R
R
Receive Gain:
T ⁄ R
V
-------------
rcv
g
g
=
=
fr
V
7.86
-------------------------------------------------------------------------------------
rcv
RCV
RCV
R
R
Z
T
Z
T/R
1 + --------------- + --------------- 1 + ------------
T3
GP
R
R
Transmit Gain:
GSX
V
--------------
tx
g =
T ⁄ R
V
X
R
R
403
----------
x
----------
tx
g =
T6
Z
T
Hybrid Balance:
GSX
V
--------------
bal
h
= 20log
T ⁄ R
V
To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0.
The following expressions assume the test network is the same as the termination impedance:
X
R
------------------------
HB
R
=
tx × rcv
g
g
X
R
R
-----------
bal
h
tx × rcv
g
= 20log
– g
HB
Agere Systems Inc.
25
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Applications (continued)
ac Design (continued)
Example 2: Complex Termination (First-Generation Codec)
Below are design equations for complex termination (see Figure 17 and Figure 18).
7.86
-----------
201.2
1
1
---------------------------------- -----------------
T1
T2
P
TGP
TGS
R
R
= 2R +
•
–
R
|| R
T3
T3
N1
R
R
R
1 +
+
-------- -----------
--------
1 +
GP
RCV
N2
R
R
R
TGP
TGS
7.86
201.2
R
⁄ R
1
TGP
R
TGS
|| R
= ----------- + ---------------------------------- + -----------------
T3
T3
N1
R
R
R
1 +
+
-------- -----------
--------
1 +
GP
RCV
N2
R
R
R
2
N2
TGP
1
7.86
201.2
1
R
N1
1
CTG
R
TGP
1
T3
1
TGP ||
------
CT
---------------- ----------------------------------------------
---------- ------------------------------------
---------------------------------------------- ---------------------
–
TGS
•
•
=
R
R
+
C
N1
TGS
T3
N1
R
+ R
R
R
R
(
R
N2)2
+ R
1 + ----------- + ---------------
----------
1 +
GP
RCV
N2
R
R
R
X
TG
R
R
1
Z
---------- ---------------- ----------
tx
g =
T6
201.2
Z
T
7.86
1
----------------------------------------------- -----------------------
rcv =
g
×
RCV
RCV
T
R
R
Z
--------------- ---------------
-------------
1 +
+
1 +
T3
GP
T ⁄ R
R
R
Z
X
R
R
-----------
bal
h
tx × rcv
= 20log
– g
g
HB
where:
T/R
1
2
Z
Z
= R + R || C
TG
TGP
TGS
G
= R
|| (R
+ C )
TGP
R
R
= 8.06 kΩ
1
R
-------
TGS
TGP
R
=
2
R
2
2
R
TGP(
------------------------------------------
G
C =
x C
1
2)
R
R + R
and
P
2R
N
N2
G
TGP
C R = ------------ C R
3167
TGS
R
R
3167
------------
-------------
N1
N2
R
= R
– 1
TGP
P
2R
The equations above do not include the blocking capacitors.
26
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Applications (continued)
ac Design (continued)
Example 2: Complex Termination (First-Generation Codec) (continued)
RTGS
CGS
RX
RTGP = 8.06 k
AX
Ω
–IT/R
201.2
CB1
R
T6
–
+
CODEC
OP AMP
CN
RT3
RN1
RN2
RCVN
RCVP
CODEC
OUTPUT
DRIVE
AMP
RRCV
RGP
5-6401 (F).l
Figure 17. Interface Circuit Using First-Generation Codec (±5 V Codec)
RTGS
CG
Rx
RTGP = 8.06 k
AX
Ω
–IT/R
201.2
RT6
–
+
CB1
CODEC
OP AMP
–2.4 V
CN
RT3
RN1
RN2
RCVN
RCVP
CODEC
RRCV
OUTPUT
DRIVE
AMP
CB2
RGP
5-6400 (F).o
Figure 18. Interface Circuit Using First-Generation Codec (5 V Only Codec)
Agere Systems Inc.
27
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Loop power = (25 mA • 1.08)2 •
Applications (continued)
(200 Ω + 100 Ω)
Power Derating
Loop power = 0.219 W
SLIC power = 1.579 W – 0.219 W = 1.36
SLIC power = 1.36 W < 1.51 W
Operating temperature range, maximum current limit,
maximum battery voltage, minimum dc loop, and pro-
tection resistor values will influence the overall thermal
performance. This section shows the relevant design
equations and considerations in evaluating the SLIC
thermal performance.
Thus, in this example, the thermal design ensures that
the SLIC will not enter the thermal shutdown state.
Consider the L9217 SLIC in a 28-pin PLCC package.
The thermal resistance on a 2-layer board with natural
convection is 43 °C/W.
Pin-for-Pin Compatibility with L9218/L9219
The L9217 can be a pin-for-pin replacement for the
L9218/L9219. The exceptions are as follows: L9217
has three logic control inputs: B0, B1, and B2. The
L9218 has only two logic control inputs: B0 and B1. Pin
13 in L9218 is NC, so a connection between the con-
troller and pin 13 will not affect L9218 operation. In
L9217, pin 28 is PPMOUT, pin 21 is PPMIN, and pin 27
is OVH. In L9218/9, pin 28 is NC, pin 21 is NC, and pin
27 is TSD
The SLIC will enter the thermal shutdown state at a
minimum of 150 °C. The thermal shutdown design
should ensure that the SLIC temperature does not
reach 150 °C under normal operating conditions.
Assume a maximum ambient operating temperature of
85 °C, a design current limit of 25 mA, and a maximum
battery of –52 V. Furthermore, assume a (worst-case)
minimum dc loop of 200 Ω, and that 50 Ω protection
resistors are used at both tip and ring.
PCB Layout Information
TSD
AMBIENT(max)
– T
1. T
= allowed thermal rise.
150 °C – 85 °C = 65 °C
BAT
Make the leads to BGND and V
as wide as possible
for thermal and electrical reasons. Also, maximize the
amount of PCB copper in the area of (and specifically
on) the leads connected to this device for the lowest
operating temperature.
2. Allowed thermal rise = package thermal
impedance • SLIC power dissipation.
65 °C = 43 °C/W • SLIC power dissipation
DISS
SLIC power dissipation (P
) = 1.51 W
When powering the device, make certain that no exter-
nal potential creates a voltage on any pin of the device
that exceeds the device ratings. In this application,
some of the conditions that cause such potentials dur-
ing powerup are the following:
Thus, if the total power dissipated in the SLIC is less
than 1.51 W, it will not enter the thermal shutdown
state. Total SLIC power is calculated as:
DISS
Total P
•
= Maximum battery maximum
1. An inductor connected to PT and PR (this can force
current limit (including effects of accuracy)
+ SLIC quiescent power
BAT
an overvoltage on V
through the protection
BAT
devices if the V
connection chatters).
BAT
2. Inductance in the V
lead (this could resonate
Q
For the L9217, SLIC quiescent power (P ) is maximum
at 0.175 W. Thus,
BAT
with the V
filter capacitor to cause a destructive
overvoltage).
DISS
DISS
DISS
•
•
Total P
Total P
Total P
= (–52 V [25 mA 1.08]) + 0.175 W
= 1.404 W + 0.175 W
= 1.579 W
This device is normally used on a circuit card that is
subjected to hot plug-in, meaning the card is plugged
into a biased backplane connector. In order to prevent
damage to the IC, all ground connections must be
applied before, and removed after, all other connec-
tions.
The power dissipated in the SLIC is the total power dis-
sipation minus the power that is dissipated in the loop.
DISS
SLIC P
= Total power – loop power
2
LIM
•
dcLOOP
P
Loop power = (I
)
(R
min + 2R )
28
Agere Systems Inc.
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Outline Diagram
28-Pin PLCC
Dimensions are in millimeters.
12.446 ± 0.127
11.506 ± 0.076
PIN #1 IDENTIFIER
ZONE
4
1
26
25
5
11.506
± 0.076
12.446
± 0.127
11
19
12
18
4.572
MAX
SEATING PLANE
0.10
0.51 MIN
TYP
1.27 TYP
0.330/0.533
5-2506 (F) r.8
Agere Systems Inc.
29
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Data Sheet
November 2001
Ordering Information
Device
Package
Comcode
LUCL9217AAR-DT
28-Pin PLCC
(Tape & Reel, Dry-bagged)
Gain of 8
108760737
108760729
108760760
108760752
LUCL9217AAR-D
LUCL9217GAR-DT
LUCL9217GAR-D
28-Pin PLCC
(Dry-bagged)
Gain of 8
28-Pin PLCC
(Tape & Reel, Dry-bagged)
Gain of 2
28-Pin PLCC
(Dry-bagged)
Gain of 2
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
HP is a registered trademark of Hewlett-Packard Company.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
E-MAIL:
http://www.agere.com
docmaster@agere.com
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA:
Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
Tel. (44) 7000 624624, FAX (44) 1344 488 045
EUROPE:
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
November 2001
DS02-038ALC (Replaces DS02-002ALC)
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