CA16_技术文档

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

■ Multiple alarms:

— Loss of signal.

— Loss of reference clock.

— Loss of framing.

— Laser degrade alarm.

Applications

■ Telecommunications:

— Inter- and intraoffice SONET/SDH

— Subscriber loop

— Metropolitan area networks

■ High-speed data communications

The CA16-type transponders integrate up to 15 discrete

ICs and optical components, including a 2.5Gbits/s op-

tical transmitter and receiver pair, all in a single, com-

pact package.

Description

The CA16-type transponder performs the parallel-to-

serial-to-optical transport and optical transport-to-

serial-to-parallel function of the section and photonic

layers of the SONET/SDH protocol. The CA16 trans-

mitter section performs the bit serialization and opti-

cal transmission of SONET/SDH OC-48/STM-16

data that has been formatted into standard SONET/

SDH compliant 16-bit parallel format. The CA16

receiver performs the optical-to-electrical conversion

function and is then able to detect frame and byte

boundaries and demultiplex the serial data into 16-bit

parallel OC-48/STM-16 format.

Features

■ 2.5 Gbits/s optical transmitter and receiver with

16-channel 155 Mbits/s multiplexer/demultiplexer.

■ Available with 1.55 µm cooled DFB laser transmit-

ter and an APD receiver for long-reach applica-

tions:

— Offers 45 standard ITU wavelengths with

100 GHz spacing.

— Each module is capable of two wavelengths

under user control.

The CA16 transponder does not perform byte-level

multiplexing or interleaving.

■ Pigtailed, low-profile package.

■ Differential LVPECL data interface.

■ Operating case temperature range: 0 °C to 65 °C.

■ Automatic transmitter optical power control.

■ Laser bias monitor output.

■ Transmitter laser disable input.

■ Line loopback and diagnostic loopback capability.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Table of Contents

Contents

Page

Tables

Page

Features ................................................................... 1

Applications .............................................................. 1

Description ............................................................... 1

Absolute Maximum Ratings ...................................... 3

Block Diagram........................................................... 4

Pin Information ......................................................... 5

Pin Descriptions....................................................... 6

Functional Description ........................................... 12

Receiver ............................................................ 12

Transmitter ........................................................ 12

Loopback Modes............................................... 13

Transponder Interfacing ..................................... 13

Optical Characteristics ........................................... 15

Electrical Characteristics ........................................ 16

Timing Characteristics ........................................... 18

Transmitter Data Input Timing ........................... 18

Input Timing Mode 1 .......................................... 19

Input Timing Mode 2 .......................................... 20

Forward Clocking ............................................... 21

PCLK-to PICLK Timing ........................................ 22

PHERR/PHINIT.................................................. 23

Receiver Framing............................................... 25

Wavelength Selection ............................................. 26

Qualification and Reliability .................................... 27

Laser Safety Information ....................................... 27

Class I Laser Product......................................... 27

Electromagnetic Emissions and Immunity.......... 27

Outline Diagram ..................................................... 28

Ordering Information .............................................. 29

Related Product Information ................................... 29

Table 1. CA16-Type Transponder Pinout .................6

Table 2. CA16-Type Transponder Input Pin

Descriptions...............................................10

Table 3. CA16-Type Transponder Output Pin

Descriptions ...............................................11

Table 4. OC-48/STM-16 Transmitter Optical

Characteristics ..........................................15

Table 5. OC-48/STM-16 Receiver Optical

Characteristics ..........................................15

Table 6. Power Supply Characteristics....................16

Table 7. Transmitter Electrical I/O Characteristics...16

Table 8. Receiver Electrical I/O Characteristics ......17

Table 9. Transmitter ac Timing Characteristics .......24

Table 10. Receiver ac Timing Characteristics .........24

Table 11. Ordering Information................................29

Table 12. Related Product Information ....................29

Figures

Page

Figure 1. CA16-Type Transponder Block Diagram....4

Figure 2. CA16-Type Transponder Pinout.................5

Figure 3. Transponder Interfacing............................13

Figure 4. Interfacing to the TXREFCLK Input.............14

Figure 5. Block Diagram Timing Mode 1..................19

Figure 6. Block Diagram Timing Mode 2..................20

Figure 7. Forward Clocking of the

CA16 Transponder ..................................21

Figure 8. PCLK-to PICLK Timing...............................22

Figure 9. PHERR/PHINIT Timing.............................23

Figure 10. ac Input Timing .......................................24

Figure 11. Receiver Output Timing Diagram ...........24

Figure 12. Frame and Byte Detection......................25

Figure 13. OOF Timing (FRAMEN = High) ..............25

Figure 14. FRAMEN Timing.....................................26

2

Agere Systems Inc..

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

The optical transmitter is available at any ITU grid

wavelength with a 1.55 µm cooled DFB laser for long-

reach applications. The optical output signal is SONET

and ITU compliant for OC-48/STM-16 applications as

shown in Table 4, OC-48/STM-16Transmitter Optical

Characteristics.

Description (continued)

Figure 1 shows a simplified block diagram of the CA16-

Type transponder. This device is a bidirectional module

designed to provide a SONET or SDH compliant elec-

tro-optical interface between the SONET/SDH photonic

physical layer and the electrical section layer. The mod-

ule contains a wavelength-tunable (two channels at

100 GHz) 2.5 Gbits/s optical transmitter and a

2.5 Gbits/s optical receiver in the same physical pack-

age along with the electronics necessary to multiplex

and demultiplex sixteen 155 Mbits/s electrical channels.

Clock synthesis, clock recovery, and SONET/SDH

frame detection circuits are also included within the

module.

In the receive direction, the transponder module

receives a 2488.32 Mbits/s optical signal and converts

it to an electrical signal, and then extracts a clock sig-

nal and demultiplexes the data into sixteen 155 Mbits/s

differential LVPECL data signals. When enabled, the

module can also detect SONET/SDH frame bound-

aries. The optical receiver is available with an APD

photodetector. The receiver operates over the wave-

length range of 1.1 µm to 1.6 µm and is fully compliant

to SONET/SDH OC-48/STM-16 physical layer specifi-

cations as shown in Table 5, OC-48/STM-16 Receiver

Optical Characteristics.

In the transmit direction, the transponder module multi-

plexes sixteen 155 Mbits/s PECL electrical data signals

into an optical signal at 2488.32 Mbits/s for launching

into optical fiber. An internal 2.488 GHz reference oscil-

lator is phase-locked to an external 155.52 MHz data

timing reference.

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect reliability.

Parameter

Symbol

Min

Max

Unit

Operating Case Temperature Range

Storage Case Temperature Range

Supply Voltage

T^C

T^S

0

75

85

°C

–40

—

–0.5

5.5

V^CC

50

V

Voltage on Any LVPECL Pin

—

0

—

High-speed LVPECL Output Source Current

—

mA

V

1

Static Discharge Voltage

ESD

RH

P^IN

—

500

85

Relative Humidity (noncondensing)

Receiver Optical Input Power—Biased APD

Minimum Fiber Bend Radius

—

%

0

dBm

in. (mm)

1.25 (31.8)

—

1. Human body model.

3

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Block Diagram

WS (WAVELENGTH

SELECT)

TXDIS

WDEA

LSR ALRM

LPM

16

TXD[0:15]P

16:1 PARALLEL

16

TO SERIAL

TXD[0:15]N

D

OC-48/STM-16

2

PICLKP/N

PHINIT

OPTICAL TRANSMITTER

TIMING

GENERATION

PHERR

PCLKP/N

2

TXREFCLKP/N

CLOCK DIVIDER

AND

PHASE DETECT

LOCKDET

LLOOP

RESET

DLOOP

OOF

FRAMEN

SEARCH

FP

FRAME/BYTE

DETECT

TIMING

GEN

2

POCLKP/N

CK

OC-48/STM-16

OPTICAL RECEIVER

W/CLOCK RECOVERY

16

RXQ[0:15]P

RXQ[0:15]N

D

1:16 SERIAL

TO PARALLEL

LOS

IPDMON

1-1011(F).f

Figure 1. CA16-Type Transponder Block Diagram

4

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Pin Information

80

FGND

NC

FGND

160

150

140

130

120

110

100

NC

RXDGND

RXQ00N

RXQ00P

RXQ02N

RXQ02P

RXDGND

RXQ04N

RXQ04P

RXQ06N

RXQ06P

RXDGND

RXQ08N

RXQ08P

RXQ10N

RXQ10P

RXDGND

RXQ12N

RXQ12P

RXQ14N

RXQ14P

RXDGND

VTEC

RXDGND

RXQ01N

RXQ01P

RXQ03N

RXQ03P

RXDGND

RXQ05N

RXQ05P

RXQ07N

RXQ07P

RXDGND

RXQ09N

RXQ09P

RXQ11N

RXQ11P

RXDGND

RXQ13N

RXQ13P

RXQ15N

RXQ15P

RXDGND

VTEC

70

60

50

40

30

20

RX

VTEC

WS

RXDGND

RXAGND

RX3.3A

RXAGND

NC

POCLKN

POCLKP

RX3.3A

RXAGND

SEARCH

RX3.3D

RXDGND

OOF

RX3.3D

RXDGND

FRAMEN

FP

WDEA

DLOOP

NC

RXDGND

LOS

LLOOP

PHERR

NC

TXDIS

PHINIT

NC

TX3.3A

TX3.3D

TXAGND

TXDGND

PCLKN

PCLKP

TXDGND

TXD00N

TXD00P

TXDGND

TXD02N

TXD02P

TXD04N

TXD04P

TXDGND

TXD06N

TXD06P

TXD08N

TXD08P

TXDGND

TXD10N

TXD10P

TXD12N

TXD12P

TXDGND

TXD14N

TXD14P

TXREFCLKN

TXREFCLKP

TXDGND

RESET

FGND

LSRBIAS

LSRALM

LPM

TXAGND

TX3.3A

TXAGND

TX3.3D

TXDGND

LOCKDET

PICLKN

PICLKP

TXDGND

TXD01N

TXD01P

TXD03N

TXD03P

TXDGND

TXD05N

TXD05P

TXD07N

TXD07P

TXDGND

TXD09N

TXD09P

TXD11N

TXD11P

TXDGND

TXD13N

TXD13P

TXD15N

TXD15P

TXDGND

IPDMON

FGND

TX

90

81

10

TOP VIEW

1

1-1014(F).d

Figure 2. CA16-Type Transponder Pinout

5

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Pin Descriptions

Table 1. CA16-Type Transponder Pinout

Pin #

Pin Name

I/O

Logic

Description

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

FGND

IPDMON

TxDGND

TxD15P

TxD15N

TxD13P

TxD13N

TxDGND

TxD11P

TxD11N

TxD09P

TxD09N

TxDGND

TxD07P

TxD07N

TxD05P

TxD05N

TxDGND

TxD03P

TxD03N

TxD01P

TxD01N

TxDGND

PICLKP

PICLKN

LOCKDET

TxDGND

Tx3.3D

I

O

I

Supply

Analog

Supply

Frame Ground¹

Receiver Photodiode Current Monitor

Transmitter Digital Ground

I

LVPECL Transmitter 155 Mbits/s MSB Data Input

LVPECL Transmitter 155 Mbits/s Data Input

I

Supply

Transmitter Digital Ground

I

LVPECL Transmitter 155 Mbits/s Data Input

SUPPLY Transmitter Digital Ground

I

LVPECL Transmitter 155 Mbits/s Data Input

I

Supply

Transmitter Digital Ground

I

LVPECL Transmitter 155 Mbits/s Data Input

I

Supply

Transmitter Digital Ground

I

LVPECL Byte-Aligned Parallel Input Clock at 155 MHz

I

O

I

LVTTL

Supply

Analog

Lock Detect

Transmitter Digital Ground

Transmitter 3.3 V Digital Supply

Transmitter Analog Ground

Transmitter 3.3 V Analog Supply

Transmitter Analog Ground

Laser Power Monitor

I

Tx3.3D

I

TxAGND

Tx3.3A

I

Tx3.3A

I

TxAGND

LPM

I

O

—

I

LSRALM

LSRBIAS

NC

5 V CMOS Laser Degrade Alarm

Analog

—

Not Implemented on the CA16-TypeTransponder

No User Connection Permitted²

DLOOP

LVTTL

Diagnostic Loopback

WDEA

O

I

5 V CMOS Wavelength Deviation Error Alarm

LVPECL Frame Pulse

FP

FRAMEN

LVTTL

Frame Enable

1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).

2. Pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to VCC, Ground,

or any signal node.

6

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Pin Descriptions (continued)

Table 1. CA16-Type Transponder Pinout (continued)

Pin #

Pin Name

I/O

Logic

Description

Receiver Digital Ground

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

RxDGND

Rx3.3D

NC

I

Supply

—

Receiver 3.3 V Digital Supply

No User Connection Permitted²

Receiver Analog Ground

I

—

I

RxAGND

Rx3.3A

RxAGND

RxDGND

VTEC

Supply

I

Receiver Analog Ground

I

Receiver 3.3 V Analog Supply

Receiver Analog Ground

I

Receiver Analog Ground

I

Receiver Digital Ground

I

TEC Cooler 3 V Analog Supply Voltage

Receiver Digital Ground

VTEC

I

VTEC

I

RxDGND

RxQ14P

RxQ14N

RxQ12P

RxQ12N

RxDGND

RxQ10P

RxQ10N

RxQ08P

RxQ08N

RxDGND

RxQ06P

RxQ06N

RxQ04P

RxQ04N

RxDGND

RxQ02P

RxQ02N

RxQ00P

RxQ00N

RxDGND

NC

I

O

I

LVPECL Receiver 155 Mbits/s Data Output

Supply

Receiver Digital Ground

O

I

LVPECL Receiver 155 Mbits/s Data Output

SUPPLY Receiver Digital Ground

O

I

LVPECL Receiver 155 Mbits/s Data Output

Supply

Receiver Digital Ground

O

I

LVPECL Receiver 155 Mbits/s Data Output

LVPECL Receiver 155 Mbits/s LSB Data Output

Supply

—

Receiver Digital Ground

No User Connection Permitted²

Frame Ground¹

—

I

NC

—

NC

—

NC

—

FGND

Supply

—

FGND

I

Frame Ground¹

Reset

I

Master Reset

1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).

2. Pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to VCC, Ground,

or any signal node.

7

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Pin Descriptions (continued)

Table 1. CA16-Type Transponder Pinout (continued)

Pin #

Pin Name

I/O

Logic

Description

Transmitter Digital Ground

83

84

TxDGND

TxREFCLKP

TxREFCLKN

TxD14P

TxD14N

TxDGND

TxD12P

TxD12N

TxD10P

TxD10N

TxDGND

TxD08P

TxD08N

TxD06P

TxD06N

TxDGND

TxD04P

TxD04N

TxD02P

TxD02N

TxDGND

TxD00P

TxD00N

TxDGND

PCLKP

I

Supply

LVPECL Transmitter 155 Mbits/s Reference Clock Input

LVPECL Transmitter 155 Mbits/s Reference ClockInput

LVPECL Transmitter 155 Mbits/s Data Input

85

I

86

I

87

I

LVPECL Transmitter 155 Mbits/s Data Input

88

I

Supply

Transmitter Digital Ground

89

I

LVPECL Transmitter 155 Mbits/s Data Input

SUPPLY Transmitter Digital Ground

90

I

91

I

92

I

93

I

94

I

LVPECL Transmitter 155 Mbits/s Data Input

95

I

96

I

97

I

98

I

Supply

Transmitter Digital Ground

99

I

LVPECL Transmitter 155 Mbits/s Data Input

SUPPLY Transmitter Digital Ground

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

I

LVPECL Transmitter 155 Mbits/s LSB Data Input

I

Supply

Transmitter Digital Ground

O

I

LVPECL Transmitter Parallel Reference Clock Output

PCLKN

TxDGND

TxAGND

Tx3.3D

I

Supply

—

Transmitter Digital Ground

I

Transmitter Analog Ground

Transmitter Digital 3.3 V Supply

Transmitter Analog 3.3 V Supply

Future Function (I²C Clock)

I

Tx3.3A

I

NC

—

I

PHINIT

TXDIS

LVPECL Phase Initialization

I

TTL

—

Transmitter Disable

Future Function (I²C Data)

NC

—

O

I

PHERR

LLOOP

LVPECL Phase Error

LVTTL

Supply

LVTTL

Supply

Line Loopback (active-low)

LOS

O

I

Loss of Signal

RxDGND

OOF

Receiver Digital Ground

Out of Frame (enable frame detection)

Receiver Digital Ground

Receiver Digital 3.3 V Supply

I

RxDGND

Rx3.3D

I

1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).

2. Pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to VCC, Ground,

or any signal node.

8

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Pin Descriptions (continued)

Table 1. CA16-Type Transponder Pinout (continued)

Pin #

Pin Name

I/O

Logic

Description

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

Rx3.3D

SEARCH

RxAGND

Rx3.3A

POCLKP

POCLKN

NC

I

O

I

SUPPLY Receiver Digital 3.3 V Supply

LVTTL

Supply

Frame Search Output

Receiver Analog Ground

Receiver Analog 3.3 V Supply

I

O

—

I

LVPECL Byte-Aligned Parallel Output Clock at 155 MHz

—

No User Connection Permitted²

WS

LVTTL

Supply

Binary Input to Select One of Two Grid Wavelengths

TEC Cooler 3 V Analog SupplyVoltage

Receiver Digital Ground

VTEC

I

VTEC

I

RxDGND

RxQ15P

RxQ15N

RxQ13P

RxQ13N

RxDGND

RxQ11P

RxQ11N

RxQ09P

RxQ09N

RxDGND

RxQ07P

RxQ07N

RxQ05P

RxQ05N

RxDGND

RxQ03P

RxQ03N

RxQ01P

RxQ01N

RxDGND

NC

I

O

I

LVPECL Receiver MSB 155 Mbits/s Data Output

LVPECL Receiver 155 Mbits/s Data Output

Supply

Receiver Digital Ground

O

I

LVPECL Receiver 155 Mbits/s Data Output

Supply

Receiver Digital Ground

O

I

LVPECL Receiver 155 Mbits/s Data Output

Supply

Receiver Digital Ground

O

I

LVPECL Receiver 155 Mbits/s Data Output

Supply

—

Receiver Digital Ground

—

I

No User Connection Permitted²

Frame Ground¹

NC

—

NC

—

NC

—

FGND

Supply

1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).

2. Pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to VCC, Ground, or any signal

node.

9

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Pin Descriptions (continued)

Table 2. CA16-Type Transponder Input Pin Descriptions

Pin Name

Pin Description

TxD[0:15]P 16-Bit Differential LVPECL Parallel Input Data Bus. TxD15P/N is the most significant bit of the

TxD[0:15]N input word and is the first bit serialized. TxD00P/N is the least significant bit of the input word and

is the last bit serialized. TxD[0:15]P/N is sampled on the rising edge of PICLK.

PICLKP

PICLKN

Differential LVPECL Parallel Input Clock. A 155 MHz nominally 50% duty cycle input clock to

which TxD[0:15]P/N is aligned. The rising edge of PICLK transfers the data on the 16 TxD inputs

into the holding register of the parallel-to-serial converter.

TxREFCLKP Differential LVPECL Low Jitter 155.520 MHz Input Reference Clock. This input is used as the

TxREFCLKN reference for the internal clock frequency synthesizer, which generates the 2.5 GHz bit rate clock

used to shift data out of the parallel-to-serial converter and also for the byte-rate clock, which

transfers the 16-bit parallel input data from the input holding register into the parallel-to-serial shift

register. Input is internally terminated and biased. See discussion on timing interface, page 18.

TxDIS

Transmitter Disable Input. A logic high on this input pin shuts off the transmitter’s laser so that

there is no optical output.

WS

Wavelength Select. When this input is a logic 0 or left floating, the output wavelength will be the

nominal wavelength (at 25 °C); when it is a logic 1, the wavelength will increase by approximately

0.8 nm (100 GHz frequency decrease).

DLOOP

Diagnostic Loopback Enable (LVTTL). When the DLOOP input is low, the 2.5 Gbits/s serial data

stream from the parallel-to-serial converter is looped back internally to the serial-to-parallel con-

verter along with an internally generated bit synchronous serial clock. The received serial data

path from the optical receiver is disabled.

LLOOP

PHINIT

Line Loopback Enable (LVTTL). When LLOOP is low, the 2.5 Gbits/s serial data and recovered

clock from the optical receiver are looped directly back to the optical transmitter. The multiplexed

serial data from the parallel-to-serial converter is ignored.

Phase Initialization (Single-Ended LVPECL). This input is used to align the internal elastic store

(FIFO). A rising edge on PHINIT will realign the internal timing (see FIFO discussion, pages 12

and 18).

FRAMEN^*Frame Enable Input (LVTTL). Enables the frame detection circuitry to detect A1, A2 byte align-

ment and to lock to a word boundary. The CA16 transponder will continually perform frame acqui-

sition as long as FRAMEN is held high. When this input islow, the frame-detection circuitry is

disabled. Frame-detection process is initiated by rising edge of out-of-frame pulse.

OOF^*

Out of Frame (LVTTL). This input indicator is typically generated by external SONET/SDH over-

head monitor circuitry in response to a state in which the frame boundaries of the received

SONET/SDH signal are unknown, i.e., after system reset or loss of synchronization. The rising

edge of the OOF input initiates the frame detection function if FRAMEN is high. The FP output

goes high when the frame boundary is detected in the incoming serial data stream from the opti-

cal receiver.

RESET

Master Reset (LVTTL). Reset input for the multiplexer and demultiplexer. A logic low on this input

clears all buffers and registers. During RESET, POCLK and PCLK do not toggle.

* Future versions of the cooled transponder will not support the frame-detect function.

10

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Pin Descriptions (continued)

Table 3. CA16-Type Transponder Output Pin Descriptions

Pin Name

Pin Description

RxQ[0:15]P 16-Bit Differential LVPECL Parallel Output Data Bus. RxQ[0:15] is the 155 Mbyte/s 16-bit output

RxQ[0:15]N word. RxQ15P/N is the most significant bit of the received word and is the first bit serialized.

RxQ00P/N is the least significant bit of the received word and is the last bit serialized. RxQ[0:15]P/

N is updated on the falling edge of POCLK.

POCLKP

POCLKN

Differential LVPECL Parallel Output Clock. A 155 MHz nominally 50% duty cycle, byte rate out-

put clock that is aligned to the RxQ[0:15] byte serial output data. RxQ[0:15] and FP are updated on

the falling edge of POCLK.

*

FP

Frame Pulse (LVPECL). Indicates frame boundaries in the received serial data stream. If framing

pattern detection is enabled (FRAMEN high and OOF), FP pulses high for one POCLK cycle when

a 32-bit sequence matching the framing pattern is detected in the received serial data. FP is

updated on the falling edge of POCLK.

*

SEARCH

LOS

A1 A2 Frame Search Output (LVTTL). A high on this output pin indicates that the frame detection

circuit is active and is searching for a new A1 A2 byte alignment. This output will be high during the

entire A1 A2 frame search. Once a new alignment is found, this signal will remain high for a mini-

mum of one 155 MHz clock period beyond the third A2 byte before it will be set low.

Loss of Signal (LVTTL). A low on this output indicates a loss of clock by the clock recovery circuit

in the optical receiver.

LSRBIAS Laser Bias Alarm (Analog). The analog bias alarm is not available on the CA16 transponders.

LSRALM

Laser Degrade Alarm (5 V CMOS). This output goes to a logic 0 when the laser output power

degrades 2 dB below the nominal output power.

LPM

Laser Power Monitor (Analog). Provides an indication of the output power level from the transmit-

ter laser. This output is set at 500 mV for the nominal transmitter optical output power. If the optical

power decreases by 3 dB, this output will drop to approximately 250 mV, and if the output power

should increase by 3 dB, this output will increase to1000 mV.

PCLKP/N

Parallel Byte Clock (Differential LVPECL). A byte-rate reference clock generated by dividing the

internal 2.488 GHz serial bit clock by 16. This output is normally used to synchronize byte-wide

transfers from upstream logic into the CA16 transponder. See timing discussion for additional

details, page 18.

PHERR

Phase Error Signal (Single-Ended LVPECL). Pulses high during each PCLK cycle for which there

is a potential setup/hold timing violation between the internal byte clock and the PICLK timing

domain. PHERR is updated on the falling edge of the PCLK outputs.

IPDMON

Receiver Photodiode Current Monitor (Analog). This output provides a current output that is a

mirror of the of the photocurrent generated by the optical receiver’s photodetector diode (APD or

PIN). A 10 kΩ resistor from pin 2 to ground provides a voltage at this output ranging from ~1 mV to

~800 mV, depending on the optical input power.

WDEA

Wavelength Deviation Alarm (5 V TTL). This output changes logic levels whenever the optical

transmitter’s wavelength deviates from the nominal wavelength by more than ±100 pm.

LOCKDET Lock Detect (LVTTL). This output goes low after the transmit side PLL has locked to the clock sig-

nal provided at the TXREFCLK input pins. LOCKDET is an asychronous output.

* Future versions of the cooled transponder will not support the frame-detect function.

11

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

by a serial data stream developed in the parallel-to-serial

conversion logic and by a 2488.32 MHz serial bit clock sig-

nal synthesized from the 155.52 MHz TXREFCLK input.

Functional Description

Receiver

Note that the clock divider and phase-detect circuitry

shown in Figure 1 generates internal reference clocks and

timing functions for the transmitter. Therefore, it is impor-

tant that the TxREFCLK input is generated from a precise

and stable source. To prevent internal timing signals from

producing jitter in the transmitted serial data that exceeds

the SDH/SONET jitter generation requirements of 0.01 UI,

it is required that the TxREFCLK input be generated from a

crystal oscillator or other source having a frequency accu-

racy better than 20 ppm. In order to meet the SDH/

The optical receiver in the CA16-type transponder has an

APD and is optimized for the particular SDH/SONET

application segment in which it was designed to operate.

The detected serial data output of the optical receiver is

connected to a clock and data recovery circuit (CDR),

which extracts a 2488.32 MHz clock signal. This recov-

ered serial bit clock signal and a retimed serial data signal

are presented to the 16-bit serial-to-parallel converter and

to the frame and byte detection logic.

SONET jitter generation requirement, the reference clock

jitter must be guaranteed to be less than 1 ps rms over the

12 kHz to 20 MHz bandwidth. When used in SONET net-

work applications, this input clock must be derived from a

source that is synchronized to the primary reference clock.

The serial-to-parallel converter consists of three 16-bit

registers. The first is a serial-in parallel-out shift register,

which performs serial-to-parallel conversion. The second

is an internal 16-bit holding register, which transfers data

from the serial-to-parallel register on byte boundaries as

determined by the frame and byte detection logic. On the

falling edge of the free-running POCLK signal, the data in

the holding register is transferred to the output holding

register where it becomes available as RxQ[0:15].

The timing generation circuitry provides two separate

functions. It develops a byte rate clock that is synchro-

nized to the 2488.32 MHz transmit serial clock, and it pro-

vides a mechanism for aligning the phase between the

incoming byte clock (PICLK) and the clock that loads the

parallel data from the input register into the parallel-to-

serial shift register.

Note: Future versions of the cooled transponder will

not support the frame-detect function.

The frame and byte boundary detection circuitry searches

the incoming data for three consecutive A1 bytes followed

immediately by an A2 byte. Framing pattern detection is

enabled and disabled by the FRAMEN input. The frame

detection process is started by a rising edge on OOF

while FRAMEN is active (FRAMEN = high). It is disabled

when a framing pattern is detected. When framing pattern

detection is enabled (FRAMEN = high), the framing pat-

tern is used to locate byte and frame boundaries in the

incoming serial data stream from the CDR circuits. During

this time, the parallel output data bus (RxQ[0:15]) will not

contain valid data. The timing generator circuitry takes the

located byte boundary and uses it to block the incoming

serial data stream into bytes for output on the parallel out-

put data bus (RxQ[0:15]). The frame boundary is reported

on the framing pulse (FP) output when any 32-bit pattern

matching the framing pattern is detected in the incoming

serial data stream. When framing detection is disabled

(FRAMEN = low), the byte boundary is fixed at the loca-

tion found when frame detection was previously enabled.

The PCLK output is a byte rate (155 MHz) version of the

serial transmit clock and is intended for use by upstream

multiplexing and overhead processing circuits. Using

PCLK for upstream circuits will ensure a stable frequency

and phase relationship between the parallel data coming

into the transmitter and the subsequent parallel-to-serial

timing functions. In the parallel-to-serial conversion pro-

cess, the incoming data is passed from the PICLK byte

clock timing domain to the internally generated byte clock

timing domain that is phase aligned to the internal serial

transmit clock. The timing generator also produces a feed-

back reference clock to the phase detector. A counter

divides the synthesized clock down to the same frequency

as the reference clock TxREFCLK.

The parallel-to-serial converter shown in Figure 1 is com-

prised of an FIFO and a parallel-to-serial register. The

FIFO input latches the data from the TxD[0:15]P/N bus on

the rising edge of PICLK. The parallel-to-serial register is a

loadable shift register that takes parallel input from the

FIFO output. An internally generated divide-by-16 clock,

which is phase aligned to the transmit serial clock, as

described above, activates the parallel data transfer

between registers. The serial data is shifted out of the par-

allel-to-serial register at the transmit serial clock rate.

Transmitter

The optical transmitter in the CA16-type transponder is

optimized for the particular SDH/SONET segment in

which it is destined to operate. The transmitter has a

cooled DFB laser as the optical element and operates at a

nominal 1550 nm (45 standard ITU wavelengths are avail-

able for DWDM applications). Under user control, the

transmitter can switch to either one of two adjacent ITU

wavelengths (100 GHz spacing). The transmitter is driven

12

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Functional Description (continued)

Transponder Interfacing

The TxD[0:15]P/N, TxREFCLKP/N, and PICLKP/N

inputs and the RxQ[0:15]P/N, POCLKP/N, and PCLKP/

N outputs are high-speed (155 Mbits/s),LVPECL differ-

ential data and clock signals.To maintain optimum sig-

nal fidelity, these inputs and outputs must be

Loopback Modes

The CA16-type transponder is capable of operating in

either of two loopback modes: diagnostic loopback or

line loopback.

connected to their terminating devices via 50 ¾ con-

trolled-impedance transmission lines. The transmitter

inputs (TxD[0:15]P/N, TxREFCLKP/N, and PICLKP/N)

must be terminated as close as possible to the CA16

transponder connector with a Thevenin equivalent

impedance equal to 50 Ω terminated to Vcc – 2 V. The

receiver outputs (RxQ[0:15]P/N, POCLKP/N, and

PCLKP/N) must be terminated as close as possible to

the device (IC) that these signals interface to with a

Thevenin equivalent impedance equal to 50 Ω termi-

nated to Vcc – 2 V.

Line Loopback

When LLOOP is pulled low, the received serial data

stream and recovered 2488.32 MHz serial clock from

the optical receiver are connected directly to the serial

data and clock inputs of the optical transmitter. This

establishes a receive-to-transmit loopback at the serial

line rate.

Diagnostic Loopback

When DLOOP is pulled low, a loopback path is estab-

lished from the transmitter to the receiver. In this mode,

the serial data from the parallel-to-serial converter and

the transmit serial clock is looped back to the serial-to-

parallel converter and the frame and byte detect cir-

cuitry, respectively.

Figure 3, below, shows one example of the proper ter-

minations. Other methods may be used, provided they

meet the requirements stated above.

3.3 V

SONET/SDH

INTERFACE IC

CA16-TYPE TRANSPONDER

130 Ω

80 Ω

130 Ω

80 Ω

TxD[0:15]P

(LVPECL)

50 Ω IMPEDANCE

TRANSMISSION LINES

TxLINE

MUX

Tx

TxD[0:15]N

(LVPECL)

3.3 V

130 Ω

80 Ω

130 Ω

80 Ω

RxD[0:15]P

(LVPECL)

50 Ω IMPEDANCE

TRANSMISSION LINES

RxLINE

DEMUX

Rx

RxD[0:15]N

(LVPECL)

1-1054(F)

Figure 3. Transponder Interfacing

13

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

differently than the TXD and PICLK inputs. Differentially,

the input impedance at this input is 100 Ω, but due to

the way it is biased internally, when driven single-

ended, the impedance appears as 60 Ω. The proper

termination scheme for the TXREFCLK input is shown in

Figure 4.

Functional Description (continued)

Transponder Interfacing (continued)

TxREFCLKP/N

The TXREFCLK input is different than the other inputs to

the transmitter because it is internally terminated, ac-

coupled, and self-biased. Therefore, it must be treated

CA16 TRANSPONDER

MULTIPLEXER

LVPECL

SONET/SDH

INTERFACE

IC

TXREFCLKP

PLL

CLOCK

SYNTHESIZER

TXREFCLKN

(VCC = 3.3 V)

50 Ω TRANSMISSION LINES

DIFFERENTIAL INTERFACE

CA16 TRANSPONDER

MULTIPLEXER

LVPECL

SONET/SDH

INTERFACE

IC

TXREFCLKP

TXREFCLKN

PLL

CLOCK

SYNTHESIZER

(VCC = 3.3 V)

0.1 µF

50 Ω TRANSMISSION LINES

FOR A SINGLE-ENDED INPUT,

THE INPUT IMPEDANCE IS

EQUIVALENT TO 60 Ω.

SINGLE-ENDED INTERFACE

1-1084 (F).c

Figure 4. Interfacing to the TxRefClk Input

14

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Optical Characteristics

Minimum and maximum values specified over operating case temperature range at 50% duty cycle data signal.

Typical values are measured at room temperature unless otherwise noted.

Table 4. OC-48/STM-16 Transmitter Optical Characteristics (Tc = 0 °C to 65 °C)

Parameter

Symbol

Min

Typ

Max

Unit

1

Average Output Power:

Long Reach (1.55 µm DFB laser)

Po

λ

–2

0

3

dBm

nm

Operating Wavelength:

Long Reach (1.55 µm DFB laser);

All 48 100 GHz ITU Grid Channels Available

1528

–0.06

—

1563

0.06

Variation in Center Wavelength Over Operating

Temperature (EOL)

∆λ

nm

Spectral Width:

2

Long Reach (DFB laser)

∆λ²⁰

SSR

re

—

30

—

1

nm

dB

3

Side-mode Suppression Ratio (DFB laser)

—

4

Extinction Ratio

8.2

Optical Rise and Fall Time:

CA16A2-Type

tR, tF

—

140

130

ps

CA16B2-Type

Dispersion Penalty:

CA16A2-Type

DP

—

2.0

dB

CA16B2-Type

5, 6

Eye Mask of Optical Output

Compliant with GR-253 and ITU-T G.957

Compliant with GR-253 and ITU-T G.958

Jitter Generation

1. Output power definitions and measurements per ITU-T Recommendation G.957.

2. Full spectral width measured 20 dB down from the central wavelength peak under fully modulated conditions.

3. Ratio of the average output power in the dominant longitudinal mode to the power in the most significant side mode under fulyl modulated

conditions.

4. Ratio of logic 1 output power to logic 0 output power under fully modulated conditions.

5. GR-253-CORE, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria.

6. ITU-T Recommendation G.957, Optical Interfaces for Equipment and Systems Relating to the Synchronous Digital Hierarchy.

Table 5. OC-48/STM-16 Receiver Optical Characteristics (Tc = 0 °C to 65 °C)

Parameter

Symbol

Min

Typ

Max

Unit

Average Receiver Sensitivity¹:

APD Receiver

–29

–8

–34

–6

—

dBm

PRMIN

Maximum Optical Power:

APD Receiver (long reach)

PRMAX

Link Status Switching Threshold:

APD Decreasing Light Input

LSTD

—

3

TBD

—

100

2

dBm

µs

Link Status Response Time

Optical Path Penalty

—

dB

Receiver Reflectance

—

–27

dB

Jitter Tolerance and Jitter Transfer

Compliant with GR-253 and ITU-T G.958

1. At 1310 nm, 1 x 10^–10BER, 2²³– 1 pseudorandom data input.

15

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Electrical Characteristics

Table 6. Power Supply Characteristics (Tc = 0 °C to 65 °C)

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

V^CC

I^CC

3.13

—

3.3

2000

3.3

3.47

—

V

mA

V

dc Power Supply Current Drain

TEC Voltage

VTEC

TEC_I^CC

P^DISS

3.0

—

3.5

TEC-Only Current Drain

Power Dissipation

0.6

1200

—

mA

W

—

<9

Table 7. Transmitter Electrical I/O Characteristics (TC = 0 °C to 65 °C, VCC = 3.3 V ± 5%)

Parameter

Parallel Input Clock

Symbol

Logic

Min

Typ

Max

Unit

PICLKP/N

Diff.

153.90

155.52

157.00

MHz

LVPECL

Parallel Clock in Duty Cycle

—

40

—

60

20

%

Reference Clock Freq. Tolerance

TxREFCLKP/N

Diff.

–20

ppm

LVPECL

Reference Clock Input Duty Cycle

—

30

—

70

%

1

Reference Clock Rise and Fall Time

tR, tF

0.5

ns

2

Reference Clock Signal Levels :

TxREFCLK

Diff.

Differential Input Signal Level, ∆V^INDIFF

Single-ended Input Sig. Level, ∆V^INSINGLE

Differential Input Resistance, ∆R

LVPECL

300

150

80

—

100

1200

600

120

mV

Ω

Input Data Signal Levels:

Input High, V^IH

TxD[0:15]P/N

Diff.

LVPECL V^CC– 1.2

V^CC– 2.0

—

V^CC– 0.3

V^CC– 1.5

—

V

mV

Input Low, V^IL

Input Voltage Swing, ∆V^IN

300

3

Transmitter Disable Input

TxD^IS

TxE^N

WS

TTL (5 V)

TTL

2.0

0

—

5.0

0.8

V

3

Transmitter Enable Input

Wavelength-Select Voltage:

Channel N Select, VλN

0

2.0

—

0.8

V^CC

V

Channel N – 1 Select, VλN–1

Wavelength Deviation Alarm:

Normal Mode, VNO-ALARM

Wavelength Alarm, VALARM

Alarm Setting (active-high)⁴

WDEA

TTL

0

4.5

–100

—

0.3

5

100

V

pm

Laser Degrade Alarm:

Normal Mode, VNO-ALARM

Laser Degraded, VALARM

LSRALM

4.5

0

—

5

0.3

V

5

Laser Power Monitor Output

LPM

Analog

35

500

1000

mV

Phase Initialization:

Input High, V^IH

Input Low, V^IL

PHINIT

LVPECL

V^CC– 1.0

V^CC– 2.3

—

V^CC– 0.57

V^CC– 1.44

V

1. 20% to 80%.

2. Internally biased and ac-coupled.

3. The transmitter is normally enabled and only requires an external voltage to disable.

4. The WDEA alarm becomes active when the optical wavelength deviates from the nominal center wavelength by more than 100 pm.

5. Set at 500 mV at nominal optical output power. Provides linear PO tracking (–3 dB = 250 mV, +3 dB = 1000 V).

6. Terminated into 200 Ω to GND and 100 Ω line-to-line.

16

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Electrical Characteristics (continued)

Table 7. Transmitter Electrical I/O Characteristics (TC = 0 °C to 65 °C, VCC = 3.3 V ± 5%) (continued)

Parameter

Symbol

Logic

Min

Typ

Max

Unit

Phase Error⁵:

PHERR

LVPECL

Output High, V^OH

Output Low, V^OL

V^CC– 1.2

V^CC– 2.2

—

V^CC– 0.65

V^CC– 1.5

V

Line Loopback Enable:

Active-low:

L^LOOP

LVTTL

Input High, V^IH

Input Low, V^IL

2.0

0

—

V^CC+ 1.0

0.8

V

Diagnostic Loopback Enable:

Active- low:

D^LOOP

Input High, V^IH

Input Low, V^IL

2.0

0

—

V^CC+ 1.0

0.8

V

Parallel Output Clock⁶:

PCLKP/N

Output High, V^OH

Output Low, V^OL

Differential Voltage Swing, ∆V^DIFF

S-E Voltage Swing, ∆V^SINGLE

Differential V^CC– 1.15

LVPECL V^CC– 1.95

—

V^CC– 0.6

V^CC– 1.45

1900

V

mV

800

400

950

1. 20% to 80%.

2. Internally biased and ac-coupled.

3. The transmitter is normally enabled and only requires an external voltage to disable.

4. The WDEA alarm becomes active when the optical wavelength deviates from the nominal center wavelength by more than 100 pm.

5. Set at 500 mV at nominal optical output power. Provides linear PO tracking (–3 dB = 250 mV, +3 dB = 1000 V).

6. Terminated into 200 Ω to GND and 100 Ω line-to-line.

Table 8. Receiver Electrical I/O Characteristics (Tc = 0 °C to 65 °C, Vcc = 3.3 V ± 5%)

Parameter

Symbol

Logic

Min

Typ

Max

Unit

Parallel Output Clock:

Output High, V^OH

Output Low, V^OL

POCLKP/N

Differential

LVPECL

V^CC– 1.3

V^CC– 2.0

—

V^CC– 0.7

V^CC– 1.4

V

POCLk Duty Cycle

—

40

—

60

%

Output Data Signal Levels¹:

Output High, V^OH

Output Low, V^OL

RxQ[0:15]P/N Differential

LVPECL

V^CC– 1.3

V^CC– 2.0

V^CC– 0.7

V^CC– 1.4

—

V

RxQ[0:15] Rise/Fall Time²

—

1.0

ns

Frame Pulse:

Output High, V^OH

Output Low, V^OL

FP

LVPECL

V^CC– 1.3

V^CC– 2.0

V^CC– 0.7

V^CC– 1.4

—

V

Loss-of-Signal Output:

Output High, V^OH

Output Low, V^OL

LOS

LVTTL

2.4

0

—

V^CC

0.4

V

Out-of-Frame Input:

Input High, V^IH

Input Low, V^IL

OOF

LVTTL

V

2.0

0.0

—

TTL V^CC+ 1.0

0.8

Frame Enable Input

Input High, V^IH

Input Low, V^IL

FRAMEN

2.0

0.0

—

TTL V^CC+ 1.0

0.8

V

1. Terminated into 330 Ω to ground.

2. 20% to 80%, 330 Ω to ground.

17

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

During normal operation, the incoming data is passed

from the PICLK input timing domain to the internally

generated divide-by-16 PCLK timing domain. Although

the frequency of PICLK and PCLK is the same, their

phase relationship is arbitrary. To prevent errors caused

by short setup or hold times between the two domains,

the timing generator circuitry monitors the phase rela-

tionship between PICLK and PCLK.

Timing Characteristics

Transmitter Data Input Timing

The CA16 transponder utilizes a unique FIFO to

decouple the internal and external (PICLK) clocks. The

FIFO can be initialized, which allows the system

designer to have an infinite PCLK-to-PICLK delay

through this interfacing logic (ASIC or commercial chip

set). The configuration of the FIFO is dependent upon

the I/O pins, which comprise the synch timing loop.

This loop is formed from PHERR to PHINIT and PCLK

to PICLK.

When an FIFO timing violation is detected, the phase

error (PHERR) signal pulses high. If the condition per-

sists, PHERR will remain high. When PHERR is fed

back into the PHINIT input (by shorting them on the

printed-circuit board [PCB]), PHINIT will initialize the

FIFO if PHINIT is held high for at least two byte clocks.

The initialization of the FIFO prevents PCLK and PICLK

from concurrently trying to read and write over the

same FIFO bank.

The FIFO can be thought of as a memory stack that

can be initialized by PHINT or LOCKDET. The PHERR

signal is a pointer that goes high when a potential tim-

ing mismatch is detected between PICLK and the inter-

nally generated PCLK clock. When PHERR is fed back

to PHINIT, it initializes the FIFO so that it does not over-

flow or underflow.

During realignment, one-to-three bytes (16 bits wide)

will be lost. Alternatively, the customer logic can take in

the PHERR signal, process it, and send an output to

the PHINIT input in such a way that only idle bytes are

lost during the initialization of the FIFO. Once the FIFO

has been initialized, PHERR will go inactive.

The internally generated divide-by-16 clock is used to

clock-out data from the FIFO. PHINIT and LOCKDET

signals will center the FIFO after the third PICLK pulse.

This is done to ensure that PICLK is stable. This

scheme allows the user to have an infinite PCLK to

PICLK delay through the ASIC. Once the FIFO is cen-

tered, the PCLK and PICLK can have a maximum drift of

±5 ns.

18

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Timing Characteristics (continued)

Since the delay in the customer ASIC is unknown, the

two clocks (PCLK and PICLK) might drift in respect to

each other and try to perform the read and writer oper-

ation on the same bank in the FIFO at the same time.

However, before such a clock mismatch can occur,

Input Timing Mode 1

In the configuration shown in Figure 5, PHERR to

PHINIT has a zero delay (shorted on the PCB) and the

PCLK is used to clock 16-bit-wide data out of the cus-

tomer ASIC. The FIFO in the multiplexer ia 16-bits wide

and six registers deep.

PHERR goes high and, if externally connected to

PHINIT, will initialize the FIFO provided PHINIT

remains high for at least two byte clocks. One to three

16-bit words of data will be lost during the initialization

of the FIFO.

The PCLK and PICLK signals respectively control the

READ and WRITE counters for the FIFO. The data

bank from the FIFO has to be read by the internally

generated clock (PCLK) only once after it has been writ-

ten by the PICLK input.

OSCILLATOR

155.52 MHz ± 20 ppm

TXREFCLK

PCLK

DIVIDER

PLL

INTERNAL

PCLK

PICLK

CLOCK

TXD[0:15]

16

DATA

FIFO

TIMING

GENERATOR

PHERR

PHINIT

CENTERS

FIFO

D

Q

LOCKDET

CUSTOMER LOGIC

CA16 TRANSPONDER

1-1121(F).b

Figure 5. Block Diagram Timing Mode 1

19

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

dummy bytes to the CA16 on the TXD[0:15] bus. This

should continue until PHERR goes low.

Transmitter Data Input Timing (continued)

Input Timing Mode 2

The FIFO is initialized two-to-eight byte clocks after

PHINIT goes high for two byte clocks. PHERR goes low

after the FIFO is initialized. Upon detecting a low on

PHERR, the customer logic can start sending real data

bytes on TXD[0:15]. The two timing loops (PCLK to

PICLK and PHERR to PHINIT) do not have to be of

equal length.

To avoid the loss of data, idle or dummy bytes should

be sent on the TXD[0:15] bus whenever PHERR goes

high. In the configuration shown in Figure 6, the

PHERR signal is used as an input to the customer

logic. Upon detecting a high on the PHERR signal, the

customer logic should return a high signal, one that

remains high for at least two byte-clock cycles, to the

PHINIT input of the CA16. Also, when PHERR goes

high, the customer logic should start sending idle or

OSCILLATOR

155.52 MHz ± 20 ppm

TXREFCLK

PCLK

DIVIDER

PLL

INTERNAL

PCLK

PICLK

CLOCK

TXD[0:15]

16

DATA

FIFO

TIMING

GENERATOR

PHERR

PHINIT

CENTERS

FIFO

D

Q

LOCKDET

CUSTOMER LOGIC

CA16 TRANSPONDER

1121(F).b

Figure 6. Block Diagram Timing Mode 2

20

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Timing Characteristics (continued)

reference clock to the internal load signal over temper-

ature and voltage. The connections required to imple-

ment this clocking method are shown in Figure 7. The

setup and hold times for PICLK to TxD[0:15] must be

met by the customer logic.

Forward Clocking

In some applications, it is necessary to forward-clock

the data in a SONET/SDH system. In this application,

the reference clock from which the high-speed serial

clock is synthesized and the parallel data clock both

originate from the same source on the customer appli-

cation circuit. The timing control logic in the CA16 tran-

sponder transmitter automatically generates an internal

load signal that has a fixed relationship to the reference

clock. The logic takes into account the variation of the

Possible problems: to meet the jitter generation specifi-

cations required by SONET/SDH, the jitter of the refer-

ence clock must be minimized. It could be difficult to

meet the SONET jitter generation specifications using

a reference clock generated from the customer logic.

OSCILLATOR

155.52 MHz ± 20 ppm

CLOCK

BUFFER

TXREFCLK

PCLK

DIVIDER

PLL

INTERNAL

PCLK

PICLK

CLOCK

TXD[0:15]

16

DATA

FIFO

TIMING

GENERATOR

CENTERS

FIFO

PHERR

PHINIT

LOCKDET

CUSTOMER LOGIC

CA16 TRANSPONDER

1-1122(F).a

Figure 7. Forward Clocking of the CA16Transponder

21

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Timing Characteristics (continued)

on the third PICLK after LOCKDET goes active. The

PCLK-to-PICLK delay (tD) can have any value before the

FIFO is initialized. The tD is fixed at the third PICLK

after LOCKDET goes active. Once the FIFO is initial-

ized, PCLK and PICLK cannot drift more than 5.2 ns;

tCH cannot be more than 5.2 ns.

PC^LK-to-PIC^LKTiming

After powerup or RESET, the LOCKDET signal will go

active, signifying that the PLL has locked to the clock

provided on the TXREFCLK input. The FIFO is initialized

PCLK

tD

PICLK

1ST

2ND

3RD

tCH

LOCKDET

PCLK-TO-PICLK DELAY IS FIXED AND FIFO

IS INITALIZED AT THE THIRD RISING EDGE OF

PICLK AFTER LOCKDET GOES ACTIVE.

ACTIVE

1-1123(F)

Figure 8. PCLK-to-PICLK Timing

22

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Case 2—PHERR signal is input to the customer logic

and the customer logic outputs a signal to PHINIT:

Timing Characteristics (continued)

PHERR/PHINIT

Another possible configuration is where the PHERR

signal is input into the customer logic and the customer

logic sends an output to the PHINIT input. However,

the customer logic must ensure that, upon detecting a

high on PHERR, the PHINIT signal remains high for

more than two byte clocks. If PHINIT is high for less

than two byte clocks, the FIFO is not guaranteed to be

initialized. Also, the customer logic must ensure that

PHINIT goes low after the FIFO is initialized (PHERR

goes low).

Case 1—PHERR and PHINIT are shorted on the

printed-circuit board:

PHINIT would go high whenever there is a potential tim-

ing mismatch between PCLK and PICLK. PHINIT would

remain high as long as the timing mismatch between

PCLK and PICLK. If PHINIT is high for more than two

byte clocks, the FIFO will be initialized. PHINIT will ini-

tialize the FIFO two-to-eight byte clocks after it is high

for at least two byte clocks, PHERR (and thus PHINIT)

goes active once the FIFI is initialized.

2 BYTE

CLOCKS

2—8 BYTE CLOCKS

PHERR

MINIMUM PULSE

WIDTH REQUIRED

TO CENTER

THE FIFO

CUSTOMER ASIC SENDS A

MINIMUM PULSE WIDTH OF

2 BYTE CLOCKS UPON DETECTING

A HIGH ON PHERR

PHINIT

PCLK

PICLK

INTERNAL

PCLK

PHERR GOES HIGH ON

FIFO IS INITIALIZED 2—8 BYTE CLOCKS

DETECTING A FIFO TIMING ERROR

AFTER PHINIT IS HIGH FOR 2 BYTE CLOCKS

1125(F)

Figure 9. PHERR/PHINIT Timing

23

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Timing Characteristics (continued)

Transmitter Data Input Timing (continued)

Table 9. Transmitter ac Timing Characteristics

Symbol

Description

Min

Max

Unit

tSTXD

tHTXD

—

TxD[0:15] Setup Time w. r. t. PICLK

TxD[0:15] Hold Time w. r. t. PICLK

PCLKP/N Duty Cycle

1.5

0.5

40

—

55

60

5

ns

%

—

PICLKP/N Duty Cycle

%

tPPICLK

PICLK-to-PICLK Drift After FIFO Centered

ns

tSTXD

tHTXD

PICLKP

TXD[0:15]

Figure 10. ac Input Timing

Table 10. Receiver ac Timing Characteristics

Symbol

Description

Min

Max

Unit

—

POCLK Duty Cycle

45

—

–1

2

55

1.0

1

%

1

—

RxD[15:0] Rise and Fall Time

ns

tP^POUT

tSPOUT

tHPOUT

POCLK Low to RxD[15:0] Valid Propagation Delay

RxD[15:0] and FP Setup Time w. r. t. POCLK

RxD[15:0] and FP Hold Time w. r. t. POCLK

—

2

1. 20% to 80%; 330 Ω to GND.

POCLKP

tPPOUT

tSPOUT

tHPOUT

FP

RXD[15:0]

Figure 11. Receiver Output Timing Diagram

24

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

going data bus (RxD[15:0]). Concurrently, the frame

pulse (FP) is set high for one POCLK cycle.

Timing Characteristics (continued)

Receiver Framing

The frame and byte boundary detection block is acti-

vated by the rising edge of OOF and stays active until

the first FP pulse.

Note: Future versions of the cooled transponder

will not support the frame-detect function.

Figure 13 shows the frame and byte boundary detec-

Figure 12 shows a typical reframe sequence in which a

byte realignment is made. The frame and byte bound-

ary detection is enabled by the rising edge of OOF.

Both the frame and byte boundaries are recognized

upon receipt of the first A2 byte following three consec-

utive A1 bytes. The third A2 byte is the first data byte to

be reported with the correct byte alignment on the out-

tion activation by a rising edge of OOF and deactiva-

tion by the first FP pulse.

Figure 14 shows the frame and byte boundary detec-

tion by the activation of a rising edge of OOF and deac-

tivation by the FRAMEN input.

RECOVERED

CLOCK

OOF

SERIAL

DATA

A1

A2

RXD[15:0]

A1, A1 A1, A1 A1, A1 A2, A2 A2, A2 A2, A2 A2, A2

INVALID DATA VALID DATA

ROCLK

FP

1-1023(F)r.3

Figure 12. Frame and Byte Detection

BOUNDARY DETECTION ENABLED

OOF

FP

SEARCH

1-1024(F)

Figure 13. OOF Timing (FRAMEN = High)

25

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Timing Characteristics (continued)

BOUNDARY DETECTION ENABLED

OOF

FRAMEN

FP

SEARCH

1-1025(F)

Figure 14. FRAMEN Timing

Wavelength Selection

When the wavelength select (WS) pin is at a logic low or open circuited, the optical wavelength from the CA16

transmitter will be a nominal wavelength as determined by the device code purchased. If the WS pin is pulled high

(logic 1), the optical wavelength will change to the next lower ITU channel number (100 GHz spacing, λ will

increase approximately 0.8 nm).

During the wavelength change, the transmitter’s optical output will be disabled and the wavelength deviation error

alarm will be active until the wavelength has stabilized at its new value. The LSRALM will also be active (logic 1)

during the wavelength change process.

26

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Qualification and Reliability

To help ensure high product reliability and customer satisfaction, Agere Systems Inc. is committed to an intensive

quality pro-gram that starts in the design phase and proceeds through the manufacturing process. Optoelectronics

modules are qualified to Agere internal standards using MIL-STD-883 test methods and procedures and using

sampling techniques consistent with Telcordia Technologies* requirements. This qualification program fully meets

the intent of Telcordia Technologies reliability practices TR-NWT-000468 andTA-TSY-000983. In addition, the

Agere Optoelectronics design, development, and manufacturing facility has been certified to be in full compliance

with the latest ISO ^†9001 Quality System Standards.

* Telcordia Technologies is a trademark of Telcordia Technologies, Inc.

† ISO is a registered trademark of The International Organization for Standardization.

Laser Safety Information

Class I Laser Product

All versions of the CA16-type transponders are classified as Class I laser products per FDA/CDRH, 21 CFR 1040

Laser Safety requirements. The transponders have been registered/certified with the FDA under accession number

8720009. All versions are classified as Class I laser products per IEC^‡825-1:1993.

CAUTION: Use of controls, adjustments, and procedures other than those specified herein may result in

hazardous laser radiation exposure.

This product complies with 21 CFR 1040.10 and 1040.11.

8.8 µm single-mode pigtail with connector.

Wavelength = 1.5 µm.

Maximum power = 2.0 mW.

Product is not shipped with power supply.

Because of size constraints, laser safety labeling is not affixed to the module but is attached to the outside of the

shipping carton.

NOTICE

Unterminated optical connectors can emit laser radiation.

Do not view with optical instruments.

Electromagnetic Emissions and Immunity

The CA16 transponder will be tested against CENELEC EN50 081 part 1 and part 2, FCC 15, Class B limits for

emissions.

The CA16 transponder will be tested against CENELEC EN50 082 part 1 immunity requirements.

‡ IEC is a registered trademark of The International Electrotechnical Commission.

27

Agere Systems Inc.

CA16-Type 2.5 Gbits/sDWDMTransponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Outline Diagram

Dimensions are in inches and (millimeters) (for initial samples; production version will be slightly smaller).

4.00 (101.6)

1.02 (25.91)

0.76 (19.3)

0.25 (6.4)

1.65 (41.9)

3.50 (88.9)

0.87 (22.1)

0.29 (7.4)

0.55 (14.0)

0.17 (4.3)

0.015 (0.38)

0.20 (5.08)

0.45 (11.4)

0.30 (7.6)

0.83 (21.1)

(3x) M2.5 x 0.45 MOUNTING HOLES

2 mm MAXIMUM LENGTH INTO PACKAGE

1.84 (46.7)

1.70 (43.2)

0.83 (21.1)

1.80 (45.7)

1-1103(F)

28

Agere Systems Inc.

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Ordering Information

ORDER CODE: CA 16–XX–X–XX

BASIC PART NUMBER

OPTIONS

AA = Unspecified

17—61 = ITU frequency (191.7 THz—196.1 THz)

STM LEVEL

16 = STM-16 (SONET OC-48)

CONNECTOR*

C = SC

F = FC

APPLICATION

A2 = 1800 ps-nm (100 km)

B2 = 3000 ps-n (170 km)

* Other connectors may be made available.

Table 11. Ordering Information

Code

Application

Connector

Comcode

CA16A2CAA

CA16A2FAA

CA16A2Cnn

CA16A2Fnn

CA16B2CAA

CA16B2FAA

CA16B2Cnn

CA16B2Fnn

Unspecified wavelength (1800 ps-nm)

Specified wavelength (1800 ps-nm)

Unspecified wavelength (3000 ps-nm)

Specified wavelength (3000 ps-nm)

SC

FC/PC

SC

108701475

108701483

†

—

†

FC/PC

SC

—

108701491

108701509

FC/PC

SC

†

—

†

FC/PC

—

† For specific order codes for these products, please contact your local Agere account manager.


型号：	CA16
厂家：	AGERE SYSTEMS
描述：	CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer CA16型2.5 Gb / s的DWDM转发器，具有16通道155 Mb / s的复用器/解复用器解复用器
文件：	总30页 (文件大小：442K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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