ACT5231 [AEROFLEX]

ACT5231 32-Bit Superscaler Microprocessor; ACT5231 32位超标量微处理器


型号：	ACT5231
厂家：	AEROFLEX CIRCUIT TECHNOLOGY
描述：	ACT5231 32-Bit Superscaler Microprocessor ACT5231 32位超标量微处理器微处理器
文件：	总4页 (文件大小：96K)
中文：	中文翻译
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ACT5231

32-Bit Superscaler Microprocessor

Features

■ Full militarized QED RM5231 microprocessor

■ High-performance floating point unit

● 532 MFLOPS single-precision performance

● Single cycle repeat rate for common single precision opera-tions

and some double precision operations

■ Pinout compatible with popular RM5230 with split power sup

plies (2.5V and 3.3V)

● Two cycle repeat rate for double precision multiply and double

precision combined multiply-add operations

● Single cycle repeat rate for single precision combined multiply-

add operation

■ Dual Issue superscalar microprocessor - can issue one

integer and one floating-point instruction per cycle

● 133, 150 and 200 MHz operating frequencies – Consult Factory for

latest speeds

● 325 Dhrystone2.1 MIPS

● SPECInt95 5.0, SPECfp95 5.25

■ MIPS IV instruction set

● Floating point multiply-add instruction increases performance in

signal processing and graphics applications

● Conditional moves to reduce branch frequency

● Index address modes (register + register)

■ System interface optimized for embedded applications

● 32-bit system interface lowers total system cost

● High performance write protocols maximize uncached write

bandwidth with 600 MB per second peak throughput

● Operates at processor clock divisors 2, 2.5, 3, 3.5,4, 4.5, 5, 6, 7, 8, 9

● IEEE 1149.1 JTAG boundary scan

■ Embedded application enhancements

● Specialized DSP integer Multiply-Accumulate instruction and 3

operand multiply instruction

● I and D cache locking by set

● Optional dedicated exception vector for interrupts

■ Integrated on-chip caches

● 32KB instruction and 32KB data - 2 way set associative and per

set locking

■ Fully static CMOS design with power down logic

● Standby reduced power mode with WAIT instruction

● 2.7 W typical power @ 200MHz

● Virtually indexed, physically tagged

● Write-back and write-through on per page basis

● Pipeline restart on first double for data cache misses

● 2.5V core with 3.3V IO’s

■ Integrated memory management unit

● Fully associative joint TLB (shared by I and D translations)

● 48 dual entries map 96 pages

■ 128-pin Power Quad-4 package (F22), Consult Factory for

package configuration

● Variable page size (4KB to 16MB in 4x increments)

Block Diagram

Preliminary

Technology

eroflex Circuit

– RISC TurboEngines For The Future © SCD5231 REV 1 12/22/98

DESCRIPTION

Integer Unit

The ACT5231 is a highly integrated superscalar

microprocessor that implements a superset of the

MIPS IV Instruction Set Architecture(ISA). It has a

high performance 64-bit integer unit, a high

throughput, fully pipelined 64-bit floating point unit,

an operating system friendly memory management

unit with a 48-entry fully associative TLB, a 32KB

2-way set associative instruction cache, a 32KB

2-way set associative data cache, and an efficient

32-bit system interface. The ACT5231 can issue

both an integer and a floating point instruction in the

same cycle.

The ACT5231 implements the MIPS IV

Instruction Set Architecture, and is therefore fully

upward compatible with applications that run on

processors implementing the earlier generation

MIPS I-III instruction sets. Additionally, the

ACT5231 includes two implementation specific

instructions not found in the baseline MIPS IV ISA

but that are useful in the embedded market place.

Described in detail in the QED RM5231 datasheet,

these instructions are integer multiply-accumulate

and 3-operand integer multiply.

The ACT5231 integer unit includes thirty-two

general purpose 64-bit registers, a load/store

architecture with single cycle ALU operations (add,

sub, logical, shift) and an autonomous multiply/

divide unit. Additional register resources include:

the HI/LO result registers for the two-operand

integer multiply/divide operations, and the program

counter(PC).

The ACT5231 is ideally suited for high-end

embedded

internetworking,

control

high

applications

such

performance

image

manipulation, high speed printing, and 3-D

visualization.

HARDWARE OVERVIEW

The ACT5231 offers a high-level of integration

targeted

high-performance

embedded

The ACT5231 has thirty-two general purpose

registers with register location 0 hard wired to zero.

These registersich allo are used for scalar integer

operations and address calculation. The register

file has two read ports and one write port and is fully

bypassed to minimize operation latency in the

pipeline.

applications. The key elements of the ACT5231 are

briefly described below.

Superscalar Dispatch

The ACT5231 has an efficient asymmetric

superscalar dispatch unit which allows it to issue an

integer instruction and a floating-point computation

instruction simultaneously. With respect to

superscalar issue, integer instructions include alu,

branch, load/store, and floating-point load/ store,

while floating-point computation instructions

include floating-point add, subtract, combined

multiply-add, converts, etc. In combination with its

high throughput fully pipelined floating-point

execution unit, the superscalar capability of the

ACT5231 provides unparalleled price/performance

ALU

The ACT5231 ALU consists of the integer adder/

subtractor, the logic unit, and the shifter. The adder

performs address calculations in addition to

arithmetic operations, the logic unit performs all

logical and zero shift data moves, and the shifter

performs shifts and store alignment operations.

Each of these units is optimized to perform all tions

in a single processor cycle.

computationally

intensive

embedded

applications.

CPU Registers

For additional Detail Information regarding the

operation of the Quantum Effect Design (QED)

Like all MIPS ISA processors, the ACT5231 CPU

has a simple, clean user visible state consisting of

32 general purpose registers, two special purpose

registers for integer multiplication and division, a

program counter, and no condition code bits.

RISCMark

RM 5231 , 32-Bit Superscalar

Microprocessor see the latest QED datasheet.

Pipeline

For integer operations, loads, stores, and other

non-floating-point operations, the ACT5231 uses

the simple 5-stage pipeline also found in the

ACT52xx family, R4600, R4700, and R5000. In

addition to this standard pipeline, the ACT5231

uses an extended seven stage pipeline for

floating-point operations. The ACT5231 does

virtual to physical translation in parallel with cache

access.

Aeroflex Circuit Technology

SCD5231 REV 1 12/22/98 Plainview NY (516) 694-6700

ACT5231 Microprocessor PQUAD Pinouts

(Pinouts subject to change – Contact Factory)

Pin #

Function

Vcc

Pin #

Function

Pin #

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

Function

Vcc

Pin #

157

158

159

160

161

162

163

164

165

166

167

168

169

Function

Vcc

Vss

Vcc

Vss

NMI*

Vcc

ExtRqst*

Reset*

ColdReset*

VccOK

BigEndian

Vcc

SysAD4

SysAD36

SysAD5

SysAD37

Vcc†

ModeIn

RdRdy*

WrRdy*

ValidIn*

ValidOut*

Release*

VccP

VssP

SysClock

Vcc†

Vss

SysAD28

SysAD60

SysAD29

SysAD61

Vss

SysAD16

SysAD48

Vcc†

Vss

Vcc†

)

Vss

SysAD6

SysAD38

Vcc

Vss

SysAD30

SysAD17

SysAD49

SysAD18

SysAD62

¹⁷⁰t

Vss

171

Vcc

Vss

n₁₇₂

SysAD7

SysAD39

SysAD8

SysAD40

Vcc†

Vss

Vcc

Vss

Vcc†

SysAD50

n ^Vcc

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

SysAD31

SysAD63

SysADC2

SysADC6

Vcc†

–

123

Vss

SysAD19

SysAD51

Vcc†

₁₂₄c

Vss

t₁₂₅

Vss

SysCmd0

_SysCmd1j

SysAD9

SysAD41

Vcc

Vss

SysAD10

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

Vss

SysCmd2

Vss

SysADC3

SysADC7

Vcc

SysCmd3

Vcc

SysAD20

SysAD52

SysAD21

SysAD53

Vcc

₇₇i

Vss

SysAD42

SysCmd4

SysCmd5

Vcc

SysADC0

SysADC4

Vcc†

SysAD11

(

SysAD43

Vss

Vcc†

Vss

SysAD22

SysAD54

Vcc†

Vss

SysCmd6

SysCmd7

SysCmd8

SysCmdP

Vcc†

Vss

SysADC1

SysADC5

SysAD0

SysAD32

Vcc

SysAD12

SysAD44

Vcc

Vss

SysAD23

SysAD55

SysAD24

SysAD56

Vcc

Vss

SysAD13

SysAD45

SysAD14

SysAD46

Vcc†

Vss

Vcc†

Vss

Vcc

Vss

Int0*

Int1*

Int2*

Int3*

Int4*

Int5*

Vcc

Vss

SysAD1

SysAD33

Vcc†

Vss

SysAD25

SysAD57

Vcc†

Vss

SysAD2

SysAD34

SysAD3

SysAD35

Vcc

SysAD15

SysAD47

Vcc

Vss

ModeClock

JTDO

Vss

SysAD26

SysAD58

SysAD27

SysAD59

Vcc

Vss

Vcc

Vss

JTDI

JTCK

JTMS

Vcc

100

101

102

103

104

Vss

† These VCC pins may be 2.5V in future higher performance devices

Aeroflex Circuit Technology

SCD5231 REV 1 12/22/98 Plainview NY (516) 694-6700

C IRC UIT TEC HNO LO G Y

Sample Ordering Information

Part Number

Screening

Speed (MHz)

Package

ACT-5231PC-133F22C

ACT-5231PC-150F22T

ACT-5231PC-200F22M

Commercial Temperature

Military Temperature

Military Screening

133

150

200

128 Lead PQUAD

Part Number Breakdown

ACT– 5231 PC – 200 F22 M

Aeroflex Circuit

Technology

Screening

Base Processor Type

C = Commercial Temp, 0°C to +70°C

I = Industrial Temp, -40°C to +85°C

T = Military Temp, -55°C to +125°C

^{M = Military Temp, -55°C to +125°C, Screened}*

Q = MIL-PRF-38534 Compliant/SMD if applicable

Package Type & Size

Cache Style

PC = Primary Cache

Maximum Pipeline Freq.

133 = 150MHz

150 = 150MHz

200 = 200MHz

Surface Mount Package

F22 = 1.10" SQ 128 Lead PQUAD

Screened to the individual test methods of MIL-STD-883

Specifications subject to change without notice.

Telephone: (516) 694-6700

FAX: (516) 694-6715

Aeroflex Circuit Technology

35 South Service Road

Plainview New York 11803

www.aeroflex.com/act1.htm

Toll Free Inquiries: (800) 843-1553

E-Mail: sales-act@aeroflex.com

Aeroflex Circuit Technology

SCD5231 REV 1 12/22/98 Plainview NY (516) 694-6700

ACT5231 [AEROFLEX]

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