5962R9689103QXA [AEROFLEX]
Radiation-Hardened 32K x 8 PROM; 抗辐射32K ×8 PROM
| 型号： | 5962R9689103QXA |
| 厂家： | 
AEROFLEX CIRCUIT TECHNOLOGY |
| 描述： | Radiation-Hardened 32K x 8 PROM |
| 文件： | 总11页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Standard Products
UT28F256 Radiation-Hardened 32K x 8 PROM
Data Sheet
December 2002
FEATURES
q Programmable, read-only, asynchronous, radiation-
-
Memory cell LET threshold: >128 MeV-cm2/mg
q QML Q & V compliant part
hardened, 32K x 8 memory
-
Supported by industry standard programmer
-
AC and DC testing at factory
o
q 45ns and 40ns maximum address access time (-55 C to
q Packaging options:
o
+125 C)
-
-
28-lead 50-mil center flatpack (0.490 x 0.74)
28-lead 100-mil center DIP (0.600 x 1.4) - contact factory
q TTL compatible input and TTL/CMOS compatible output
levels
q VDD: 5.0 volts + 10%
q Three-state data bus
q Standard Microcircuit Drawing 5962-96891
q Low operating and standby current
-
Operating: 125mA maximum @25MHz
Derating: 3mA/MHz
Standby: 2mA maximum (post-rad)
·
PRODUCT DESCRIPTION
-
q Radiation-hardened process and design; total dose
The UT28F256 amorphous silicon anti-fuse PROM is a high
performance, asynchronous, radiation-hardened,
irradiation testing to MIL-STD-883, Method 1019
32K x 8 programmable memory device. The UT28F256 PROM
features fully asychronous operation requiring no external clocks
or timing strobes. An advanced radiation-hardened twin-well
CMOS process technology is used to implement the UT28F256.
The combination of radiation-hardness, fast access time, and low
power consumption make the UT28F256 ideal for high speed
systems designed for operation in radiation environments.
-
-
Total dose: 1E6 rad(Si)
LETTH(0.25) ~ 100 MeV-cm2/mg
-
SEL Immune >128 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 1.0E-11
- 1.2E-8 errors/device-day, Adams 90% geosynchronous
heavy ion
MEMORY
ARRAY
A(14:0)
DECODER
SENSE AMPLIFIER
CE
CONTROL
LOGIC
PE
OE
DQ(7:0)
PROGRAMMING
Figure 1. PROM Block Diagram
DEVICE OPERATION
PIN NAMES
The UT28F256 has three control inputs: Chip Enable (CE),
Program Enable (PE), and Output Enable (OE); fifteen address
inputs, A(14:0); and eight bidirectional data lines, DQ(7:0).CE
is the device enable input that controls chip selection, active, and
standby modes. AssertingCE causes I DD to rise to its active value
A(14:0)
CE
Address
Chip Enable
OE
Output Enable
Program Enable
Data Input/Data Output
and decodes the fifteen address inputs to select one of 32,768
words in the memory. PE controls program and read operations.
During a read cycle, OE must be asserted to enable the outputs.
PE
DQ(7:0)
PIN CONFIGURATION
Table 1. Device Operation Truth Table 1
1
A14
A12
A7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
OE
X
0
PE
1
CE
1
I/O MODE
Three-state
Data Out
Data In
MODE
Standby
Read
2
PE
A13
A8
3
A6
A5
4
1
0
5
A9
1
0
0
Program
A4
A3
A2
6
A11
2
1
1
0
Three-state
7
OE
Read
8
A10
Notes:
A1
A0
9
CE
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
10
11
12
13
14
DQ7
DQ6
DQ0
DQ1
DQ2
DQ5
DQ4
V
DQ3
SS
ABSOLUTE MAXIMUM RATINGS 1
(Referenced to VSS
SYMBOL
VDD
)
PARAMETER
LIMITS
UNITS
DC supply voltage
-0.3 to 7.0
V
V
VI/O
TSTG
PD
Voltage on any pin
-0.5 to (VDD + 0.5)
Storage temperature
-65 to +150
1.5
°C
Maximum power dissipation
Maximum junction temperature
W
TJ
+175
°C
Thermal resistance, junction-to-case 2
DC input current
QJC
II
3.3
°C/W
mA
±10
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
2. Test per MIL-STD-883, Method 1012, infinite heat sink.
2
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDD
PARAMETER
LIMITS
4.5 to 5.5
UNITS
V
Positive supply voltage
Case temperature range
DC input voltage
TC
-55 to +125
°C
VIN
0 to VDD
V
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(VDD = 5.0V ±10%; -55°C < TC < +125°C)
SYMBOL
VIH
PARAMETER
High-level input voltage
Low-level input voltage
CONDITION
MINIMUM
MAXIMUM
UNIT
(TTL)
(TTL)
2.4
V
V
VIL
0.8
0.4
VOL1
VOL2
VOH1
VOH2
Low-level output voltage
Low-level output voltage
High-level output voltage
High-level output voltage
Input capacitance
IOL = 4.0mA, VDD = 4.5V (TTL)
IOL = 200mA, VDD = 4.5V (CMOS)
IOH = -200mA, VDD = 4.5V (CMOS)
IOH = -2.0mA, VDD = 4.5V (TTL)
V
VSS + 0.10
V
VDD -0.1
2.4
V
V
1
¦ = 1MHz, VDD = 5.0V
15
15
pF
CIN
VIN = 0V
1, 4
Bidirectional I/O capacitance ¦ = 1MHz, VDD = 5.0V
pF
CIO
VOUT = 0V
IIN
Input leakage current
VIN = 0V to VDD
-5
5
mA
mA
IOZ
Three-state output leakage
current
VO = 0V to VDD
VDD = 5.5V
OE= 5.5V
-10
10
2,3
Short-circuit output current
VDD = 5.5V, VO = VDD
VDD = 5.5V, VO = 0V
90
mA
mA
IOS
-90
5
Supply current operating
@25.0MHz (40ns product)
TTL inputs levels (IOUT = 0), VIL =
0.2V
IDD1(OP)
125
117
mA
mA
@22.2MHz (45ns product)
VDD, PE = 5.5V
IDD2(SB) Supply current standby
post-rad
CMOS input levels VIL = VSS +0.25V
CE = VDD - 0.25 VIH = VDD - 0.25V
2
mA
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rad(Si).
1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Functional test.
5. Derates at 3.0mA/MHz.
3
READ CYCLE
The chip enable-controlled access is initiated byCE going active
while OE remains asserted, PE remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
tELQV is satisfied, the eight-bit word addressed by A(14:0)
A combination of PE greater than VIH(min), and CE less than
VIL(max) defines a read cycle. Read access time is measured
from the latter of device enable, output enable, or valid address
to valid data output.
appears at the data outputs DQ(7:0).
Output enable-controlled access is initiated by OE going active
while CE is asserted, PE is deasserted, and the addresses are
stable. Read access time is tGLQV unless tAVQV or tELQV have
An address access read is initiated by a change in address inputs
while the chip is enabled withOE asserted and PE deasserted.
Valid data appears on data output, DQ(7:0), after the specified
tAVQV is satisfied. Outputs remain active throughout the entire
not been satisfied.
cycle. As long as device enable and output enable are active, the
address inputs may change at a rate equal to the minimum read
cycle time.
AC CHARACTERISTICS READ CYCLE (Post-Radiation)*
(VDD = 5.0V ±10%; -55°C < TC < +125°C)
SYMBOL
PARAMETER
28F256-45
28F256-40
UNIT
MIN
MAX
MIN
MAX
1
Read cycle time
45
40
ns
tAVAV
tAVQV
Read access time
Output hold time
45
40
ns
ns
2
0
0
0
0
tAXQX
2
OE-controlled output enable time
ns
tGLQX
tGLQV
tGHQZ
OE-controlled access time
OE-controlled output three-state time
CE -controlled output enable time
15
15
15
15
ns
ns
ns
2
0
0
tELQX
tELQV
tEHQZ
CE -controlled access time
45
15
40
15
ns
ns
CE-controlled output three-state time
Notes:
Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rads(Si).
*
1. Functional test.
2. Three-state is defined as a 400mV change from steady-state output voltage.
4
tAVAV
A(14:0)
CE
tAVQV
tELQX
tELQV
tEHQZ
OE
tGHQZ
tAXQX
tGLQV
tGLQX
tAVQV
DQ(7:0)
Figure 2. PROM Read Cycle
RADIATION HARDNESS
maintaining the circuit density and reliability. For transient
radiation hardness and latchup immunity, UTMC builds all
radiation-hardened products on epitaxial wafers using an
advanced twin-tub CMOS process. In addition, UTMC pays
special attention to power and ground distribution during the
design phase, minimizing dose-rate upset caused by rail collapse.
The UT28F256 PROM incorporates special design and layout
features which allow operation in high-level radiation
environments. UTMC has developed special low-temperature
processing techniques designed to enhance the total-dose
radiation hardness of both the gate oxide and the field oxide while
RADIATION HARDNESS DESIGN SPECIFICATIONS 1
Total Dose
1E6
rad(Si)
MeV-cm2/mg
MeV-cm2/mg
MeV-cm2/mg
cm 2
Latchup LET Threshold
>128
Memory Cell LET Threshold
Transient Upset LET Threshold
>128
54
Transient Upset Device Cross Section @ LET=128 MeV-cm2/mg
1E-6
Note:
1. The PROM will not latchup during radiation exposure under recommended operating conditions.
5
330 ohms
TTL
3.0V
V
=1.73V
REF
90%
90%
50pF
10%
10%
0V
< 5ns
< 5ns
Input
Pulses
Notes:
1. 50pF including scope probe and test socket.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(TTL input = 1.5V).
Figure 3. AC Test Loads and Input Waveforms
6
0.015
0.008
6
PIN NO. 1 ID.
k
0.015
0.008
k
26 PLACES
0.050 BSC
e
-A-
-B-
D
0.740 MAX
S1
(4) PLACES
0.000 MIN.
E1
0.036
M
H
A-B
S
D
S
0.550 MAX
0.022
0.015
b
28 PLACES
0.010
7
5
M
H
A-B
S
D
S
5
TOP VIEW
E
0.520
0.460
-D-
c
A
0.009
0.004
0.115
0.045
7
0.040
-H-
-C-
Q
0.045
0.026
E2
0.180 MIN
L
E3
0.030 MIN
0.370
0.250
END VIEW
Notes:
1. All exposed metalized areas to be plated per MIL-PRF-38535.
2. The lid is connected to V
.
SS
3. Lead finishes are in accordance with MIL-PRF-38535.
4. Dimension letters refer to MIL-STD-1835.
5. Lead position and coplanarity are not measured.
6. ID mark symbol is vendor option.
7. With solder, increase maximum by 0.003.
8. Total weight is approximately 2.4 grams.
Figure 5. 28-Lead 50-mil Center Flatpack (0.490 x 0.74)
7
ORDERING INFORMATION
256K PROM: SMD
5962
* 96891 *
*
*
*
Lead Finish:
(A)
(C)
=
=
Solder
Gold
(X)
=
Optional
Case Outline:
(Y)
(X)
=
=
28-pin DIP (contact factory)
28-lead Flatpack
Class Designator:
(Q)
(V)
=
=
Class Q
Class V
Device Type
(03) = 45ns Access Time, TTL inputs, CMOS/TTL compatible outputs
(04) = 40ns Access Time, TTL inputs, CMOS/TTL compatible outputs
Drawing Number: 96891
Total Dose:
(F)
=
=
=
=
3E5 rads(Si)
5E5 rads(Si)
1E6 rads(Si)
1E5 rads(Si)
(G)
(H)
(R)
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
4. Check factory for availability of 45ns part.
5. Lead finish: Factory programming either solder or gold. Field programming gold only.
8
256K PROM
UT **** *** - * * * * * *
Total Dose:
( ) Total dose characteristics neither tested nor guaranteed
=
Lead Finish:
(A)
(C)
(X)
=
=
=
Solder
Gold
Optional
Screening:
(C)
(P)
=
=
Mil Temp
Prototype
Package Type:
(P)
(U)
=
=
28-lead DIP (contact factory)
28-lead Flatpack
Access Time:
(40) = 40ns access time, TTL compatible inputs, CMOS/TTL compatible outputs
(45) = 45ns access time, TTL compatible inputs, CMOS/TTL compatible outputs
Device Type Modifier:
(T)
=
TTL compatible inputs and CMOS/TTL compatible outputs
Device Type:
(28F256) = 32Kx8 One Time Programmable PROM
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may
not be specified.
4. Prototype flow per UTMC Manufacturing Flows Document. Devices have prototype assembly and are tested at 25°C only. Radiation characteristics
are neither tested nor guaranteed and may not be specified.
5. Check factory for availability of 45ns part.
6. Lead finish: Factory programming either solder or gold. Field programming gold only.
9
Notes
10
Notes
11
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